Semiconductor memory device

Abstract

According to an embodiment, a semiconductor memory device includes first and second array chips and a circuit chip. A first memory cell array includes a first memory cell and first and second selection transistors. A second memory cell array includes a second memory cell and third and fourth selection transistors. A third memory cell array includes a third memory cell and fifth and sixth selection transistors. A fourth memory cell array includes a fourth memory cell and seventh and eighth selection transistors. A first word line is connected to the first and third memory cells. A second word line is connected to the second and fourth memory cells. A first bit line is connected to the first and seventh selection transistors. A second bit line is connected to the third and fifth selection transistors. In a write operation, different voltage application conditions are set for the first array chip and the second array chip.

Description

Semiconductor memory device

[0001] An embodiment of the present invention relates to a semiconductor memory device.

[0002] As a semiconductor memory device, a NAND type flash memory is known.

[0003] Japanese Patent Application Laid-Open No. 2023-72960

[0004] In one embodiment of the present invention, a semiconductor memory device capable of suppressing a decrease in processing ability is provided.

[0005] The semiconductor memory device according to this embodiment includes a first array chip including a first memory cell array and a second memory cell array, a second array chip including a third memory cell array and a fourth memory cell array, a circuit chip including a first word line, a second word line, a first bit line, a second bit line, a first source line, a second source line, a third source line, a fourth source line, a first selection gate line, a second selection gate line, a third selection gate line, a fourth selection gate line, a fifth selection gate line, a sixth selection gate line, a seventh selection gate line, an eighth selection gate line, a first row decoder, a second row decoder, a first sense amplifier, and a second sense amplifier. The first memory cell array includes a first memory string including a first memory cell, a first selection transistor, and a second selection transistor. The second memory cell array includes a second memory string including a second memory cell, a third selection transistor, and a fourth selection transistor, and is arranged adjacent to the first memory cell array in a first direction. The third memory cell array includes a third memory string comprising a third memory cell, a fifth selection transistor, and a sixth selection transistor. The fourth memory cell array includes a fourth memory string comprising a fourth memory cell, a seventh selection transistor, and an eighth selection transistor, and is arranged adjacent to the third memory cell array in the first direction. The first word line is connected to the gates of the first and third memory cells, respectively. The second word line is connected to the gates of the second and fourth memory cells, respectively. The first bit line is connected to the first selection transistor and the seventh selection transistor. The second bit line is connected to the third selection transistor and the fifth selection transistor. The first source line is connected to the second selection transistor. The second source line is connected to the fourth selection transistor. The third source line is connected to the sixth selection transistor. The fourth source line is connected to the eighth selection transistor. The first selection gate line is connected to the gate of the first selection transistor. The second selection gate line is connected to the gate of the second selection transistor. The third selection gate line is connected to the gate of the third selection transistor. The fourth selection gate line is connected to the gate of the fourth selection transistor. The fifth selection gate line is connected to the gate of the fifth selection transistor.The sixth selection gate line is connected to the gate of the sixth selection transistor. The seventh selection gate line is connected to the gate of the seventh selection transistor. The eighth selection gate line is connected to the gate of the eighth selection transistor. The first row decoder is connected to the first word line, the first selection gate line, the second selection gate line, the fifth selection gate line, and the sixth selection gate line. The second row decoder is connected to the second word line, the third selection gate line, the fourth selection gate line, the seventh selection gate line, and the eighth selection gate line. The first sense amplifier is connected to the first bit line. The second sense amplifier is connected to the second bit line. During the write operation, different voltage application conditions are set for the first array chip and the second array chip.

[0006] A block diagram showing an example of the overall configuration of a semiconductor memory device according to the first embodiment. A circuit diagram showing an example of the circuit configuration of memory cell arrays 11_1a, 11_1b, 11_2a, and 11_2b of the semiconductor memory device according to the first embodiment. A circuit diagram showing an example of the circuit configuration of block BLK0 of the semiconductor memory device according to the first embodiment. A circuit diagram showing an example of the circuit configuration of block BLK1 of the semiconductor memory device according to the first embodiment. A cross-sectional view showing the arrangement of circuit chips and array chips 10_1 and 10_2 of the semiconductor memory device according to the first embodiment. A perspective view showing the arrangement of memory cell arrays 11_1a, 11_1b, 11_2a, and 11_2b and circuit chips of the semiconductor memory device according to the first embodiment. A block diagram showing an example of the sense amplifier and data register of the semiconductor memory device according to the first embodiment. A circuit diagram showing an example of the circuit configuration of the sense amplifier unit of the semiconductor memory device according to the first embodiment. A diagram showing the threshold voltage distribution and data allocation when the memory cell transistors of the semiconductor memory device according to the first embodiment are TLC (Triple Level Cell). A diagram showing an example of the data writing sequence in the NAND string of the semiconductor memory device according to the first embodiment. A threshold voltage distribution diagram showing an example of the relationship between two types of verify voltages that can be used for each write state and two types of program conditions in the write operation of the semiconductor memory device according to the first embodiment. A graph showing an example of the relationship between the voltage of node SEN and sense time in the program verify operation of the semiconductor memory device according to the first embodiment. A diagram showing a specific example of the relationship between the program loop and the write characteristics of the array chip 10. A timing chart showing the voltage of each wire in the first example of program operation in the semiconductor memory device according to the first embodiment. A diagram showing the voltage applied to the NAND string during the period from time t2 to t3 in the timing chart shown in Figure 14. A timing chart showing the voltage of each wire in the second example of program operation in the semiconductor memory device according to the first embodiment. A diagram showing the voltage applied to the NAND string during the period from time t2 to t3 in the timing chart shown in Figure 16. A timing chart showing the voltage of each wire in the third example of program operation in the semiconductor memory device according to the first embodiment.Figure 18 shows the voltage applied to the NAND string during the period from time t2 to t3 in the timing chart. A timing chart showing the voltage of each wire in the fourth example of program operation in the semiconductor memory device according to the first embodiment. Figure 20 shows the voltage applied to the NAND string during the period from time t2 to t3 in the timing chart. A timing chart showing an example of the voltage of each wire during the erase pulse application operation in the semiconductor memory device according to the first embodiment. Figure 22 shows the voltage applied to the NAND string during the period from time t0 to t1 in the timing chart. A graph showing a specific example of the relationship between the gate-source voltage Vgs of the selected memory cell transistor and the cell current Icell flowing through the selected memory cell transistor during read operation. A timing chart showing the voltage of each wire and each signal in the first example of read operation in the semiconductor memory device according to the first embodiment. A timing chart showing the voltage of each wire and each signal in the second example of read operation in the semiconductor memory device according to the first embodiment. A timing chart showing the voltage of each wire in the first example of subpage read operation in the semiconductor memory device according to the second embodiment. A timing chart showing the voltage of each wire in a second example of subpage read operation in a semiconductor memory device according to the second embodiment. A timing chart showing the voltage of each wire in a third example of subpage read operation in a semiconductor memory device according to the second embodiment. A timing chart showing the voltage of each wire in a fourth example of subpage read operation in a semiconductor memory device according to the second embodiment. A cross-sectional view showing an example of the arrangement of circuit chips and array chips 10_1, 10_2, and 10_3 when the semiconductor memory device according to the third embodiment includes three array chips. A cross-sectional view showing an example of the arrangement of circuit chips and array chips 10_1, 10_2, 10_3, and 10_4 when the semiconductor memory device according to the third embodiment includes four array chips.

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having substantially the same function and configuration will be denoted by the same reference numerals. Duplicate explanations may be omitted if unnecessary. Furthermore, the embodiments shown below are examples of devices and methods for realizing the technical concept of this embodiment. The technical concept of the embodiments does not limit the materials, shapes, structures, arrangements, etc., of the components to those described below. Various modifications can be made to the technical concept of the embodiments without departing from the gist of the invention. These embodiments and their variations are included in the scope of the invention described in the claims and its equivalents.

[0008] 1. First Embodiment A semiconductor memory device according to the first embodiment will be described.

[0009] 1.1 Configuration 1.1.1 Overall Configuration of Semiconductor Memory Device First, an example of the overall configuration of the semiconductor memory device 1 will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the overall configuration of the semiconductor memory device 1. Note that in Figure 1, some of the connections between each component are shown by arrow lines, but the connections between components are not limited to these.

[0010] The semiconductor memory device 1 is, for example, a three-dimensional stacked NAND flash memory. The three-dimensional stacked NAND flash memory includes a plurality of non-volatile memory cell transistors arranged in three dimensions on a semiconductor substrate.

[0011] As shown in Figure 1, the semiconductor memory device 1 includes a plurality of array chips 10 and a circuit chip 20. The array chip 10 is a chip on which an array of non-volatile memory cell transistors is provided. The circuit chip 20 is a chip on which a circuit for controlling the array chip 10 is provided. In the example shown in Figure 1, the semiconductor memory device 1 includes two array chips 10_1 and 10_2. Note that the number of array chips 10 may be three or more. Hereafter, unless the array chip 10_1 and 10_2 are specified, they will be referred to as "array chip 10". Also, unless the array chip 10 and the circuit chip 20 are specified, they will simply be referred to as "chip".

[0012] Each array chip 10 includes a plurality of memory cell arrays 11. A memory cell array 11 is a region in which non-volatile memory cell transistors are arranged in three dimensions. In the example shown in Figure 1, array chip 10_1 includes memory cell arrays 11_1a and 11_1b. Array chip 10_2 includes memory cell arrays 11_2a and 11_2b. Note that each array chip 10 may include three or more memory cell arrays 11. Hereinafter, unless limited to one of the memory cell arrays 11_1a, 11_1b, 11_2a, and 11_2b, it will be referred to as memory cell array 11.

[0013] Each memory cell array 11 includes multiple subblocks SBLK. In the example shown in Figure 1, memory cell array 11_1a includes subblocks SBLK0_1 and SBLK2_1. Memory cell array 11_2a includes subblocks SBLK0_2 and SBLK2_2. Memory cell array 11_1b includes subblocks SBLK1_1 and SBLK2_1. Memory cell array 11_2b includes subblocks SBLK1_2 and SBLK3_2. Hereafter, unless a specific subblock SBLK is identified, it will be referred to simply as "subblock SBLK".

[0014] A block BLK is formed by a combination of one subblock SBLK from each of the multiple array chips 10. That is, a block BLK includes one subblock SBLK from any one of the array chips 10. For example, block BLK0 is formed by subblock SBLK0_1 of memory cell array 11_1a and subblock SBLK0_2 of memory cell array 11_2a. In other words, block BLK0 includes subblock SBLK0_1 of memory cell array 11_1a and subblock SBLK0_2 of memory cell array 11_2a. Similarly, block BLK1 includes subblock SBLK1_1 of memory cell array 11_1b and subblock SBLK1_2 of memory cell array 11_2b. Block BLK2 includes subblock SBLK2_1 of memory cell array 11_1a and subblock SBLK2_2 of memory cell array 11_2a. Block BLK3 includes subblock SBLK3_1 of memory cell array 11_1b and subblock SBLK3_2 of memory cell array 11_2b. Hereafter, unless a specific block BLK is identified, it will be referred to simply as block BLK.

[0015] A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased all at once. The multiple memory cell transistors within each block BLK (each subblock SBLK) are associated with rows and columns. The number of block BLKs and subblock SBLKs is arbitrary. The circuit configuration of the memory cell array 11 will be described later.

[0016] Next, the circuit chip 20 will be described. The circuit chip 20 is connected to an external controller (not shown). The circuit chip 20 transmits and receives signals DQ and timing signals DQS and DQSn with the external controller. Signal DQ is, for example, data DAT, address ADD, or command CMD. Timing signals DQS and DQSn are timing signals used when inputting and outputting data DAT. Timing signal DQSn is the inverted signal of timing signal DQS.

[0017] The circuit chip 20 also receives various control signals from an external controller. For example, the circuit chip 20 receives the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the read enable signal REEn. The chip enable signal CEn is a signal for enabling the semiconductor memory device 1. The command latch enable signal CLE is a signal indicating that signal DQ is a command. The address latch enable signal ALE is a signal indicating that signal DQ is an address. The write enable signal WEn is a signal for taking the received signal DQ into the circuit chip 20 when signal DQ is address ADD or command CMD. The read enable signal REEn is a signal for the external controller to read data from the circuit chip 20.

[0018] The circuit chip 20 includes an input / output circuit 21, a logic control circuit 22, a command register 23, an address register 24, a sequencer 25, multiple row decoders 26, multiple sense amplifiers 27, a data register 28, a column decoder 29, and a source line driver 30. In the example shown in Figure 1, the circuit chip 20 includes two row decoders 26a and 26b, and two sense amplifiers 27a and 27b. Hereinafter, unless one of the row decoders 26a or 26b is specified, it will be referred to as row decoder 26. Unless one of the sense amplifiers 27a or 27b is specified, it will be referred to as sense amplifier 27. The source line driver 30 may be divided into multiple parts, similar to the row decoders 26 and sense amplifiers 27.

[0019] The input / output circuit 21 is a circuit that performs input and output of signals DQ. The input / output circuit 21 is connected to an external controller. The input / output circuit 21 is also connected to the logic control circuit 22, command register 23, address register 24, and data register 28.

[0020] The input / output circuit 21 sends the command CMD to the command register 23 if the input signal DQ is the command CMD. Also, if the input signal DQ is the address ADD, it sends the address ADD to the address register 24.

[0021] If the input signal DQ is data DAT, the input / output circuit 21 receives the input signal DQ based on the timing signals DQS and DQSn. The input / output circuit 21 then transmits the data DAT to the data register 28. The input / output circuit 21 also outputs the data DAT as an output signal DQ to the external controller along with the timing signals DQS and DQSn.

[0022] The logic control circuit 22 is a circuit that performs logic control based on control signals. The logic control circuit 22 is connected to an external controller. The logic control circuit 22 is also connected to the input / output circuit 21 and the sequencer 25. The logic control circuit 22 receives multiple control signals from the external controller. Based on the received control signals, the logic control circuit 22 controls the input / output circuit 21 and the sequencer 25.

[0023] Command register 23 is a register that temporarily stores command CMD. Command CMD is input from an external controller (not shown). Command register 23 is connected to the sequencer 25. Command register 23 sends command CMD to the sequencer 25.

[0024] The address register 24 is a register that temporarily stores address ADD. The address register 24 receives input from an external controller. For example, address ADD includes a row address and a column address. The row address is the address that specifies the row-direction wiring of the memory cell array 11. The column address is the address that specifies the column-direction wiring of the memory cell array 11. For example, the row address is used for selecting block BLK. The column address is used for selecting bit line BL. The address register 24 is connected to the row decoder 26 and the column decoder 29. For example, the address register 24 sends the row address to the row decoder 26. The address register 24 also sends the column address to the column decoder 29.

[0025] The sequencer 25 is a circuit that controls the semiconductor memory device 1. For example, the sequencer 25 is connected to the row decoders 26a and 26b, the sense amplifiers 27a and 27b, the data register 28, the column decoder 29, and the source line driver 30. The sequencer 25 controls the row decoders 26a and 26b, the sense amplifiers 27a and 27b, the data register 28, the column decoder 29, and the source line driver 30. The sequencer 25 also controls the overall operation of the semiconductor memory device 1 based on the control of an external controller. More specifically, the sequencer 25 performs write operations, read operations, erase operations, etc.

[0026] The row decoder 26 is a circuit that decodes row addresses. Based on the result of decoding the row addresses, the row decoder 26 selects the row-direction wiring of the memory cell array 11. In this embodiment, the row decoder 26a corresponds to memory cell arrays 11_1a and 11_2a. The row decoder 26b corresponds to memory cell arrays 11_1b and 11_2b.

[0027] The row decoder 26a is connected to memory cell arrays 11_1a and 11_2a in common via multiple word lines WLa. In other words, memory cell array 11_1a (array chip 10_1) and memory cell array 11_2a (array chip 10_2) share the word line WLa. Furthermore, the row decoder 26a is connected to memory cell array 11_1a via selection gate lines SGD1a and SGS1a. In addition, the row decoder 26a is connected to memory cell array 11_2a via multiple selection gate lines SGD2a and SGS2a.

[0028] The row decoder 26b is connected to memory cell arrays 11_1b and 11_2b in common via multiple word lines WLb. In other words, memory cell array 11_1b (array chip 10_1) and memory cell array 11_2b (array chip 10_2) share the word line WLb. Furthermore, the row decoder 26b is connected to memory cell array 11_1b via selection gate lines SGD1b and SGS1b. In addition, the row decoder 26b is connected to memory cell array 11_2b via selection gate lines SGD2b and SGS2b. That is, each memory cell array 11 does not share the selection gate lines SGD and SGS.

[0029] Word lines WLa and WLb are wiring used to control the memory cell transistors. Selection gate lines SGD1a, SGD1b, SGD2a, SGD2b, SGS1a, SGS1b, SGS2a, and SGS2b are wiring used to select the substring units, which will be described later.

[0030] The sense amplifier 27 is a circuit that performs data writing and reading. During a read operation, the sense amplifier 27 senses the data read from the corresponding memory cell array 11. During a write operation, the sense amplifier 27 supplies a voltage to the memory cell array 11 corresponding to the data to be written. In this embodiment, the sense amplifier 27a corresponds to memory cell arrays 11_1a and 11_2b. The sense amplifier 27b corresponds to memory cell arrays 11_1b and 11_2a.

[0031] The sense amplifier 27a is connected to memory cell arrays 11_1a and 11_2b in common via multiple bit lines BLa. In other words, memory cell array 11_1a and memory cell array 11_2b share bit lines BLa.

[0032] The sense amplifier 27b is connected to memory cell arrays 11_1b and 11_2a in common via multiple bit lines BLb. In other words, memory cell array 11_1b and memory cell array 11_2a share the bit line BLb.

[0033] The data register 28 is a register that temporarily stores data DAT. The data register 28 transmits and receives data DAT with an external controller. The data register 28 is connected to sense amplifiers 27a and 27b. The data register 28 includes multiple latch circuits. Each latch circuit temporarily stores data DAT (written data or read data).

[0034] The column decoder 29 is a circuit that decodes column addresses. The column decoder 29 is connected to the data register 28. Based on the result of decoding the column address, the column decoder 29 selects a latch circuit in the data register 28.

[0035] The source line driver 30 is a driver that supplies voltage to the source line SL of the memory cell array 11. The source line driver 30 is connected to the memory cell array 11_1a via source line SL1a. The source line driver 30 is connected to the memory cell array 11_1b via source line SL1b. The source line driver 30 is connected to the memory cell array 11_2a via source line SL2a. The source line driver 30 is connected to the memory cell array 11_2b via source line SL2b. In other words, each memory cell array 11 does not share a source line SL.

[0036] 1.1.2 Circuit Configuration of Memory Cell Arrays Next, with reference to Figures 2 to 4, an example of the circuit configuration of memory cell arrays 11_1a, 11_1b, 11_2a, and 11_2b will be described. Figure 2 is a circuit diagram showing an example of the circuit configuration of memory cell arrays 11_1a, 11_1b, 11_2a, and 11_2b. In the example shown in Figure 2, an example of the circuit configuration of block BLK0 and block BLK1 is shown. Figure 3 is a circuit diagram showing an example of the circuit configuration of block BLK0. That is, Figure 3 is a circuit diagram extracted from the circuit configuration shown in Figure 2, with subblock SBLK0_1 of memory cell array 11_1a and subblock SBLK0_2 of memory cell array 11_2a included. Figure 4 is a circuit diagram showing an example of the circuit configuration of block BLK1. In other words, Figure 4 is a circuit diagram in which the subblock SBLK1_1 of the memory cell array 11_1b and the subblock SBLK1_2 of the memory cell array 11_2b are extracted from the circuit configuration shown in Figure 2.

[0037] As shown in Figures 2 to 4, for example, block BLK0 includes subblocks SBLK0_1 and SBLK0_2. Block BLK1 includes subblocks SBLK1_1 and SBLK1_2. Each subblock SBLK includes multiple substring units SSU. A single string unit SU is formed by a combination of one substring unit SSU from each of the multiple array chips 10. That is, the string unit SU includes any one substring unit SSU from each of the array chips 10. The string unit SU is, for example, a collection of multiple NAND strings NS that are selected collectively during a write or read operation. A NAND string NS includes a collection of multiple memory cell transistors MC connected in series.

[0038] In the examples shown in Figures 2 to 4, each block BLK includes three string units SU0, SU1, and SU2. More specifically, each of the subblocks SBLK0_1 and SBLK1_1 includes substring units SSU0_1, SSU1_1, and SSU2_1. Each of the subblocks SBLK0_2 and SBLK1_2 includes substring units SSU0_2, SSU1_2, and SSU2_2.

[0039] As shown in Figure 3, the string unit SU0 of block BLK0 is composed of the substring unit SSU0_1 of subblock SBLK0_1 and the substring unit SSU0_2 of subblock SBLK0_2. That is, the string unit SU0 of block BLK0 includes the substring unit SSU0_1 of subblock SBLK0_1 and the substring unit SSU0_2 of subblock SBLK0_2. Similarly, the string unit SU1 of block BLK0 includes the substring unit SSU1_1 of subblock SBLK0_1 and the substring unit SSU1_2 of subblock SBLK0_2. The string unit SU2 of block BLK0 includes the substring unit SSU2_1 of subblock SBLK0_1 and the substring unit SSU2_2 of subblock SBLK0_2.

[0040] As shown in Figure 4, the string unit SU0 of block BLK1 includes the substring unit SSU0_1 of subblock SBLK1_1 and the substring unit SSU0_2 of subblock SBLK1_2. Similarly, the string unit SU1 of block BLK1 includes the substring unit SSU1_1 of subblock SBLK1_1 and the substring unit SSU1_2 of subblock SBLK1_2. The string unit SU2 of block BLK1 includes the substring unit SSU2_1 of subblock SBLK1_1 and the substring unit SSU2_2 of subblock SBLK1_2.

[0041] Hereinafter, when not limiting any string unit SU, it is denoted as the string unit SU. Also, when not limiting any substring unit SSU, it is denoted as the substring unit SSU. Note that the number of string units SU within the block BLK, that is, the number of substring units SSU within the sub-block SBLK is arbitrary.

[0042] The NAND string NS includes a plurality of memory cell transistors MC, as well as selection transistors ST1 and ST2. In the examples shown in FIGS. 2 to 4, the NAND string NS includes eight memory cell transistors MC0 to MC7. Note that the number of memory cell transistors MC within the NAND string NS is arbitrary.

[0043] The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or the FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductor layer for the charge storage layer.

[0044] The selection transistors ST1 and ST2 are used for the selection of the string unit SU (substring unit SSU) during various operations. The number of selection transistors ST1 and ST2 within the NAND string NS is arbitrary. The selection transistors ST1 and ST2 only need to be included one or more in the NAND string NS respectively.

[0045] The current paths of the memory cell transistors MC, as well as the selection transistors ST1 and ST2 within each NAND string NS are connected in series. In the examples shown in FIGS. 2 to 4, the selection transistor ST2, the memory cell transistors MC0 to MC7, and the selection transistor ST1 are connected in sequence. The drain (one end of the current path) of the selection transistor ST1 is connected to any bit line BL. The source (one end of the current path) of the selection transistor ST2 is connected to any source line SL.

[0046] The drains of multiple selection transistors ST1 within a string unit SU are each connected to different bit lines BL. That is, the drains of multiple selection transistors ST1 within a substring unit SSU are each connected to different bit lines BL. In the examples shown in Figures 2 to 4, the drains of the selection transistors ST1 of n+1 (where n is a non-negative integer) NAND strings NS within the substring unit SSU are each connected to n+1 bit lines BL. That is, the drains of the selection transistors ST1 of 2(n+1) NAND strings NS within a string unit SU are each connected to 2(n+1) bit lines BL. In addition, the drain of one selection transistor ST1 of each string unit SU within each block BLK is commonly connected to one bit line BL.

[0047] For example, the n+1 selection transistors ST1 of each substring unit SSU in memory cell array 11_1a and the n+1 selection transistors ST1 of each substring unit SSU in memory cell array 11_2b are commonly connected to n+1 bit lines BLa0 to BLa(n). For example, the drains of one selection transistor ST1 each in substring units SSU0_1 to SSU2_1 of subblock SBLK0_1 and substring units SSU0_2 to SSU2_2 of subblock SBLK1_2 are commonly connected to bit line BLa0. Similarly, the n+1 selection transistors ST1 of each substring unit SSU in memory cell array 11_1b and the n+1 selection transistors ST1 of each substring unit SSU in memory cell array 11_2a are commonly connected to n+1 bit lines BLb0 to BLb(n). For example, the drains of one selection transistor ST1 in each of the substring units SSU0_1 to SSU2_1 of subblock SBLK1_1 and SSU0_2 to SSU2_2 of subblock SBLK0_2 are commonly connected to the bit line BLb0.

[0048] The control gates of the plurality of memory cell transistors MC0 to MC7 included in the block BLK are commonly connected to the word lines WL0 to WL7, respectively. For example, the control gates of the plurality of memory cell transistors MC0 to MC7 included in one sub-block SBLK of the memory cell array 11_1a and one sub-block SBLK of the memory cell array 11_2a are commonly connected to the word lines WLa0 to WLa7, respectively. More specifically, the sub-blocks SBLK0_1 and SBLK0_2 of the block BLK0 each include a plurality of memory cell transistors MC0. The control gates of these plurality of memory cell transistors MC0 in the block BLK0 are commonly connected to one word line WLa0. The other memory cell transistors MC1 to MC7 included in the sub-blocks SBLK0_1 and SBLK0_2 are similarly commonly connected to the word lines WLa1 to WLa7, respectively. That is, the sub-block SBLK0_1 and the sub-block SBLK0_2 share the word line WLa. The same applies to the other sub-blocks SBLK of the memory cell arrays 11_1a and 11_2a.

[0049] Also, the control gates of the plurality of memory cell transistors MC0 to MC7 included in one sub-block SBLK of the memory cell array 11_1b and one sub-block SBLK of the memory cell array 11_2b are commonly connected to the word lines WLb0 to WLb7, respectively. More specifically, the sub-blocks SBLK1_1 and SBLK1_2 of the block BLK1 each include a plurality of memory cell transistors MC0. The control gates of these plurality of memory cell transistors MC0 in the block BLK1 are commonly connected to one word line WLb0. The other memory cell transistors MC1 to MC7 included in the sub-blocks SBLK1_1 and SBLK1_2 are similarly commonly connected to the word lines WLb1 to WLb7, respectively. That is, the sub-block SBLK1_1 and the sub-block SBLK1_2 share the word line WLb. The same applies to the other sub-blocks SBLK of the memory cell arrays 11_1b and 11_2b.

[0050] Each substring unit SSU is connected to a different selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 included in substring unit SSU0_1 of subblock SBLK0_1 are commonly connected to selection gate line SGD1a0. The gates of multiple selection transistors ST1 included in substring unit SSU1_1 of subblock SBLK0_1 are commonly connected to selection gate line SGD1a1. The gates of multiple selection transistors ST1 included in substring unit SSU2_1 of subblock SBLK0_1 are commonly connected to selection gate line SGD1a2. The gates of multiple selection transistors ST1 included in substring unit SSU0_2 of subblock SBLK0_2 are commonly connected to selection gate line SGD2a0. The gates of multiple selection transistors ST1 included in substring unit SSU1_2 of subblock SBLK0_2 are commonly connected to selection gate line SGD2a1. The gates of multiple selection transistors ST1 included in the substring unit SSU2_2 of subblock SBLK0_2 are commonly connected to the selection gate line SGD2a2. The gates of multiple selection transistors ST1 included in the substring unit SSU0_1 of subblock SBLK1_1 are commonly connected to the selection gate line SGD1b0. The gates of multiple selection transistors ST1 included in the substring unit SSU1_1 of subblock SBLK1_1 are commonly connected to the selection gate line SGD1b1. The gates of multiple selection transistors ST1 included in the substring unit SSU2_1 of subblock SBLK1_1 are commonly connected to the selection gate line SGD1b2. The gates of multiple selection transistors ST1 included in the substring unit SSU0_2 of subblock SBLK1_2 are commonly connected to the selection gate line SGD2b0. The gates of multiple selection transistors ST1 included in the substring unit SSU1_2 of subblock SBLK1_2 are commonly connected to the selection gate line SGD2b1. The gates of multiple selection transistors ST1 included in the substring unit SSU2_2 of subblock SBLK1_2 are commonly connected to the selection gate line SGD2b2.

[0051] For example, multiple substring units SSU contained in one subblock SBLK are commonly connected to a single selection gate line SGS. That is, multiple substring units SSU contained in one subblock SBLK share the selection gate line SGS. More specifically, the gates of multiple selection transistors ST2 contained in substring units SSU0_1, SSU1_1, and SSU2_1 of subblock SBLK0_1 are commonly connected to the selection gate line SGS1a. The gates of multiple selection transistors ST2 contained in substring units SSU0_2, SSU1_2, and SSU2_2 of subblock SBLK0_2 are commonly connected to the selection gate line SGS2a. The gates of multiple selection transistors ST2 contained in substring units SSU0_1, SSU1_1, and SSU2_1 of subblock SBLK1_1 are commonly connected to the selection gate line SGS1b. The gates of the multiple selection transistors ST2 included in the substring units SSU0_2, SSU1_2, and SSU2_2 of subblock SBLK1_2 are commonly connected to the selection gate line SGS2b. Note that, similar to the selection gate line SGD, a different selection gate line SGS may be provided for each substring unit SSU.

[0052] Multiple subblocks SBLK contained in one memory cell array 11 share a source line SL. That is, multiple substring units SSU contained in one subblock SBLK share a source line SL. More specifically, the sources of the multiple selection transistors ST2 contained in substring units SSU0_1, SSU1_1, and SSU2_1 of subblock SBLK0_1 are commonly connected to source line SL1a. The sources of the multiple selection transistors ST2 contained in substring units SSU0_2, SSU1_2, and SSU2_2 of subblock SBLK0_2 are commonly connected to source line SL2a. The sources of the multiple selection transistors ST2 contained in substring units SSU0_1, SSU1_1, and SSU2_1 of subblock SBLK1_1 are commonly connected to source line SL1b. The sources of the multiple selection transistors ST2 included in the substring units SSU0_2, SSU1_2, and SSU2_2 of subblock SBLK1_2 are commonly connected to the source line SL2b.

[0053] Hereinafter, a collection of multiple memory cell transistors MC connected to a single word line WL within a single string unit SU will be referred to as a "cell unit CU". In the example shown in Figure 3, a single cell unit CU is composed of multiple memory cell transistors MC7 contained in substring units SSU0_1 and SSU0_2.

[0054] For example, when a memory cell transistor (MC) stores 1 bit of data, the storage capacity of the cell unit (CU) is defined as "1 page of data". Based on the number of bits of data stored by the memory cell transistor (MC), the cell unit (CU) may have a storage capacity of 2 pages of data or more. Below, we will describe the case where the memory cell transistor (MC) is a TLC (Triple Level Cell) that stores 3 bits of data. Note that the number of bits of data that a memory cell transistor (MC) can store is arbitrary. For example, the memory cell transistor (MC) may be an SLC (Single Level Cell) that can store 1 bit (binary) data, or an MLC (Multi Level Cell) that can store 2 bits (quadrivalent) data. Furthermore, the memory cell transistor (MC) may be a QLC (Quad Level Cell) that can store 4 bits (16-value) data, or a PLC (Penta Level Cell) that can store 5 bits (32-value) data.

[0055] For example, during a write operation, data is written to a single cell unit CU all at once. That is, multiple memory cell transistors MC of two array chips 10, which are commonly connected to a single word line WL, are selected simultaneously. For example, during a write operation, if the row decoder 26a selects the word line WLa0 and the selection gate lines SGD1a0 and SGD2a0, the memory cell transistor MC0 of substring unit SSU0_1 and the memory cell transistor MC0 of substring unit SSU0_2 are selected all at once. At this time, a voltage is applied to the memory cell transistor MC0 of substring unit SSU0_1 from the sense amplifier 27a via the bit line BLa. A voltage is applied to the memory cell transistor MC0 of substring unit SSU0_2 from the sense amplifier 27b via the bit line BLb. As a result, the page data of the cell unit CU can be processed all at once during a write operation. The read operation is similar.

[0056] 1.1.3 Chip Arrangement Next, an example of the arrangement of each chip will be described with reference to Figure 5. Figure 5 is a cross-sectional view showing the arrangement of the circuit chip 20 and array chips 10_1 and 10_2. In the example shown in Figure 5, for the sake of simplicity, one word line WLa and WLb and one bit line BLa and BLb are shown for each. The selection gate lines SGD and SGS and the source line SL are omitted. Furthermore, in the circuit chip 20, the command register 23, address register 24, sequencer 25, data register 28, column decoder 29, and source line driver 30 are omitted.

[0057] Hereinafter, the direction approximately parallel to the surface of the circuit chip 20 will be referred to as the X direction. The direction intersecting the X direction and approximately parallel to the surface of the circuit chip 20 will be referred to as the Y direction. The direction intersecting the X and Y directions and approximately perpendicular to the surface of the circuit chip 20 will be referred to as the Z direction. To further define the Z direction, the direction from the array chip 10 toward the circuit chip 20 will be referred to as the Z1 direction, and the direction opposite to the Z1 direction will be referred to as the Z2 direction.

[0058] As shown in Figure 5, the semiconductor memory device 1 of this embodiment has a structure in which a circuit chip 20, an array chip 10_1, and an array chip 10_2 are bonded together (hereinafter also referred to as the "bonded structure"). More specifically, the array chip 10_1 is provided on the circuit chip 20 in the Z2 direction. The array chip 10_2 is provided on the array chip 10_1. The surfaces where the circuit chip 20 and the array chip 10_1 are in contact, and the surfaces where the array chip 10_1 and the array chip 10_2 are in contact are the bonding surfaces.

[0059] In the circuit chip 20, row decoders 26a and 26b, and sense amplifiers 27a and 27b are provided on the semiconductor substrate 200.

[0060] In the array chip 10_1, for example, memory cell arrays 11_1a and 11_1b are arranged side by side in the Y direction. For example, in the Z2 direction, memory cell array 11_1a is provided above the row decoder 26a and sense amplifier 27a. Also, for example, in the Z2 direction, memory cell array 11_1b is provided above the row decoder 26b and sense amplifier 27b.

[0061] In the array chip 10_2, for example, memory cell arrays 11_2a and 11_2b are arranged side by side in the Y direction. In the Z2 direction, memory cell array 11_2a is located above memory cell array 11_1a. In the Z2 direction, memory cell array 11_2b is located above memory cell array 11_1b. That is, memory cell arrays 11_1a and 11_2a are stacked in the Z direction. Similarly, memory cell arrays 11_1b and 11_2b are stacked in the Z direction.

[0062] One end of word line WLa is connected to row decoder 26a. Word line WLa is also commonly connected to memory cell arrays 11_1a and 11_2a, which are stacked in the Z direction. One end of word line WLb is connected to row decoder 26b. Word line WLb is also commonly connected to memory cell arrays 11_1b and 11_2b, which are stacked in the Z direction.

[0063] Bit line BLa is connected to sense amplifier 27a. Bit line BLa is also commonly connected to memory cell arrays 11_1a and 11_2b, which are located at different positions in the Z and Y directions. Bit line BLb is connected to sense amplifier 27b. Bit line BLb is also commonly connected to memory cell arrays 11_2a and 11_1b, which are located at different positions in the Z and Y directions. In other words, bit line BL is commonly connected to two memory cell arrays 11 that do not share word line WL and are located on different array chips 10.

[0064] 1.1.4 Arrangement of Memory Cell Arrays Next, an example of the arrangement of the memory cell array 11 will be described with reference to Figure 6. Figure 6 is a perspective view showing the arrangement of memory cell arrays 11_1a, 11_1b, 11_2a, and 11_2b, and the circuit chip 20. In the example of Figure 6, for the sake of simplicity, each memory cell array 11 is shown with one word line WLa and WLb, selection gate lines SGDa, SGDb, SGSa, and SGSb, and four bit lines BLa and BLb. The source line SL is omitted.

[0065] As shown in Figure 6, the memory cell array 11 includes a cell section and a WLSG connection section. The cell section is the region where the memory cell transistor MC is located. The WLSG connection section is the region where a plurality of contact plugs connected to the word line WL and the selection gate lines SGD and SGS are provided. For example, memory cell arrays 11_1a and 11_2a are commonly connected to the row decoder 26a of the circuit chip 20 via the word line WLa. Memory cell array 11_1a is connected to the row decoder 26a of the circuit chip 20 via the selection gate lines SGD1a and SGS1a. 11_2a is connected to the row decoder 26a of the circuit chip 20 via the selection gate lines SGD2a and SGS2a. In addition, memory cell arrays 11_1b and 11_2b are commonly connected to the row decoder 26b of the circuit chip 20 via the word line WLb. The memory cell array 11_1b is connected to the row decoder 26b of the circuit chip 20 via the selection gate lines SGD1b and SGS1b. 11_2b is connected to the row decoder 26b of the circuit chip 20 via the selection gate lines SGD2b and SGS2b.

[0066] BL connection sections are provided between memory cell array 11_1a and memory cell array 11_1b, and between memory cell array 11_2a and memory cell array 11_2b. The BL connection sections are connection areas for connecting the bit lines BL provided on array chips 10_1 and 10_2 to each other. More specifically, for example, each memory cell array 11 has a cell portion provided with a plurality of bit lines BL extending in the Y direction. At the BL connection section, the bit line BLa of memory cell array 11_1a and the bit line BLa of memory cell array 11_2b are connected. The bit line BLa of memory cell array 11_1a extends from the cell portion in the Z direction and is connected to the sense amplifier 27a of the circuit chip 20. Also, at the BL connection section, the bit line BLb of memory cell array 11_2a and the bit line BLb of memory cell array 11_1b are connected. Then, the bit line BLb of the memory cell array 11_1b extends from the cell portion in the Z direction and is connected to the sense amplifier 27b of the circuit chip 20.

[0067] In the example shown in Figure 6, for example, a connection portion to the sense amplifier 27a is provided in the middle of the bit line BLa near the central part of the cell portion of the memory cell array 11_1a, but this is not limited to this. For example, a connection portion may be provided at the end of the bit line BLa. Also, the connection portions of each bit line BLa do not have to be arranged in the X direction. The same applies to the bit line BLb.

[0068] 1.1.5 Configuration of Sense Amplifier and Data Register Next, an example of the configuration of the sense amplifier 27 and data register 28 will be described with reference to Figure 7. Figure 7 is a block diagram showing an example of the sense amplifier 27 and data register 28. Figure 7 shows the sense amplifier 27a and the memory cell arrays 11_1a and 11_2b connected thereto. The sense amplifier 27b has a similar configuration.

[0069] As shown in Figure 7, the sense amplifier 27a includes a plurality of sense amplifier units SAU provided for each bit line BLa. More specifically, the sense amplifier 27a includes n+1 sense amplifier units SAU corresponding to n+1 bit lines BLa0 to BLa(n).

[0070] The data register 28 includes, for example, a plurality of latch circuits XDL provided for each sense amplifier unit SAU. The latch circuits XDL temporarily store read data and write data. The latch circuits XDL are used for data input and output between the external controller and the sense amplifier unit SAU. Each latch circuit XDL is connected to the corresponding sense amplifier unit SAU via the bus DBUS. Note that multiple sense amplifier units SAU may be connected to a single latch circuit XDL.

[0071] Next, the internal configuration of the sense amplifier unit SAU will be described. The sense amplifier unit SAU includes, for example, a sense circuit SA, latch circuits SDL, ADL, BDL, CDL, and TDL. The sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL, and TDL are all connected to the bus LBUS. In other words, the latch circuit XDL, the sense circuit SA, and the latch circuits SDL, ADL, BDL, CDL, and TDL are connected to each other so that they can send and receive data.

[0072] During a read operation, the sense circuit SA senses the data read onto the corresponding bit line BL and determines whether the read data is a "0" or a "1". During a write operation, the sense circuit SA applies a voltage to the bit line BL based on the data stored in one of the latch circuits SDL, ADL, BDL, CDL, and TDL.

[0073] The latch circuits SDL, ADL, BDL, CDL, and TDL temporarily store read and write data. For example, during a read operation, data may be transferred from the sense circuit SA to one of the latch circuits SDL, ADL, BDL, CDL, and TDL. Similarly, during a write operation, data may be transferred from the latch circuit XDL to one of the latch circuits SDL, ADL, BDL, CDL, and TDL.

[0074] The configuration of the sense amplifier unit (SAU) is not limited to this and can be modified in various ways. For example, the number of latch circuits in the sense amplifier unit (SAU) can be designed based on the number of data bits that a single memory cell transistor (MC) can store.

[0075] 1.1.6 Circuit Configuration of Sense Amplifier Unit Next, an example of the circuit configuration of the sense amplifier unit SAU will be described with reference to Figure 8. Figure 8 is a circuit diagram showing an example of the circuit configuration of the sense amplifier unit SAU. Figure 8 shows the circuit configuration of the sense amplifier unit SAU of sense amplifier 27a connected to the bit line BLa. The sense amplifier unit SAU of sense amplifier 27b has a similar configuration. The sense amplifier unit SAU of this embodiment senses the current flowing from node SEN to bit line BL. In the example shown in Figure 8, for the sake of simplicity, the latch circuits ADL, BDL, and CDL are shown in a single common circuit diagram. The circuit configurations of the latch circuits ADL, BDL, and CDL are the same as those of the latch circuits SDL and TDL. In the following description, one of the source or drain of a transistor will be referred to as "one end of the transistor," and the other of the source or drain will be referred to as "the other end of the transistor."

[0076] As shown in Figure 8, the sense amplifier unit SAU includes a BL hookup circuit BLHU, a sense circuit SA, latch circuits SDL, ADL, BDL, CDL, and TDL, an LBUS precharge circuit LBPC, and a DBUS switch circuit DBSW.

[0077] The BL hookup circuit BLHU is a circuit that connects the bit line BL and the sense circuit SA. The bit line BLa is connected to the BL hookup circuit BLHU of the sense amplifier 27a.

[0078] The LBUS precharge circuit (LBPC) is a charging circuit for the LBUS bus.

[0079] The DBUS switch circuit (DBSW) is a circuit that connects the sense amplifier unit (SAU) to the bus DBUS.

[0080] 1.1.6.1 Configuration of the BL Hook-up Circuit First, the configuration of the BL hook-up circuit BLHU will be described. The BL hook-up circuit BLHU includes high-voltage n-channel MOS transistors THN1 and THN2.

[0081] One end of transistor THN1 is connected to the bit line BLa. The other end of transistor THN1 is connected to node BLBIAS. A bias voltage is applied to node BLBIAS. The signal BIAS is input to the gate of transistor THN1. Signal BIAS is a signal that controls the electrical connection between bit line BLa and node BLBIAS. When bit line BLa and node BLBIAS are electrically connected, a high ("H") level voltage is applied to signal BIAS, which turns transistor THN1 ON.

[0082] One end of transistor THN2 is connected to the bit line BLa. The other end of transistor THN2 is connected to the sense circuit SA. The signal BLS is input to the gate of transistor THN2. Signal BLS is a signal that controls the electrical connection between the bit line BLa and the sense circuit SA. When the bit line BLa and the sense circuit SA are electrically connected, a high-level voltage is applied to signal BLS, which turns on transistor THN2.

[0083] For example, during read and write operations, if bit line BLa is selected, transistor THN1 is set to the off state and transistor THN2 is set to the on state. Conversely, if bit line BLa is not selected, transistor THN1 is set to the on state and transistor THN2 is set to the off state.

[0084] For example, the BL hookup circuit BLHU receives the signals BIAS and BLS from the sequencer 25.

[0085] 1.1.6.2 Sense Circuit Configuration Next, the configuration of the sense circuit SA will be described. The sense circuit SA includes a low-voltage p-channel MOS transistor TP1, low-voltage n-channel MOS transistors TN1 to TN11, and a capacitive element CA.

[0086] A voltage VDDSA is applied to one end of transistor TP1. Voltage VDDSA is the power supply voltage of the sense circuit SA. The other end of transistor TP1 is connected to node ND1. The gate of transistor TP1 is connected to node INV_S. Node INV_S is a node in the latch circuit SDL that can store data (inverted data). When node INV_S is at the Low ("L") level, transistor TP1 is turned ON.

[0087] One end of transistor TN1 is connected to node ND1. The other end of transistor TN1 is connected to node SRCGND. A ground voltage, such as VSS, is applied to node SRCGND. The gate of transistor TN1 is connected to node INV_S. When node INV_S is at the "H" level, transistor TN1 is turned ON. Therefore, based on the logic level of node INV_S, one of transistors TP1 and TN1 is turned ON, and the other is turned OFF. In other words, based on the data stored in the latch circuit SDL, the voltage VDDSA or the voltage of node SRCGND may be applied to node ND1.

[0088] One end of transistor TN2 is connected to node ND1. The other end of transistor TN2 is connected to node SCOM. The signal BLX is input to the gate of transistor TN2. Transistor TN2 is turned ON when the signal BLX is at the "H" level.

[0089] One end of transistor TN3 is connected to the BL hookup circuit BLHU. The other end of transistor TN3 is connected to node SCOM. The signal BLC is input to the gate of transistor TN3. Transistor TN3 can function as a clamp transistor, clamping the voltage applied to the BL hookup circuit BLHU (bit line BL) based on the voltage of the signal BLC.

[0090] One end of transistor TN4 is connected to node SCOM. The other end of transistor TN4 is connected to node SEN. Signal XXL is input to the gate of transistor TN4. Transistor TN4 is turned ON when signal XXL is at the "H" level.

[0091] One end of transistor TN5 is connected to node SCOM. The other end of transistor TN5 is connected to node SRCGND. The signal NLO is input to the gate of transistor TN5. Transistor TN5 is turned ON when the signal NLO is at the "H" level.

[0092] A voltage VDDSA is applied to one end of transistor TN6. The other end of transistor TN6 is connected to node SEN. A signal SPC is input to the gate of transistor TN6. When signal SPC is at a high level, transistor TN6 is turned ON. For example, transistor TN6 is used to charge node SEN.

[0093] One end of transistor TN7 is connected to node SEN. The other end of transistor TN7 is connected to bus LBUS. The signal BLQ is input to the gate of transistor TN7. Transistor TN7 is turned ON when signal BLQ is at the "H" level. Transistor TN7 is turned ON when bus LBUS and node SEN are electrically connected.

[0094] One end of transistor TN8 is connected to the bus LBUS. The other end of transistor TN8 is connected to one end of transistor TN9. The signal STB is input to the gate of transistor TN8. When signal STB is asserted, the sense circuit SA determines the voltage of node SEN. That is, the sense circuit SA determines the data stored in the selected memory cell transistor MC. More specifically, transistor TN8 is turned ON when a "H" level signal STB is input. During this time, if transistor TN9 is ON, the bus LBUS is discharged through transistors TN8 and TN9. Also, if transistor TN9 is OFF, the bus LBUS is not discharged through transistors TN8 and TN9. The data based on the bus LBUS voltage is stored in one of the latch circuits SDL, ADL, BDL, CDL, and TDL that share the bus LBUS.

[0095] A clock signal CLK is input to the other end of transistor TN9. The gate of transistor TN9 is connected to node SEN. Transistor TN9 functions as a sense transistor that senses the voltage of node SEN. For example, if the voltage of node SEN is greater than or equal to the threshold voltage of transistor TN9, transistor TN9 is turned ON. Conversely, if the voltage of node SEN is less than the threshold voltage of transistor TN9, transistor TN9 is turned OFF.

[0096] One electrode of the capacitive element CA is connected to node SEN. The other electrode of the capacitive element CA is input to the clock signal CLK.

[0097] One end of transistor TN10 is connected to node SEN. The other end of transistor TN10 is connected to one end of transistor TN11. The signal LSL is input to the gate of transistor TN10. Transistor TN10 is turned ON when the signal LSL is at the "H" level.

[0098] A voltage VSS is applied to the other end of transistor TN11. The gate of transistor TN11 is connected to bus LBUS.

[0099] For example, the sense circuit SA receives signals BLX, BLC, XXL, NLO, SPC, BLQ, STB, and LSL from the sequencer 25.

[0100] 1.1.6.3 Configuration of the latch circuit SDL Next, the configuration of the latch circuit SDL will be described. The latch circuit SDL includes low-voltage p-channel MOS transistors TP21 to TP24 and low-voltage n-channel MOS transistors TN21 to TN24.

[0101] A voltage VDDSA is applied to one end of transistor TP21. The other end of transistor TP21 is connected to one end of transistor TP22. The signal SLL is input to the gate of transistor TP21.

[0102] The other end of transistor TP22 is connected to one end of transistor TN22. The gate of transistor TP22 is connected to node INV_S.

[0103] A voltage VDDSA is applied to one end of transistor TP23. The other end of transistor TP23 is connected to one end of transistor TP24. The signal SLI is input to the gate of transistor TP23.

[0104] The other end of transistor TP24 is connected to one end of transistor TN23. The gate of transistor TP24 is connected to node LAT_S.

[0105] One end of transistor TN21 is connected to node LAT_S. The other end of transistor TN21 is connected to bus LBUS. The signal STL is input to the gate of transistor TN21.

[0106] The other end of transistor TN22 is grounded (ground voltage VSS is applied). The gate of transistor TN22 is connected to node INV_S.

[0107] The other end of transistor TN23 is grounded. The gate of transistor TN23 is connected to node LAT_S.

[0108] One end of transistor TN24 is connected to node INV_S. The other end of transistor TN24 is connected to bus LBUS. The signal STI is input to the gate of transistor TN24.

[0109] The latch circuit SDL stores data at node LAT_S. Furthermore, the latch circuit SDL stores the inverted data of the data stored at node LAT_S at node INV_S. For example, if the latch circuit SDL stores the data "1", a "L" level voltage (voltage VSS) is applied to node INV_S. If the latch circuit SDL stores the data "0", a "H" level voltage (voltage VDDSA) is applied to node INV_S.

[0110] For example, the latch circuit SDL receives signals SLL, SLI, STL, and STI from the sequencer 25.

[0111] 1.1.6.4 Configuration of the latch circuit TDL Next, the configuration of the latch circuit TDL will be described. The latch circuit TDL includes low-voltage p-channel MOS transistors TP31 to TP34 and low-voltage n-channel MOS transistors TN31 to TN34.

[0112] A voltage VDDSA is applied to one end of transistor TP31. The other end of transistor TP31 is connected to one end of transistor TP32. The signal TLL is input to the gate of transistor TP31.

[0113] The other end of transistor TP32 is connected to one end of transistor TN32. The gate of transistor TP32 is connected to node INV_T.

[0114] A voltage VDDSA is applied to one end of transistor TP33. The other end of transistor TP33 is connected to one end of transistor TP34. The signal TLI is input to the gate of transistor TP33.

[0115] The other end of transistor TP34 is connected to one end of transistor TN33. The gate of transistor TP34 is connected to node LAT_T.

[0116] One end of transistor TN31 is connected to node LAT_T. The other end of transistor TN31 is connected to bus LBUS. The signal TTL is input to the gate of transistor TN31.

[0117] The other end of transistor TN32 is grounded (ground voltage VSS is applied). The gate of transistor TN32 is connected to node INV_T.

[0118] The other end of transistor TN33 is grounded. The gate of transistor TN33 is connected to node LAT_T.

[0119] One end of transistor TN34 is connected to node INV_T. The other end of transistor TN34 is connected to bus LBUS. The signal TTI is input to the gate of transistor TN34.

[0120] The latch circuit TDL stores data at node LAT_T. Furthermore, the latch circuit TDL stores the inverted data of the data stored at node LAT_T at node INV_T. For example, if the latch circuit TDL stores the data "1", a "L" level voltage (voltage VSS) is applied to node INV_T. If the latch circuit TDL stores the data "0", a "H" level voltage (voltage VDDSA) is applied to node INV_T.

[0121] For example, the latch circuit TDL receives signals TLL, TLI, TTL, and TTI from the sequencer 25.

[0122] 1.1.6.5 Configuration of Latch Circuits ADL, BDL, and CDL Next, the configuration of latch circuits ADL, BDL, and CDL will be briefly explained. The configuration of latch circuits ADL, BDL, and CDL is the same as that of latch circuits SDL and TDL. For example, in the case of latch circuit ADL, the latch circuit ADL is configured by writing "A" in place of *, in the case of latch circuit ADL, the latch circuit ADL is configured by writing "A" in place of *, in the case of latch circuit BDL, the latch circuit ADL is configured by writing "B" in place of *, in the case of latch circuit CDL, the latch circuit ADL is configured by writing "A" in place of *, in the case of latch circuit BDL, the latch circuit ADL is configured by writing "B" in place of *, in the case of latch circuit CDL, the latch circuit ADL is configured by writing "C" in place of *, in the case of latch circuit CDL

[0123] 1.1.6.6 Configuration of the LBUS Precharge Circuit Next, the LBUS precharge circuit LBPC will be described. The LBUS precharge circuit LBPC is a charging circuit for the bus LBUS. The LBUS precharge circuit LBPC includes a low-voltage n-channel MOS transistor TN41. A voltage VDDSA is applied to one end of the transistor TN41. The other end of the transistor TN41 is connected to the bus LBUS. A signal LPC is input to the gate of the transistor TN41. The LBUS precharge circuit LBPC precharges the bus LBUS before transferring the sense result of the sense circuit SA to the bus LBUS in a read operation, for example.

[0124] For example, the LBUS precharge circuit LBPC receives the signal LPC from the sequencer 25.

[0125] 1.1.6.7 Configuration of the DBUS Switch Circuit Next, the DBUS switch circuit DBSW will be described. The DBUS switch circuit DBSW is a circuit that connects the sense amplifier unit SAU and the bus DBUS. In other words, the DBUS switch circuit DBSW connects the sense amplifier unit SAU and the latch circuit XDL. The DBUS switch circuit DBSW includes a low-voltage n-channel MOS transistor TN42. One end of the transistor TN42 is connected to the bus LBUS. The other end of the transistor TN42 is connected to the bus DBUS. The signal DSW is input to the gate of the transistor TN42.

[0126] For example, the DBUS switch circuit DBSW receives the signal DSW from the sequencer 25.

[0127] 1.2 Threshold Voltage Distribution of Memory Cell Transistors Next, an example of the possible threshold voltage distribution of a memory cell transistor MC will be described with reference to Figure 9. Figure 9 shows the threshold voltage distribution and data allocation when the memory cell transistor MC is TLC.

[0128] As shown in Figure 9, when the memory cell transistor MC is TLC, the threshold voltage of each memory cell transistor MC takes a value that falls within one of eight discrete distributions. Hereinafter, these eight distributions will be denoted as the “Er” state, “A” state, “B” state, “C” state, “D” state, “E” state, “F” state, and “G state,” respectively, in order of increasing threshold voltage.

[0129] The "Er" state corresponds to, for example, the data erasure state. The "A" to "G" states correspond to the state in which charge has been injected into the charge storage layer and data has been written. In the write operation, the verify voltages corresponding to each threshold voltage distribution are VA to VG. Then, these voltage values ​​have the relationship VA < VB < VC < VD < VE < VF < VG < VREAD. Voltage VREAD is the voltage applied to the non-selected word line WL during the read operation. When the voltage VREAD is applied to the gate of the memory cell transistor MC, it is turned ON regardless of the data it stores.

[0130] More specifically, the threshold voltage included in the "Er" state is less than voltage VA. The threshold voltage included in the "A" state is greater than or equal to voltage VA and less than voltage VB. The threshold voltage included in the "B" state is greater than or equal to voltage VB and less than voltage VC. The threshold voltage included in the "C" state is greater than or equal to voltage VC and less than voltage VD. The threshold voltage included in the "D" state is greater than or equal to voltage VD and less than voltage VE. The threshold voltage included in the "E" state is greater than or equal to voltage VE and less than voltage VF. The threshold voltage included in the "F" state is greater than or equal to voltage VF and less than voltage VG. And the threshold voltage included in the "G" state is greater than or equal to voltage VG and less than voltage VREAD.

[0131] Note that the verification voltage setting and the read voltage setting for each state may be the same or different. For simplicity, the following explanation will focus on the case where the verification voltage and read voltage have the same setting.

[0132] Hereinafter, the read operations corresponding to states "A" to "G" will be referred to as AR read operation, BR read operation, CR read operation, DR read operation, ER read operation, FR read operation, and GR read operation, respectively. The AR read operation determines whether the threshold voltage of the memory cell transistor MC is less than voltage VA. The BR read operation determines whether the threshold voltage of the memory cell transistor MC is less than voltage VB. The CR read operation determines whether the threshold voltage of the memory cell transistor MC is less than voltage VC. The same applies hereafter.

[0133] As described above, each memory cell transistor MC can take on eight different states by having one of eight threshold voltage distributions. By assigning these states to the binary representations "000" to "111", each memory cell transistor MC can hold three bits of data. Hereafter, these three bits of data will be referred to as the lower bit, middle bit, and upper bit. Furthermore, the set of lower bits that are written (or read) collectively to (or read from) the cell unit CU will be referred to as the lower page, the set of middle bits as the middle page, and the set of upper bits as the upper page.

[0134] In the example shown in Figure 9, data is assigned to the “higher bit / middle bit / lower bit” of the memory cell transistor MC included in each threshold voltage distribution as follows: “Er” state: “111” data “A” state: “110” data “B” state: “100” data “C” state: “000” data “D” state: “010” data “E” state: “011” data “F” state: “001” data “G” state: “101” data

[0135] When reading data allocated in this manner, the lower bits are determined by the AR and ER read operations. The middle bits are determined by the BR, DR, and FR read operations. The upper bits are determined by the CR and GR read operations. In other words, the values ​​of the lower, middle, and upper bits are determined by two, three, and two read operations, respectively. Hereafter, this data allocation will be referred to as the "2-3-2 code". Note that the data allocation to the "Er" to "G" states is not limited to the 2-3-2 code.

[0136] 1.3 Writing Operation Next, the writing operation will be described. The writing operation includes program operation and program verification operation.

[0137] Program operation is the process of increasing the threshold voltage by injecting electrons into the charge storage layer of a memory cell transistor (MC) (or maintaining the threshold voltage by hardly injecting any electrons into the charge storage layer). In program operation, based on the write data stored in the sense amplifier unit (SAU), the memory cell transistors (MC) are set to be programmable or program-unprogrammable. Programmable memory cell transistors (MC) are those that increase the threshold voltage. Program-unprogrammable memory cell transistors (MC) are those that maintain the threshold voltage. For example, if the write data is "0", the memory cell transistors (MC) are set to be programmable. If the write data is "1", the memory cell transistors (MC) are set to be program-unprogrammable. Among the memory cell transistors (MC) corresponding to "0" data, those that have not reached the threshold voltage of the write target state are set to be programmable. Also, memory cell transistors (MC) that have reached the threshold voltage of the write target state are set to be program-unprogrammable.

[0138] The program verification operation is performed after the program operation, by reading the data and determining whether the threshold voltage of the memory cell transistor MC has reached the target level (the state targeted for writing). Hereafter, if the threshold voltage of the memory cell transistor MC has reached the target level, it will be described as "verification passed," and if it has not reached the target level, it will be described as "verification failed." More specifically, for example, in the program verification operation, if the number of fail bits in the read data is greater than or equal to a preset reference value, it will be determined that "verification failed."

[0139] By repeatedly performing a combination of programmed operation and programmed verification operation (hereinafter referred to as the "program loop"), the threshold voltage of the memory cell transistor MC is raised to the target level. When the program loop is repeated, the programmed voltage in the programmed operation is stepped up.

[0140] 1.3.1 Writing Order First, an example of the data writing order in a NAND string NS will be explained with reference to Figure 10. Figure 10 is a diagram showing an example of the data writing order in a NAND string NS.

[0141] As shown in Figure 10, when a write operation is performed, the memory cell transistors MC on the bit line BL are selected as the write targets in order. Alternatively, the memory cell transistors MC on the source line SL may be selected as the write targets in order.

[0142] In the example shown in Figure 10, the PLC 25 first selects word line WL7. Then, the PLC 25 sequentially selects word lines WL6 to WL1, and finally selects word line WL0. In other words, the PLC 25 first selects memory cell transistor MC7. Then, the PLC 25 sequentially selects memory cell transistors MC6 to MC1, and finally selects memory cell transistor MC0.

[0143] 1.3.2 Details of Program Operation Next, the details of the program operation will be explained with reference to Figure 11. Figure 11 is a threshold voltage distribution diagram showing an example of the relationship between two types of verify voltages that may be used for each write state in a write operation and two types of program conditions. The example shown in Figure 11 shows the case when a memory cell transistor MC is written from the “Er” state to the “A” state.

[0144] As shown in Figure 11, for each write state, the verify low voltage VL and verify high voltage VH used for program verification are set. That is, the program verification operation includes a verification operation using the verify low voltage VL (hereinafter referred to as the "first verification operation") and a verification operation using the verify high voltage VH (hereinafter referred to as the "second verification operation"). For example, the verify high voltage VH corresponding to state "A" is the voltage VA explained using Figure 9. The relationship between the verify low voltage VL and the verify high voltage VH is VL < VH.

[0145] The verify low voltage VL is a voltage used to determine the magnitude of the difference between the target level and the threshold voltage of the memory cell transistor MC.

[0146] The sequencer 25 performs a first verification operation and a second verification operation in the program verification operation of each program loop. Based on the results of the first verification operation and the second verification operation, the sequencer 25 determines the conditions for the program operation of the next program loop.

[0147] More specifically, the program operation includes two program conditions PG0 and PG1, as well as a program prohibition condition. For example, if the threshold voltage of the memory cell transistor MC is less than or equal to the voltage VL, the sequencer 25 applies program condition PG0 in the next program loop's program operation. In other words, for memory cell transistor MC that has failed VL verification, a program operation with program condition PG0 applied (hereinafter referred to as "PG0 program operation") is executed.

[0148] Furthermore, if the threshold voltage of the memory cell transistor MC exceeds voltage VL and is less than or equal to voltage VH, the sequencer 25 applies program condition PG1 in the next program operation of the program loop. In other words, for memory cell transistor MC that has passed VL verification and failed VH verification, a program operation with program condition PG1 applied (hereinafter referred to as "PG1 program operation") is executed.

[0149] Furthermore, if the threshold voltage of the memory cell transistor MC exceeds the voltage VH, the sequencer 25 sets the memory cell transistor MC to be disabled for programming in the next program loop.

[0150] Program condition PG0 is a program condition in which the fluctuation amount of the threshold voltage of the memory cell transistor MC is relatively large. Program condition PG1 is a program condition in which the fluctuation amount of the threshold voltage of the memory cell transistor MC is smaller than that of program condition PG0. For example, when applying program condition PG0, program condition PG1, or program prohibition condition to the program operation of a single memory cell transistor MC, the fluctuation amount of the threshold voltage of the memory cell transistor MC follows the relationship "program condition PG0" > "program condition PG1" > "program prohibition". For example, if the threshold voltage of the memory cell transistor MC is above voltage VL and below voltage VH, executing the PG0 program operation may cause the threshold voltage of the memory cell transistor MC to exceed voltage VH by a relatively large amount. Therefore, in this case, the PG1 program operation is executed.

[0151] The sequencer 25 may apply the program condition PG1 in the last of the multiple program operations performed for a single write state. In other words, the memory cell transistor MC on which the PG1 program operation was performed is set to program-prohibited in subsequent program loops.

[0152] The voltage across bit line BL differs depending on the program condition PG0 and program condition PG1. For example, the voltage VSS is applied to bit line BL corresponding to program condition PG0. The voltage VQPW is applied to bit line BL corresponding to program condition PG1. The voltage VBLPG is applied to bit line BL corresponding to program disable. The voltages VSS, VQPW, and VBLPG have the relationship VSS < VQPW < VBLPG.

[0153] 1.3.3 Relationship between Verify Low Voltage, Verify High Voltage and Sense Time Next, an example of the relationship between the verify low voltage VL, verify high voltage VH and sense time will be explained with reference to Figure 12. Figure 12 is a graph showing an example of the relationship between the voltage of node SEN and sense time in program verification operation.

[0154] As shown in Figure 12, in this embodiment, in the program verification operation for one state, the sense time length of node SEN corresponding to the verify low voltage VL is different from the sense time length of node SEN corresponding to the verify high voltage VH. That is, the sense time length for setting signal XLL to "H" level is different between the first verification operation and the second verification operation. Hereinafter, the sense time corresponding to the first verification operation will be denoted as "first sense time Ts1". The sense time corresponding to the second verification operation will be denoted as "second sense time Ts2". The relationship between the first sense time Ts1 and the second sense time Ts2 is Ts1 < Ts2.

[0155] For example, when charge from node SEN is transferred to bit line BL during sense time, the voltage at node SEN decreases. The rate at which the voltage at node SEN decreases depends on the threshold voltage Vt of the memory cell transistor MC. For example, if the threshold voltage Vt is less than the verify low voltage VL (Vt < VL), the memory cell transistor MC enters a strongly ON state, and the voltage at node SEN decreases rapidly. If the threshold voltage Vt is greater than or equal to the verify low voltage VL and less than the verify high voltage VH (VL ≤ Vt < VH), the memory cell transistor MC enters a weaker ON state than in the case of Vt < VL, and the voltage at node SEN decreases relatively slowly. Also, if the threshold voltage Vt is greater than or equal to the verify high voltage VH (Vt ≥ VH), the memory cell transistor MC enters an OFF state, and the voltage at node SEN hardly decreases at all.

[0156] Based on this relationship, the sense time is set so that a memory cell transistor MC with a threshold voltage Vt below the target level is determined to have failed verification. That is, the transistor TN9 is set to the off state. More specifically, the first sense time is set so that a memory cell transistor MC with a threshold voltage Vt below the verify low voltage VL is determined to have failed verification. The second sense time is set so that a memory cell transistor MC with a threshold voltage Vt below the verify high voltage VH is determined to have failed verification.

[0157] In a program verification operation, when the first and second verification operations are performed consecutively, the time for the first sense operation may be set to Ts1, and the time for the second sense operation may be set to (Ts2 - Ts1).

[0158] 1.3.4 Specific Examples of the Relationship Between Program Loops and Array Chip Writing Characteristics Next, with reference to Figure 13, specific examples of the relationship between program loops and the writing characteristics of the array chip 10 will be described. Figure 13 is a diagram showing a specific example of the relationship between program loops and the writing characteristics of the array chip 10. The table shown in Figure 13 shows the relationship between the number of program loops and the write state to be programmed for verification assigned to the program loop. White circles are indicated in the parts where program verification operation is set. The program voltage is stepped up as the number of program loops increases.

[0159] For example, due to variations in the manufacturing process, the write characteristics of the memory cell transistors MC may vary from one array chip 10 to another. Figure 13(a) shows a specific example of a program loop in an array chip 10 with a relatively low initial value of the program voltage at which it becomes writable (hereinafter referred to as the "fast write array chip 10"). Figure 13(b) shows a specific example of a program loop in an array chip 10 with a relatively high initial value of the program voltage at which it becomes writable (hereinafter referred to as the "slow write array chip 10").

[0160] As shown in Figure 13, for example, in the case of a fast write array chip 10, the write operation ends when the program voltage corresponding to the 12th program loop is applied to the memory cell transistor MC. In contrast, in the case of a slow write array chip 10, the write operation ends when the program voltage corresponding to the 13th program loop is applied to the memory cell transistor MC. For example, if a semiconductor memory device includes one array chip 10, by setting the initial value of the program voltage corresponding to the second program loop for the slow write array chip 10, the effective number of program loops can be made the same as for a fast write array chip 10, which is 12. If a semiconductor memory device includes one array chip 10, by setting the initial value of the program voltage according to the write characteristics of the array chip 10, the variation in the number of program loop executions for each semiconductor memory device can be reduced. In other words, the variation in the processing time of the write operation can be suppressed.

[0161] In contrast, when a semiconductor memory device includes multiple array chips 10 and the array chips 10 share a word line WL, the same program voltage is applied to each array chip 10. Therefore, it is not possible to set an initial value for the program voltage that corresponds to variations in the writing characteristics of the array chips 10.

[0162] Therefore, in this embodiment, a relatively high initial value for the program voltage is set to match the slower write array chip 10 (memory cell array 11). Then, for the faster write array chip 10 (memory cell array 11), the write speed is reduced or the write time is shortened by adjusting the voltage of the bit line BL, selection gate lines SGD and SGS, or source line SL that are not shared among the memory cell arrays 11. This suppresses variations in the write characteristics between the array chips 10.

[0163] 1.3.5 Program Operation Timing Chart Next, four examples of program operation timing charts will be described. The following description will focus on the case where writing to array chip 10_2 (i.e., memory cell arrays 11_2a and 11_2b) is faster than writing to array chip 10_1 (i.e., memory cell arrays 11_1a and 11_1b). In this embodiment, the voltage application conditions to each wiring differ for each array chip 10 during program operation. That is, during program operation, at least one voltage of the bit line BL, the selection gate line SGD, and the selection gate line SGS differs for each array chip 10.

[0164] 1.3.5.1 Timing Chart of the First Example of Program Operation First, the timing chart of the first example of program operation will be described with reference to Figures 14 and 15. In the first example of program operation, the case in which variations in the write characteristics between array chips 10 are suppressed by the voltage of the bit line BL will be described. Figure 14 is a timing chart showing the voltage of each wiring in the first example of program operation. Figure 15 is a diagram showing the voltage applied to the NAND string NS during the period from time t2 to t3 in the timing chart shown in Figure 14. The examples shown in Figures 14 and 15 show the case in which data is written to block BLK0, that is, subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a). Furthermore, the examples shown in Figures 14 and 15 illustrate a case where, within the same cell unit CU, relatively slow-writing memory cell transistors MC are included in memory cell array 11_1a (array chip 10_1), and relatively fast-writing memory cell transistors MC are included in memory cell array 11_2a (array chip 10_2).

[0165] In the following description, the memory cell transistor MC included in the target cell unit CU will be referred to as the "selected memory cell transistor MC". The word line WL connected to the selected memory cell transistor MC will be referred to as the "selected word line WL_sel". The unselected word line WL will be referred to as the "unselected word line WL_usel". The string unit SU containing the target cell unit CU will be referred to as the "selected string unit SU_sel". The unselected string unit SU will also be referred to as the "unselected string unit SU_usel".

[0166] As shown in Figure 14, the word line WL and bit line BL are raised during the period from time t0 to t1. That is, the word line WLa and the bit lines BLa and BLb are charged during the period from time t0 to t1.

[0167] At time t0, the row decoder 26a applies the voltage VPRE to each word line WLa of the selected block BLK (block BLK0). The voltage VPRE is higher than the ground voltage VSS. When the voltage VPRE is applied to the gate of the memory cell transistor MC, it is turned ON regardless of the data it stores. The row decoder 26a applies the voltage VSGDoff to the selected gate lines SGD1a and SGD2a. The voltage VSGDoff is higher than the voltage VSS. The selected transistor ST1 to which the voltage VSGDoff is applied is turned OFF. The row decoder 26a also applies the voltage VSGSon to the selected gate lines SGS1a and SGS2a. The voltage VSGSon is higher than the voltage VSS. The selected transistor ST2 to which the voltage VSGSon is applied is turned ON.

[0168] The source line driver 30 applies a voltage VSRC to source lines SL1a and SL2a. The voltage VSRC is higher than the voltage VSS and lower than the voltage VSGSon.

[0169] The sense amplifier 27a is connected to the relatively slow-writing subblock SBLK0_1 via multiple bit lines BLa. When the latch circuit SDL stores "0" data (program target), the sense amplifier 27a applies a voltage VSS to the corresponding bit line BLa. When the latch circuit SDL stores "1" data (program prohibited), the sense amplifier 27a applies a voltage VBLPG to the corresponding bit line BLa. The voltage VBLPG is higher than the voltage VSS.

[0170] The sense amplifier 27b is connected to the relatively fast write-through subblock SBLK0_2 via multiple bit lines BLb. When the latch circuit SDL stores "0" data, the sense amplifier 27b applies a voltage VBS to the corresponding bit line BLb. The voltage VBS is higher than the voltage VSS and lower than the voltage VQPW. Also, similar to the sense amplifier 27a, when the latch circuit SDL stores "1" data, the sense amplifier 27b applies a voltage VBLPG to the corresponding bit line BLb.

[0171] The program is executed during the period from time t1 to t3.

[0172] At time t1, the row decoder 26a applies the voltage VPASS to each word line WLa of the selection block BLK. The voltage VPASS is higher than the voltage VPRE. The row decoder 26a applies the voltage VSGDon to the selection gate lines SGD1a and SGD2a corresponding to the selection string unit SU_sel. The voltage VSGDon is higher than the voltage VSGDoff. The selection transistor ST1 to which the voltage VSGDon is applied is turned ON. The row decoder 26a then applies the voltage VSGDoff to the selection gate lines SGD1a and SGD2a corresponding to the non-selected string unit SU_usel. The row decoder 26a also applies the voltage VSGSoff to the selection gate lines SGS1a and SGS2a. The voltage VSGSoff is higher than the voltage VSS and lower than the voltages VSGSon and VSRC. When the voltage VSGSoff is applied to the selection transistor ST2, it is set to the off state.

[0173] At time t2, the row decoder 26a applies the program voltage VPGM to the selected word line WLa_sel. Voltage VPGM is higher than voltage VPASS. The row decoder 26a then applies the voltage VPASS to the unselected word line WLa_usel. In the example shown in Figure 15, the row decoder 26a applies the voltage VPGM to the selected word line WLa4 and the voltage PASS to the unselected word lines WLa0 to WLa3 and WLa5 to WLa7.

[0174] In the sense circuits SA of sense amplifiers 27a and 27b, the signal BLC is set to the "L" level (voltage VSS is applied), and transistor TN3 is turned off. As a result, the bit lines BLa and BLb corresponding to the "1" data (program disabled) are in a floating state while maintaining the voltage VBLPG. The bit lines BLa and BLb corresponding to the "1" data remain in a floating state for the period from time t2 to t3. In sense amplifier 27a, a voltage is applied to the signal BLC to clamp the bit line BLa to the voltage VQPW. In sense amplifier 27b, a voltage is applied to the signal BLC to clamp the bit line BLb to the voltage (VPQW + VBS). The voltage (VPQW + VBS) is higher than the voltage VQPW and lower than the voltage VBLPG.

[0175] The latch circuit TDL stores data (QPW data) corresponding to program conditions PG0 and PG1. For example, "L" level data ("0" data) in the latch circuit TDL corresponds to program condition PG0, and "H" level data ("1" data) corresponds to program condition PG1. A logical OR operation is performed between the data in the latch circuit TDL and the data in the latch circuit SDL. As a result, "L" level data ("0" data) is stored in the latch circuit SDL corresponding to program condition PG0. In addition, "H" level data ("1" data) is stored in the latch circuit SDL corresponding to the program prohibition condition and program condition PG1. As a result, the sense amplifier 27a continues to apply the voltage VSS to the bit line BLa corresponding to program condition PG0 among the bit lines BLa corresponding to "0" data (program target). Then, sense amplifier 27a applies a voltage VQPW, clamped by transistor TN3, to the bit line BLa corresponding to program condition PG1 among the bit lines BLa corresponding to "0" data (program target). Meanwhile, sense amplifier 27b continues to apply a voltage VBS to the bit line BLb corresponding to program condition PG0 among the bit lines BLb corresponding to "0" data. Then, sense amplifier 27b applies a voltage (VQPW + VBS), clamped by transistor TN3, to the bit line BLb corresponding to program condition PG1 among the bit lines BLb corresponding to "0" data. In other words, sense amplifier 27b applies a higher voltage to the bit line BLb corresponding to the fast-writing memory cell array 11_2a than to the bit line BLa corresponding to the slow-writing memory cell array 11_1a.

[0176] As a result, in memory cell array 11_1a, PG0 program operation based on the voltage difference (VPGM-VSS) and PG1 program operation based on the voltage difference (VPGM-VQPW) are executed. In memory cell array 11_2a, PG0 program operation based on the voltage difference (VPGM-VBS) and PG1 program operation based on the voltage difference (VPGM-(VQPW+VBS)) are executed. Note that the rise in the threshold voltage of the memory cell transistor MC connected to the bit lines BLa and BLb corresponding to the "1" data (program prohibited) is suppressed by channel self-boost technology, etc. The voltage difference (VPGM-VBS) is smaller than the voltage difference (VPGM-VSS). Also, the voltage difference (VPGM-(VQPW+VBS)) is smaller than the voltage difference (VPGM-VQPW). Therefore, in the memory cell array 11_2a, which has a relatively fast writing speed, weaker writes (smaller threshold voltage increase) are performed than in the memory cell array 11_1a, which has a relatively slow writing speed. As a result, the variation between the threshold voltage increase of the memory cell transistors MC in the memory cell array 11_1a and the threshold voltage increase of the memory cell transistors MC in the memory cell array 11_2a is suppressed.

[0177] During the period from time t3 to t4, the bit line BL and word line WL are brought down. More specifically, during the period from time t3 to t4, the row decoder 26a applies the voltage VSS to each word line WLa. The voltage applied to the word line WLa may be higher than the voltage VSS and lower than the voltage VPGM. This suppresses voltage fluctuations of the word line WLa when transitioning to the next program verification operation. The row decoder 26a also applies the voltage VSS to the selected gate lines SGD1a and SGD2a and the selected gate lines SGS1a and SGS2a. The source line driver 30 applies the voltage VSS to the source lines SL1a and SL2a. The sense amplifier 27a applies the voltage VSS to the bit line BLa. The sense amplifier 27b applies the voltage VSS to the bit line BLb.

[0178] 1.3.5.2 Timing Chart for a Second Program Operation Next, the timing chart for a second program operation will be described with reference to Figures 16 and 17. In the second program operation, a case is described in which variations in the write characteristics between array chips 10 are suppressed by adjusting the write time using the bit line BL. Figure 16 is a timing chart showing the voltage of each wiring in the second program operation. Figure 17 is a diagram showing the voltage applied to the NAND string NS during the period from time t2 to t3 in the timing chart shown in Figure 16. The examples shown in Figures 16 and 17 show the case in which data is written to block BLK0, that is, subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a). Furthermore, the examples shown in Figures 16 and 17 illustrate a case where, within the same cell unit CU, relatively slow-writing memory cell transistors MC are included in memory cell array 11_1a (array chip 10_1), and relatively fast-writing memory cell transistors MC are included in memory cell array 11_2a (array chip 10_2). The following explanation will focus on the differences from the first example of program operation.

[0179] As shown in Figure 16, the voltages applied to the word line WLa, the selected gate lines SGD1a and SGD2a, the selected gate lines SGS1a and SGS2a, the source lines SL1a and SL2a, and the bit line BLa during the period from time t0 to t4 are the same as those in the first example of program operation described using Figure 14.

[0180] At time t0, the sense amplifier 27b in this example, similar to the sense amplifier 27a (bit line BLa), applies a voltage VSS to the corresponding bit line BLb if the latch circuit SDL stores "0" data. Furthermore, if the latch circuit SDL stores "1" data, the sense amplifier 27b applies a voltage VBLPG to the bit line BLb.

[0181] The program is executed during the period from time t1 to t3.

[0182] At time t1, similar to the first example of program operation, the row decoder 26a applies the voltage VPASS to each word line WLa of the selected block BLK. The row decoder 26a applies the voltage VSGDon to the selected gate lines SGD1a and SGD2a corresponding to the selected string unit SU_sel. The row decoder 26a also applies the voltage VSGDoff to the selected gate lines SGD1a and SGD2a corresponding to the unselected string unit SU_usel.

[0183] At time t2, the row decoder 26a applies the program voltage VPGM to the selected word line WLa_sel. The row decoder 26a then applies the voltage VPASS to the unselected word line WLa_usel. In the example shown in Figure 17, the row decoder 26a applies the voltage VPGM to the selected word line WLa4 and the voltage PASS to the unselected word lines WLa0 to WLa3 and WLa5 to WLa7.

[0184] The sense amplifier 27a sets the bit line BLa corresponding to the "1" data (program prohibited) to a floating state, similar to the first example of program operation. The sense amplifier 27a applies a voltage VSS to the bit line BLa corresponding to the program condition PG0 among the bit lines BLa corresponding to the "0" data (program target). The sense amplifier 27a applies a voltage VQPW to the bit line BLa corresponding to the program condition PG1 among the bit lines BLa corresponding to the "0" data.

[0185] Similar to sense amplifier 27a, sense amplifier 27b sets the bit line BLb corresponding to the "1" data to a floating state. Sense amplifier 27b applies voltage VSS to the bit line BLb corresponding to program condition PG0 among the bit lines BLb corresponding to "0" data. Sense amplifier 27b applies voltage VQPW to the bit line BLb corresponding to program condition PG1 among the bit lines BLb corresponding to "0" data.

[0186] At time t2', the sense amplifier 27b applies the voltage VBLPG to the bit line BLb corresponding to the "0" data. That is, the voltage of the bit line BLb is boosted from the voltage VSS or the voltage VQPW to the voltage VBLPG.

[0187] As a result, in the memory cell array 11_1a, PG0 program operation based on the voltage difference (VPGM-VSS) and PG1 program operation based on the voltage difference (VPGM-VQPW) are executed during the period from time t2 to t3. Hereinafter, the period during which charge is injected into the charge storage layer of the memory cell transistor MC will be referred to as the "program period". In contrast, in the memory cell array 11_2a, PG0 program operation based on the voltage difference (VPGM-VSS) and PG1 program operation based on the voltage difference (VPGM-VQPW) are executed during the period from time t2 to t2'. The length of the period from time t2 to t2' is shorter than the length of the period from time t2 to t3. Therefore, in the memory cell array 11_2a, which has a faster write speed, the program is executed for a shorter period than in the memory cell array 11_1a, which has a slower write speed. In other words, a different program period is applied to each array chip 10. As a result, the variation between the increase in threshold voltage of the memory cell transistor MC in memory cell array 11_1a and the increase in threshold voltage of the memory cell transistor MC in memory cell array 11_2a is suppressed.

[0188] During the period from time t3 to t4, the falling edges of the bit line BL and word line WL are executed, similar to the first example of program operation.

[0189] 1.3.5.3 Timing Chart for the Third Program Operation Next, the timing chart for the third program operation will be described with reference to Figures 18 and 19. In the third program operation, a case is described in which variations in the writing characteristics between array chips 10 are suppressed by adjusting the writing time using the selected gate line SGD. Figure 18 is a timing chart showing the voltage of each wiring in the third program operation. Figure 19 is a diagram showing the voltage applied to the NAND string NS during the period from time t2 to t3 in the timing chart shown in Figure 18. The examples shown in Figures 18 and 19 show the case in which data is written to block BLK0, that is, subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a). Furthermore, the examples shown in Figures 18 and 19 illustrate a case where, within the same cell unit CU, relatively slow-writing memory cell transistors MC are included in memory cell array 11_1a (array chip 10_1), and relatively fast-writing memory cell transistors MC are included in memory cell array 11_2a (array chip 10_2). The following explanation will focus on the differences between the first and second examples of program operation.

[0190] As shown in Figures 18 and 19, the voltages on each wire during the period from time t0 to t2' are the same as in the second example of the program operation described using Figure 16. In the example shown in Figure 19, the row decoder 26a applies the voltage VPGM to the selected word line WLa4 and the voltage PASS to the unselected word lines WLa0 to WLa3 and WLa5 to WLa7.

[0191] At time t2', the row decoder 26a applies the voltage VSGDoff to the selection gate line SGD2a corresponding to the selection string unit SU_sel. The selection transistor ST1 to which the voltage VSGDoff is applied is turned off.

[0192] As a result, similar to the second example of program operation, in the memory cell array 11_1a, PG0 program operation based on the voltage difference (VPGM-VSS) and PG1 program operation based on the voltage difference (VPGM-VQPW) are executed during the period from time t2 to t3. In contrast, in the memory cell array 11_2a, PG0 program operation based on the voltage difference (VPGM-VSS) and PG1 program operation based on the voltage difference (VPGM-VQPW) are executed during the period from time t2 to t2'. The length of the period from time t2 to t2' is shorter than the length of the period from time t2 to t3. Therefore, in the memory cell array 11_2a, which has a faster write speed, writing is performed for a shorter period than in the memory cell array 11_1a, which has a slower write speed. In other words, different program periods are applied to each array chip 10. As a result, the variation between the increase in threshold voltage of the memory cell transistor MC in memory cell array 11_1a and the increase in threshold voltage of the memory cell transistor MC in memory cell array 11_2a is suppressed.

[0193] During the period from time t3 to t4, the falling edges of the bit line BL and word line WL are executed, similar to the first example of program operation.

[0194] 1.3.5.4 Timing Chart for the Fourth Program Operation Next, the timing chart for the fourth program operation will be described with reference to Figures 20 and 21. In the third program operation, a case is described in which variations in the write characteristics between array chips 10 are suppressed by adjusting the write time using the selected gate line SGS. Figure 20 is a timing chart showing the voltage of each wiring in the fourth program operation. Figure 21 is a diagram showing the voltage applied to the NAND string NS during the period from time t2 to t3 in the timing chart shown in Figure 20. The examples shown in Figures 20 and 21 show the case in which data is written to block BLK0, that is, subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a). Furthermore, the examples shown in Figures 20 and 21 illustrate a case where, within the same cell unit CU, relatively slow-writing memory cell transistors MC are included in memory cell array 11_1a (array chip 10_1), and relatively fast-writing memory cell transistors MC are included in memory cell array 11_2a (array chip 10_2). The following explanation will focus on the differences from the first to third examples of program operation.

[0195] As shown in Figures 20 and 21, the voltages on each wire during the period from time t0 to t2' are the same as in the second example of the program operation described using Figure 16. In the example shown in Figure 21, the row decoder 26a applies the voltage VPGM to the word line WLa4 and the voltage PASS to the word lines WLa0 to WLa3 and WLa5 to WLa7.

[0196] At time t2', the row decoder 26a applies the voltage VSGDoff to the selection gate line SGD2a corresponding to the selection string unit SU_sel. The row decoder 26a also applies the voltage VSGSon to the selection gate line SGS2a corresponding to the selection string unit SU_sel. The selection transistor ST2 to which the voltage VSGSon is applied is turned ON.

[0197] As a result, similar to the second and third examples of program operation, in the memory cell array 11_1a, the PG0 program operation based on the voltage difference (VPGM-VSS) and the PG1 program operation based on the voltage difference (VPGM-VQPW) are executed during the period from time t2 to t3. In contrast, in the memory cell array 11_2a, the PG0 program operation based on the voltage difference (VPGM-VSS) and the PG1 program operation based on the voltage difference (VPGM-VQPW) are executed during the period from time t2 to t2'. The length of the period from time t2 to t2' is shorter than the length of the period from time t2 to t3. Therefore, in the memory cell array 11_2a, which has a faster write speed, writing is performed for a shorter period than in the memory cell array 11_1a, which has a slower write speed. In other words, a different program period is applied to each array chip 10. As a result, the variation between the increase in threshold voltage of the memory cell transistor MC in memory cell array 11_1a and the increase in threshold voltage of the memory cell transistor MC in memory cell array 11_2a is suppressed.

[0198] During the period from time t3 to t4, the falling edges of the bit line BL and word line WL are executed, similar to the first example of program operation.

[0199] The first to fourth examples of program operation may be combined as much as possible. For example, the second, third, and fourth examples may be combined to change the voltages of the selected gate lines SGD2a and SGS2a and the bit line BLb at time t2'.

[0200] 1.4. Erasure Operation Next, the erasure operation will be explained. The erasure operation broadly includes the erasure pulse application operation and the erasure verification operation. The erasure pulse application operation is the operation of applying an erasure pulse to lower the threshold voltage of the memory cell transistor MC. The erasure verification operation is the operation of determining whether the threshold voltage of the memory cell transistor MC has fallen below the target value as a result of applying the erasure pulse. In the erasure operation, the threshold voltage of the memory cell transistor MC is lowered to the "Er" state by repeatedly performing the erasure pulse application operation and the erasure verification operation.

[0201] For example, similar to the write characteristics, variations in the manufacturing process cause variations in the erase characteristics of the memory cell transistors MC for each array chip 10. That is, when an erase pulse is applied, array chips 10 with relatively large threshold voltage fluctuations and array chips 10 with relatively small threshold voltage fluctuations coexist. In this case, the variation in the threshold voltage distribution of the "Er" state becomes large. In this embodiment, variations between array chips 10 are suppressed by changing the conditions for generating GIDL (Gate Induced Drain Leakage) current for each array chip 10 during the erase pulse application operation. The application time of the erase pulse voltage may also be changed for each array chip 10. Hereinafter, when the threshold voltage fluctuation is relatively large during the erase pulse application operation, it will be referred to as "fast erasure." Conversely, when the threshold voltage fluctuation is relatively small, it will be referred to as "slow erasure."

[0202] The timing chart for the erase pulse application operation will be explained with reference to Figures 22 and 23. Figure 22 is a timing chart showing an example of the voltage of each wire during the erase pulse application operation. Figure 23 is a diagram showing the voltage applied to the NAND string NS during the period from time t0 to t1 in the timing chart shown in Figure 22. The examples shown in Figures 22 and 23 show the case where data in block BLK0, i.e., subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a) is erased. Furthermore, the examples shown in Figures 22 and 23 show the case where a relatively slow erase memory cell transistor MC is included in memory cell array 11_1a (array chip 10_1), and a relatively fast erase memory cell transistor MC is included in memory cell array 11_2a (array chip 10_2).

[0203] As shown in Figures 22 and 23, first, at time t0, the source line driver 30 applies voltage VERAH to source line SL1a and voltage VERAL to source line SL2a. Voltages VERAH and VERAL are high voltages for generating GIDL current. Voltage VERAH is a higher voltage than voltage VERAL.

[0204] Sense amplifier 27a applies the same voltage VERAH to the bit line BLa as to the source line SL1a. Sense amplifier 27b applies the same voltage VERAL to the bit line BLb as to the source line SL2a.

[0205] The row decoder 26a applies the voltage VERASGH to the selected gate lines SGD1a and SGS1a of the block BLK (block BLK0) to be erased, and the voltage VERASGL to the selected gate lines SGD2a and SGS2a. Voltages VERASGH and VERASGL are voltages required to generate GIDL in the selection transistors ST1 and ST2. Voltage VERASGH is lower than voltage VERAH. Voltage VERASGL is lower than voltage VERAL. Furthermore, voltage VERASGH is higher than voltage VERASGL. The row decoder 26a also applies the voltage VISO to each word line WLa. Voltage VISO is higher than voltage VSS and lower than voltage VERASGL.

[0206] During the period from time t0 to t1, holes generated by GIDL are injected into the charge storage layer of the memory cell transistor MC in the selection block BLK. At this time, a lower voltage is applied to the source line SL2a, bit line BLa, and selection gate lines SGD2a and SGS2a of the relatively fast erasable memory cell array 11_2a than to the source line SL1a, bit line BLa, and selection gate lines SGD1a and SGS1a of the relatively slow erasable memory cell array 11_1a. As a result, the variation in the threshold voltage fluctuation (decrease) of the memory cell transistor MC in the memory cell array 11_1a and the variation in the threshold voltage fluctuation (decrease) of the memory cell transistor MC in the memory cell array 11_2a is suppressed.

[0207] During the period from time t1 to t2, the power drops of each wire are performed. More specifically, during the period from time t1 to t2, the row decoder 26a applies voltage VSS to the word line WLa, the selection gate lines SGD1a and SGD2a, and the selection gate lines SGS1a and SGS2a. The source line driver 30 applies voltage VSS to the source lines SL1a and SL2a. The sense amplifier 27a applies voltage VSS to the bit line BLa. The sense amplifier 27b applies voltage VSS to the bit line BLb.

[0208] 1.5 Reading Operation Next, we will explain the reading operation.

[0209] 1.5.1 Variation in Cell Current per Array Chip First, an example of variation in cell current per array chip 10 will be explained with reference to Figure 24. Figure 24 is a graph showing a specific example of the relationship between the gate-source voltage Vgs of the selective memory cell transistor MC and the cell current Icell flowing through the selective memory cell transistor MC during read operation. Figure 24 shows the results of comparing the cell current Icell of the same state selective memory cell transistor MC contained in each of the array chips 10_1 and 10_2.

[0210] For example, due to variations in the manufacturing process, the data retention characteristics of the memory cell transistors MC may vary from one array chip 10 to another. In this case, the amount of threshold voltage fluctuation due to data retention will vary from one array chip 10 to another. That is, the threshold voltage of memory cell transistors MC in the same state will vary from one array chip 10 to another. Therefore, the optimal value of the read voltage will vary from one array chip 10 to another. In other words, the read characteristics will vary from one array chip 10 to another.

[0211] As shown in Figure 24, for example, we compare the memory cell transistor MC of array chip 10_1 and the memory cell transistor MC of array chip 10_2 in the same state. When the gate-source voltage Vgs of each memory cell transistor MC is voltage V2 (black circle shown in Figure 24), current I1 flows through the memory cell transistor MC of array chip 10_1, and current I2 flows through the memory cell transistor MC of array chip 10_2. Current I1 is smaller than current I2. In this case, the threshold voltage of the selected memory cell transistor MC of array chip 10_1 is higher than the threshold voltage of the selected memory cell transistor MC of array chip 10_2. For example, when the gate-source voltage Vgs of the memory cell transistor MC of array chip 10_2 is lowered to voltage V1 (white circle shown in Figure 24), current I1 flows through the memory cell transistor MC. The difference ΔVt between the threshold voltage of the selected memory cell transistor MC of array chip 10_1 and the threshold voltage of the selected memory cell transistor MC of array chip 10_2 at this time is voltage (V2 - V1).

[0212] When a semiconductor memory device 1 includes multiple array chips 10 and the array chips 10 share a word line WL, the same read voltage is applied to the select memory cell transistor MC of each array chip 10. Therefore, it is not possible to set the read voltage (word line WL voltage) for each array chip 10 according to the difference ΔVt.

[0213] Therefore, in this embodiment, the read voltage is set to match the array chip 10 (memory cell array 11) with a relatively high threshold voltage. Then, for the array chip 10 with a relatively low threshold voltage, the voltage of the bit line BL that is not shared between the array chips 10 is adjusted, or the sense time is adjusted. This suppresses variations in read characteristics between the array chips 10.

[0214] 1.5.2 Timing Chart for Read Operation Next, two examples of the timing chart for read operation will be explained. In the following explanation, we will focus on memory cell transistors MC in the same state and describe the case where the memory cell transistors MC in array chip 10_2 (memory cell arrays 11_2a and 11_2b) are more likely to conduct cell current than the memory cell transistors MC in array chip 10_1 (memory cell arrays 11_1a and 11_1b). In other words, we will describe the case where, focusing on memory cell transistors MC in the same state, the threshold voltage of the memory cell transistors MC in array chip 10_2 is relatively lower than that of the memory cell transistors MC in array chip 10_1. In this embodiment, the voltage application conditions to each wiring during read operation differ for each array chip 10. That is, during read operation, at least one voltage of the bit line BL, the selection gate line SGD, the selection gate line SGS, and the source line SL differs for each array chip 10.

[0215] 1.5.2.1 Timing Chart for the First Example of Read Operation First, the timing chart for the first example of read operation will be explained with reference to Figure 25. In the first example of read operation, the case where the sense time differs between array chips 10 with a relatively high threshold voltage and array chips 10 with a relatively low threshold voltage will be explained. Figure 25 is a timing chart showing the voltage of each wiring and signal in the first example of read operation. The example shown in Figure 25 shows the case of reading lower page data from block BLK0, that is, subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a). Furthermore, the example shown in Figure 25 shows the case where, within the same cell unit CU, among memory cell transistors MC of the same state, the memory cell transistor MC with a relatively high threshold voltage is included in memory cell array 11_1a (array chip 10_1), and the memory cell transistor MC with a relatively low threshold voltage is included in memory cell array 11_2a (array chip 10_2).

[0216] As shown in Figure 25, the bit line BL is charged during the period from time t0 to t2.

[0217] More specifically, during the period from time t0 to t1, the source line driver 30 increases the voltage of source lines SL1a and SL2a from voltage VSS to voltage VSRC.

[0218] Sense amplifier 27a boosts the voltage of the bit line BLa from voltage VSS to voltage VSRC. Similarly, sense amplifier 27b boosts the voltage of the bit line BLb from voltage VSS to voltage VSRC.

[0219] During the period from time t1 to t2, sense amplifier 27a boosts the voltage of bit line BLa from voltage VSRC to voltage VBLRD. Similarly, sense amplifier 27b boosts the voltage of bit line BLb from voltage VSRC to voltage VBLRD. Voltage VBLRD is the voltage applied to bit lines BLa and BLb during read operation. Voltage VBLRD is a higher voltage than voltage VSRC.

[0220] During the period from time t0 to t2, the row decoder 26a increases the voltage of the selected gate lines SGD1a and SGD2a from voltage VSS to voltage VSGDon. The row decoder 26a also increases the voltage of the selected gate lines SGS1a and SGS2a from voltage VSS to voltage VSGSonn.

[0221] During the period from time t1 to t2, the row decoder 26a increases the voltage of each word line WLa from voltage VSS to voltage VREAD. As a result, each memory cell transistor MC of the selection block BLK is turned ON.

[0222] The AR read operation is performed during the period from time t2 to t8.

[0223] At time t2, the row decoder 26a applies the voltage VSGDoff to the selection gate lines SGD1a and SGD2a corresponding to the unselected string unit SU_usel. This turns off the selection transistor ST1 of the unselected string unit SU_usel. The row decoder 26a also applies the read voltage VA to the selection word line WLa_usel. For example, if the threshold voltage of the selection memory cell transistor MC to be read is less than voltage VA, the selection memory cell transistor MC is turned on (also referred to as "on cell"). If the threshold voltage of the selection memory cell transistor MC to be read is greater than or equal to voltage VA, the memory cell transistor MC is turned off (also referred to as "off cell").

[0224] At time t3, sense amplifier 27a applies the voltage VDDSA to node SEN(SENa) of sense circuit SA. Similarly, sense amplifier 27b applies the voltage VDDSA to node SEN(SENb).

[0225] At time t4, the voltage VDDSA ("H" level voltage) is applied to the signals CLK(CLKa) of sense amplifier 27a and CLK(CLKb) of sense amplifier 27b. Due to the clock-up, the voltages at nodes SENa and SENb rise to the voltage VSEN. Voltage VSEN is higher than the voltage VDDSA.

[0226] At time t5, a voltage VXXL ("H" level voltage) is applied to the signals XXL (XXLa) of sense amplifier 27a and XXL (XXLb) of sense amplifier 27b. As a result, the transistors TN4 of sense amplifiers 27a and 27b are turned ON. When the corresponding selective memory cell transistor MC is an ON cell, current flows from node SEN to bit line BL (charge moves from node SEN). Therefore, the voltages of nodes SENa and SENb corresponding to the ON cell decrease. At this time, the voltage of node SENa corresponding to the selective memory cell transistor MC, which has a relatively high threshold voltage, decreases more slowly than the voltage of node SENb corresponding to the selective memory cell transistor MC, which has a relatively low threshold voltage. Also, when the corresponding selective memory cell transistor MC is an OFF cell, almost no current flows from node SEN to bit line BL. Therefore, the voltages of nodes SENa and SENb corresponding to the OFF cell hardly decrease.

[0227] At time t6', a voltage VSS ("L" level voltage) is applied to the signal XXL (XXLb) of the sense amplifier 27b. This turns off the transistor TN4 of the sense amplifier 27b. The period from time t5 to t6' is the sense time for the bit line BLb, i.e., the sense time in the memory cell array 11_2a.

[0228] At time t6, a voltage VSS ("L" level voltage) is applied to the signal XXL (XXLa) of the sense amplifier 27a. This turns off the transistor TN4 of the sense amplifier 27a. The period from time t5 to t6 is the sense time for the bit line BLa, i.e., the memory cell array 11_1a.

[0229] The length of the period from time t5 to t6' is shorter than the length of the period from time t5 to t6. Therefore, in the memory cell array 11_2a, which has a relatively low threshold voltage, the sense operation is performed for a shorter period than in the memory cell array 11_1a, which has a relatively high threshold voltage. As a result, the variation between the voltage drop of node SENa corresponding to an on-cell in the memory cell array 11_1a and the voltage drop of node SENb corresponding to an on-cell in the memory cell array 11_2a is suppressed.

[0230] At time t7, a voltage VSS ("L" level voltage) is applied to signals CLKa and CLKb. Due to the clock down, the voltages of nodes SENa and SENb decrease. For example, in the sense circuit SA corresponding to the off-cell, node SEN is set to the "H" level. Therefore, transistor TN9 is turned ON.

[0231] During the period from time t7 to t8, strobes are executed on bit lines BLa and BLb. For example, in the case of an off-cell, transistor TN9 is set to the ON state, and as a result, the bus LBUS of sense amplifier 27 is set to the "L" level. In the case of an on-cell, transistor TN9 is set to the OFF state, and as a result, the bus LBUS is set to the "H" level. Then, the data from the bus LBUS is transferred to the latch circuit SDL. For example, in the case of an off-cell, the "L" level data from the bus LBUS is transferred to the latch circuit SDL. Therefore, node LAT_S is set to the "L" level and node INV_S is set to the "H" level. In other words, if the memory cell transistor MC is storing data in one of the "A" to "G" states, the latch circuit SDL stores "0" data. In the case of an on-cell, the "H" level data from the bus LBUS is transferred to the latch circuit SDL. Therefore, node LAT_S is set to the "H" level, and node INV_S is set to the "L" level. In other words, when the memory cell transistor MC stores data in the "Er" state, the latch circuit SDL stores "1" data.

[0232] The ER read operation is performed during the period from time t8 to t14.

[0233] At time t8, the row decoder 26a applies a read voltage VE to the selected word line WLa_sel.

[0234] At time t9, sense amplifier 27a applies the voltage VDDSA to node SEN(SENa). Similarly, sense amplifier 27b applies the voltage VDDSA to node SEN(SENb).

[0235] At time t10, the voltage VDDSA is applied to the signals CLK(CLKa) of sense amplifier 27a and CLK(CLKb) of sense amplifier 27b. Due to the clock-up, the voltages at nodes SENa and SENb rise to the voltage VSEN.

[0236] At time t11, the voltage VXXL is applied to the signals XXL(XXLa) of sense amplifier 27a and XXL(XXLb) of sense amplifier 27b. As a result, the transistors TN4 of sense amplifiers 27a and 27b are turned ON. When the corresponding selective memory cell transistor MC is an ON cell, the voltages at nodes SENa and SENb decrease. When the corresponding selective memory cell transistor MC is an OFF cell, the voltages at nodes SENa and SENb hardly decrease.

[0237] At time t12', a voltage VSS is applied to the signal XXL (XXLb) of the sense amplifier 27b. This turns off the transistor TN4 of the sense amplifier 27b. The period from time t11 to t12' is the sense time for the bit line BLb, i.e., the sense time in the memory cell array 11_2a.

[0238] At time t12, the voltage VSS is applied to the signal XXL (XXLa) of the sense amplifier 27a. As a result, the transistor TN4 of the sense amplifier 27a is turned off. The period from time t11 to t12 is the sense time for the bit line BLa, i.e., the sense time in the memory cell array 11_1a.

[0239] At time t13, the voltage VSS is applied to signals CLKa and CLKb. Due to the clock down, the voltages of nodes SENa and SENb decrease.

[0240] During the period from time t13 to t14, strobes are executed on the bit lines BLa and BLb. If the memory cell transistor MC is storing data in any of the "E" to "G" states, the latch circuit SDL stores "0" data. If the memory cell transistor MC is storing data in the "Er" to "D" states, the latch circuit SDL stores "1" data.

[0241] At time t14, the word line WL and the bit line BL are brought down. More specifically, the row decoder 26a applies voltage VSS to the word line WLa, the selection gate lines SGD1a and SGD2a, and the selection gate lines SGS1a and SGS2a. The source line driver 30 applies voltage VSS to the source lines SL1a and SL2a. The sense amplifier 27a applies voltage VSS to the bit line BLa. The sense amplifier 27b applies voltage VSS to the bit line BLb.

[0242] 1.5.2.2 Timing Chart for the Second Example of Read Operation Next, the timing chart for the second example of read operation will be described with reference to Figure 26. The second example of read operation describes the case where the voltage of the bit line BL differs between array chip 10 with a relatively high threshold voltage and array chip 10 with a relatively low threshold voltage. Figure 26 is a timing chart showing the voltage of each wiring and signal in the second example of read operation. The example shown in Figure 26 shows the case of reading lower page data from block BLK0, i.e., subblock SBLK0_1 (memory cell array 11_1a) and subblock SBLK0_2 (memory cell array 11_2a). Furthermore, the example shown in Figure 26 shows the case where, within the same cell unit CU, among memory cell transistors MC of the same state, the memory cell transistor MC with a relatively high threshold voltage is included in memory cell array 11_1a (array chip 10_1), and the memory cell transistor MC with a relatively low threshold voltage is included in memory cell array 11_2a (array chip 10_2). The following explanation will focus on the differences from the first example of the read operation.

[0243] As shown in Figure 26, the voltages applied to the word line WLa, the selected gate lines SGD1a and SGD2a, the selected gate lines SGS1a and SGS2a, and the source lines SL1a and SL2a during the period from time t0 to t14 are the same as those in the first example of the read operation described using Figure 26.

[0244] During the period from time t0 to t1, sense amplifier 27a boosts the voltage of bit line BLa from voltage VSS to voltage VSRC. Similarly, sense amplifier 27b boosts the voltage of bit line BLb from voltage VSS to voltage VSRC.

[0245] During the period from time t1 to t2, sense amplifier 27a boosts the voltage of bit line BLa from voltage VSRC to voltage VBLRD1. Voltage VBLRD1 is the voltage applied to bit line BLa during read operation. Similarly, sense amplifier 27b boosts the voltage of bit line BLb from voltage VSRC to voltage VBLRD2. Voltage VBLRD2 is the voltage applied to bit line BLb during read operation. Voltages VBLRD1 and VBLRD2 are higher than voltage VSRC. Also, voltage VBLRD1 is higher than voltage VBLRD2.

[0246] The AR read operation is performed during the period from time t2 to t8.

[0247] At time t3, sense amplifier 27a applies the voltage VDDSA to node SEN(SENa). Similarly, sense amplifier 27b applies the voltage VDDSA to node SEN(SENb).

[0248] At time t4, the voltage VDDSA is applied to the signals CLK(CLKa) of sense amplifier 27a and CLK(CLKb) of sense amplifier 27b. Due to the clock-up, the voltages at nodes SENa and SENb rise to the voltage VSEN.

[0249] At time t5, the voltage VXXL is applied to the signals XXL(XXLa) of sense amplifier 27a and XXL(XXLb) of sense amplifier 27b. As a result, the transistors TN4 of sense amplifiers 27a and 27b are turned ON. When the corresponding selective memory cell transistor MC is an ON cell, the voltages at nodes SENa and SENb decrease. When the corresponding selective memory cell transistor MC is an OFF cell, the voltages at nodes SENa and SENb hardly decrease.

[0250] At time t6, the voltage VSS is applied to the signals XXL(XXLa) of sense amplifier 27a and XXL(XXLb) of sense amplifier 27b. As a result, the transistors TN4 of sense amplifiers 27a and 27b are turned off. The period from time t5 to t6 is the sense time for bit lines BLa and BLb, i.e., for memory cell arrays 11_1a and 11_2a. At this time, the relationship between voltage VBLRD1 and voltage VBLRD2 is VBLRD1 > VBLRD2. For example, if the threshold voltage of the memory cell transistor MC of array chip 10_1 and the threshold voltage of the memory cell transistor MC of array chip 10_2 are the same, the amount of current flowing from bit line BLa to source line SL1a will be greater than the amount of current flowing from bit line BLb to source line SL1b. As a result, the variation between the voltage drop (decrease rate) of node SENa corresponding to an on-cell in memory cell array 11_1a and the voltage drop (decrease rate) of node SENb corresponding to an on-cell in memory cell array 11_2a is suppressed.

[0251] At time t7, the voltage VSS is applied to signals CLKa and CLKb. Due to the clock down, the voltages of nodes SENa and SENb decrease.

[0252] During the period from time t7 to t8, strobes are executed on bit lines BLa and BLb. If the memory cell transistor MC is storing data in one of the states "A" to "G", the latch circuit SDL stores the data "0". If the memory cell transistor MC is storing data in the "Er" state, the latch circuit SDL stores the data "1".

[0253] The ER read operation is performed during the period from time t8 to t14.

[0254] At time t9, sense amplifier 27a applies the voltage VDDSA to node SEN(SENa). Similarly, sense amplifier 27b applies the voltage VDDSA to node SEN(SENb).

[0255] At time t10, the voltage VDDSA is applied to the signals CLK(CLKa) of sense amplifier 27a and CLK(CLKb) of sense amplifier 27b. Due to the clock-up, the voltages at nodes SENa and SENb rise to the voltage VSEN.

[0256] At time t11, the voltage VXXL is applied to the signals XXL(XXLa) of sense amplifier 27a and XXL(XXLb) of sense amplifier 27b. As a result, the transistors TN4 of sense amplifiers 27a and 27b are turned ON. When the corresponding selective memory cell transistor MC is an ON cell, the voltages at nodes SENa and SENb decrease. When the corresponding selective memory cell transistor MC is an OFF cell, the voltages at nodes SENa and SENb hardly decrease.

[0257] At time t12, the voltage VSS is applied to the signal XXL(XXLa) of sense amplifier 27a and the signal XXL(XXLb) of sense amplifier 27b. As a result, the transistors TN4 of sense amplifiers 27a and 27b are turned off. The period from time t11 to t12 is the sense time for the bit lines BLa and BLb, i.e., the memory cell arrays 11_1a and 11_2a.

[0258] At time t13, the voltage VSS is applied to signals CLKa and CLKb. Due to the clock down, the voltages of nodes SENa and SENb decrease.

[0259] During the period from time t13 to t14, strobes are executed on the bit lines BLa and BLb. If the memory cell transistor MC is storing data in any of the "E" to "G" states, the latch circuit SDL stores "0" data. If the memory cell transistor MC is storing data in the "Er" to "D" states, the latch circuit SDL stores "1" data.

[0260] At time t14, the word line WL and the bit line BL are brought down. More specifically, the row decoder 26a applies voltage VSS to the word line WLa, the selection gate lines SGD1a and SGD2a, and the selection gate lines SGS1a and SGS2a. The source line driver 30 applies voltage VSS to the source lines SL1a and SL2a. The sense amplifier 27a applies voltage VSS to the bit line BLa. The sense amplifier 27b applies voltage VSS to the bit line BLb.

[0261] 1.6 Effects of this Embodiment With the configuration of this embodiment, a semiconductor memory device 1 that can suppress a decrease in processing power can be provided. These effects will be described in detail below.

[0262] For example, if a semiconductor memory device 1 includes multiple array chips 10, the characteristics of the memory cell transistors MC (write characteristics, erase characteristics, and read characteristics) may vary from one array chip 10 to the other. If the semiconductor memory device 1 includes only one array chip 10, the variation in processing time for each semiconductor memory device 1 can be reduced by setting the voltage of the word line WL to match the characteristics of the memory cell transistors MC. However, if the semiconductor memory device 1 includes multiple array chips 10 and the multiple array chips 10 share the word line WL, the same voltage is applied to the word line WL of each array chip 10. Therefore, it is difficult to suppress the variation in the characteristics of the memory cell transistors MC between array chips 10 due to the voltage of the word line WL.

[0263] In contrast, in the configuration according to this embodiment, the semiconductor memory device 1 includes a plurality of array chips 10 and shares a word line WL among the plurality of array chips 10. More specifically, a plurality of memory cell arrays 11 stacked on top of the circuit chip 20 share a word line WL. The semiconductor memory device 1 does not share a bit line BL, a selection gate line SGD and SGS, or a source line SL among the plurality of memory cell arrays 11 stacked on top of the circuit chip 20. As a result, the semiconductor memory device 1 can set different voltage application conditions for the bit line BL, the selection gate lines SGD and SGS, or the source line SL for each memory cell array 11. This suppresses the increase in processing time due to variations in the characteristics of each array chip 10. Therefore, a decrease in the processing capacity of the semiconductor memory device 1 can be suppressed.

[0264] Furthermore, in the configuration according to this embodiment, a higher voltage can be applied to the bit line BL of a fast-writing memory cell array 11 (array chip 10) in a single block BLK than to a slow-writing memory cell array 11 (array chip 10). This allows the relatively fast-writing memory cell array 11 to perform weaker writes than the relatively slow-writing memory cell array 11. Also, in the configuration according to this embodiment, different voltages can be applied to at least one of the selection gate line SGD, bit line BL, and selection gate line SGS for each memory cell array 11 (array chip 10) in a single block BLK. This allows different program periods to be set for each memory cell array 11 (array chip 10). Therefore, the increase in processing time for write operations due to variations in the write characteristics of each array chip 10 can be suppressed.

[0265] Furthermore, with the configuration according to this embodiment, in a single block BLK, a lower voltage can be applied to the source line SL, bit line BL, and selection gate lines SGD and SGS of a relatively fast erasing memory cell array 11 (array chip 10) than to a relatively slow erasing memory cell array 11 (array chip 10). This suppresses the variation in the threshold voltage fluctuation of the memory cell transistor MC included in the relatively fast erasing memory cell array 11 (array chip 10) and the variation in the threshold voltage fluctuation of the memory cell transistor MC included in the relatively slow erasing memory cell array 11 (array chip 10). Therefore, the increase in processing time for erasing due to variations in erasing characteristics for each array chip 10 can be suppressed.

[0266] Furthermore, with the configuration according to this embodiment, different sense times can be set for each memory cell array 11 (array chip 10) in a single block BLK. In addition, a lower voltage can be applied to the bit line BL of a memory cell array 11 (array chip 10) with a relatively high threshold voltage for the same state than to a memory cell array 11 (array chip 10) with a relatively low threshold voltage for the same state. This suppresses the variation in the voltage drop (decrease rate) of the node SEN in a memory cell array 11 with a relatively high threshold voltage for the same state and the voltage drop (decrease rate) of the node SEN in a memory cell array 11 with a relatively low threshold voltage for the same state. Therefore, misreading can be suppressed and the reliability of the semiconductor memory device 1 can be improved.

[0267] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, the case in which data is read from one of the multiple array chips 10 will be described. The differences from the first embodiment will be described below.

[0268] 2.1 Read Operation The read operation will now be described. For example, an external controller may request the read of data with a length shorter than one page (referred to as a "subpage"). In this embodiment, a read operation (hereinafter referred to as a "subpage read operation") can be performed in which data is read from the subblock SBLK (array chip 10) that stores the requested data, among multiple subblock SBLKs (multiple array chips 10) that share a word line, and data is not read from the other subblock SBLKs (array chips 10).

[0269] The following are four examples of how subpages are loaded.

[0270] 2.1.1 Timing Chart for the First Example of Subpage Read Operation First, the timing chart for the first example of subpage read operation will be explained with reference to Figure 27. Figure 27 is a timing chart showing the voltage of each wiring in the first example of subpage read operation. The example shown in Figure 27 shows the case in which, during the subpage read operation of block BLK0, lower page data of subblock SBLK0_1 (memory cell array 11_1a) is read, but data from subblock SBLK0_2 (memory cell array 11_2a) is not read.

[0271] In the following explanation, the memory cell array 11 corresponding to the subblock SBLK to be read will be referred to as "selected memory cell array 11" or "selected array 11". The memory cell array 11 corresponding to the subblock SBLK that is not to be read will be referred to as "unselected memory cell array 11" or "unselected array 11".

[0272] As shown in Figure 27, the bit line BL is charged during the period from time t0 to t2.

[0273] More specifically, during the period from time t0 to t1, the source line driver 30 increases the voltage of source lines SL1a and SL2a from voltage VSS to voltage VSRC.

[0274] Sense amplifier 27a boosts the voltage of the bit line BLa from voltage VSS to voltage VSRC. Similarly, sense amplifier 27b boosts the voltage of the bit line BLb from voltage VSS to voltage VSRC.

[0275] During the period from time t1 to t2, sense amplifier 27a increases the voltage of the bit line BLa corresponding to the selected memory cell array 11 from voltage VSRC to voltage VBLRD. Sense amplifier 27b maintains the voltage of the bit line BLb corresponding to the non-selected memory cell array 11 at voltage VSRC.

[0276] During the period from time t0 to t2, the row decoder 26a increases the voltage of the selected gate lines SGD1a and SGD2a from voltage VSS to voltage VSGDon. The row decoder 26a also increases the voltage of the selected gate lines SGS1a and SGS2a from voltage VSS to voltage VSGSonn. As a result, the selection transistors ST1 and ST2 are turned ON in the selected memory cell array 11 and the non-selected memory cell array 11. Consequently, the potential of the channel of the NAND string NS in the non-selected memory cell array 11 is increased to voltage VSRC.

[0277] During the period from time t1 to t2, the row decoder 26a increases the voltage of each word line WLa from voltage VSS to voltage VREAD. This turns on each memory cell transistor MC of the selection block BLK. At this time, the charging current for charging the word line WLa to voltage VREAD is defined as IREAD1.

[0278] The AR read operation is performed during the period from time t2 to t3.

[0279] At time t2, the row decoder 26a applies the voltage VSGDoff to the selection gate lines SGD1a and SGD2a corresponding to the unselected string unit SU_usel of the selection memory cell array 11. Similarly, the row decoder 26a applies the voltage VSGDoff to the selection gate lines SGD1a and SGD2a corresponding to the unselected memory cell array 11. As a result, the selection transistor ST1 of the unselected string unit SU_usel and each string unit SU of the unselected memory cell array 11 are turned off. The row decoder 26a also applies the read voltage VA to the selection word line WLa_usel.

[0280] The ER read operation is performed during the period from time t3 to t4.

[0281] At time t3, the row decoder 26a applies a read voltage VE to the selected word line WLa_sel.

[0282] At time t4, the word line WL and the bit line BL are brought down. More specifically, the row decoder 26a applies voltage VSS to the word line WLa, the selection gate lines SGD1a and SGD2a, and the selection gate lines SGS1a and SGS2a. The source line driver 30 applies voltage VSS to the source lines SL1a and SL2a. The sense amplifier 27a applies voltage VSS to the bit line BLa. The sense amplifier 27b applies voltage VSS to the bit line BLb.

[0283] 2.1.2 Timing Chart for a Second Example of Subpage Read Operation Next, the timing chart for a second example of subpage read operation will be described with reference to Figure 28. Figure 28 is a timing chart showing the voltage of each wiring in a second example of subpage read operation. The example shown in Figure 28 shows the case in which, during a subpage read operation of block BLK0, lower page data of subblock SBLK0_1 (memory cell array 11_1a) is read, but data from subblock SBLK0_2 (memory cell array 11_2a) is not read.

[0284] As shown in Figure 28, the voltages applied to the word line WLa, the selected gate lines SGD1a and SGS1a of the selected memory cell array 11, the source line SL1a, and the bit line BLa during the period from time t0 to t4 are the same as those in the first example of the subpage read operation described using Figure 27.

[0285] During the period from time t0 to t1, the source line driver 30 increases the voltage of the source line SL2a corresponding to the non-selected memory cell array 11 from voltage VSS to voltage VSRC.

[0286] During the period from time t1 to t2, the sense amplifier 27b boosts the voltage of the bit line BLb corresponding to the unselected memory cell array 11 from voltage VSRCS to voltage VBLRD.

[0287] During the period from time t0 to t2, the row decoder 26a increases the voltage of SGD2a from voltage VSS to voltage VSGDoff. The row decoder 26a also increases the voltage of the selected gate line SGS2a from voltage VSS to voltage VSGSoff. As a result, the selection transistors ST1 and ST2 in the non-selected memory cell array 11 are turned off. In this example, during the period from time t0 to t4, the channels of the NAND string NS in the non-selected memory cell array 11 are in a floating state. During the period from time t1 to t4, that is, throughout the entire period in which the subpage read operation is performed, the channels of the NAND string NS in the non-selected memory cell array 11 are boosted by coupling. Hereafter, this state will also be referred to as "full string boost".

[0288] During the period from time t1 to t2, the row decoder 26a increases the voltage of each word line WLa from voltage VSS to voltage VREAD. As a result, each memory cell transistor MC of the selection block BLK is turned ON.

[0289] The potential of the channel of the NAND string NS of the floating non-selected memory cell array 11 is boosted to voltage VCH1 by coupling with the word line WLa. Voltage VCH1 is higher than voltage VSS. At this time, IREAD2 is the charging current for charging voltage VREAD to the word line WLa. The channel of the non-selected memory cell array 11 is floating. Therefore, the charging capacity of the word line WLa is smaller than when voltage VSRC is applied to the channel, as explained in the first example of subpage read operation. Therefore, current IREAD2 is lower than current IREAD1.

[0290] 2.1.3 Timing Chart for the Third Example of Subpage Read Operation Next, the timing chart for the third example of subpage read operation will be described with reference to Figure 29. Figure 29 is a timing chart showing the voltage of each wiring in the third example of subpage read operation. The example shown in Figure 29 shows the case in which, during the subpage read operation of block BLK0, lower page data of subblock SBLK0_1 (memory cell array 11_1a) is read, but data from subblock SBLK0_2 (memory cell array 11_2a) is not read.

[0291] As shown in Figure 29, the voltages applied to the word line WLa, the selected gate lines SGD1a and SGS1a of the selected memory cell array 11, the source line SL1a, and the bit line BLa during the period from time t0 to t4 are the same as those in the first example of the subpage read operation described using Figure 27.

[0292] During the period from time t0 to t1, the source line driver 30 increases the voltage of the source line SL2a corresponding to the non-selected memory cell array 11 from voltage VSS to voltage VSRC.

[0293] The sense amplifier 27b boosts the voltage of the bit line BLb from voltage VSS to voltage VSRC.

[0294] During the period from time t1 to t2, the sense amplifier 27b boosts the voltage of the bit line BLb corresponding to the unselected memory cell array 11 from voltage VSS to voltage VBLRD.

[0295] During the period from time t0 to t2', the row decoder 26a increases the voltage of SGD2a from voltage VSS to voltage VSGDon. The row decoder 26a also increases the voltage of the selection gate line SGS2a from voltage VSS to voltage VSGSonn. As a result, the selection transistors ST1 and ST2 in the non-selected memory cell array 11 are turned ON.

[0296] During the period from time t2' to t2, the row decoder 26a steps down the voltage of SGD2a from voltage VSGDon to voltage VSGDoff. The row decoder 26a also steps down the voltage of the selected gate line SGS2a from voltage VSGSoon to voltage VSGSoff. As a result, the selection transistors ST1 and ST2 in the non-selected memory cell array 11 are turned off. In this example, during the period from time t2' to t4, the channels of the NAND string NS in the non-selected memory cell array 11 are in a floating state. During the period from time t2' to t4, that is, for a part of the period during which the subpage read operation is performed, the channels of the NAND string NS in the non-selected memory cell array 11 are boosted by coupling. Hereafter, this state will also be referred to as "partial string boost".

[0297] During the period from time t1 to t2, the row decoder 26a increases the voltage of each word line WLa from voltage VSS to voltage VREAD. As a result, each memory cell transistor MC of the selection block BLK is turned ON.

[0298] In the non-selected memory cell array 11, during the boosting of the word line WLb (time t2'), the channel of the NAND string NS is put into a floating state. The potential of the channel is boosted to voltage VCH2 by coupling with the word line WLa. Voltage VCH2 is lower than voltage VCH1. At this time, the charging current for charging voltage VREAD to the word line WLa is denoted as IREAD3. The channel of the non-selected memory cell array 11 is put into a floating state during the boosting of the word line WLa. Therefore, the charging capacity of the word line WLa is smaller than when voltage VSRC is applied to the channel, but larger than in full string boost. Consequently, current IREAD3 is higher than current IREAD3 and lower than current IREAD2.

[0299] 2.1.4 Timing Chart for the Fourth Example of Subpage Read Operation Next, the timing chart for the fourth example of subpage read operation will be described with reference to Figure 30. Figure 30 is a timing chart showing the voltage of each wiring in the second example of subpage read operation. The example shown in Figure 30 shows the case in which, during the subpage read operation of block BLK0, lower page data of subblock SBLK0_1 (memory cell array 11_1a) is read, but data from subblock SBLK0_2 (memory cell array 11_2a) is not read.

[0300] As shown in Figure 30, the voltages applied to the word line WLa, the selected gate lines SGD1a and SGS1a of the selected memory cell array 11, the source line SL1a, and the bit line BLa during the period from time t0 to t4 are the same as those in the first example of the subpage read operation described using Figure 27.

[0301] During the period from time t0 to t1, the source line driver 30 increases the voltage of the source line SL2a corresponding to the non-selected memory cell array 11 from voltage VSS to voltage VSRC.

[0302] The sense amplifier 27b boosts the voltage of the bit line BLb from voltage VSS to voltage VSRC.

[0303] During the period from time t1 to t2, the sense amplifier 27b boosts the voltage of the bit line BLb corresponding to the unselected memory cell array 11 from voltage VSS to voltage VBLCH. Voltage VBLCH is higher than voltage VBLRD.

[0304] During the period from time t0 to t2, the row decoder 26a increases the voltage of SGD2a from voltage VSS to voltage VSGDon. The row decoder 26a also increases the voltage of the selected gate line SGS2a from voltage VSS to voltage VSGSoff. As a result, in the non-selected memory cell array 11, the selection transistor ST1 is turned ON and the selection transistor ST2 is turned OFF. Consequently, the potential of the channel of the NAND string NS in the non-selected memory cell array 11 is increased to voltage VBLCH.

[0305] The channels of the NAND string NS in the non-selected memory cell array 11 are in a voltage floating state.

[0306] During the period from time t1 to t2, the row decoder 26a increases the voltage of each word line WLa from voltage VSS to voltage VREAD. At this time, the voltage increase rate of the word line WLa increases due to capacitive coupling with the channel of the non-selected memory cell array 11 to which voltage VBLCH is applied from the bit line BLb. For this reason, the length of the period from time t1 to t2 can be shortened compared to, for example, the first to third examples of subpage read operations.

[0307] 2.2 Effects of this embodiment This embodiment can be applied to the configuration according to the first embodiment. This provides the same effects as the first embodiment.

[0308] Furthermore, with the configuration according to this embodiment, a subpage read operation can be performed in a single block BLK, where data is read from the selected memory cell array 11 (array chip 10) and no data is read from the non-selected memory cell array 11 (array chip 10).

[0309] Furthermore, with the configuration according to this embodiment, full string boost or partial string boost can be performed in the non-selected memory cell array 11 (array chip 10) during subpage read operation. This reduces the charging current of the word line WL. Therefore, the increase in power consumption during read operation can be suppressed.

[0310] Furthermore, with the configuration according to this embodiment, in subpage read operation, the voltage of the bit line BL of the non-selected memory cell array 11 (array chip 10) can be made higher than the bit line BL of the selected memory cell array 11 (array chip 10). This allows the channel potential of the NAND string NS of the non-selected memory cell array 11 (array chip 10) to be raised to voltage VBLCH. Capacitive coupling between the channel of the NAND string NS of the non-selected memory cell array 11 (array chip 10) and the word line WL can increase the voltage boosting speed of the word line WL. As a result, the charging period of the word line WL can be shortened. Therefore, the processing capacity of the semiconductor memory device can be improved.

[0311] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, the case in which the number of array chips 10 included in the semiconductor memory device 1 is 3 or 4 will be described. The following description will focus on the differences from the first embodiment.

[0312] 3.1 Chip arrangement when a semiconductor memory device includes three array chips Next, an example of the arrangement of each chip will be described with reference to Figure 31. Figure 31 is a cross-sectional view showing an example of the arrangement of the circuit chip 20 and the array chips 10_1, 10_2, and 10_3. In the example shown in Figure 31, for the sake of simplicity, one word line WLa, WLb, and WLc and one bit line BLa, BLb, and BLc are shown for each. The selection gate lines SGD and SGS, and the source line SL are omitted. Furthermore, in the circuit chip 20, the command register 23, address register 24, sequencer 25, data register 28, column decoder 29, and source line driver 30 are omitted.

[0313] As shown in Figure 31, the semiconductor memory device 1 in this example includes a circuit chip 20 and three array chips 10_1, 10_2, and 10_3.

[0314] Array chip 10_1 includes memory cell arrays 11_1a, 11_1b, and 11_1c. Array chip 10_2 includes memory cell arrays 11_2a, 11_2b, and 11_2c. Array chip 10_3 includes memory cell arrays 11_3a, 11_3b, and 11_3c.

[0315] The circuit chip 20 includes three row decoders 26a, 26b, and 26c, and three sense amplifiers 27a, 27b, and 27c.

[0316] The semiconductor memory device 1 in this example has a bonded structure in which a circuit chip 20, array chip 10_1, array chip 10_2, and array chip 10_3 are bonded together. More specifically, in the Z2 direction, array chip 10_1 is provided on the circuit chip 20. Array chip 10_2 is provided on top of array chip 10_1. And array chip 10_3 is provided on top of array chip 10_2. The surfaces where the circuit chip 20 and array chip 10_1 are in contact, the surfaces where array chip 10_1 and array chip 10_2 are in contact, and the surfaces where array chip 10_2 and array chip 10_3 are in contact are bonded surfaces.

[0317] In the circuit chip 20, row decoders 26a, 26b, and 26c, and sense amplifiers 27a, 27b, and 27c are provided on the semiconductor substrate 200.

[0318] In the array chip 10_1, for example, memory cell arrays 11_1a, 11_1b, and 11_1c are arranged side by side in the Y direction. For example, in the Z2 direction, memory cell array 11_1a is provided above the row decoder 26a and sense amplifier 27a. In the Z2 direction, memory cell array 11_1b is provided above the row decoder 26b and sense amplifier 27b. Also, in the Z2 direction, memory cell array 11_1c is provided above the row decoder 26c and sense amplifier 27c.

[0319] In the array chip 10_2, for example, memory cell arrays 11_2a, 11_2b, and 11_2c are arranged side by side in the Y direction. In the Z2 direction, memory cell array 11_2a is located above memory cell array 11_1a. In the Z2 direction, memory cell array 11_2b is located above memory cell array 11_1b. In the Z2 direction, memory cell array 11_2c is located above memory cell array 11_1c.

[0320] In the array chip 10_3, for example, memory cell arrays 11_3a, 11_3b, and 11_3c are arranged side by side in the Y direction. In the Z2 direction, memory cell array 11_3a is located above memory cell array 11_2a. In the Z2 direction, memory cell array 11_3b is located above memory cell array 11_2b. In the Z2 direction, memory cell array 11_3c is located above memory cell array 11_2c.

[0321] For example, memory cell arrays 11_1a, 11_2a, and 11_3a are stacked in the Z direction. Similarly, memory cell arrays 11_1b, 11_2b, and 11_3b are stacked in the Z direction. Memory cell arrays 11_1c, 11_2c, and 11_3c are stacked in the Z direction.

[0322] One end of word line WLa is connected to row decoder 26a. Word line WLa is then commonly connected to memory cell arrays 11_1a, 11_2a, and 11_3a stacked in the Z direction. One end of word line WLb is connected to row decoder 26b. Word line WLb is then commonly connected to memory cell arrays 11_1b, 11_2b, and 11_3b stacked in the Z direction. One end of word line WLc is connected to row decoder 26c. Word line WLc is then commonly connected to memory cell arrays 11_1c, 11_2c, and 11_3c stacked in the Z direction.

[0323] Bit line BLa is connected to sense amplifier 27a. Bit line BLa is also commonly connected to memory cell arrays 11_1a, 11_3b, and 11_2c, which are located at different positions in the Z and Y directions. Bit line BLb is connected to sense amplifier 27b. Bit line BLb is also commonly connected to memory cell arrays 11_2a, 11_1b, and 11_3c, which are located at different positions in the Z and Y directions. Bit line BLc is connected to sense amplifier 27c. Bit line BLc is also commonly connected to memory cell arrays 11_3a, 11_2b, and 11_1c, which are located at different positions in the Z and Y directions. In other words, bit line BL is commonly connected to three memory cell arrays 11 that do not share word line WL and are located on different array chips 10.

[0324] 3.2 Chip arrangement when a semiconductor memory device includes four array chips Next, an example of the arrangement of each chip will be described with reference to Figure 32. Figure 32 is a cross-sectional view showing an example of the arrangement of the circuit chip 20 and array chips 10_1, 10_2, 10_3, and 10_4. In the example shown in Figure 32, for the sake of simplicity, one word line WLa, WLb, WLc, and WLd and one bit line BLa, BLb, BLc, and BLd are shown for each. The selection gate lines SGD and SGS, and the source line SL are omitted. Furthermore, in the circuit chip 20, the command register 23, address register 24, sequencer 25, data register 28, column decoder 29, and source line driver 30 are omitted.

[0325] As shown in Figure 32, the semiconductor memory device 1 in this example includes a circuit chip 20 and four array chips 10_1, 10_2, 10_3, and 10_4.

[0326] Array chip 10_1 includes memory cell arrays 11_1a, 11_1b, 11_1c, and 11_1d. Array chip 10_2 includes memory cell arrays 11_2a, 11_2b, 11_2c, and 11_2d. Array chip 10_3 includes memory cell arrays 11_3a, 11_3b, 11_3c, and 11_3d. Array chip 10_4 includes memory cell arrays 11_4a, 11_4b, 11_4c, and 11_4d.

[0327] The circuit chip 20 includes four row decoders 26a, 26b, 26c, and 26d, and four sense amplifiers 27a, 27b, 27c, and 27d.

[0328] The semiconductor memory device 1 in this example has a bonded structure in which a circuit chip 20, array chip 10_1, array chip 10_2, array chip 10_3, and array chip 10_4 are bonded together. More specifically, in the Z2 direction, array chip 10_1 is provided on the circuit chip 20. Array chip 10_2 is provided on array chip 10_1. Array chip 10_3 is provided on array chip 10_2. And array chip 10_4 is provided on array chip 10_3. The surfaces where the circuit chip 20 and array chip 10_1 are in contact, the surfaces where array chip 10_1 and array chip 10_2 are in contact, the surfaces where array chip 10_2 and array chip 10_3 are in contact, and the surfaces where array chip 10_3 and array chip 10_4 are in contact are bonded surfaces.

[0329] In the circuit chip 20, row decoders 26a, 26b, 26c, and 26d, and sense amplifiers 27a, 27b, 27c, and 27d are provided on the semiconductor substrate 200.

[0330] In the array chip 10_1, for example, memory cell arrays 11_1a, 11_1b, 11_1c, and 11_1d are arranged in the Y direction. For example, in the Z2 direction, memory cell array 11_1a is provided above the row decoder 26a and sense amplifier 27a. In the Z2 direction, memory cell array 11_1b is provided above the row decoder 26b and sense amplifier 27b. In the Z2 direction, memory cell array 11_1c is provided above the row decoder 26c and sense amplifier 27c. In the Z2 direction, memory cell array 11_1d is provided above the row decoder 26d and sense amplifier 27d.

[0331] In the array chip 10_2, for example, memory cell arrays 11_2a, 11_2b, 11_2c, and 11_2d are arranged in the Y direction. In the Z2 direction, memory cell array 11_2a is located above memory cell array 11_1a. In the Z2 direction, memory cell array 11_2b is located above memory cell array 11_1b. In the Z2 direction, memory cell array 11_2c is located above memory cell array 11_1c. In the Z2 direction, memory cell array 11_2d is located above memory cell array 11_1d.

[0332] In the array chip 10_3, for example, memory cell arrays 11_3a, 11_3b, 11_3c, and 11_3d are arranged in the Y direction. In the Z2 direction, memory cell array 11_3a is located above memory cell array 11_2a. In the Z2 direction, memory cell array 11_3b is located above memory cell array 11_2b. In the Z2 direction, memory cell array 11_3c is located above memory cell array 11_2c. In the Z2 direction, memory cell array 11_3d is located above memory cell array 11_2d.

[0333] In the array chip 10_4, for example, memory cell arrays 11_4a, 11_4b, 11_4c, and 11_4d are arranged in the Y direction. In the Z2 direction, memory cell array 11_4a is located above memory cell array 11_3a. In the Z2 direction, memory cell array 11_4b is located above memory cell array 11_3b. In the Z2 direction, memory cell array 11_4c is located above memory cell array 11_3c. In the Z2 direction, memory cell array 11_4d is located above memory cell array 11_3d.

[0334] For example, memory cell arrays 11_1a, 11_2a, 11_3a, and 11_4a are stacked in the Z direction. Similarly, memory cell arrays 11_1b, 11_2b, 11_3b, and 11_4b are stacked in the Z direction. Memory cell arrays 11_1c, 11_2c, 11_3c, and 11_4c are stacked in the Z direction. Memory cell arrays 11_1d, 11_2d, 11_3d, and 11_4d are stacked in the Z direction.

[0335] One end of word line WLa is connected to row decoder 26a. Word line WLa is then commonly connected to memory cell arrays 11_1a, 11_2a, 11_3a, and 11_4a stacked in the Z direction. One end of word line WLb is connected to row decoder 26b. Word line WLb is then commonly connected to memory cell arrays 11_1b, 11_2b, 11_3b, and 11_4b stacked in the Z direction. One end of word line WLc is connected to row decoder 26c. Word line WLc is then commonly connected to memory cell arrays 11_1c, 11_2c, 11_3c, and 11_4c stacked in the Z direction. One end of word line WLd is connected to row decoder 26d. Word line WLd is then commonly connected to memory cell arrays 11_1d, 11_2d, 11_3d, and 11_4d stacked in the Z direction.

[0336] Bit line BLa is connected to sense amplifier 27a. Bit line BLa is also commonly connected to memory cell arrays 11_1a, 11_4b, 11_3c, and 11_2d, which are located at different positions in the Z and Y directions. Bit line BLb is connected to sense amplifier 27b. Bit line BLb is also commonly connected to memory cell arrays 11_2a, 11_1b, 11_4c, and 11_3d, which are located at different positions in the Z and Y directions. Bit line BLc is connected to sense amplifier 27c. Bit line BLc is also commonly connected to memory cell arrays 11_3a, 11_2b, 11_1c, and 11_4d, which are located at different positions in the Z and Y directions. Bit line BLd is connected to sense amplifier 27d. The bit line BLd is connected in common to the memory cell arrays 11_4a, 11_3b, 11_2c, and 11_1d, which are located at different positions in the Z and Y directions. In other words, the bit line BL is connected in common to the four memory cell arrays 11, which do not share the word line WL and are located on different array chips 10.

[0337] 3.3 Effects of this embodiment Furthermore, with the configuration of this embodiment, the same effects as in the first embodiment can be obtained.

[0338] Furthermore, this embodiment may be combined with the second embodiment.

[0339] 4. Modified Examples The semiconductor memory device according to the above embodiment includes a first array chip (10_1) including a first memory cell array (11_1a) and a second memory cell array (11_1b), a second array chip (10_2) including a third memory cell array (11_2a) and a fourth memory cell array (11_2b), a first word line (WLa), a second word line (WLb), a first bit line (BLa), a second bit line (BLb), a first source line (SL1a), a second source line (SL1b), a third source line (SL2a) The first memory cell array includes a first memory cell array (MC), a first selection transistor (ST1), and a second selection transistor (ST2). The second memory cell array includes a second memory string (NS) containing a second memory cell (MC), a third selection transistor (ST1), and a fourth selection transistor (ST2), and is arranged adjacent to the first memory cell array in the first direction (Y direction). The third memory cell array includes a third memory string (NS) containing a third memory cell (MC), a fifth selection transistor (ST1), and a sixth selection transistor (ST2). The fourth memory cell array includes a fourth memory string (NS) containing a fourth memory cell (MC), a seventh selection transistor (ST1), and an eighth selection transistor (ST2), and is arranged adjacent to the third memory cell array in the first direction. The first word line is connected to the gates of the first and third memory cells, respectively. The second word line is connected to the gates of the second and fourth memory cells, respectively. The first bit line is connected to the first selection transistor and the seventh selection transistor. The second bit line is connected to the third selection transistor and the fifth selection transistor. The first source line is connected to the second selection transistor.The second source line is connected to the fourth selection transistor. The third source line is connected to the sixth selection transistor. The fourth source line is connected to the eighth selection transistor. The first selection gate line is connected to the gate of the first selection transistor. The second selection gate line is connected to the gate of the second selection transistor. The third selection gate line is connected to the gate of the third selection transistor. The fourth selection gate line is connected to the gate of the fourth selection transistor. The fifth selection gate line is connected to the gate of the fifth selection transistor. The sixth selection gate line is connected to the gate of the sixth selection transistor. The seventh selection gate line is connected to the gate of the seventh selection transistor. The eighth selection gate line is connected to the gate of the eighth selection transistor. The first row decoder is connected to the first word line, the first selection gate line, the second selection gate line, the fifth selection gate line, and the sixth selection gate line. The second row decoder is connected to the second word line, the third selection gate line, the fourth selection gate line, the seventh selection gate line, and the eighth selection gate line. The first sense amplifier is connected to the first bit line. The second sense amplifier is connected to the second bit line. During the write operation, different voltage application conditions are set for the first array chip and the second array chip.

[0340] By applying the above embodiment, a semiconductor memory device that can suppress a decrease in processing power can be provided.

[0341] Furthermore, the term "connection" in the above embodiment also includes a state in which the devices are indirectly connected by interposing something else, such as a transistor or a resistor.

[0342] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

Claims

A first memory cell array including a first memory cell, a first selection transistor, and a first memory string including a second selection transistor, A second memory string includes a second memory cell, a third selection transistor, and a fourth selection transistor, and the second memory cell array is arranged adjacent to the first memory cell array in a first direction. A first array chip including, A third memory cell array including a third memory cell, a fifth selection transistor, and a third memory string including a sixth selection transistor, A fourth memory string including a fourth memory cell, a seventh selection transistor, and an eighth selection transistor, the fourth memory cell array being arranged adjacent to the third memory cell array in the first direction A second array chip including, A first word line connected to the gates of the first memory cell and the third memory cell, A second word line connected to the gates of the second memory cell and the fourth memory cell, The first bit line connected to the first selection transistor and the seventh selection transistor, The second bit line connected to the third selection transistor and the fifth selection transistor, The first source line connected to the second selection transistor, The second source line connected to the fourth selection transistor, The third source line connected to the sixth selection transistor, The fourth source line connected to the eighth selection transistor, A first selection gate line connected to the gate of the first selection transistor, The second selection gate line connected to the gate of the second selection transistor, The third selection gate line connected to the gate of the third selection transistor, The fourth selection gate line connected to the gate of the fourth selection transistor, A fifth selection gate line connected to the gate of the fifth selection transistor, The sixth selection gate line connected to the gate of the sixth selection transistor, The seventh selection gate line connected to the gate of the seventh selection transistor, The eighth selection gate line connected to the gate of the eighth selection transistor, A first row decoder to which the first word line, the first selection gate line, the second selection gate line, the fifth selection gate line, and the sixth selection gate line are connected, A second row decoder to which the second word line, the third selection gate line, the fourth selection gate line, the seventh selection gate line, and the eighth selection gate line are connected, The first sense amplifier to which the first bit line is connected, The second sense amplifier to which the second bit line is connected and A circuit chip including, Equipped with, In the writing operation, different voltage application conditions are set for the first array chip and the second array chip. Semiconductor memory device. 　 The circuit chip, the first array chip, and the second array chip are bonded together in a second direction intersecting the first direction. The semiconductor memory device according to claim 1. 　 In a second direction intersecting the first direction, the third memory cell array is provided above the first memory cell array, and the fourth memory cell array is provided above the second memory cell array. The semiconductor memory device according to claim 1. 　 In the writing operation of the first memory cell and the third memory cell, The first sense amplifier applies one of the following to the first bit line: a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The second sense amplifier applies to the second bit line any of the following: a fourth voltage higher than the first voltage and lower than the second voltage, a fifth voltage higher than the second voltage and lower than the third voltage, and the third voltage. The semiconductor memory device according to claim 1. In the writing operation of the first memory cell and the third memory cell, The first sense amplifier applies one of the following to the first bit line: a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The second sense amplifier applies one of the first voltage, the second voltage, and the third voltage to the second bit line, and if either the first voltage or the second voltage is applied to the second bit line, it applies the third voltage after applying either the first voltage or the second voltage. The semiconductor memory device according to claim 1. 　 In the writing operation of the first memory cell and the third memory cell, When the first voltage is applied to the first bit line and the second bit line, the period during which the first voltage is applied to the second bit line is shorter than the period during which the first voltage is applied to the first bit line. When the second voltage is applied to the first bit line and the second bit line, the period during which the second voltage is applied to the second bit line is shorter than the period during which the second voltage is applied to the first bit line. The semiconductor memory device according to claim 5. 　 When the second sense amplifier applies the second voltage to the second bit line, the period during which the second voltage is applied to the second bit line is shorter than the period during which the program voltage is applied to the first word line. The semiconductor memory device according to claim 5. 　 In the writing operation of the first memory cell and the third memory cell, the first row decoder applies a sixth voltage to the first selected gate line for a first period, and applies the sixth voltage to the fifth selected gate line for a second period shorter than the first period. The semiconductor memory device according to claim 1. 　 In the writing operation of the first memory cell and the third memory cell, the first row decoder applies the sixth voltage to the fifth selection gate line while the program voltage is applied to the first word line. The semiconductor memory device according to claim 8. 　 In the writing operation of the first memory cell and the third memory cell, the first row decoder applies a seventh voltage to the second selected gate line during the third period, and applies the seventh voltage to the sixth selected gate line during the fourth period, which is shorter than the third period. The semiconductor memory device according to claim 1. 　 In the writing operation of the first memory cell and the third memory cell, the first row decoder applies an eighth voltage higher than the seventh voltage to the sixth selection gate line while the program voltage is applied to the first word line. The semiconductor memory device according to claim 10. 　 The sixth selection transistor is turned ON when the eighth voltage is applied. The semiconductor memory device according to claim 11. 　 In the erasure operation of the first memory cell and the third memory cell, A ninth voltage is applied to the first bit line and the first source line. A tenth voltage lower than the ninth voltage is applied to the second bit line and the third source line. An eleventh voltage is applied to the first and second selected gate lines. A twelfth voltage lower than the eleventh voltage is applied to the fifth and sixth selection gate lines. The semiconductor memory device according to claim 1. 　 In the read operation of the first memory cell and the third memory cell, the sense time of the second bit line is shorter than the sense time of the first bit line. The semiconductor memory device according to claim 1. 　 In the read operation of the first memory cell and the third memory cell, The first sense amplifier applies a 13th voltage to the first bit line. The second sense amplifier applies a 14th voltage lower than the 13th voltage to the second bit line. The semiconductor memory device according to claim 1. 　 If the data from the first memory cell is read, but the data from the third memory cell is not read, The first row decoder applies a 14th voltage to the first selected gate line and a 15th voltage lower than the 14th voltage to the fifth selected gate line. The first sense amplifier applies a 16th voltage to the first bit line. The second sense amplifier applies a 17th voltage lower than the 16th voltage to the second bit line. The semiconductor memory device according to claim 1. 　 If the data from the first memory cell is read, but the data from the third memory cell is not read, The first row decoder applies a voltage 18 to the first selected gate line, a voltage 19 to the second selected gate line, a voltage 20 lower than the voltage 18 to the fifth selected gate line, and a voltage 21 lower than the voltage 19 to the sixth selected gate line. The first sense amplifier applies a 22nd voltage to the first bit line. The second sense amplifier applies the 22nd voltage to the second bit line. The semiconductor memory device according to claim 1. 　 During the period when the 20th voltage is applied to the 5th selection gate line, the 5th selection transistor is in the off state. During the period when the 21st voltage is applied to the 6th selection gate line, the 6th selection transistor is in the off state. The third memory string is in a floating state. The semiconductor memory device according to claim 17. 　 If the data from the first memory cell is read and the data from the third memory cell is not read, the first row decoder applies the voltage 18 to the fifth selection gate line, followed by the voltage 20, and applies the voltage 19 to the sixth selection gate line, followed by the voltage 21. The semiconductor memory device according to claim 17. 　 If the data from the first memory cell is read, but the data from the third memory cell is not read, The first row decoder applies a 24th voltage to the first and fifth selected gate lines, a 22nd voltage to the second selected gate line, and a 23rd voltage lower than the 22nd voltage to the sixth selected gate line. The first sense amplifier applies a 24th voltage to the first bit line. The second sense amplifier applies a 25th voltage higher than the 24th voltage to the second bit line. The semiconductor memory device according to claim 1.

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