Multilayer ceramic capacitor

Abstract

This multilayer ceramic capacitor comprises: a capacitor body (100); a plurality of first via conductors (140) and a plurality of second via conductors (150) provided inside the capacitor body (100); and a resin part (20) covering a peripheral side face (103) of the capacitor body (100) and having a flat first end face (21) on one side in the lamination direction. Respective first ends (T1) of the plurality of first via conductors (140) and of the plurality of second via conductors (150) exposed from a first main surface (101) have a maximum height difference of 1.5 um or less in the lamination direction. The respective first ends (T1) of the plurality of first via conductors (140) and of the plurality of second via conductors (150) and the first main surface (101) are located in a space (A) surrounded by the resin part (20).

Description

Multilayer ceramic capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] As a prior art document disclosing the structure of a ceramic capacitor, there is JP-A-2005-136231 (Patent Document 1). The ceramic capacitor described in Patent Document 1 is formed by sintering a conductor material containing Ni particles inside a laminate formed by laminating a plurality of dielectric layers, and includes an internal electrode interposed between adjacent dielectric layers, and a via conductor formed by sintering a conductor material containing Cu particles and Ni particles and connected to the internal electrode. It is a ceramic electronic component in which the via conductor is embedded.

[0003] JP-A-2005-136231

[0004] When the laminate is fired, warping may occur in the laminate. When warping occurs in the laminate, variations occur in the positions of the end faces of the plurality of via conductors, and it is impossible to stably and electrically connect the end faces of the plurality of via conductors to the electrodes of the mounting substrate.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a multilayer ceramic capacitor capable of stably and electrically connecting the end faces of a plurality of via conductors to the electrodes of a mounting substrate.

[0006] The multilayer ceramic capacitor according to the present invention comprises a capacitor body, a plurality of first via conductors, a plurality of second via conductors, and a resin part. The capacitor body includes a plurality of first internal electrode layers and a plurality of second internal electrode layers that are alternately stacked one layer at a time in the stacking direction with a dielectric layer in between, and has a first main surface, a second main surface located on the opposite side of the stacking direction from the first main surface, and a circumferential surface connecting the first main surface and the second main surface. The plurality of first via conductors are provided inside the capacitor body and are electrically connected to the plurality of first internal electrode layers. The plurality of second via conductors are provided inside the capacitor body and are electrically connected to the plurality of second internal electrode layers. The resin part covers the circumferential surface of the capacitor body and has a flat first end surface on one side in the stacking direction. The maximum height difference in the stacking direction of the first ends of each of the plurality of first via conductors and plurality of second via conductors exposed from the first main surface is 1.5 μm or less. The first ends and first main surfaces of each of the multiple first via conductors and the multiple second via conductors are located within a space surrounded by a resin portion.

[0007] According to the present invention, the end faces of multiple via conductors can be stably electrically connected to electrodes on a mounting substrate.

[0008] This is a perspective view of a multilayer ceramic capacitor according to Embodiment 1 of the present invention, viewed from the first main surface side. This is a plan view of the multilayer ceramic capacitor in Figure 1. This is a cross-sectional view of the multilayer ceramic capacitor in Figure 2, viewed from the direction of the arrow III-III. This is a schematic cross-sectional view showing the detailed dimensional relationship of the first main surface side of the multilayer ceramic capacitor according to Embodiment 1 of the present invention. This is a cross-sectional view showing the fired laminate embedded in resin. This is a photograph of the first main surface side of the multilayer ceramic capacitor according to the embodiment. This is a graph showing the change in height at each position from the first line to the fifth line in Figure 6. This is a cross-sectional view of a multilayer ceramic capacitor according to a modified example of Embodiment 1 of the present invention. This is a cross-sectional view of a multilayer ceramic capacitor according to Embodiment 2 of the present invention. This is a cross-sectional view of a multilayer ceramic capacitor according to a modified example of Embodiment 2 of the present invention.

[0009] Hereinafter, multilayer ceramic capacitors according to each embodiment of the present invention will be described with reference to the figures. In the following description of embodiments, the same or corresponding parts in the figures will be denoted by the same reference numerals, and their descriptions will not be repeated.

[0010] (Embodiment 1) Figure 1 is a perspective view of a multilayer ceramic capacitor according to Embodiment 1 of the present invention, viewed from the first main surface side. Figure 2 is a plan view of the multilayer ceramic capacitor of Figure 1. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor of Figure 2, viewed from the direction of the arrow III-III.

[0011] As shown in Figures 1 to 3, the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention comprises a capacitor body 100, a plurality of first via conductors 140, and a resin part 20.

[0012] As shown in Figure 3, the capacitor body 100 includes a plurality of first internal electrode layers 120 and a plurality of second internal electrode layers 130 that are alternately stacked one layer at a time in the stacking direction (Z-axis direction) with a dielectric layer 110 in between, and has a first main surface 101, a second main surface 102 located on the opposite side of the stacking direction (Z-axis direction) from the first main surface 101, and a circumferential surface 103 connecting the first main surface 101 and the second main surface 102.

[0013] The dielectric layer 110 is made of a ceramic material mainly composed of, for example, BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3. These main components may also contain a secondary component selected from the group consisting of Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds, in a lower content than the main components. The Vickers hardness of the dielectric layer 110 is preferably 800 HV or more and 1100 HV or less.

[0014] The shape of the capacitor body 100 is arbitrary. In this embodiment, the capacitor body 100 has a rectangular parallelepiped shape overall. A rectangular parallelepiped shape overall means a shape that is not a perfect rectangular parallelepiped, for example, a rectangular parallelepiped with rounded corners and edges, but has six surfaces and can be considered as a rectangular parallelepiped overall. The peripheral surface 103 of the capacitor body 100 constitutes four surfaces of the capacitor body 100 other than the first main surface 101 and the second main surface 102.

[0015] The dimensions of the capacitor body 100 are, for example, as viewed from the first main surface 101, such that the vertical dimension (Y-axis direction) of the rectangle is 0.3 mm or more and 3.0 mm or less, the horizontal dimension (X-axis direction) is 0.3 mm or more and 3.0 mm or less, and the total dimension of the dielectric layer 110, the first internal electrode layer 120, and the second internal electrode layer 130 in the stacking direction (Z-axis direction) is 50 μm or more and 200 μm or less. The dimension of the capacitor body 100 in the stacking direction (Z-axis direction) is the distance in the stacking direction (Z-axis direction) from the position on the first main surface 101 that is closest to the other side of the stacking direction (Z-axis direction) on the second main surface 102.

[0016] Each of the multiple first internal electrode layers 120 has a rectangular shape when viewed from the stacking direction (Z-axis direction). The second internal electrode layer 130 has a rectangular shape that is substantially the same as that of the first internal electrode layer 120 when viewed from the stacking direction (Z-axis direction). As shown in Figure 3, each of the multiple first internal electrode layers 120 has multiple first through holes 120h formed therein for inserting multiple second via conductors 150. Each of the multiple second internal electrode layers 130 has multiple second through holes 130h formed therein for inserting multiple first via conductors 140.

[0017] The material of the first internal electrode layer 120 and the second internal electrode layer 130 mainly contains metals such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or alloys containing these metals. The first internal electrode layer 120 and the second internal electrode layer 130 may also contain the same ceramic material as the dielectric ceramic contained in the dielectric layer 110 as a common material. In that case, the proportion of the common material contained in the first internal electrode layer 120 and the second internal electrode layer 130 is, for example, 20 vol% or less.

[0018] The thickness of the first internal electrode layer 120 and the second internal electrode layer 130 is, for example, approximately 0.3 μm to 1.0 μm. The number of layers of the first internal electrode layer 120 and the second internal electrode layer 130 is arbitrary, but the total number of layers is, for example, approximately 2 to 150.

[0019] In the multilayer ceramic capacitor 1, capacitance is formed when the first internal electrode layer 120 and the second internal electrode layer 130 face each other via the dielectric layer 110.

[0020] As shown in Figures 1 to 3, the resin part 20 covers the peripheral surface 103 of the capacitor body 100. The resin part 20 has a rectangular ring shape when viewed from the first main surface 101 side. However, the outer shape of the resin part 20 when viewed from the first main surface 101 side is not limited to a rectangle.

[0021] The resin portion 20 has a flat first end face 21 on one side in the lamination direction (Z-axis direction). As shown in Figure 3, in this embodiment, the resin portion 20 has a flat second end face 22 on the other side in the lamination direction (Z-axis direction). The second end face 22 is located substantially parallel to the first end face 21.

[0022] The resin portion 20 does not cover the first main surface 101 and the second main surface 102. However, the resin portion 20 may cover the peripheral edge of the first main surface 101. The resin portion 20 may also cover the peripheral edge of the second main surface 102. The resin portion 20 is made of a thermosetting resin such as epoxy resin, phenolic resin, or silicone resin.

[0023] As shown in Figure 3, the multiple first via conductors 140 are provided inside the capacitor body 100 and are electrically connected to the multiple first internal electrode layers 120. The multiple first via conductors 140 pass through second through holes 130h formed in each of the multiple second internal electrode layers 130 and are insulated from the multiple second internal electrode layers 130.

[0024] Each of the multiple first via conductors 140 is provided inside the capacitor body 100 in such a manner that it extends in the stacking direction (Z-axis direction) from the first main surface 101 to the second main surface 102 of the capacitor body 100. Each of the multiple first via conductors 140 is exposed from the first main surface 101.

[0025] In this embodiment, the first end T1 of each of the multiple first via conductors 140 on one side in the stacking direction (Z-axis direction) protrudes from the first main surface 101. Note that the first end T1 of each of the multiple first via conductors 140 only needs to be exposed from the first main surface 101 and may be substantially flush with the first main surface 101. Each of the multiple first via conductors 140 is exposed from the second main surface 102. The second end T2 of each of the multiple first via conductors 140 on the other side in the stacking direction (Z-axis direction) protrudes from the second main surface 102. Note that the second end T2 of each of the multiple first via conductors 140 only needs to be exposed from the second main surface 102 and may be substantially flush with the second main surface 102.

[0026] As shown in Figure 3, the multiple second via conductors 150 are provided inside the capacitor body 100 and are electrically connected to the multiple second internal electrode layers 130. The multiple second via conductors 150 are inserted through the first through holes 120h formed in each of the multiple first internal electrode layers 120 and are insulated from the multiple first internal electrode layers 120.

[0027] In this embodiment, the multiple first via conductors 140 and the multiple second via conductors 150 are arranged alternately in the row direction (X-axis direction) and the column direction (Y-axis direction). Because the multiple first via conductors 140 and the multiple second via conductors 150 are arranged alternately in the row direction (X-axis direction) and the column direction (Y-axis direction), the magnetic fields induced by the currents flowing through the first via conductors 140 and the second via conductors 150 cancel each other out, thereby lowering the equivalent series inductance (ESL) of the multilayer ceramic capacitor 1.

[0028] Each of the multiple second via conductors 150 is provided inside the capacitor body 100 in such a manner that it extends in the stacking direction from the first main surface 101 toward the second main surface 102 of the capacitor body 100. Each of the multiple second via conductors 150 is exposed from the first main surface 101.

[0029] In this embodiment, the first end T1 on one side of each of the multiple second via conductors 150 in the stacking direction (Z-axis direction) protrudes from the first main surface 101. Note that the first end T1 of each of the multiple second via conductors 150 only needs to be exposed from the first main surface 101, and may be substantially flush with the first main surface 101. Each of the multiple second via conductors 150 is exposed from the second main surface 102. The second end T2 on the other side of each of the multiple second via conductors 150 in the stacking direction (Z-axis direction) protrudes from the second main surface 102. Note that the second end T2 of each of the multiple second via conductors 150 only needs to be exposed from the second main surface 102, and may be substantially flush with the second main surface 102.

[0030] As shown in Figures 1 and 3, the first end T1 and first main surface 101 of each of the multiple first via conductors 140 and multiple second via conductors 150 are located within the space A surrounded by the resin portion 20. That is, the first end surface 21 of the resin portion 20 is located on one side in the stacking direction (Z-axis direction) relative to the first end T1 and first main surface 101 of each of the multiple first via conductors 140 and multiple second via conductors 150. The first main surface 101 is recessed on the other side in the stacking direction (Z-axis direction) relative to the first end surface 21 of the resin portion 20. The first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 is located within the range between the position of the first end surface 21 and the position of the first main surface 101 of the resin portion 20 in the stacking direction (Z-axis direction).

[0031] As shown in Figure 3, the second end T2 and second main surface 102 of each of the multiple first via conductors 140 and multiple second via conductors 150 are located within the space B surrounded by the resin portion 20. That is, the second end surface 22 of the resin portion 20 is located on the other side in the stacking direction (Z-axis direction) relative to the second end T2 and second main surface 102 of each of the multiple first via conductors 140 and multiple second via conductors 150. The second main surface 102 is recessed on one side in the stacking direction (Z-axis direction) relative to the second end surface 22 of the resin portion 20. The second end T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 is located within the range between the position of the second end surface 22 and the position of the second main surface 102 of the resin portion 20 in the stacking direction (Z-axis direction).

[0032] Figure 4 is a schematic cross-sectional view showing the details of the dimensional relationship on the first main surface side of a multilayer ceramic capacitor according to Embodiment 1 of the present invention. As shown in Figure 4, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101 is 1.5 μm or less. Preferably, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 is 1.0 μm or less. Even more preferably, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 is 0.5 μm or less.

[0033] Similarly, the maximum height difference in the stacking direction (Z-axis direction) of the second end T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the second main surface 102 is 1.5 μm or less. Preferably, the maximum height difference in the stacking direction (Z-axis direction) of the second end T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 is 1.0 μm or less. Even more preferably, the maximum height difference in the stacking direction (Z-axis direction) of the second end T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 is 0.5 μm or less.

[0034] As shown in Figure 4, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 is smaller than the maximum height difference Hg2 in the stacking direction (Z-axis direction) of the first main surface 101. That is, the relationship Hg1 < Hg2 is satisfied. However, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 may be greater than or equal to the maximum height difference Hg2 in the stacking direction (Z-axis direction) of the first main surface 101. That is, the relationship Hg1 ≥ Hg2 may be satisfied. Hg2 is, for example, 0.5 μm or more and 3 μm or less. In Figure 4, the peripheral portion of the first main surface 101 is shown as being located on one side in the stacking direction (Z-axis direction) from the central portion. However, the diagram is not limited to this configuration, and the central portion of the first main surface 101 may also be located on one side in the stacking direction (Z-axis direction) from the peripheral portion.

[0035] Similarly, the maximum height difference in the stacking direction (Z-axis direction) of the second ends T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 is smaller than the maximum height difference in the stacking direction (Z-axis direction) of the second main surface 102. However, the maximum height difference in the stacking direction (Z-axis direction) of the second ends T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 may be greater than or equal to the maximum height difference in the stacking direction (Z-axis direction) of the second main surface 102. The maximum height difference in the stacking direction (Z-axis direction) of the second main surface 102 is, for example, 0.5 μm or more and 3 μm or less. The peripheral portion of the second main surface 102 may be located on the other side of the stacking direction (Z-axis direction) from the central portion, or the central portion of the second main surface 102 may be located on the other side of the stacking direction (Z-axis direction) from the peripheral portion.

[0036] As shown in Figure 4, the distance Lg3 in the stacking direction (Z-axis direction) between the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 that is located on the farther side in the stacking direction (Z-axis direction) and the portion of the first main surface 101 that is located on the farther side in the stacking direction (Z-axis direction) is preferably 1.2 μm or less. It is even more preferable that the distance Lg3 is 0.1 μm or more and 1 μm or less.

[0037] Similarly, the distance in the stacking direction (Z-axis direction) between the second end T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 that is located on the furthest side in the stacking direction (Z-axis direction) and the portion of the second main surface 102 that is located on the furthest side in the stacking direction (Z-axis direction) is preferably 1.2 μm or less. It is even more preferable that this distance be 0.1 μm or more and 1 μm or less.

[0038] The shapes of the first via conductor 140 and the second via conductor 150 are arbitrary, for example, cylindrical. In that case, the diameters of the first via conductor 140 and the second via conductor 150 are, for example, approximately 20 μm to 150 μm. Also, the distance between adjacent first via conductors 140 and second via conductors 150, more specifically, the distance between the center of the first via conductor 140 and the center of the second via conductor 150, is, for example, approximately 50 μm to 500 μm.

[0039] The material of the first via conductor 140 and the second via conductor 150 can be, for example, a metal such as Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy containing such metals.

[0040] Here, a method for manufacturing a multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention will be described. First, a ceramic green sheet and a conductive paste are prepared. From the prepared ceramic green sheet, the conductive paste is screen printed in a predetermined pattern onto the ceramic green sheet on which the first internal electrode layer 120 and the second internal electrode layer 130 will be formed. This predetermined pattern is, for example, a rectangle with a plurality of circular gaps. This forms the conductive pattern that will become the first internal electrode layer 120 and the second internal electrode layer 130.

[0041] Next, a predetermined number of ceramic green sheets printed with conductive patterns that will form the first internal electrode layer 120 and the second internal electrode layer 130 are stacked, and a predetermined number of ceramic green sheets without the conductive patterns that will form the first internal electrode layer 120 and the second internal electrode layer 130 are stacked on the upper and lower sides in the stacking direction. This creates a mother laminate. The mother laminate is then compressed from both sides in the stacking direction by a hydrostatic press or the like, as needed.

[0042] Next, multiple via holes are formed in the stacking direction of the mother stack by laser irradiation or NC turret punching. In this embodiment, the via holes are formed in a matrix.

[0043] Next, conductive paste is filled into the via holes by screen printing to form the first via conductor 140 and the second via conductor 150. At this time, it is preferable to apply a mask to the main surface of the mother laminate to prevent the conductive paste from adhering to parts other than the via holes. Furthermore, it is preferable to suction the conductive paste from the opening opposite the opening into which the conductive paste is filled in, in order to facilitate the passage of the conductive paste into the via holes.

[0044] Next, the mother laminate is cut into a predetermined size to obtain an unfired ceramic laminate. This unfired ceramic laminate is fired within a temperature range of 900°C or higher and 1300°C or lower in an atmosphere of air, nitrogen, or a mixed gas of water vapor and nitrogen. Thereby, a fired laminate is obtained.

[0045] FIG. 5 is a cross-sectional view showing a state where the fired laminate is embedded in a resin. Next, as shown in FIG. 5, the fired laminate 100f is embedded in the resin 200 to form an embedded body 300. In FIG. 5, a state where one fired laminate 100f is embedded in the resin 200 is illustrated, but it is not limited thereto, and a plurality of laminates 100f arranged in a matrix with a gap therebetween may be embedded in the resin 200. In FIG. 5, the state where the laminate 100f is warped by firing is exaggeratedly shown.

[0046] Next, lapping and polishing are performed on the upper and lower surfaces of the laminate 100f to flatten them. As shown in FIG. 5, the upper surface of the laminate 100f is flattened by performing polishing so that the polished surface CL1 is exposed. The lower surface of the laminate 100f is flattened by performing polishing so that the polished surface CL2 is exposed.

[0047] The lapping and polishing apparatus includes an upper platen and a lower platen. A carrier, which is a disk with holes formed therein, is placed on the lower platen. An embedded body 300 is disposed inside the holes. When performing lapping and polishing, the upper platen is lowered to sandwich the carrier between the upper platen and the lower platen from the vertical direction. After that, while injecting a slurry mixed with abrasive grains, the upper platen and the lower platen are rotated. As a result, with the embedded body 300 fixed by the carrier, the upper surface of the embedded body 300 is polished, and the polished surface CL1 is exposed. Note that the pressure for sandwiching the carrier between the upper platen and the lower platen, the rotation speed for rotating the upper platen and the lower platen, the material and particle size of the abrasive grains, etc. are appropriately adjusted according to the configuration of the multilayer ceramic capacitor 1. When polishing the lower surface of the embedded body 300 as well, the embedded body 300 is turned upside down and disposed inside the holes, and polishing is performed in the same manner as the upper surface of the embedded body 300. At that time, polishing may be performed until the polished surface CL2 is exposed, or polishing may be finished with the polished surface covered with the resin 200. Through the above steps, the multilayer ceramic capacitor 1 is completed.

[0048] In lapping and polishing, since the slurry mixed with abrasive grains moves substantially parallel to the upper surface of the laminate 100f, the laminate 100f formed of a brittle ceramic is cut, while the first via conductor 140 and the second via conductor 150 having ductility are stretched without being cut off. Therefore, the upper end portions of the first via conductor 140 and the second via conductor 150 protrude from the upper surface of the capacitor body 100. Further, since the upper surface of the laminate 100f is cut, the upper surface is flattened, and the warpage amount of the laminate 100f is reduced. Furthermore, since the oxide film existing on the surfaces of the first via conductor 140 and the second via conductor 150 is removed, the electrical resistance value at the upper end portions of the first via conductor 140 and the second via conductor 150 is reduced.

[0049] When polishing the lower surface of the laminate 100f following the polishing of the upper surface of the laminate 100f, the slurry containing abrasive particles moves against the lower surface of the laminate 100f. As a result, the lower surface of the laminate 100f, which is made of brittle ceramic, is scraped away, while the ductile first via conductor 140 and second via conductor are stretched without being scraped away. Therefore, the lower ends of the first via conductor 140 and second via conductor protrude from the lower surface of the capacitor body 100. In addition, since the lower surface of the laminate 100f is scraped away, the lower surface is flattened, and the amount of warping of the laminate 100f is reduced. Furthermore, since the oxide film present on the surfaces of the first via conductor 140 and second via conductor 150 is removed, the electrical resistance values ​​at the lower ends of the first via conductor 140 and second via conductor 150 are reduced.

[0050] The first end face 21 of the resin portion 20, formed by polishing the ductile resin 200 by lapping, protrudes from the first main surface 101 of the capacitor body 100 to one side in the stacking direction (Z-axis direction). Similarly, if the lower surface of the laminate 100f is also polished, the second end face 22 of the resin portion 20 protrudes from the second main surface 102 of the capacitor body 100 to the other side in the stacking direction (Z-axis direction).

[0051] Since the first via conductor 140 and the second via conductor 150 are more ductile than the resin 200, the first via conductor 140 and the second via conductor 150 are stretched more than the resin 200 in the in-plane direction perpendicular to the lamination direction (Z-axis direction), resulting in a shorter protrusion length from the first main surface 101 in the lamination direction (Z-axis direction). As a result, the first end T1 on one side of the lamination direction (Z-axis direction) of each of the multiple first via conductors 140 and the multiple second via conductors 150 is located on the other side of the lamination direction (Z-axis direction) from the first end surface 21 of the resin portion 20. Similarly, the second end T2 on the other side of the lamination direction (Z-axis direction) of each of the multiple first via conductors 140 and the multiple second via conductors 150 is located on one side of the lamination direction (Z-axis direction) from the second end surface 22 of the resin portion 20.

[0052] In addition to lapping, other processing methods such as ultrasonic machining, blasting, and barrel polishing exist, but for the following reasons, processing methods other than lapping are not suitable for processing the top and bottom surfaces of the laminate 100f. First, ultrasonic machining and barrel polishing have weak polishing power, making it difficult to adequately polish the sintered laminate 100f. With blasting, abrasive particles are blasted perpendicularly to the top and bottom surfaces of the laminate 100f, so there is a risk that the ends of the first via conductor 140 and the second via conductor 150 will be pushed into the interior of the laminate 100f.

[0053] The ceramic green sheet and conductive paste contain a binder and a solvent, and known organic binders and organic solvents can be used for this binder and solvent.

[0054] According to the multilayer ceramic capacitor 1 of this embodiment described above, the upper surface of the laminate 100f is flattened after firing. Therefore, even if the laminate 100f warps during firing, the flattening process can suppress variations in the height of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 in the stacking direction (Z-axis direction).

[0055] Furthermore, the flattened first end face 21 of the resin portion 20 can be positioned on the furthest side in the stacking direction (Z-axis direction) of the multilayer ceramic capacitor 1. That is, the first end T1 of each of the multiple first via conductors 140 and the multiple second via conductors 150 is located within the space A surrounded by the resin portion 20.

[0056] As a result, by mounting the multilayer ceramic capacitor 1 onto the mounting substrate with the first end face 21 of the resin part 20 in contact with the mounting substrate, the first ends T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate. Furthermore, tilting of the multilayer ceramic capacitor 1 during mounting can be suppressed. In addition, when mounting the multilayer ceramic capacitor 1, which is held by the mounter, onto the mounting substrate, the first end face 21 of the resin part 20 comes into contact with the mounting substrate, which mitigates the impact on the capacitor body 100 and suppresses damage to the capacitor body 100.

[0057] In this embodiment, the lower surface of the laminate 100f is flattened after firing. Therefore, even if the laminate 100f warps during firing, the flattening process can suppress variations in the height of the second end T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 in the stacking direction (Z-axis direction).

[0058] Furthermore, the flattened second end face 22 of the resin portion 20 can be positioned on the farthest side in the stacking direction (Z-axis direction) of the multilayer ceramic capacitor 1. That is, the second ends T2 of each of the multiple first via conductors 140 and the multiple second via conductors 150 are located within the space B surrounded by the resin portion 20.

[0059] As a result, by mounting the multilayer ceramic capacitor 1 onto the mounting substrate with the second end face 22 of the resin part 20 in contact with the mounting substrate, the second ends T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate. Furthermore, tilting of the multilayer ceramic capacitor 1 during mounting can be suppressed. In addition, when mounting the multilayer ceramic capacitor 1, which is held by the mounter, onto the mounting substrate, the second end face 22 of the resin part 20 comes into contact with the mounting substrate, which mitigates the impact on the capacitor body 100 and prevents damage to the capacitor body 100.

[0060] In the above manufacturing method, via holes are formed after the mother stack is fabricated, and conductive paste is filled into the via holes to form via conductors. However, the method of forming via conductors is not limited to this. For example, via holes may be formed in a ceramic green sheet, conductive paste may be filled into the via holes, and then the ceramic green sheets may be stacked to fabricate the mother stack.

[0061] Furthermore, in the above manufacturing method, the mother laminate was cut before firing the unfired laminate, but the procedure for producing the laminate is not limited to this. For example, notches may be formed at the planned cutting positions of the mother laminate, the mother laminate may be fired, and the fired mother laminate may be divided along the notches to produce the laminate.

[0062] (Experimental Example) This section describes experimental examples of measurements taken for a multilayer ceramic capacitor according to the embodiment and a multilayer ceramic capacitor according to a comparative example, which does not have a resin part and whose main surfaces on both sides of the capacitor body are not polished. These measurements concern the maximum height difference and variation of the first ends T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 in the stacking direction (Z-axis direction), as well as the maximum height difference of the first main surface 101 in the stacking direction (Z-axis direction).

[0063] In each of the multilayer ceramic capacitors according to the Examples and Comparative Examples, the dielectric layer 110 was made of BaTiO3. The first internal electrode layer 120 and the second internal electrode layer 130 were made of Ni. The first via conductor 140 and the second via conductor 150 were made of Ni. The first via conductor 140 and the second via conductor 150 were formed to have a diameter of 30 μm after firing. The total number of first via conductors 140 and second via conductors 150 was 12. The firing temperature was 1250°C. The dimensions of the laminate 100f after firing were 0.7 mm in length, 0.7 mm in width, and 90 μm in thickness. The resin part 20 of the multilayer ceramic capacitor according to the Examples was made of epoxy resin. The height of each component was measured using a white light interferometer.

[0064] Figure 6 is a photograph of the first main surface side of a multilayer ceramic capacitor according to the embodiment. Figure 7 is a graph showing the change in height at each position from the first line to the fifth line in Figure 6. In Figure 7, the vertical axis shows height (μm) and the horizontal axis shows the horizontal position (mm). In Figures 6 and 7, the first line L1 is shown as a thick dotted line, the second line L2 as a dashed line, the third line L3 as a solid line, the fourth line L4 as a thin dotted line, and the fifth line L5 as a double dashed line.

[0065] As shown in Figure 7, the first end T1 of each of the multiple first via conductors 140 and the multiple second via conductors 150 protrudes from the first main surface 101. The first end T1 of each of the multiple first via conductors 140 and the multiple second via conductors 150, and the first main surface 101, are located within a space A surrounded by the resin portion 20.

[0066] The maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101 was 1.07 μm in the example and 2.95 μm in the comparative example. The height variation (standard deviation) in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101 was 0.307 in the example and 0.917 in the comparative example. From these results, it was confirmed that the multilayer ceramic capacitor according to the example satisfies the requirement that the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101 is 1.5 μm or less. Furthermore, it was confirmed that the multilayer ceramic capacitor according to the embodiment can reduce the variation in height in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101, compared to the multilayer ceramic capacitor according to the comparative example.

[0067] The maximum height difference Hg2 in the stacking direction (Z-axis direction) of the first main surface 101 was 1.47 μm in the example and 3.99 μm in the comparative example. From these results, it was confirmed that the multilayer ceramic capacitor according to the example satisfies the relationship Hg1 < Hg2. Furthermore, it was confirmed that the multilayer ceramic capacitor according to the example can reduce the maximum height difference Hg2 compared to the multilayer ceramic capacitor according to the comparative example.

[0068] The maximum height difference in the stacking direction (Z-axis direction) of the first end face 21 of the resin portion 20 of the multilayer ceramic capacitor according to the embodiment was 0.518 μm. From this result, it was confirmed that the maximum height difference in the stacking direction (Z-axis direction) of the first end face 21 of the resin portion 20 of the multilayer ceramic capacitor is smaller than the maximum height difference Hg2 in the stacking direction (Z-axis direction) of the first main surface 101.

[0069] In the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101 is 1.5 μm or less. The first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 and the first main surface 101 are located within a space A surrounded by the resin portion 20. As a result, by mounting the multilayer ceramic capacitor 1 on a mounting substrate with the first end face 21 of the resin portion 20 in contact with the mounting substrate, the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate.

[0070] In the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention, the maximum height difference in the stacking direction (Z-axis direction) of the second ends T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the second main surface 102 is 1.5 μm or less. The second ends T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 and the second main surface 102 are located within the space B surrounded by the resin portion 20. As a result, by mounting the multilayer ceramic capacitor 1 on the mounting substrate with the second end surface 22 of the resin portion 20 in contact with the mounting substrate, the second ends T2 of each of the multiple first via conductors 140 and multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate.

[0071] In the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the plurality of first via conductors 140 and plurality of second via conductors 150 is smaller than the maximum height difference Hg2 in the stacking direction (Z-axis direction) of the first main surface 101. This reduces the height variation in the stacking direction (Z-axis direction) of the first end T1 of each of the plurality of first via conductors 140 and plurality of second via conductors 150 exposed from the first main surface 101, and enables stable electrical connection of the first end T1 of each of the plurality of first via conductors 140 and plurality of second via conductors 150 by the electrodes of the mounting substrate.

[0072] In the multilayer ceramic capacitor 1 according to Embodiment 1 of the present invention, the maximum height difference Hg1 in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101 is 1.0 μm or less. This reduces the height variation in the stacking direction (Z-axis direction) of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 exposed from the first main surface 101, and enables stable electrical connection of the first end T1 of each of the multiple first via conductors 140 and multiple second via conductors 150 by the electrodes of the mounting substrate.

[0073] The following describes a modified example of the multilayer ceramic capacitor according to Embodiment 1 of the present invention. In the following description of the modified example, components that are the same as those in the multilayer ceramic capacitor according to Embodiment 1 of the present invention are denoted by the same reference numerals and their descriptions are not repeated.

[0074] Figure 8 is a cross-sectional view of a multilayer ceramic capacitor according to a modified example of Embodiment 1 of the present invention. As shown in Figure 8, in the multilayer ceramic capacitor 1a according to a modified example of Embodiment 1 of the present invention, the second ends T2 of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 are not exposed from the second main surface 102. That is, the second ends T2 of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 are covered by the dielectric layer 110. The second main surface 102 is located in a space B surrounded by the resin portion 20. That is, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed on the first main surface 101 of the capacitor body 100a, but not on the second main surface 102. This makes it possible to suppress short circuits between electronic components arranged on the second main surface 102 side and the multilayer ceramic capacitor 1a.

[0075] In this modified example as well, by mounting the multilayer ceramic capacitor 1a onto the mounting substrate with the first end face 21 of the resin portion 20 in contact with the mounting substrate, the first ends T1 of each of the multiple first via conductors 140 and the multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate.

[0076] (Embodiment 2) Hereinafter, a multilayer ceramic capacitor according to Embodiment 2 of the present invention will be described with reference to the figures. The multilayer ceramic capacitor according to Embodiment 2 of the present invention differs from the multilayer ceramic capacitor according to Embodiment 1 of the present invention in that the resin portion covers the second main surface. Therefore, components that are the same as those in the multilayer ceramic capacitor according to Embodiment 1 of the present invention are denoted by the same reference numerals and their descriptions will not be repeated.

[0077] Figure 9 is a cross-sectional view of a multilayer ceramic capacitor according to Embodiment 2 of the present invention. As shown in Figure 9, in the multilayer ceramic capacitor 2 according to Embodiment 2 of the present invention, the resin portion 20 covers the second main surface 102 of the capacitor body 100. That is, the side of the capacitor body 100 facing the second main surface 102 is not polished, or the resin portion 20 facing the second main surface 102 of the capacitor body 100 is polished to the extent that the second main surface 102 is not exposed.

[0078] The second end T2 of each of the multiple first via conductors 140 and the multiple second via conductors 150, opposite to the first end T1, is exposed from the second main surface 102 and is covered by the resin portion 20. This makes it possible to suppress short circuits between the electronic components located on the second main surface 102 side and the multilayer ceramic capacitor 2.

[0079] In the multilayer ceramic capacitor 2 according to Embodiment 2 of the present invention, by mounting the multilayer ceramic capacitor 2 on the mounting substrate with the first end face 21 of the resin portion 20 in contact with the mounting substrate, the first ends T1 of each of the multiple first via conductors 140 and the multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate.

[0080] The following describes a modified example of the multilayer ceramic capacitor according to Embodiment 2 of the present invention. In the following description of the modified example, components that are the same as those in the multilayer ceramic capacitor according to Embodiment 2 of the present invention are denoted by the same reference numerals and their descriptions are not repeated.

[0081] Figure 10 is a cross-sectional view of a multilayer ceramic capacitor according to a modified example of Embodiment 2 of the present invention. As shown in Figure 10, in the multilayer ceramic capacitor 2a according to a modified example of Embodiment 2 of the present invention, the second ends T2 of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 are not exposed from the second main surface 102. That is, the second ends T2 of each of the plurality of first via conductors 140 and the plurality of second via conductors 150 are covered by the dielectric layer 110. In other words, each of the plurality of first via conductors 140 and the plurality of second via conductors 150 is exposed on the first main surface 101 of the capacitor body 100a, but not on the second main surface 102. This makes it possible to suppress short circuits between electronic components arranged on the second main surface 102 side and the multilayer ceramic capacitor 2a.

[0082] In this modified example as well, by mounting the multilayer ceramic capacitor 2a onto the mounting substrate with the first end face 21 of the resin portion 20 in contact with the mounting substrate, the first ends T1 of each of the multiple first via conductors 140 and the multiple second via conductors 150 can be stably electrically connected to the electrodes of the mounting substrate.

[0083] (Note) Those skilled in the art will understand that the exemplary embodiments described above are specific examples of the following embodiments.

[0084] <1> A multilayer ceramic capacitor comprising: a capacitor body having a first main surface, a second main surface located on the opposite side of the first main surface in the stacking direction, and a peripheral surface connecting the first main surface and the second main surface, wherein the capacitor body includes a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in the stacking direction with a dielectric layer in between, and has a first main surface, a second main surface located on the opposite side of the stacking direction from the first main surface, and a peripheral surface connecting the first main surface and the second main surface; a plurality of first via conductors provided inside the capacitor body and electrically connected to the plurality of first internal electrode layers; a plurality of second via conductors provided inside the capacitor body and electrically connected to the plurality of second internal electrode layers; and a resin part covering the peripheral surface of the capacitor body and having a flat first end surface on one side in the stacking direction, wherein the maximum height difference in the stacking direction of the first end of each of the plurality of first via conductors and the plurality of second via conductors exposed from the first main surface is 1.5 μm or less, and the first end of each of the plurality of first via conductors and the plurality of second via conductors and the first main surface are located in a space surrounded by the resin part.

[0085] <2> The multilayer ceramic capacitor according to <1>, wherein the maximum height difference in the stacking direction of the first end of each of the plurality of first via conductors and the plurality of second via conductors is smaller than the maximum height difference in the stacking direction of the first main surface.

[0086] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the first end of each of the plurality of first via conductors and the plurality of second via conductors protrudes from the first main surface.

[0087] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the maximum height difference in the stacking direction of the first end of each of the plurality of first via conductors and the plurality of second via conductors is 1.0 μm or less.

[0088] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the maximum height difference in the stacking direction of the second ends of each of the plurality of first via conductors and the plurality of second via conductors exposed from the second main surface is 1.5 μm or less, and the second ends and second main surfaces of each of the plurality of first via conductors and the plurality of second via conductors are located within the space surrounded by the resin portion.

[0089] <6> The resin portion covers the second main surface, and is a multilayer ceramic capacitor according to any one of <1> to <4>.

[0090] <7> The multilayer ceramic capacitor according to <6>, wherein the second end of each of the plurality of first via conductors and the plurality of second via conductors opposite to the first end is exposed from the second main surface and is covered by the resin portion.

[0091] In the description of the embodiments described above, the combinable configurations may be combined with each other.

[0092] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended.

[0093] 1, 1a, 2, 2a Multilayer ceramic capacitor, 20 Resin part, 21 First end face, 22 Second end face, 100 Capacitor body, 100a Capacitor body, 100f Laminate, 101 First main surface, 102 Second main surface, 103 Peripheral side surface, 110 Dielectric layer, 120 First internal electrode layer, 120h First through hole, 130 Second internal electrode layer, 130h Second through hole, 140 First via conductor, 150 Second via conductor, 200 Resin, 300 Embedded body, A Space, B Space, T1 First end, T2 Second end.

Claims

1. A multilayer ceramic capacitor comprising: a capacitor body having a first main surface, a second main surface located on the opposite side of the first main surface in the stacking direction, and a peripheral surface connecting the first main surface and the second main surface, wherein the capacitor body includes a plurality of first internal electrode layers and a plurality of second internal electrode layers stacked alternately in the stacking direction with a dielectric layer in between, and has a first main surface, a second main surface located on the opposite side of the stacking direction from the first main surface, and a peripheral surface connecting the first main surface and the second main surface; a plurality of first via conductors provided inside the capacitor body and electrically connected to the plurality of first internal electrode layers; a plurality of second via conductors provided inside the capacitor body and electrically connected to the plurality of second internal electrode layers; and a resin portion covering the peripheral surface of the capacitor body and having a flat first end surface on one side in the stacking direction, wherein the maximum height difference in the stacking direction of the first end of each of the plurality of first via conductors and the plurality of second via conductors exposed from the first main surface is 1.5 μm or less, and the first end of each of the plurality of first via conductors and the plurality of second via conductors and the first main surface are located within a space surrounded by the resin portion.

2. The multilayer ceramic capacitor according to claim 1, wherein the maximum height difference in the stacking direction of the first end of each of the plurality of first via conductors and the plurality of second via conductors is smaller than the maximum height difference in the stacking direction of the first main surface.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the first end of each of the plurality of first via conductors and the plurality of second via conductors protrudes from the first main surface.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the maximum height difference in the stacking direction of the first end of each of the plurality of first via conductors and the plurality of second via conductors is 1.0 μm or less.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the maximum height difference in the stacking direction of the second ends of each of the plurality of first via conductors and the plurality of second via conductors exposed from the second main surface is 1.5 μm or less, and the second ends and second main surfaces of each of the plurality of first via conductors and the plurality of second via conductors are located within a space surrounded by the resin portion.

6. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the resin portion covers the second main surface.

7. The multilayer ceramic capacitor according to claim 6, wherein the second end of each of the plurality of first via conductors and the plurality of second via conductors opposite to the first end is exposed from the second main surface and is covered by the resin portion.

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