Two-step patterning methods for barium titanate films in photonic devices

Abstract

An etching method includes forming a patterned hard mask comprising silicon oxide over a metal oxide layer including barium titanate, performing a first etch step using an ion beam to etch the metal oxide layer in regions not covered by the patterned hard mask, and performing a second etch step using a hydrogen and fluorine containing etchant to remove etch residue from the first etch step and to form a metal oxide pattern.

Description

[0001] Attorney Docket No. 35113-0617WO

[0002] TWO-STEP PATTERNING METHODS FOR BARIUM TITANATE FILMS IN PHOTONIC DEVICES

[0003] Inventors: Nicholas LICAUSI; Christopher PRINDLE; Henrik JOHANSSON; and Vimal Kumar KAMINENI

[0004] FIELD

[0005]

[0001] Embodiments herein relate generally to methods for etching materials to generate components of electro-optic devices, such as phase shifters and switches.

[0006] BACKGROUND

[0007]

[0002] Electro-optic (EO) modulators and optical switches are useful components for the control and manipulation of optical signals. Some EO modulators utilize free-carrier electrorefraction, free-carrier electro-absorption, the Pockel’s effect, or the DC Kerr effect to modify optical properties during operation, for example, to change a phase of light propagating through the EO modulator or switch. Optical phase modulators may be used in integrated optics systems, waveguide structures, integrated optoelectronics, etc.

[0008] SUMMARY

[0009]

[0003] An embodiment etching method includes forming a patterned hard mask comprising silicon oxide over a metal oxide layer including barium titanate, performing a first etch step using an ion beam to etch the metal oxide layer in regions not covered by the patterned hard mask, and performing a second etch step using a hydrogen and fluorine containing etchant to remove etch residue from the first etch step and to form a metal oxide pattern.

[0010] BRIEF DESCRIPTION OF THE DRAWINGS

[0011]

[0004] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate example embodiments of the disclosure, and together with the general description given above and the detailed description given below, serve to explain the features of the disclosure.

[0012]

[0005] FIG. l is a simplified schematic diagram illustrating an optical switch, according to various embodiments.

[0013]

[0006] FIG. 2 is a schematic diagram of a pre-fabricated wafer including stacked layers, according to various embodiments. Attorney Docket No. 35113-0617WO

[0014]

[0007] FIG. 3 A is a simplified schematic diagram illustrating a cross section of a waveguide structure that shows the direction of an induced electric field, according to various embodiments.

[0015]

[0008] FIG. 3B is a simplified schematic diagram illustrating a cross section of a waveguide structure, according to various embodiments.

[0016]

[0009] FIG. 4 is a simplified schematic diagram showing a top view of a waveguide structure, according to various embodiments.

[0017]

[0010] FIG. 5 is a schematic illustration of an ion milling etch procedure.

[0018] [OH] FIGS. 6 A - 6D are schematic illustrations of steps using to pattern a metal oxide layer comprising barium titanate with a silicon oxide hard mask using a two-step etching process.

[0019] DETAILED DESCRIPTION

[0020]

[0012] The various embodiments are described in detail with reference to the accompanying drawings. The drawings are not necessarily to scale, and are intended to illustrate various features of the disclosure. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the disclosure or the claims.

[0021]

[0013] It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first electrode layer could be termed a second electrode layer, and, similarly, a second electrode layer could be termed a first electrode layer, without departing from the scope of the various described embodiments. The first electrode layer and the second electrode layer are both electrode layers, but they are not the same electrode layer.

[0022]

[0014] Disclosed embodiments relate etching and patterning methods for constructing components of optical systems. Example embodiments are provided in the context of integrated optical systems that include active optical devices, but the disclosure is not limited to such examples and has wide applicability to a variety of optical and optoelectronic systems. Attorney Docket No. 35113-0617WO

[0023]

[0015] According to some embodiments, the active photonic devices described herein utilize electro-optic effects, such as free carrier induced refractive index variation in semiconductors, the Pockels effect, and / or the DC Kerr effect to implement modulation and / or switching of optical signals. Thus, embodiments are applicable to both modulators, in which the transmitted light is modulated either ON or OFF, or light is modulated with a partial change in transmission percentage, as well as optical switches, in which the transmitted light is output on a first output (e.g., waveguide) or a second output (e.g., waveguide) or an optical switch with more than two outputs, as well as more than one input. Thus, embodiments of this disclosure are applicable to a variety of system configurations including an M(input) x N(output) systems that utilize the methods, devices, and techniques discussed herein. Some embodiments also relate to electro-optic phase shifter devices, also referred to herein as phase adjustment sections, which may be employed within switches or modulators.

[0024]

[0016] FIG. l is a simplified schematic diagram illustrating an optical switch, according to various embodiments. Referring to FIG. 1, switch 100 includes two inputs: Input 1 and Input 2 as well as two outputs: Output 1 and Output 2. As an example, the inputs and outputs of switch 100 may be implemented as optical waveguides configured to support single mode or multimode optical beams. As an example, switch 100 may be implemented as a Mach- Zehnder interferometer coupled with a set of 50 / 50 beam splitters 105 and 107, respectively. As illustrated in FIG. 1, Input 1 and Input 2 are optically coupled to a first 50 / 50 beam splitter 105, also referred to as a directional coupler, which receives light from the Input 1 or Input 2 and, through evanescent coupling in the 50 / 50 beam splitter, directs 50% of the input light from Input 1 into waveguide 110 and 50% of the input light from Input 1 into waveguide 112. Concurrently, first 50 / 50 beam splitter 105 directs 50% of the input light from Input 2 into waveguide 110 and 50% of the input light from Input 2 into waveguide 112. Considering only input light from Input 1, the input light is split evenly between waveguides 110 and 112.

[0025]

[0017] Mach-Zehnder interferometer 120 includes phase adjustment section 122. Voltage Vo may be applied across the waveguide in phase adjustment section 122 such that it may have an index of refraction in phase adjustment section 122 that is controllably varied. Because light in waveguides 110 and 112 may still have a well-defined phase relationship (e.g., they may be in-phase, 180° out-of-phase, etc.) after propagation through the first 50 / 50 beam Attorney Docket No. 35113-0617WO splitter 105, phase adjustment in phase adjustment section 122 may introduce a predetermined phase difference between the light propagating in waveguides 130 and 132. The phase relationship between the light propagating in waveguides 130 and 132 may cause output light to be present at Output 1 (e.g., light beams are in-phase) or Output 2 (e.g., light beams are out of phase), thereby providing switch functionality as light is directed to Output 1 or Output 2 as a function of the voltage Vo applied at the phase adjustments section 122. Although a single active arm is illustrated in FIG. 1, in other embodiments both arms of the Mach-Zehnder interferometer may include phase adjustment sections.

[0026]

[0018] As illustrated in FIG. 1, electro-optic switch technologies, in comparison to all-optical switch technologies, use an applied electrical bias (e.g., Vo in FIG. 1) across the active region of the switch to produce optical variation. The electric field and / or current that is induced by application of this voltage bias causes changes in one or more optical properties of the active region, such as the index of refraction or absorbance. Although a Mach-Zehnder interferometer implementation is illustrated in FIG. 1, the disclosure is not limited to this particular switch architecture and other phase adjustment devices are included within the scope of this disclosure, including ring resonator designs, Mach-Zehnder modulators, generalized Mach-Zehnder modulators, and the like.

[0027]

[0019] The optical switch illustrated in FIG. 1 may include a waveguide structure that has been patterned from a wafer. FIG. 2 illustrates an example wafer that may be received from a wafer manufacturer and etched according to embodiments described herein, to produce the waveguide structure. FIG. 2 illustrates a cross section of a first wafer including a layer stack that may be received as part of a fabrication process for various devices described herein, according to various embodiments. As illustrated, a first insulating substrate layer 202 may be (optionally) disposed beneath a seed layer 204, which is disposed beneath an electro-optic layer 206, which is (optionally) disposed beneath an electrode layer 208, which is (optionally) disposed beneath a second insulating substrate layer 210. Alternatively, the electrode layer 208 may be located between the electro-optic layer 206 and the first insulating substrate layer 202. While FIG. 2 illustrates that each of the five layers 202 to 210 are present, any one or more of these layers may be absent, in various embodiments. In other words, the first wafer may be of various types depending on the specific fabrication method to be employed, and the seed layer, electrode layer, and second substrate layer may be Attorney Docket No. 35113-0617WO optionally present or not present, as desired. One or more of the layers illustrated in FIG. 2 may be chemically etched to produce an electro-optical component, according to embodiments described herein.

[0028]

[0020] Each of the layers of the wafer may be of any of a variety of types of materials. For example, the electrode layer 208 may include a conducting material such as a metal, or alternatively they may be composed of a semiconductor material. In various embodiments, the electrode layer may include one of gallium arsenide (GaAs), an aluminum gallium arsenide (AlGaAs) / GaAs heterostructure, an indium gallium arsenide (InGaAs) / GaAs heterostructure, zinc oxide (ZnO), zinc sulfide (ZnS), indium oxide (InO), doped silicon, strontium titanate (STO), doped STO, barium titanate (BTO), barium strontium titanate (BST), hafnium oxide, lithium niobite, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconium titanate (PZT), lead lanthanum zirconium titanate (PLZT), strontium barium niobate (SBN), aluminum oxide, aluminum oxide, doped variants or solid solutions thereof, or a two-dimensional electron gas. For embodiments where the electrode layer may include doped STO, the STO may be either niobium doped or lanthanum doped, or include vacancies, according to various embodiments.

[0029]

[0021] In various embodiments, the electro-optic layer 206 may include one or more of STO, BTO, BST, hafnium oxide, lithium niobite, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, PZT, PLZT, SBN, aluminum oxide, aluminum oxide, or doped variants or solid solutions thereof. The electro-optic layer may be composed of a transparent material having an index of refraction that is larger than an index of refraction of the first and second insulating substrate layers, in some embodiments.

[0030]

[0022] FIG. 3 A is a simplified schematic diagram illustrating a cross section of an example completed waveguide structure, where the direction of the induced electric field is illustrated with arrows, according to some embodiments. The waveguide structure illustrated in FIG.

[0031] 3 A may be fabricated from the wafer illustrated in FIG. 2 by performing etching techniques of embodiments described herein. FIG. 3 A exhibits two electrical contacts, and each electrical contact includes a lead (330 and 332) connected to an electrode (340 and 342). It is noted that, as used herein, the term “electrode” refers to a device component that directly couples to the waveguide structure (e.g., to alter the voltage drop across the waveguide structure and actuate a photonic switch). Further, the term “lead” may refer to a backend Attorney Docket No. 35113-0617WO structure that couples the electrodes to other components of the device (e.g., the leads may couple the electrodes to a controllable voltage source), but the leads are isolated from and do not directly couple to the waveguide structure. In some embodiments, the leads may be composed of a metal (e.g., copper, gold, etc.), or alternatively, a semiconductor material.

[0032]

[0023] As illustrated, FIG. 3 A illustrates a photonic device including first and second cladding layers, 310 and 312, on either side of the waveguide. It is noted that the terms “first” and “second” are meant simply to distinguish between the two cladding layers, and, for example, the term “first cladding layer” may refer to the cladding layer on either side of the waveguide.

[0033]

[0024] FIG. 3 A further illustrates a slab layer 320 including a first material that is coupled to the first electrode of the first electrical contact and the second electrode of the second electrical contact. In some embodiments, the waveguide structure further includes a ridge portion 351 composed of the first material (or a different material) and coupled to the slab layer, where the ridge portion is disposed between the first electrical contact and the second electrical contact.

[0034]

[0025] As illustrated in FIG. 3 A, the small arrows show the induced electric field direction which generally points along the positive x-direction through the electrodes of the device. The electric field curves in a convex manner both above and below the electrodes, as illustrated. Furthermore, the large arrow 350 pointing in the positive x-direction illustrates the direction of polarization of an optical mode that may travel through the slab layer and the waveguide.

[0035]

[0026] FIG. 3B illustrates an architecture where the ridge portion of the waveguide structure 351 is disposed on the top side of the slab layer and extends into a first cladding layer 312, the first electrode and the second electrode are coupled to the slab layer on the bottom side of the slab layer opposite the top side. As illustrated, the combination of the ridge portion and the slab layer has a first thickness 362 greater than a second thickness 360 of the slab layer alone 320, and the excess of the first thickness relative to the second thickness extends into the first cladding layer 312 on the top side of the slab layer 320. As illustrated in FIG. 3B, the first electrode 340 and the second electrode 342 may be coupled to the slab layer 320 on the bottom side of the slab layer opposite the top side. Further, the first electrical contact 330 may be coupled to the first electrode 340 by penetrating through the slab layer 320 from the Attorney Docket No. 35113-0617WO top side of the slab layer to the bottom side of the slab layer, and the second electrical contact 332 may be coupled to the second electrode 342 by penetrating through the slab layer 320 from the top side of the slab layer to the bottom side of the slab layer.

[0036]

[0027] FIG. 4 is a top-down view of a photonic phase-shifter architecture of FIGS. 3 A and 3B, which may be patterned according to embodiments described herein. As illustrated, the phase-shifter may include first 430 and second 432 leads, first 440 and second 442 electrodes, a slab (e.g., waveguide) layer 420, and a ridge portion of the waveguide structure 451.

[0037]

[0028] FIG. 5 illustrates an ion milling (i.e., ion beam etching) method for etching BTO (i.e., BaTiCh). BTO is a difficult material to pattern using reactive ion etch (RIE), because BTO does not form volatile by-products with fluorine or chlorine, the halides commonly used in plasma etching. The chemical by-products of etching BTO using conventional fluorine and chlorine are non-volatile below approximately 1500 °C. Accordingly, these by-products may not desorb from the wafer at the temperatures and pressures available in an RIE chamber. As a consequence, as illustrated in FIG. 5, a BTO layer 20 is patterned by ion beam etching using argon using a silicon oxide hard mask 22. During ion milling, argon ions are accelerated towards the BTO layer 20 surface and physically break off barium and titanium atoms. These atoms are then pumped out through the exhaust. However, the etched atoms of barium, titanium and / or silicon (from the silicon oxide hard mask 22) may often redeposit elsewhere on the surface of the wafer as an etch residue, causing undesirable defects.

[0038]

[0029] In various embodiments, an ion beam etching process (i.e., an ion milling process) is used pattern the BTO thin film, followed by a hydrogen and fluorine etchant containing etch to remove the etch residue which adheres to the sidewalls of the BTO patterns. In one embodiment, a silicon oxide hard mask may be used as an etch mask during patterning of the BTO thin film. In this embodiment, the etch residue includes silicon and oxygen (e.g., silicon oxide and / or metal silicate residue, such as barium and / or titanium silicate residue from etching BTO covered by a silicon oxide hard mask). Such residue can be removed using the hydrogen and fluorine containing etchant, such as hydrofluoric acid.

[0039]

[0030] FIG. 6A is a vertical cross-sectional view of an intermediate structure that may be used in the formation of an optical component, according to various embodiments. The intermediate structure may include an metal oxide layer 20L which comprises barium titanate (BTO) located over an insulating layer 202, such as a silicon oxide layer. The barium titanate Attorney Docket No. 35113-0617WO may comprise undoped barium titanate (e.g., BaTiCE) or doped barium titanate (e.g., barium strontium titanate). In one embodiment, the metal oxide layer 20L may comprise an electrooptic layer for a phase shifter device. The metal oxide layer 20L may be deposited as a blanket (i.e., un-pattemed) layer. The intermediate structure may further include a silicon oxide (e.g., SiCh ) hard mask layer 22L and a patterned soft masking layer, such as a patterned photoresist 24. The patterned photoresist 24 may be formed by depositing a blanket layer (not shown) of photoresist material and patterning the photoresist material using photolithography techniques to form the patterned photoresist 24.

[0040]

[0031] Referring to FIG. 6B, the patterned photoresist 24 is then be used as an etch mask layer to pattern the hard mask layer 22L into a patterned hard mask 22. The hard mask layer 22L may be etched to form the patterned hard mask 22 using any suitable silicon oxide etching method, such as a reactive ion etch (RIE) method. The RIE stops on the metal oxide layer 20L, which is used as an etch stop. The patterned photoresist 24 is then removed after patterning the hard mask layer 22L and before patterning the metal oxide layer 20L. The patterned photoresist 24 may be removed by ashing or selective etching.

[0041]

[0032] Referring to FIG. 6C, the patterned hard mask 22 is used as a mask during patterning of the metal oxide layer 20L. The patterning may comprise a first etching step using an ion beam etching method using inert gas ions (e.g., argon) as the ion beam. The metal oxide layer 20L is patterned into a BTO pattern 20, such as an electro-optic component pattern of an electro-optic device, such as a waveguide layer of a Mach-Zehdner interferometer. As discussed above, the ion beam etching forms etch residue 26 on the sidewalls of the BTO pattern 20 and / or sidewalls and / or top of the patterned etch mask 22.

[0042]

[0033] Referring to FIG. 6D, the etch residue 26 is removed using a second etching step using an etchant comprising hydrogen and fluorine. As discussed above, since the etch residue 26 contains silicon oxide or a metal silicate, it is removed using an etchant containing hydrogen and fluorine selective to the BTO pattern 20. The silicon oxide patterned hard mask 22 may be partially or entirely removed during the second etching step.

[0043]

[0034] In one embodiment, the second etch step may comprise a hydrogen and fluorine containing vapor etch step, such as a SiConi™ process from Applied Materials, Inc. The SiConi process involves the simultaneous exposure of a substrate to EE, NF3 and NH3 plasma by-products, which are believed to generate a NH4F intermediate product which reacts with Attorney Docket No. 35113-0617WO silicon oxide in the etch residue 26 to form a (NH^SiFe salt and water vapor by-products. The salt sublimates at a temperature of about 100 degrees Celsius and is dissociated into volatile SiF4, NH3 and HF products which are pumped away from the etching chamber.

[0044]

[0035] In another embodiment, the second etch step may comprise a chemical oxide removal (“COR”) plasma etch step from Tokyo Electron Limited. In this process, hydrofluoric acid (HF) vapor and ammonia (NH3) are used an etchant.

[0045]

[0036] In other embodiments, the second etch step may comprise a HF vapor etchant or a dilute HF liquid etchant that is used to remove the etch residue 26.

[0046]

[0037] The above-described etching method may be used in many applications including photonics (e.g., devices with electro-optic materials, oxide perovskite materials, optical switches, interferometers, etc.); microelectromechanical systems (MEMS) (e.g., disclosed embodiments may be used in thermal detectors to etch pixels in a focal plane arrays (FPA) and bolometers which use oxide perovskite materials); communications systems (e.g., disclosed embodiments may be used to pattern reflectarray antennas); memory devices (e.g., disclosed embodiments may be used to pattern thin film capacitors and varactors, e.g., DRAM with BTO layers); high-k dielectrics, etc.

[0047]

[0038] The foregoing descriptions are provided merely as illustrative examples and are not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As may be appreciated by one of ordinary skill in the art, the order of steps in the foregoing embodiments may be performed in any order. Words such as “thereafter,” “then,” “next,” etc., are not necessarily intended to limit the order of the steps; these words may be used to guide the reader through the description of the methods. Further, any reference to claim elements in the singular, for example, using the articles “a,” “an,” or “the,” is not to be construed as limiting the element to the singular. Further, any step or component of any embodiment described herein may be used in any other embodiment.

[0048]

[0039] The preceding description of the disclosed aspects is provided to enable persons of ordinary skill in the art to make and / or use the disclosed embodiments. Various modifications to these aspects may be readily apparent to those of ordinary skill in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, embodiments of the disclosure are not intended to be Attorney Docket No. 35113-0617WO limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

Attorney Docket No. 35113-0617WOCLAIMSWHAT IS CLAIMED IS:

1. An etching method, comprising: forming a patterned hard mask comprising silicon oxide over a metal oxide layer comprising barium titanate; performing a first etch step using an ion beam to etch the metal oxide layer in regions not covered by the patterned hard mask; and performing a second etch step using a hydrogen and fluorine containing etchant to remove etch residue from the first etch step and to form a metal oxide pattern.

2. The method of claim 1, wherein the etch residue comprises silicon and oxygen.

3. The method of claim 2, wherein the etch residue further comprises barium and titanium.

4. The method of claim 1, wherein the hydrogen and fluorine containing etchant comprises a vapor etchant.

5. The method of claim 4, wherein the hydrogen and fluorine containing etchant comprises hydrofluoric acid vapor.

6. The method of claim 5, wherein the hydrogen and fluorine containing etchant further comprises ammonia.

7. The method of claim 6, wherein the second etch step comprises a plasma chemical oxide removal step.

8. The method of claim 4, wherein the hydrogen and fluorine containing etchant comprises H2, NF3 and NH3 plasma by-products.Attorney Docket No. 35113-0617WO9. The method of claim 8, wherein: the plasma by-products generate a NH4F intermediate product which reacts with the etch residue to form a (NH^SiFe salt and water vapor by-products; and the (NF ^SiFe salt sublimates at an elevated temperature and is dissociated into volatile SiF4, NH3 and HF products which are pumped away from an etching chamber containing the metal oxide layer.

10. The method of claim 1, wherein the hydrogen and fluorine containing etchant comprises a dilute hydrofluoric acid solution.

11. The method of claim 1, further comprising depositing a hard mask layer comprising silicon oxide over the metal oxide layer, and patterning a hard mask layer into the patterned hard mask.

12. The method of claim 1, wherein the patterning the hard mask layer into the patterned hard mask comprises forming a photoresist pattern over the hard mask layer, etching the hard mask layer using the photoresist pattern as a mask, and removing the photoresist pattern prior to the first etching step.

13. The method of claim 1, wherein the first etching step comprises an ion beam etching process using an argon ion beam.

14. The method of claim 1, wherein the metal oxide pattern is located over a silicon oxide layer.

15. The method of claim 1, wherein the metal oxide pattern comprises a waveguide layer of a Mach-Zehnder interferometer.

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