Signal processing method, circuit and chip, and electronic device

Abstract

A signal processing method, circuit and chip, and an electronic device. The signal processing method comprises: performing PWM on an input signal to obtain a PWM positive signal and a PWM negative signal (101); and outputting a positive output signal and a negative output signal on the basis of the PWM positive signal and the PWM negative signal (102), wherein in response to the absolute value of the amplitude of the input signal being greater than a threshold value, one of the positive output signal and the negative output signal includes no pulse, and the other one of the positive output signal and the negative output signal includes two pulses within one pulse cycle. The method can improve the performance of an output signal while improving the performance.

Description

Signal processing method, circuit, chip and electronic device TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and in particular to a signal processing method, circuit, chip and electronic device. BACKGROUND

[0002] Pulse-Width Modulation (PWM) is a technology that uses the digital output of a microprocessor to control analog circuits. By modulating the width of the pulse, the required waveform (including shape and amplitude) can be obtained, that is, the voltage and frequency can be adjusted by changing the duty cycle.

[0003] Currently, a D-class power amplifier (also known as a digital power amplifier or a switching power amplifier) using PWM technology is used to amplify an audio signal.

[0004] However, the D-class power amplifier makes a trade-off between performance and efficiency. Improving performance will simultaneously result in a decrease in efficiency, which is particularly evident when the absolute value of the input signal amplitude is large.

[0005] SUMMARY

[0006] In view of the above, embodiments of the present application provide a signal processing method, circuit, chip and electronic device to at least partially solve the above problems.

[0007] According to a first aspect of embodiments of the present application, a signal processing method is provided, comprising: PWM modulating an input signal to obtain a PWM positive signal and a PWM negative signal; and outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an absolute value of an amplitude of the input signal being greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses in one pulse period.

[0008] According to a second aspect of embodiments of the present application, a signal processing circuit is provided, comprising: a modulation module configured to PWM modulate an input signal to obtain a PWM positive signal and a PWM negative signal; and a power output module configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an absolute value of an amplitude of the input signal being greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses in one pulse period.

[0009] According to a third aspect of the embodiments of the present application, a signal processing chip is provided, which is configured to perform the method according to the first aspect.

[0010] According to a fourth aspect of the embodiments of the present application, an electronic device is provided, which comprises a signal source, a signal receiving end and a signal processing device, wherein the signal processing device comprises the signal processing circuit according to the second aspect or the signal processing chip according to the third aspect; the signal processing device is connected between the signal source and the signal receiving end; the signal source is configured to transmit an input signal to the signal processing device; and the signal receiving end is configured to receive a positive output signal and a negative output signal output by the signal processing device.

[0011] According to the embodiments of the present application, the input signal is PWM modulated to obtain a PWM positive signal and a PWM negative signal, and the positive output signal and the negative output signal are output according to the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than a threshold, one of the positive output signal and the negative output signal does not include a pulse, and the other includes two pulses in a pulse period, i.e., there is no common-mode component in the positive output signal and the negative output signal, and the differential signal of the positive output signal and the negative output signal is concentrated on a single side, so that the differential-mode pulse width of the positive output signal and the negative output signal does not exist loss. Moreover, since the pulses included in the positive output signal and the negative output signal are generated based on the switching of the switch in the circuit, only one of the positive output signal and the negative output signal includes a pulse, which reduces the switching times in the process of generating the positive output signal and the negative output signal, thereby improving the output efficiency. In the PWM modulation process, the number of pulse occurrences in a unit time is positively correlated with the suppression effect on the loop nonlinearity and noise. When the absolute value of the amplitude of the input signal is greater than a threshold, one of the positive output signal and the negative output signal includes two pulses in a pulse period, so that the suppression effect on the loop nonlinearity and noise can be improved in the case that the absolute value of the amplitude of the input signal is large, thereby improving the performance of the output signal. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0013] FIG. 1 is a flowchart of a signal processing method according to an embodiment of the present application;

[0014] FIG. 2 is a flowchart of a PWM modulation method according to an embodiment of the present application;

[0015] Fig. 3 is a schematic diagram of the PWM positive signal and the PWM negative signal when the input signal amplitude equals to 0 according to one embodiment of the present application;

[0016] Fig. 4 is a schematic diagram of the PWM positive signal and the PWM negative signal when the input signal amplitude equals to 0 according to another embodiment of the present application;

[0017] Fig. 5 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is less than a threshold according to one embodiment of the present application;

[0018] Fig. 6 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is less than a threshold according to another embodiment of the present application;

[0019] Fig. 7 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is less than a threshold according to yet another embodiment of the present application;

[0020] Fig. 8 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is less than a threshold according to still another embodiment of the present application;

[0021] Fig. 9 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is greater than a threshold according to one embodiment of the present application;

[0022] Fig. 10 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is greater than a threshold according to another embodiment of the present application;

[0023] Fig. 11 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is greater than a threshold according to yet another embodiment of the present application;

[0024] Fig. 12 is a schematic diagram of the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is greater than a threshold according to still another embodiment of the present application;

[0025] Fig. 13 is a schematic diagram of the process of generating the PWM positive signal and the PWM negative signal according to one embodiment of the present application;

[0026] Fig. 14 is a flow chart of the method of generating the PWM positive signal and the PWM negative signal according to one embodiment of the present application;

[0027] Fig. 15 is a schematic diagram of the process of generating the PWM positive signal and the PWM negative signal when the input signal amplitude equals to 0 according to one embodiment of the present application;

[0028] Fig. 16 is a schematic diagram of the process of generating the PWM positive signal and the PWM negative signal when the input signal amplitude equals to 0 according to another embodiment of the present application;

[0029] Fig. 17 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is less than a threshold value, according to one embodiment of the present application;

[0030] Fig. 18 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is less than a threshold value, according to another embodiment of the present application;

[0031] Fig. 19 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is less than a threshold value, according to yet another embodiment of the present application;

[0032] Fig. 20 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is less than a threshold value, according to still another embodiment of the present application;

[0033] Fig. 21 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is greater than a threshold value, according to one embodiment of the present application;

[0034] Fig. 22 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is greater than a threshold value, according to another embodiment of the present application;

[0035] Fig. 23 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is greater than a threshold value, according to yet another embodiment of the present application;

[0036] Fig. 24 is a schematic diagram of the generation of the PWM positive signal and the PWM negative signal when the absolute value of the amplitude of the input signal is greater than a threshold value, according to still another embodiment of the present application;

[0037] Fig. 25 is a schematic diagram of a signal processing circuit, according to one embodiment of the present application;

[0038] Fig. 26 is a schematic diagram of a signal processing circuit, according to another embodiment of the present application;

[0039] Fig. 27 is a schematic diagram of an electronic device, according to one embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to enable persons skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by persons skilled in the art based on the embodiments in the present application shall fall within the scope of protection of the present application.

[0041] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in this application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0042] It is to be understood that, although the terms first, second, third, etc. can be used herein to describe various information, the information should not be limited to these terms. These terms are only used to distinguish one piece of information from another. For example, a first information can also be termed a second information, and, similarly, a second information can also be termed a first information, without departing from the scope of the present application. Depending on the context, the word "if' as used herein can be interpreted as meaning "when" or "in response to determining" or "in response to ascertaining".

[0043] For the purpose of clarity, technical solutions and advantages of the present application will be further described in detail below with reference to the accompanying drawings.

[0044] Signal processing method

[0045] Fig. 1 is a flow chart of a signal processing method according to an embodiment of the present application. As shown in Fig. 1, the signal processing method comprises the following steps:

[0046] Step 101, performing PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal.

[0047] The input signal can comprise a positive input signal and a negative input signal, and the input signal can be an analog signal. The PWM modulation on the input signal can be performed in multiple steps, for example, first coupling a differential mode signal of the positive input signal and the negative input signal comprised in the input signal to an input end of a loop filter unit, then delivering the filtered signal to a comparison unit and a triangular wave for comparison, and then performing logic processing on the comparison result to obtain the PWM positive signal and the PWM negative signal.

[0048] The input signal can be an audio signal or other signal having a PWM modulation requirement.

[0049] Step 102, outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal.

[0050] After the PWM positive signal and the PWM negative signal are obtained, the PWM positive signal and the PWM negative signal can be processed, such as amplification, inversion, and the like, to obtain a positive output signal and a negative output signal, and then the positive output signal and the negative output signal are output. In one example, when the input signal is an audio signal, the output positive output signal and the output negative output signal can be used to drive a loudspeaker after being filtered (such as LC filtering).

[0051] The pulse width of the PWM positive signal and the PWM negative signal is related to the absolute value of the input signal amplitude, and the positive output signal and the negative output signal are obtained based on the PWM positive signal and the PWM negative signal, so the positive output signal and the negative output signal are related to the absolute value of the input signal amplitude. Specifically, in response to the absolute value of the input signal amplitude being greater than a threshold, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes 2 pulses in one pulse period. When the absolute value of the input signal amplitude is greater than the threshold, if the positive output signal does not include a pulse, the negative output signal includes 2 pulses in one pulse period, and if the negative output signal does not include a pulse, the positive output signal includes 2 pulses in one pulse period. It should be noted that including 2 pulses in one pulse period means that there are only 2 pulses in one pulse period.

[0052] The amplitude of the input signal refers to the amplitude of the differential mode signal of the positive input signal and the negative input signal, and the signal strength of the input signal is positively correlated with the absolute value of the amplitude of the input signal. It should be noted that, for ease of description, the input signal amplitude described hereinafter refers to the amplitude of the input signal. The threshold is greater than 0 and less than the maximum value of the absolute value of the input signal amplitude.

[0053] In one example, when the absolute value of the input signal amplitude is less than the threshold, the period (frequency) of the positive output signal and the negative output signal is the same as the period (frequency) of the PWM positive signal and the PWM negative signal, and the period (frequency) of the PWM positive signal and the PWM negative signal is the same as the period (frequency) of the triangular wave. When the absolute value of the input signal amplitude is greater than the threshold, the frequency of the positive output signal or the negative output signal is equal to 0, that is, one of the positive output signal and the negative output signal does not include a pulse.

[0054] In the embodiment of the present application, the input signal is PWM modulated to obtain a PWM positive signal and a PWM negative signal, and a positive output signal and a negative output signal are output according to the PWM positive signal and the PWM negative signal. When the absolute value of the input signal amplitude is greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other includes two pulses in a pulse period, that is, the positive output signal and the negative output signal do not have a common-mode component, and the differential signal of the positive output signal and the negative output signal is concentrated on a single side, so that the differential-mode pulse width of the positive output signal and the negative output signal does not have loss. Since the pulses included in the positive output signal and the negative output signal are generated based on the switching of the switch tube in the circuit, one of the positive output signal and the negative output signal does not include a pulse in a pulse period, and the other includes two pulses. Compared with the case where the positive output signal and the negative output signal each include one pulse, the frequency of the pulse is increased, and the number of switching of the switch tube is not increased, so that the performance of the output signal can be improved while ensuring the output efficiency. In the PWM modulation process, the number of pulse occurrences in a unit time is positively correlated with the suppression effect on loop nonlinearity and noise. When the absolute value of the input signal amplitude is greater than the threshold value, one of the positive output signal and the negative output signal includes two pulses in a pulse period, so that the suppression effect on loop nonlinearity and noise can be improved in the case where the absolute value of the input signal amplitude is large, and thus the performance of the output signal can be improved.

[0055] In a possible implementation, when the absolute value of the input signal amplitude is greater than 0 and less than a threshold value, the positive output signal and the negative output signal each include one pulse in a pulse period, and the differential-mode signal of the positive output signal and the negative output signal has a pulse width greater than 0, that is, the pulse widths of the pulses included in the positive output signal and the negative output signal are different. In addition, the differential-mode signal of the positive output signal and the negative output signal includes one pulse in a pulse period.

[0056] When the absolute value of the input signal amplitude is greater than 0 and less than a threshold value, the positive output signal and the negative output signal each include one pulse in each pulse period, and the positive output signal and the negative output signal have a differential-mode signal. The pulse width of the differential-mode signal is related to the absolute value of the input signal amplitude, and the pulse width of the differential-mode signal of the positive output signal and the negative output signal is greater than 0 when the input signal amplitude is not equal to 0.

[0057] In the embodiment of the present application, when the absolute value of the input signal amplitude is greater than 0 and less than a threshold value, in one pulse period, the positive output signal and the negative output signal each include one pulse, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is greater than 0. Since the pulse width of the differential mode signal of the positive output signal and the negative output signal is related to the absolute value of the input signal amplitude, when the absolute value of the input signal amplitude is large, the performance and efficiency of the output signal are ensured, and when the absolute value of the input signal amplitude is small, the output signal can also reflect the change of the input signal, thereby ensuring the reliability of signal processing.

[0058] In a possible implementation, when the amplitude of the input signal is equal to 0, in one pulse period, the positive output signal and the negative output signal each include one pulse, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, that is, the differential mode signal of the positive output signal and the negative output signal does not include any pulse.

[0059] The positive output signal and the negative output signal match the input signal, and when the amplitude of the input signal changes, the differential mode signal of the positive output signal and the negative output signal needs to change accordingly, so as to ensure the correctness of signal processing. When the amplitude of the input signal is equal to 0, in one pulse period, the positive output signal and the negative output signal each include one pulse, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, so as to ensure that the differential mode signal of the positive output signal and the negative output signal matches the input signal, and ensure the reliability and accuracy of signal processing.

[0060] In the embodiment of the present application, the number of pulses and the pulse width of the common mode signal of the positive output signal and the negative output signal are negatively related to the efficiency of signal processing, which can indicate power consumption. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in each pulse period, so that the common mode signal of the positive output signal and the negative output signal includes a smaller number of pulses, thereby ensuring lower power consumption in the standby state. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse, thereby ensuring that the feedback loop in the signal processing process can operate normally, thereby ensuring the performance of signal processing. As shown in FIG. 26, the feedback loop is composed of a loop filter unit, a comparison unit, a logic processing unit and a power output module. The differential mode signal of the positive input signal and the negative input signal is coupled to the input end of the loop filter unit, and is transmitted to the comparison unit and the triangular wave for comparison after filtering processing. Then, the comparison result is logically processed to obtain the PWM positive signal and the PWM negative signal. The power output module generates the positive output signal and the negative output signal based on the PWM positive signal and the PWM negative signal. The power output module feeds back the positive output signal and the negative output signal to the loop filter unit. The loop filter unit filters the input positive input signal and the negative input signal based on the feedback positive output signal and the negative output signal.

[0061] In a possible implementation, the pulse width of the differential mode signal of the positive output signal and the negative output signal is positively related to the absolute value of the amplitude of the input signal.

[0062] When the amplitude of the input signal is equal to 0, the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0. When the absolute value of the amplitude of the input signal is greater than 0, the pulse width of the differential mode signal of the positive output signal and the negative output signal is greater than 0, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is positively related to the absolute value of the amplitude of the input signal. After processing the input signal, the change of the input signal can be correctly reflected on the differential mode signal of the positive output signal and the negative output signal, thereby ensuring the accuracy and reliability of signal processing.

[0063] In a possible implementation, the processing of the input signal can be based on a preset delay duration. According to different absolute values of the amplitude of the input signal, the pulse width of the pulse included in the positive output signal and the negative output signal satisfies the following relationship with the delay duration:

[0064] (1) When the amplitude of the input signal is equal to 0, the pulse width of the pulse included in the positive output signal and the negative output signal is equal to the delay duration.

[0065] (2) when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, one of the positive output signal and the negative output signal includes a pulse with a pulse width greater than the delay time length, and the other of the positive output signal and the negative output signal includes a pulse with a pulse width less than the delay time length;

[0066] (3) when the absolute value of the input signal amplitude is greater than the threshold value, at least one pulse included in the positive output signal or the negative output signal has a pulse width greater than the delay time length.

[0067] When the amplitude of the input signal is equal to 0, both the positive output signal and the negative output signal include one pulse with a pulse width equal to the delay time length, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, that is, the rising edge and the falling edge of the pulses included in the positive output signal and the negative output signal are time-aligned, so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, ensuring the accuracy of signal processing.

[0068] When the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, both the positive output signal and the negative output signal include one pulse. When the pulse included in the positive output signal has a pulse width greater than the delay time length, the pulse included in the negative output signal has a pulse width less than the delay time length, and when the pulse included in the negative output signal has a pulse width greater than the delay time length, the pulse included in the positive output signal has a pulse width less than the delay time length. When the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the rising edge and the falling edge of the pulses included in the positive output signal and the negative output signal are not time-aligned, and the midpoints of the pulses included in the positive output signal and the negative output signal are time-aligned, so that the pulse width of the differential mode signal of the positive output signal and the negative output signal is not equal to 0, and as the absolute value of the input signal amplitude increases (decreases), the pulse width of the differential mode signal of the positive output signal and the negative output signal correspondingly increases (decreases), so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, ensuring the accuracy of signal processing.

[0069] When the absolute value of the amplitude of the input signal is greater than the threshold value, one of the positive output signal and the negative output signal includes two pulses, the other of the positive output signal and the negative output signal does not include a pulse, and the pulse width of at least one of the two pulses included in the output signal is greater than the delay time length. When the absolute value of the amplitude of the input signal is greater than the threshold value, if the positive output signal includes two pulses, the pulse width of at least one of the two pulses included in the positive output signal is greater than the delay time length, and if the negative output signal includes two pulses, the pulse width of at least one of the two pulses included in the negative output signal is greater than the delay time length. When the absolute value of the amplitude of the input signal is greater than the threshold value, as the absolute value of the amplitude of the input signal increases (decreases), the sum of the pulse widths of the two pulses included in the positive output signal or the negative output signal correspondingly increases (decreases), so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, and the accuracy of signal processing is ensured.

[0070] In the embodiments of the present application, the pulse width of the pulses included in the positive output signal and the negative output signal is related to the preset delay time length, and the performance of the output signal is related to the pulse width of the pulses included in the positive output signal and the negative output signal. The appropriate delay time length can be set according to the requirement for the performance of the output signal, for example, the delay time length can be 1 / 40 to 1 / 10 of the period of a triangular wave. A smaller delay time length is set on the premise of meeting the requirement for the performance of the output signal, so that the pulse width of the pulses included in the positive output signal and the negative output signal is smaller when the amplitude of the input signal is equal to 0, thereby reducing the standby power consumption.

[0071] In a possible implementation, when the input signal is PWM modulated, a square wave signal can be generated based on the input signal, and then the PWM positive signal and the PWM negative signal can be generated based on the generated square wave signal and the delay time length. As shown in the flowchart of the PWM modulation method in FIG. 2, the input signal can be PWM modulated by the method including the following steps:

[0072] In step 201, the input signal is filtered to obtain a first positive signal and a first negative signal.

[0073] The input signal includes a positive input signal and a negative input signal. The first positive signal and the first negative signal can be obtained by filtering the positive input signal and the negative input signal. For example, the differential mode signal of the positive input signal and the negative input signal is coupled to the input end of a loop filter unit, and the first positive signal and the first negative signal can be obtained by filtering the positive input signal and the negative input signal through the loop filter unit.

[0074] In one example, the loop filter unit does not perform reverse processing at its output end, the waveform of the first positive signal matches the waveform of the positive input signal, and the waveform of the first negative signal matches the waveform of the negative input signal. In another example, the loop filter unit performs reverse processing at its output end, the waveform of the first positive signal matches the waveform of the negative input signal, and the waveform of the first negative signal matches the waveform of the positive input signal. The output end of the loop filter unit outputs the first positive signal and the first negative signal.

[0075] Step 202, compare the first positive signal and the first negative signal with the triangular wave, and generate the second positive signal and the second negative signal according to the comparison result.

[0076] After obtaining the first positive signal and the first negative signal, the first positive signal and the first negative signal can be input into the comparison unit respectively, the comparison unit compares the first positive signal and the first negative signal with the triangular wave respectively, generates the second positive signal according to the comparison result of the first positive signal and the triangular wave, and generates the second negative signal according to the comparison result of the first negative signal and the triangular wave.

[0077] When the comparison unit compares the first positive signal and the first negative signal with the triangular wave, the second positive signal / second negative signal is determined according to the size relationship between the first positive signal / first negative signal and the triangular wave.

[0078] In one example, as shown in the schematic diagram of the second positive signal and the second negative signal in FIG. 9, the first positive signal IN+ (the first negative signal IN-) is greater than the signal segment of the triangular wave, which corresponds to the high level of the second positive signal CMP+ (the second negative signal CMP-), and the first positive signal IN+ (the first negative signal IN-) is less than the signal segment of the triangular wave, which corresponds to the low level of the second positive signal CMP+ (the second negative signal CMP-).

[0079] In another example, as shown in the schematic diagram of the second positive signal and the second negative signal in FIG. 11, the first positive signal IN+ (the first negative signal IN-) is greater than the signal segment of the triangular wave, which corresponds to the low level of the second positive signal CMP+ (the second negative signal CMP-), and the first positive signal IN+ (the first negative signal IN-) is less than the signal segment of the triangular wave, which corresponds to the high level of the second positive signal CMP+ (the second negative signal CMP-).

[0080] It should be noted that FIG. 9 and FIG. 11 show the triangular waves of two pulse periods. For the convenience of the description, in the subsequent embodiments, the first positive signal is denoted as IN+, the first negative signal is denoted as IN-, the second positive signal is denoted as CMP+, the second negative signal is denoted as CMP-, the PWM positive signal is denoted as PWM+, and the PWM negative signal is denoted as PWM-.

[0081] When the IN+ and IN- signals are compared with the triangular wave to generate the CMP+ and CMP- signals, the reverse processing can be performed or not performed. When the reverse processing is not performed, the waveforms of the CMP+ and CMP- signals are as shown in FIG. 9, and when the reverse processing is performed, the waveforms of the CMP+ and CMP- signals are as shown in FIG. 11. Whether the reverse processing is performed when the CMP+ and CMP- signals are generated can be set according to the application scenario requirement, so as to meet different requirements and improve the applicability of the signal processing method in the embodiments of the present application.

[0082] In step 203, the PWM positive signal and the PWM negative signal are generated according to the second positive signal, the second negative signal, and the delay duration.

[0083] After the second positive signal and the second negative signal are generated, the second positive signal and the second negative signal can be logically processed based on the delay duration, and then the PWM positive signal and the PWM negative signal are generated.

[0084] In the embodiments of the present application, the positive output signal and the negative output signal are generated based on the PWM positive signal and the PWM negative signal. When the absolute value of the input signal amplitude is greater than the threshold value and less than the threshold value, the PWM positive signal and the PWM negative signal are generated based on the second positive signal, the second negative signal, and the delay duration, without the need to generate the PWM positive signal and the PWM negative signal in a feedback manner through a complex feedback network, so as to make the signal processing simpler and reduce the cost of the signal processing circuit.

[0085] In a possible implementation manner, when the amplitude of the input signal is equal to 0, the pulse width of the pulse included in the PWM positive signal and the PWM negative signal is equal to the delay duration, and the leading edge of the pulse included in the PWM positive signal and the PWM negative signal is time-aligned with the rising edge of the pulse included in the second positive signal and the second negative signal. The pulse included in the second positive signal and the second negative signal can be low or high. In the second positive signal and the second negative signal, if the pulse is low, the leading edge of the pulse is the falling edge, and the trailing edge of the pulse is the rising edge, and if the pulse is high, the leading edge of the pulse is the rising edge, and the trailing edge of the pulse is the falling edge. The PWM positive signal and the PWM negative signal are described below by taking the pulse included in the second positive signal (the second negative signal) as an example.

[0086] When the reverse processing is not performed in the generation of the CMP+ and the CMP-, the PWM positive signal and the PWM negative signal are as shown in FIG. 3, the pulses included in the CMP+ and the CMP- are low, the pulses included in the PWM+ and the PWM- are high, the rising edge of the pulse included in the PWM+ is time-aligned with the rising edge (the trailing edge) of the pulse included in the CMP+ and the CMP-, and the pulse width of the pulse included in the PWM+ and the PWM- is equal to the delay time T d . Wherein, Diff is used to represent the differential mode signal of the CMP+ and the CMP-.

[0087] When the reverse processing is performed in the generation of the CMP+ and the CMP-, the PWM positive signal and the PWM negative signal are as shown in FIG. 4, the pulses included in the CMP+ and the CMP- are high, the pulses included in the PWM+ and the PWM- are high, the rising edge of the pulse included in the PWM+ is time-aligned with the rising edge (the leading edge) of the pulse included in the CMP+ and the CMP-, and the pulse width of the pulse included in the PWM+ and the PWM- is equal to the delay time T d . Wherein, Diff is used to represent the differential mode signal of the CMP+ and the CMP-.

[0088] It should be noted that FIG. 3 and FIG. 4 show the PWM+ and the PWM- in two pulse periods.

[0089] In the embodiment of the present application, when the amplitude of the input signal is equal to 0, the pulse width of the pulse included in the PWM positive signal and the PWM negative signal is equal to the delay time, and the leading edge of the pulse included in the PWM positive signal and the PWM negative signal is time-aligned with the rising edge of the pulse included in the second positive signal and the second negative signal, which ensures that the differential mode signal of the PWM positive signal and the PWM negative signal does not include any pulse, so that the differential mode signal of the PWM positive signal and the PWM negative signal matches the input signal, and ensures the accuracy of signal processing. In addition, by setting a small delay time, the pulse width of the pulse included in the PWM positive signal and the PWM negative signal when the amplitude of the input signal is equal to 0 can be small, thereby reducing the standby power consumption.

[0090] In a possible implementation, when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the pulse width of the pulses included in the PWM positive signal and the PWM negative signal is different according to the size relationship between the first positive signal and the first negative signal. When the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the rising edge of the pulse included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second positive signal, the rising edge of the pulse included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal, if the first positive signal is greater than the first negative signal, the pulse width of the pulse included in the PWM positive signal is greater than the pulse width of the pulse included in the PWM negative signal, and if the first positive signal is less than the first negative signal, the pulse width of the pulse included in the PWM positive signal is less than the pulse width of the pulse included in the PWM negative signal.

[0091] When no reverse processing is performed in the generation of the CMP+ and the CMP-, if the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, and IN+ is greater than IN-, the PWM positive signal and the PWM negative signal are as shown in FIG. 5. Referring to FIG. 5, the pulses included in the CMP+ and the CMP- are low, the pulses included in the PWM+ and the PWM- are high, the pulse width of the pulse included in the PWM+ is equal to T diff1 +T d , the pulse width of the pulse included in the PWM- is equal to T d -T diff2 , the rising edge of the pulse included in the PWM+ is time-aligned with the rising edge of the pulse included in the CMP+, and the rising edge of the pulse included in the PWM- is time-aligned with the rising edge of the pulse included in the CMP-. Wherein, Diff is used to represent the differential mode signal of the CMP+ and the CMP-, T diff1 and T diff2 are used to represent the pulse width of the two pulses included in the Diff.

[0092] When no reverse processing is performed in the generation of the CMP+ and the CMP-, if the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, and IN+ is less than IN-, the PWM positive signal and the PWM negative signal are as shown in FIG. 6. Referring to FIG. 6, the pulses included in the CMP+ and the CMP- are low, the pulses included in the PWM+ and the PWM- are high, the pulse width of the pulse included in the PWM+ is equal to T d -T diff2 , the pulse width of the pulse included in the PWM- is equal to T diff1 +T d , the rising edge of the pulse included in the PWM+ is time-aligned with the rising edge of the pulse included in the CMP+, and the rising edge of the pulse included in the PWM- is time-aligned with the rising edge of the pulse included in the CMP-. Wherein, Diff is used to represent the differential mode signal of the CMP+ and the CMP-, T diff1 and T diff2to characterize the pulse width of the two pulses comprised by Diff.

[0093] In the case of reverse processing in the generation of CMP+ and CMP-, if the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, and IN+ is greater than IN-, the PWM positive signal and the PWM negative signal are as shown in FIG. 7. Referring to FIG. 7, the pulses comprised by CMP+ and CMP- are high, the pulses comprised by PWM+ and PWM- are high, the pulse width of the pulse comprised by PWM+ is equal to T d -T diff2 , the pulse width of the pulse comprised by PWM- is equal to T diff1 +T d , the rising edge of the pulse comprised by PWM+ is time-aligned with the rising edge of the pulse comprised by CMP+, and the rising edge of the pulse comprised by PWM- is time-aligned with the rising edge of the pulse comprised by CMP-. Wherein, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 are used to characterize the pulse width of the two pulses comprised by Diff.

[0094] In the case of reverse processing in the generation of CMP+ and CMP-, if the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, and IN+ is less than IN-, the PWM positive signal and the PWM negative signal are as shown in FIG. 8. Referring to FIG. 8, the pulses comprised by CMP+ and CMP- are high, the pulses comprised by PWM+ and PWM- are high, the pulse width of the pulse comprised by PWM+ is equal to T diff1 +T d , the pulse width of the pulse comprised by PWM- is equal to T d -T diff2 , the rising edge of the pulse comprised by PWM+ is time-aligned with the rising edge of the pulse comprised by CMP+, and the rising edge of the pulse comprised by PWM- is time-aligned with the rising edge of the pulse comprised by CMP-. Wherein, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 are used to characterize the pulse width of the two pulses comprised by Diff.

[0095] It should be noted that FIGS. 5-8 show two pulse periods of PWM+ and PWM-. As shown in FIGS. 5-8, when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the rising edge and the falling edge of the pulse comprised by PWM+ and PWM- are not time-aligned, and the midpoint of the pulse comprised by PWM+ and PWM- is time-aligned.

[0096] In the case of no reverse processing in the generation of CMP+ and CMP-, when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, if IN+ is greater than IN-, referring to FIG. 5, as the absolute value of the input signal amplitude increases, Tdiff1 and T diff2 increases, the pulse width of the pulses included in PWM+ increases from T d begins to decrease, the pulse width of the pulses included in PWM- increases from T d begins to decrease, the sum of the pulse widths of the pulses included in PWM+ and PWM- equals T diff1 + T diff2 .

[0097] Without inverting the CMP+ and CMP- generation process, if IN+ is less than IN- when the absolute value of the input signal amplitude is greater than 0 and less than the threshold, see Fig. 6, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increases, the pulse width of the pulses included in PWM+ increases from T d begins to decrease, the pulse width of the pulses included in PWM- increases from T d begins to decrease, the sum of the pulse widths of the pulses included in PWM+ and PWM- equals T diff1 + T diff2 .

[0098] With inverting the CMP+ and CMP- generation process, if IN+ is greater than IN- when the absolute value of the input signal amplitude is greater than 0 and less than the threshold, see Fig. 7, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increases, the pulse width of the pulses included in PWM+ decreases from T d begins to increase, the pulse width of the pulses included in PWM- decreases from T d begins to increase, the sum of the pulse widths of the pulses included in PWM+ and PWM- equals T diff1 + T diff2 .

[0099] With inverting the CMP+ and CMP- generation process, if IN+ is less than IN- when the absolute value of the input signal amplitude is greater than 0 and less than the threshold, see Fig. 8, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increases, the pulse width of the pulses included in PWM+ increases from T d begins to decrease, the pulse width of the pulses included in PWM- increases from T d begins to decrease, the sum of the pulse widths of the pulses included in PWM+ and PWM- equals T diff1 + T diff2 .

[0100] In the embodiment of the present application, when the absolute value of the input signal amplitude is greater than 0 and less than a threshold value, PWM+ and PWM- each include one pulse, and the sum of the pulse widths of the differential mode signal of PWM+ and PWM- is equal to T diff1 +T diff2 When the absolute value of the input signal amplitude changes, T diff1 +T diff2 correspondingly changes, so that the change of the input signal can be reflected on the differential mode signal of PWM+ and PWM-, thereby ensuring the accuracy of signal processing.

[0101] In a possible implementation, when the absolute value of the input signal amplitude is greater than a threshold value, according to the size relationship between the first positive signal and the first negative signal, the pulse widths of the pulses included in the PWM positive signal and the PWM negative signal are different.

[0102] When the absolute value of the input signal amplitude is greater than a threshold value, if the pulses included in the second positive signal and the second negative signal are low, and the first positive signal is greater than the first negative signal, the pulse widths of the two pulses included in the PWM positive signal are T diff1 +T d and T diff2 -T d respectively, the PWM negative signal does not include a pulse, and the pulse width of the PWM positive signal is T diff1 +T d The rising edge of the pulse included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second positive signal, and the pulse width of the PWM positive signal is T diff2 -T d The falling edge of the pulse included in the PWM positive signal is time-aligned with the falling edge of the pulse included in the second positive signal.

[0103] When no reverse processing is performed in the generation of CMP+ and CMP-, the pulses included in the second positive signal and the second negative signal are low, if the absolute value of the input signal amplitude is greater than a threshold value, and IN+ is greater than IN-, the PWM positive signal and the PWM negative signal are as shown in FIG. 9. Referring to FIG. 9, the pulses included in CMP+ and CMP- are low, the pulse included in PWM+ is high, the pulse widths of the two pulses included in PWM+ are T diff1 +T d and T diff2 -T d respectively, PWM- does not include a pulse, and the pulse width of PWM+ is T diff1 +T d The rising edge of the pulse included in PWM+ is time-aligned with the rising edge of the pulse included in CMP+, and the pulse width of PWM+ is T diff2 -T dthe falling edge of the pulse of CMP+ is time-aligned with the falling edge of the pulse of CMP-. Wherein, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 are used to represent the pulse width of the two pulses of Diff.

[0104] If the pulses of the second positive signal and the second negative signal are low, and the first positive signal is less than the first negative signal, the pulse width of the two pulses of the PWM negative signal is T diff1 +T d and T diff2 -T d respectively, the PWM positive signal does not include a pulse, and the pulse width of the PWM negative signal is T diff1 +T d the rising edge of the pulse of the PWM negative signal is time-aligned with the rising edge of the second negative signal, and the pulse width of the PWM negative signal is T diff2 -T d the falling edge of the pulse of the PWM negative signal is time-aligned with the falling edge of the second negative signal.

[0105] If the pulses of the second positive signal and the second negative signal are low, and the first positive signal is less than the first negative signal, the pulse width of the two pulses of the PWM negative signal is T diff1 +T d and T diff2 -T d respectively, the PWM positive signal does not include a pulse, and the pulse width of the PWM negative signal is T diff1 +T d the rising edge of the pulse of the PWM negative signal is time-aligned with the rising edge of the second negative signal, and the pulse width of the PWM negative signal is T diff2 -T d the falling edge of the pulse of the PWM negative signal is time-aligned with the falling edge of the second negative signal. Wherein, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 are used to represent the pulse width of the two pulses of Diff.

[0106] If the pulses of the second positive signal and the second negative signal are high, and the first positive signal is greater than the first negative signal, the pulse width of the two pulses of the PWM negative signal is T diff1 +T d and Tdiff2 -T d , the PWM positive signal includes no pulse, and the PWM negative signal includes a pulse with a pulse width of T diff1 +T d , the rising edge of the pulse of the PWM positive signal is time-aligned with the rising edge of the second positive signal, and the PWM negative signal includes a pulse with a pulse width of T diff2 -T d , the falling edge of the pulse of the PWM positive signal is time-aligned with the falling edge of the second positive signal.

[0107] When the reverse processing is performed in the generation of the CMP+ and the CMP-, if the absolute value of the input signal amplitude is greater than the threshold value, and the IN+ is greater than the IN-, the second positive signal and the second negative signal include a pulse with a high level, and the PWM positive signal and the PWM negative signal are as shown in FIG. 11. Referring to FIG. 11, the CMP+ and the CMP- include a pulse with a high level, the PWM- includes a pulse with a high level, and the PWM- includes two pulses with pulse widths of T diff1 +T d and T diff2 -T d , the PWM positive signal includes no pulse, and the PWM negative signal includes a pulse with a pulse width of T diff1 +T d , the rising edge of the pulse of the PWM positive signal is time-aligned with the rising edge of the pulse included in the CMP-, and the PWM negative signal includes a pulse with a pulse width of T diff2 -T d , the falling edge of the pulse of the PWM positive signal is time-aligned with the falling edge of the pulse included in the CMP-. Wherein, Diff is used to represent the differential mode signal of the CMP+ and the CMP-, T diff1 and T diff2 are used to represent the pulse widths of the two pulses included in the Diff.

[0108] If the absolute value of the input signal amplitude is greater than the threshold value, and the second positive signal and the second negative signal include a pulse with a high level, and the first positive signal is less than the first negative signal, the PWM positive signal includes two pulses with pulse widths of T diff1 +T d and T diff2 -T d , the PWM negative signal includes no pulse, and the PWM positive signal includes a pulse with a pulse width of T diff1 +T d , the rising edge of the pulse of the PWM positive signal is time-aligned with the rising edge of the second positive signal, and the PWM positive signal includes a pulse with a pulse width of T diff2 -T d , the falling edge of the pulse of the PWM positive signal is time-aligned with the falling edge of the second positive signal.

[0109] During the reverse processing of generating CMP+ and CMP-, the pulses included in the second positive signal and the second negative signal are at a high level. If the absolute value of the input signal amplitude is greater than the threshold, and IN+ is less than IN-, the PWM positive signal and PWM negative signal are as shown in Figure 12. Referring to Figure 12, the pulses included in CMP+ and CMP- are at a high level, the pulses included in PWM+ are at a high level, and the pulse widths of PWM+ are T... diff1 +T d and T diff2 -T d Two pulses, PWM- does not include the pulse, PWM+ includes the pulse width T. diff1 +T d The rising edge of the pulse is aligned with the rising edge timing of the pulse included in CMP+, and the pulse width included in PWM+ is T. diff2 -T d The falling edge of the pulse is aligned with the falling edge timing of the pulse included in CMP+. Here, Diff represents the differential signal of CMP+ and CMP-, and T... diff1 and T diff2 Used to characterize the pulse width of the two pulses included in the Diff.

[0110] It should be noted that Figure 9-12 shows PWM+ and PWM- for two pulse cycles. Referring to Figure 9-12, when the absolute value of the input signal amplitude is greater than the threshold, as the absolute value of the input signal amplitude increases, T... diff1 and T diff2 Increase, PWM+ or PWM- includes a pulse width of T diff1 +T d The pulse width is from 2T d As it begins to increase, the pulse width included in PWM+ or PWM- is T. diff2 -T d The pulse width of the pulse increases from 0, and the sum of the pulse widths of the differential mode signals of PWM+ and PWM- equals T. diff1 +T diff2 .

[0111] In the embodiment of the present application, when the absolute value of the input signal amplitude is greater than the threshold value, one of the PWM+ and the PWM- includes two pulses, and the other does not include a pulse. Under the premise that the frequency of the triangular wave is constant, the PWM+ or the PWM- includes two pulses in one pulse period, which improves the suppression effect on the loop nonlinearity and noise, thereby improving the performance of the output signal. One of the PWM+ and the PWM- includes a pulse, and the other does not include a pulse, that is, there is no common-mode component in the PWM+ and the PWM-. The differential signal of the PWM+ and the PWM- is concentrated on one side, so that the differential-mode pulse width of the PWM+ and the PWM- does not exist loss, and the number of switching times in the process of generating the positive output signal and the negative output signal is reduced, thereby improving the output efficiency.

[0112] In a possible implementation, FIG. 13 shows a process diagram of generating the PWM+ and the PWM- according to one embodiment of the present application. As shown in FIG. 13, the process of generating the PWM+ and the PWM- includes a differential-mode pulse width extraction, a differential-mode pulse width detection, a common-mode pulse width generation, a differential-mode pulse width generation, and a PWM signal generation.

[0113] The differential-mode pulse width extraction process: differential-mode pulse width extraction is performed on the CMP+ and the CMP- to obtain a first positive differential-mode signal A+ and a first negative differential-mode signal A-.

[0114] The differential-mode pulse width detection process: differential-mode pulse width detection is performed on the first positive differential-mode signal A+ and the first negative differential-mode signal A- to obtain a second positive differential-mode signal B+ and a second negative differential-mode signal B-.

[0115] The common-mode pulse width generation process: common-mode pulse width generation is performed according to the first positive differential-mode signal A+, the first negative differential-mode signal A-, the second positive differential-mode signal B+, and the second negative differential-mode signal B- to obtain a positive common-mode signal CM+ and a negative common-mode signal CM-.

[0116] The differential-mode pulse width generation process: differential-mode pulse width generation is performed according to the first positive differential-mode signal A+ and the first negative differential-mode signal A- to obtain a third positive differential-mode signal DM+ and a third negative differential-mode signal DM-.

[0117] The PWM signal generation process: PWM signal generation is performed according to the positive common-mode signal CM+, the negative common-mode signal CM-, the third positive differential-mode signal DM+, the third negative differential-mode signal DM-, and a preset delay time length to obtain the PWM+ and the PWM-.

[0118] In the embodiments of the present application, differential mode pulse width extraction, differential mode pulse width detection, common mode pulse width generation, differential mode pulse width generation and PWM signal generation are performed based on CMP+ and PWM-, PWM+ and PWM- are obtained, the pulse width of CMP+ and CMP- can be determined through differential mode pulse width detection, and then PWM+ and PWM- are generated based on the pulse width of CMP+ and CMP-, so as to ensure the quality of signal processing.

[0119] In a possible implementation, PWM+ and PWM- are generated based on CMP+, CMP- and delay time T d When generating PWM+ and PWM-, one of CMP+ and CMP- can be reversed and then logically processed to obtain PWM+ and PWM-. FIG. 14 shows a flowchart of a method for generating PWM+ and PWM- according to an embodiment of the present application. As shown in FIG. 14, the method comprises the following steps:

[0120] Step 1401, logically inverting CMP+ to obtain a first inverted signal;

[0121] Step 1402, delaying CMP- by a preset delay time to obtain a first delayed signal;

[0122] Step 1403, logically ORing the first inverted signal and the first delayed signal to obtain PWM+;

[0123] Step 1404, logically inverting CMP- to obtain a second inverted signal;

[0124] Step 1405, delaying CMP+ by a preset delay time to obtain a second delayed signal;

[0125] Step 1406, logically ORing the second inverted signal and the second delayed signal to obtain PWM-.

[0126] Based on the method shown in FIG. 14, the process of generating PWM+ and PWM- for input signals with different amplitudes according to the size of IN+ and IN- and the waveform characteristics of PWM+ and PWM- are described as follows:

[0127] When the amplitude of the input signal is equal to 0, that is, IN+ is equal to IN-, the process of generating PWM+ and PWM- is shown in FIG. 15, logically inverting CMP+ to obtain CMP+_INV, delaying CMP+ by T d obtaining CMP-_DELAY, logically ORing CMP+_INV and CMP-_DELAY to obtain PWM+. Logically inverting CMP- to obtain CMP-_INV, delaying CMP+ by T dCMP+_DELAY is obtained, and PWM- is obtained by performing a logical OR operation on CMP+_INV and CMP-_DELAY. PWM+ and PWM- each include one pulse with a pulse width of T d The rising edge of the pulse included in PWM+ and PWM- is time-aligned with the rising edge of the pulse included in CMP+ and CMP-. PWM+ and PWM- obtained by the logical processing method shown in FIG. 4 are identical to PWM+ and PWM- shown in FIG. 4.

[0128] In the case where the reverse processing is performed in the generation of CMP+ and CMP-, when the amplitude of the input signal is equal to 0, i.e., IN+ is equal to IN-, the generation of PWM+ and PWM- is as shown in FIG. 16. CMP+_INV is obtained by performing a logical NOT operation on CMP+, and CMP-_DELAY is obtained by delaying CMP- by T d PWM+ is obtained by performing a logical OR operation on CMP+_INV and CMP-_DELAY. CMP-_INV is obtained by performing a logical NOT operation on CMP+, and CMP+_DELAY is obtained by delaying CMP+ by T d PWM- is obtained by performing a logical OR operation on CMP-_INV and CMP+_DELAY. PWM+ and PWM- each include one pulse with a pulse width of T d The rising edge of the pulse included in PWM+ and PWM- is time-aligned with the rising edge of the pulse included in CMP+ and CMP-. PWM+ and PWM- obtained by the logical processing method shown in FIG. 4 are identical to PWM+ and PWM- shown in FIG. 4.

[0129] In the case where no reverse processing is performed in the generation of CMP+ and CMP-, when the absolute value of the amplitude of the input signal is greater than 0 and less than a threshold value, if IN+ is greater than IN-, the generation of PWM+ and PWM- is as shown in FIG. 17. CMP+_INV is obtained by performing a logical NOT operation on CMP+, and CMP-_DELAY is obtained by delaying CMP- by T d PWM+ is obtained by performing a logical OR operation on CMP+_INV and CMP-_DELAY. PWM+ includes one pulse with a pulse width of T diff1 +T d The rising edge of the pulse included in PWM+ is time-aligned with the rising edge of the pulse included in CMP+. CMP-_INV is obtained by performing a logical NOT operation on CMP-, and CMP+_DELAY is obtained by delaying CMP+ by T d PWM- is obtained by performing a logical OR operation on CMP-_INV and CMP+_DELAY. PWM- includes one pulse with a pulse width of T d -T diff2 The rising edge of the pulse included in PWM- is time-aligned with the rising edge of the pulse included in CMP-. PWM+ and PWM- obtained by the logical processing method shown in FIG. 17 are identical to PWM+ and PWM- shown in FIG. 5.

[0130] In the case that no reverse processing is performed in the generation of CMP+ and CMP-, if IN+ is less than IN- when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the generation of PWM+ and PWM- is as shown in Fig. 18. CMP+ is subjected to logical NOT processing to obtain CMP+_INV, and CMP+ is delayed by T d to obtain CMP+_DELAY. CMP-_INV and CMP+_DELAY are subjected to logical OR processing to obtain PWM+, which includes one pulse with a pulse width of T d -T diff2 , the rising edge of which is time-aligned with the rising edge of the pulse included in CMP+. CMP- is subjected to logical NOT processing to obtain CMP-_INV, and CMP- is delayed by T d to obtain CMP+_DELAY. CMP-_INV and CMP+_DELAY are subjected to logical OR processing to obtain PWM-, which includes one pulse with a pulse width of T diff1 +T d , the rising edge of which is time-aligned with the rising edge of the pulse included in CMP-. PWM+ and PWM- obtained by the logical processing method shown in Fig. 18 are identical to PWM+ and PWM- shown in Fig. 6.

[0131] In the case that reverse processing is performed in the generation of CMP+ and CMP-, if IN+ is greater than IN- when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the generation of PWM+ and PWM- is as shown in Fig. 19. CMP+ is subjected to logical NOT processing to obtain CMP+_INV, and CMP- is delayed by T d to obtain CMP+_DELAY. CMP+_INV and CMP+_DELAY are subjected to logical OR processing to obtain PWM+, which includes one pulse with a pulse width of T d -T diff2 , the rising edge of which is time-aligned with the rising edge of the pulse included in CMP+. CMP- is subjected to logical NOT processing to obtain CMP-_INV, and CMP+ is delayed by T d to obtain CMP+_DELAY. CMP+_INV and CMP+_DELAY are subjected to logical OR processing to obtain PWM-, which includes one pulse with a pulse width of T diff1 +T d , the rising edge of which is time-aligned with the rising edge of the pulse included in CMP-. PWM+ and PWM- obtained by the logical processing method shown in Fig. 19 are identical to PWM+ and PWM- shown in Fig. 7.

[0132] In the case of reverse processing in the generation of CMP+ and CMP-, if IN+ is less than IN- when the absolute value of the input signal amplitude is greater than 0 and less than the threshold value, the generation of PWM+ and PWM- is as shown in Fig. 20. CMP+ is logically inverted to obtain CMP+_INV, and CMP is delayed by T d to obtain CMP+_DELAY. CMP+_INV and CMP+_DELAY are logically ORed to obtain PWM+, which includes one pulse with a pulse width of T diff1 +T d , and the rising edge of the pulse is time-aligned with the rising edge of the pulse included in CMP+. CMP- is logically inverted to obtain CMP-_INV, and CMP+ is delayed by T d to obtain CMP+_DELAY. CMP-_INV and CMP+_DELAY are logically ORed to obtain PWM-, which includes one pulse with a pulse width of T d -T diff2 , and the rising edge of the pulse is time-aligned with the rising edge of the pulse included in CMP-. PWM+ and PWM- obtained by the logical processing method shown in Fig. 20 are consistent with PWM+ and PWM- shown in Fig. 8.

[0133] In the case of no reverse processing in the generation of CMP+ and CMP-, if IN+ is greater than IN- when the absolute value of the input signal amplitude is greater than the threshold value, the generation of PWM+ and PWM- is as shown in Fig. 21. CMP+ is logically inverted to obtain CMP+_INV, and CMP is delayed by T d to obtain CMP+_DELAY. CMP+_INV and CMP+_DELAY are logically ORed to obtain PWM+, which includes one pulse with a pulse width of T diff1 +T d and one pulse with a pulse width of T diff2 -T d , and the rising edge of the pulse with a pulse width of T diff1 +T d is time-aligned with the rising edge of the pulse included in CMP+, and the falling edge of the pulse with a pulse width of T diff2 -T d is time-aligned with the falling edge of the pulse included in CMP+. CMP- is logically inverted to obtain CMP-_INV, and CMP+ is delayed by T d to obtain CMP+_DELAY. CMP-_INV and CMP+_DELAY are logically ORed to obtain PWM-, which includes no pulse. PWM+ and PWM- obtained by the logical processing method shown in Fig. 21 are consistent with PWM+ and PWM- shown in Fig. 9.

[0134] In the case that no reverse processing is performed in the generation of CMP+ and CMP-, if the absolute value of the input signal amplitude is greater than the threshold value, and if IN+ is less than IN-, the generation of PWM+ and PWM- is as shown in Fig. 22. CMP+ is logically inverted to obtain CMP+_INV, and CMP is delayed by T d CMP-_DELAY is obtained, and CMP+_INV and CMP-_DELAY are logically ORed to obtain PWM+, which does not include a pulse. CMP- is logically inverted to obtain CMP-_INV, and CMP+ is delayed by T d CMP+_DELAY is obtained, and CMP+_INV and CMP-_DELAY are logically ANDed to obtain PWM-, which includes one pulse with a pulse width of T diff1 +T d and one pulse with a pulse width of T diff2 -T d The rising edge of the pulse with a pulse width of T diff1 +T d is time-aligned with the rising edge of the pulse included in CMP-, and the falling edge of the pulse with a pulse width of T diff2 -T d is time-aligned with the falling edge of the pulse included in CMP-. PWM+ and PWM- obtained by the logical processing method shown in Fig. 22 are identical to PWM+ and PWM- shown in Fig. 10.

[0135] In the case that reverse processing is performed in the generation of CMP+ and CMP-, if the absolute value of the input signal amplitude is greater than the threshold value, and if IN+ is greater than IN-, the generation of PWM+ and PWM- is as shown in Fig. 23. CMP+ is logically inverted to obtain CMP+_INV, and CMP is delayed by T d CMP-_DELAY is obtained, and CMP+_INV and CMP-_DELAY are logically ORed to obtain PWM+, which does not include a pulse. CMP- is logically inverted to obtain CMP-_INV, and CMP+ is delayed by T d CMP+_DELAY is obtained, and CMP+_INV and CMP-_DELAY are logically ORed to obtain PWM-, which includes one pulse with a pulse width of T diff1 +T d and one pulse with a pulse width of T diff2 -T d The rising edge of the pulse with a pulse width of T diff1 +T d is time-aligned with the rising edge of the pulse included in CMP-, and the falling edge of the pulse with a pulse width of T diff2 -T dthe falling edge of the pulse included in PWM+ is time-aligned with the falling edge of the pulse included in CMP-. PWM+ and PWM- obtained by the logic processing method shown in Fig. 23 are identical to PWM+ and PWM- shown in Fig. 11.

[0136] In the case of reverse processing in the generation of CMP+ and CMP-, if IN+ is smaller than IN- when the absolute value of the input signal amplitude is greater than the threshold value, the generation process of PWM+ and PWM- is shown in Fig. 24. CMP+_INV is obtained by performing logic inversion on CMP+, and CMP+_DELAY is obtained by delaying CMP+ by T d CMP-_DELAY is obtained, and PWM+ is obtained by performing logic OR inversion on CMP+_INV and CMP-_DELAY. PWM+ includes one pulse with a pulse width of T diff1 +T d and one pulse with a pulse width of T diff2 -T d The rising edge of the pulse with a pulse width of T diff1 +T d in PWM+ is time-aligned with the rising edge of the pulse included in CMP+. The falling edge of the pulse with a pulse width of T diff2 -T d in PWM+ is time-aligned with the falling edge of the pulse included in CMP+. CMP-_INV is obtained by performing logic inversion on CMP-, and CMP+_DELAY is obtained by delaying CMP+ by T d CMP+_DELAY is obtained, and PWM- is obtained by performing logic OR inversion on CMP-_INV and CMP+_DELAY. PWM- does not include a pulse. PWM+ and PWM- obtained by the logic processing method shown in Fig. 24 are identical to PWM+ and PWM- shown in Fig. 12.

[0137] In the embodiments of the present application, the delay time length is set in advance, so that the CMP+ and the CMP- are delayed to obtain a delay signal, and the CMP+ and the CMP- are processed reversely (logical NOT) to obtain a reverse signal, and then the delay signal and the reverse signal are processed logically to obtain the PWM+ and the PWM-. The PWM+ and the PWM- are not generated by feedback, so that the signal processing process is simpler, the loop of the whole system is simpler, and the common-mode pulse width of the PWM+ and the PWM- is determined by the delay unit generating the delay time length, so that the influence of the fluctuation of the power supply voltage on the common-mode pulse width of the PWM+ and the PWM- is smaller. Since the special differential signal pulse width detection circuit is not needed to be set to switch the common mode, but the common mode is switched according to the differential signal of the CMP+ and the CMP- and the delay time length to generate the PWM+ and the PWM-, with the increase of the differential-mode pulse width of the CMP+ and the CMP-, the common-mode component of the PWM+ and the PWM- gradually decreases, which is a smooth and automatic conversion process, and in this process, the differential signal in the differential-mode pulse width of the CMP+ and the CMP- is not lost, so that the common-mode signal of the PWM+ and the PWM- will not be mutated, the amplitude of the input signal is not mutated at 0 and the preset threshold, so that the quality of the signal processing is ensured.

[0138] It should be noted that in the above embodiments, T diff1 and T diff2 are the pulse widths of two pulses included in the differential-mode signal of the CMP+ and the CMP-. diff1 and T diff2 may be the same or different. When the rising slope and the falling slope of the triangular wave are equal, T diff1 and T diff2 are the same, and when the rising slope and the falling slope of the triangular wave are not equal, T diff1 and T diff2 are not the same.

[0139] In a possible implementation, according to the preset threshold, the absolute value of the amplitude of the input signal can be divided into three sections, the amplitude of the input signal equal to 0 is defined as a standby state, the absolute value of the amplitude of the input signal greater than 0 and less than the threshold is defined as a small amplitude section, and the absolute value of the amplitude of the input signal greater than the threshold is defined as a large amplitude section. According to FIGS. 3-24 and the description of the above text, the critical condition from the standby state to the small amplitude section is that the pulse widths of the pulses included in the PWM+ and the PWM- change from the same to different, and the critical condition from the small amplitude section to the large amplitude section is that the sum of the differential-mode pulse widths of the PWM+ and the PWM- is greater than twice the delay time length in a pulse period, that is, the large amplitude section starts when the common-mode pulse width of the PWM+ and the PWM- becomes smaller and smaller until 0. Therefore, the demarcation point of the small amplitude section and the large amplitude section can be adjusted by setting the delay time length.

[0140] The delay time length is in the range of [T / 40, T / 10], where T represents the length of the pulse period. For example, the delay time length can be T / 40, T / 30, T / 20, T / 10, etc.

[0141] It should be noted that the delay time length can be a pre-set fixed value or dynamically changed. For example, when the input signal is an analog signal or a digital signal, the pulse width threshold can be a pre-set fixed value, and when the input signal is a digital signal, the delay time length can be dynamically adjusted according to the power of the input signal, so as to balance the performance of the output signal and the power consumption of the signal processing.

[0142] In the embodiments of the present application, the delay time length is used to set the maximum value of the common-mode pulse width change of the positive input signal and the negative input signal when the input signal size is switched, and the delay time length also determines the pulse width of the positive output signal and the negative output signal in the standby state. The greater the delay time length, the greater the standby power consumption. At the same time, since there is a lower limit to the minimum pulse width that the subsequent circuit can respond to, when the delay time length is in the range of [T / 40, T / 10], the delay time length can meet the loop response while achieving the smallest standby power consumption possible. By setting a smaller delay time length, a smaller output pulse width can be used as the common-mode output in the standby state under the premise of meeting the system design, thereby ensuring lower power consumption in the standby state.

[0143] In a possible implementation, when outputting the positive output signal and the negative output signal according to PWM+ and PWM-, the amplitude of PWM+ can be amplified to obtain the negative output signal, and the amplitude of PWM- can be amplified to obtain the positive output signal, or the amplitude of PWM+ can be amplified to obtain the positive output signal, and the amplitude of PWM- can be amplified to obtain the negative output signal.

[0144] Amplifying the amplitudes of PWM+ and PWM- means amplifying the amplitudes of the pulses included in PWM+ and PWM- without changing the number, rising edge position and falling edge position of the pulses included in PWM+ and PWM-. For example, the voltage corresponding to the pulses included in PWM+ is 5V, and the amplitude of PWM+ is amplified to 20V to obtain the positive output signal or the negative output signal.

[0145] When outputting the positive output signal and the negative output signal according to PWM+ and PWM-, reverse processing can be performed or not performed. If reverse processing is performed, the amplitude of PWM+ is amplified to obtain the negative output signal, and the amplitude of PWM- is amplified to obtain the positive output signal. If reverse processing is not performed, the amplitude of PWM+ is amplified to obtain the positive output signal, and the amplitude of PWM- is amplified to obtain the negative output signal.

[0146] It should be noted that the reverse processing is needed once in the process of obtaining the positive output signal and the negative output signal by processing the input signal, which can be performed in the process of generating IN+ and IN- according to the input signal, in the process of generating CMP+ and CMP- according to IN+ and IN-, in the process of generating PWM+ and PWM- according to CMP+ and CMP-, and in the process of generating the positive output signal and the negative output signal according to PWM+ and PWM-. The foregoing embodiments describe the process of performing the reverse processing in the process of generating CMP+ and CMP- according to IN+ and IN-, and the implementation of performing the reverse processing in the process of generating IN+ and IN- according to the input signal, in the process of generating PWM+ and PWM- according to CMP+ and CMP-, and in the process of generating the positive output signal and the negative output signal according to PWM+ and PWM- is similar to the process of performing the reverse processing in the process of generating CMP+ and CMP- according to IN+ and IN-, and is not described herein again.

[0147] In the embodiments of the present application, when the positive output signal and the negative output signal are output according to PWM+ and PWM-, the positive output signal and the negative output signal are obtained by amplifying the amplitudes of PWM+ and PWM- so that the positive output signal and the negative output signal can drive devices such as a loudspeaker. The reverse processing can be performed or not performed in the process of outputting the positive output signal and the negative output signal according to PWM+ and PWM-, thereby meeting the needs of different application scenarios and improving the applicability of the signal processing method in the embodiments of the present application.

[0148] In a possible implementation manner, the input signal can be an audio signal, and the positive output signal and the negative output signal can be used to drive a loudspeaker, and the loudspeaker is used to play the audio signal after signal processing. In an example, the positive output signal can be input as a positive terminal of the loudspeaker, and the negative output signal can be input as a negative terminal of the loudspeaker.

[0149] In the embodiments of the present application, the audio signal is processed by the signal processing method in the foregoing embodiments, which can make the efficiency of audio signal processing higher. While improving the efficiency, the entire audio system does not need to use advanced technology, and by optimizing the number of switching and the switching mode, the efficiency of signal processing can also be improved on the audio system using ordinary technology.

[0150] Signal processing circuit

[0151] FIG. 25 shows a schematic diagram of a signal processing circuit according to an embodiment of the present application. As shown in FIG. 25, the signal processing circuit 250 includes a modulation module 251 and a power output module 252. The modulation module 251 is configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal. The power output module 252 is configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses in a pulse period.

[0152] In the embodiment of the present application, the modulation module 251 performs PWM modulation on the input signal to obtain the PWM positive signal and the PWM negative signal. The power output module 252 outputs the positive output signal and the negative output signal according to the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses in a pulse period. That is, there is no common-mode component in the positive output signal and the negative output signal. The differential signal of the positive output signal and the negative output signal is concentrated on a single side, so that there is no loss in the differential-mode pulse width of the positive output signal and the negative output signal. Moreover, since the pulses included in the positive output signal and the negative output signal are generated based on the switching of the switch in the circuit, only one of the positive output signal and the negative output signal includes a pulse, which reduces the number of switching in the process of generating the positive output signal and the negative output signal, thereby improving the output efficiency. In the PWM modulation process, the number of pulses in a unit time is positively correlated with the suppression effect on the loop nonlinearity and noise. When the absolute value of the amplitude of the input signal is greater than a threshold value, one of the positive output signal and the negative output signal includes two pulses in a pulse period. Therefore, the suppression effect on the loop nonlinearity and noise can be improved in the case where the absolute value of the amplitude of the input signal is large, thereby improving the performance of the output signal.

[0153] In a possible implementation, as shown in FIG. 26, the signal processing circuit 250 includes a loop filter unit 2511, a comparison unit 2512, and a logic processing unit 2513.

[0154] The loop filter unit 2511 is configured to perform filtering processing on the input signal to obtain a first positive signal and a first negative signal.

[0155] The comparison unit 2512 is configured to compare the first positive signal and the first negative signal with a triangular wave signal to generate a second positive signal and a second negative signal according to the comparison result. The period of the triangular wave is equal to a pulse period. The second positive signal and the second negative signal are both square wave signals.

[0156] The logic processing unit 2513 is configured to generate a PWM positive signal and a PWM negative signal according to the second positive signal, the second negative signal, and a preset delay duration.

[0157] The positive output signal and the negative output signal output by the power output module 252 can be fed back to the loop filtering unit 2511, and the loop filtering unit 2511 performs filtering processing on the positive input signal and the negative input signal based on the signal fed back by the power output module 252, so as to realize loop filtering.

[0158] In a possible implementation, the logic processing unit 2513 is configured to perform the following processing:

[0159] Differential mode pulse width extraction is performed on the second positive signal and the second negative signal to obtain a first positive differential mode signal and a first negative differential mode signal;

[0160] Differential mode pulse width detection is performed on the first positive differential mode signal and the first negative differential mode signal to obtain a second positive differential mode signal and a second negative differential mode signal;

[0161] Common mode pulse width generation is performed according to the first positive differential mode signal, the first negative differential mode signal, the second positive differential mode signal, and the second negative differential mode signal to obtain a positive common mode signal and a negative common mode signal;

[0162] Differential mode pulse width generation is performed according to the first positive differential mode signal and the first negative differential mode signal to obtain a third positive differential mode signal and a third negative differential mode signal;

[0163] PWM signal generation is performed according to the positive common mode signal, the negative common mode signal, the third positive differential mode signal, the third negative differential mode signal, and the delay duration to obtain the PWM positive signal and the PWM negative signal.

[0164] In a possible implementation, the logic processing unit 2513 is configured to perform the following processing:

[0165] Logical NOT processing is performed on the second positive signal to obtain a first reverse signal;

[0166] The second negative signal is delayed for a preset delay duration to obtain a first delay signal;

[0167] Logical OR NOT processing is performed on the first reverse signal and the first delay signal to obtain the PWM positive signal;

[0168] Logical NOT processing is performed on the second negative signal to obtain a second reverse signal;

[0169] The first positive signal is delayed for the delay duration to obtain a second delay signal;

[0170] The second reverse signal and the second delay signal are subjected to logic OR or NOT processing to obtain a PWM negative direction signal.

[0171] It should be noted that the signal processing circuit in the embodiments of the present application is used to execute the signal processing method in the foregoing embodiments and is based on the same concept as the foregoing signal processing method embodiments. For details and advantages, refer to the description in the foregoing signal processing method embodiments, which will not be repeated here.

[0172] Signal processing chip

[0173] One embodiment of the present application provides a signal processing chip for executing the signal processing method in any of the foregoing embodiments. The signal processing chip can include the signal processing circuit 250 in any of the foregoing embodiments, that is, the signal processing circuit 250 in the foregoing embodiments is packaged in a chip. The signal processing chip can be arranged in an electronic device that has a signal processing requirement such as an audio signal or a power supply signal, and is used for signal processing.

[0174] It should be noted that the signal processing chip in the embodiments of the present application is used to execute the signal processing method in the foregoing embodiments and is based on the same concept as the foregoing signal processing method embodiments. For details and advantages, refer to the description in the foregoing signal processing method embodiments, which will not be repeated here.

[0175] Electronic device

[0176] FIG. 27 shows a schematic diagram of an electronic device according to one embodiment of the present application. As shown in FIG. 27, the electronic device 270 includes a signal source 271, a signal receiving end 272, and a signal processing apparatus 273. The signal processing apparatus 273 can include the signal processing circuit 250 or the signal processing chip in any of the foregoing embodiments.

[0177] The signal processing apparatus 273 is connected between the signal source 271 and the signal receiving end 272. The signal source 271 is configured to transmit an input signal to the signal processing apparatus 273. The signal receiving end 272 is configured to receive a positive direction output signal and a negative direction output signal output by the signal processing apparatus 273.

[0178] The input signal transmitted by the signal source 271 to the signal processing apparatus 273 can be an audio signal. After receiving the positive direction output signal and the negative direction output signal, the signal receiving end 272 can transmit the positive direction output signal and the negative direction output signal to a loudspeaker after LC filtering, so as to drive the loudspeaker to emit sound.

[0179] It should be noted that the electronic device in the embodiments of the present application is implemented based on the signal processing circuit 250 or the signal processing chip in the foregoing embodiments. For specific application of the signal processing circuit 250 and the signal processing chip in the foregoing embodiments, refer to the description in the foregoing signal processing unit embodiments and signal processing chip embodiments for specific content and beneficial effects, which will not be repeated here.

[0180] It should be understood that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the method embodiments, since the method is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can refer to the description of other embodiments.

[0181] It should be understood that the above describes specific embodiments of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired result. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired result. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0182] It should be understood that the elements described herein in singular form or only shown in the drawings as one do not limit the number of the elements to one. In addition, the modules or elements described or shown herein as separate can be combined into a single module or element, and the modules or elements described or shown herein as single can be split into multiple modules or elements.

[0183] It should also be understood that the terms and expressions used herein are only used to describe, and one or more embodiments of the present specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean the exclusion of any equivalent features described (or part thereof). It should be recognized that various modifications that can exist should be included in the scope of the claims. Other modifications, changes and replacements can also exist. Accordingly, the claims should be considered to cover all these equivalents.

Claims

1. A signal processing method, characterized by, The method comprises: performing PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal; outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein in response to an absolute value of an amplitude of the input signal being greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses in a pulse period.

2. The method of claim 1, wherein in response to the absolute value of the amplitude of the input signal being greater than 0 and less than the threshold value, both the positive output signal and the negative output signal include one pulse in a pulse period, and a pulse width of a differential mode signal of the positive output signal and the negative output signal is greater than 0.

3. The method of claim 2, wherein in response to the amplitude of the input signal being equal to 0, both the positive output signal and the negative output signal include one pulse in a pulse period, and a pulse width of a differential mode signal of the positive output signal and the negative output signal is equal to 0.

4. The method of claim 3, wherein, The pulse width of the differential mode signal of the positive output signal and the negative output signal is positively correlated with the absolute value of the amplitude of the input signal.

5. The method of claim 3, wherein in response to the amplitude of the input signal being equal to 0, a pulse width of a pulse included in the positive output signal and the negative output signal is equal to a preset delay duration; in response to the absolute value of the amplitude of the input signal being greater than 0 and less than the threshold value, a pulse width of a pulse included in one of the positive output signal and the negative output signal is greater than the delay duration, and a pulse width of a pulse included in the other of the positive output signal and the negative output signal is less than the delay duration; in response to the absolute value of the amplitude of the input signal being greater than the threshold value, a pulse width of at least one pulse included in the positive output signal or the negative output signal is greater than the delay duration.

6. The method of claim 3, wherein, The PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal comprises: performing filtering processing on the input signal to obtain a first positive signal and a first negative signal; comparing the first positive signal and the first negative signal with a triangular wave signal to generate a second positive signal and a second negative signal according to a comparison result, wherein a period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals; generating the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal, and a preset delay duration.

7. The method of claim 6, wherein, When the amplitude of the input signal is equal to 0, a pulse width of a pulse included in the PWM positive signal and the PWM negative signal is equal to the delay duration, and a front edge of the pulse included in the PWM positive signal and the PWM negative signal is time-aligned with a rising edge of a pulse included in the second positive signal and the second negative signal.

8. The method of claim 6, wherein, The absolute value of the amplitude of the input signal is greater than 0 and less than the threshold value, the rising edge of the pulse included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second positive signal, and the rising edge of the pulse included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal; if the first positive signal is greater than the first negative signal, the pulse width of the pulse included in the PWM positive signal is T diff1 +T d , and the pulse width of the pulse included in the PWM negative signal is T d -T diff2 ; if the first positive signal is less than the first negative signal, the pulse width of the pulse included in the PWM positive signal is T d -T diff2 , and the pulse width of the pulse included in the PWM negative signal is T diff1 +T d ; wherein said T diff1 and T diff2 a pulse width of 2 pulses comprising a differential mode signal of said second positive signal and said second negative signal, said T d for characterizing said time delay duration.

9. The method of claim 6, wherein, An absolute value of the amplitude of the input signal is greater than the threshold value, If the second positive signal and the second negative signal include pulses of low level, the PWM positive signal and the PWM negative signal satisfy: if the first positive signal is greater than the first negative signal, the pulse width of two pulses included in the PWM positive signal are T diff1 +T d and T diff2 -T d respectively, and the PWM negative signal does not include pulses; if the first positive signal is less than the first negative signal, the pulse width of two pulses included in the PWM negative signal are T diff1 +T d and T diff2 -T d respectively, and the PWM positive signal does not include pulses; If the pulses included in the second forward signal and the second backward signal are high level, the PWM forward signal and the PWM backward signal satisfy: if the first forward signal is greater than the first backward signal, the pulse width of the two pulses included in the PWM backward signal are T diff1 +T d and T diff2 -T d respectively, the PWM forward signal does not include pulse; when the first forward signal is less than the first backward signal, the pulse width of the two pulses included in the PWM forward signal are T diff1 +T d and T diff2 -T d respectively, the PWM backward signal does not include pulse. The pulse is included. The PWM forward signal includes 2 pulses, and the pulse width of the PWM forward signal is T diff1 +T d The rising edge of the pulse included in the PWM forward signal is time-aligned with the rising edge of the pulse included in the second forward signal, and the pulse width of the PWM forward signal is T diff2 -T d The falling edge of the pulse included in the PWM forward signal is time-aligned with the falling edge of the pulse included in the second forward signal. The PWM negative signal includes 2 pulses, and the pulse width of the PWM negative signal is T diff1 +T d The rising edge of the pulse included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal, and the pulse width of the PWM negative signal is T diff2 -T d The falling edge of the pulse included in the PWM negative signal is time-aligned with the falling edge of the pulse included in the second negative signal. wherein said T diff1 and T diff2 a pulse width of 2 pulses comprising a differential mode signal of said second positive signal and said second negative signal, said T d for characterizing said time delay duration.

10. The method of claim 6, wherein, The generating the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and a preset delay duration includes: Performing differential mode pulse width extraction on the second positive signal and the second negative signal to obtain a first positive differential mode signal and a first negative differential mode signal; Performing differential mode pulse width detection on the first positive differential mode signal and the first negative differential mode signal to obtain a second positive differential mode signal and a second negative differential mode signal; Performing common mode pulse width generation according to the first positive differential mode signal, the first negative differential mode signal, the second positive differential mode signal and the second negative differential mode signal to obtain a positive common mode signal and a negative common mode signal; Performing differential mode pulse width generation according to the first positive differential mode signal and the first negative differential mode signal to obtain a third positive differential mode signal and a third negative differential mode signal; Performing PWM signal generation according to the positive common mode signal, the negative common mode signal, the third positive differential mode signal, the third negative differential mode signal and the delay duration to obtain the PWM positive signal and the PWM negative signal.

11. The method of claim 6, wherein, The generating the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and a preset delay duration includes: Performing logical NOT processing on the second positive signal to obtain a first reverse signal; Delaying the second negative signal by the delay duration to obtain a first delay signal; Performing logical OR and NOT processing on the first reverse signal and the first delay signal to obtain the PWM positive signal; Performing logical NOT processing on the second negative signal to obtain a second reverse signal; Delaying the first positive signal by the delay duration to obtain a second delay signal; Performing logical OR and NOT processing on the second reverse signal and the second delay signal to obtain the PWM negative signal.

12. The method of any one of claims 5-11, wherein, The delay duration is in a range of [T / 40, T / 10], and T is used to represent a duration of the pulse period.

13. The method according to any one of claims 6-11, characterized in that, The outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal includes: Amplifying an amplitude of the PWM positive signal to obtain the negative output signal, and amplifying an amplitude of the PWM negative signal to obtain the positive output signal; or Amplifying an amplitude of the PWM positive signal to obtain the positive output signal, and amplifying an amplitude of the PWM negative signal to obtain the negative output signal.

14. The method of any one of claims 1-11, wherein, The input signal is an audio signal, and the positive output signal and the negative output signal are used to drive a loudspeaker, and the loudspeaker is used to play the audio signal after signal processing.

15. A signal processing circuit, characterized by comprising: The method includes: A modulation module is configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; A power output module is configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; and In response to an absolute value of the amplitude of the input signal being greater than a threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses in one pulse period.

16. The circuit of claim 15, wherein, The modulation module comprises a loop filtering unit, a comparison unit and a logic processing unit. The loop filtering unit is configured to perform filtering processing on the input signal to obtain a first positive signal and a first negative signal. The comparison unit is configured to compare the first positive signal and the first negative signal with a triangular wave signal, and generate a second positive signal and a second negative signal according to a comparison result, wherein a period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals. The logic processing unit is configured to generate the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and a preset delay duration.

17. The circuit of claim 16, wherein, The logic processing unit is configured to perform the following processing: performing differential mode pulse width extraction on the second positive signal and the second negative signal to obtain a first positive differential mode signal and a first negative differential mode signal; performing differential mode pulse width detection on the first positive differential mode signal and the first negative differential mode signal to obtain a second positive differential mode signal and a second negative differential mode signal; performing common mode pulse width generation according to the first positive differential mode signal, the first negative differential mode signal, the second positive differential mode signal and the second negative differential mode signal to obtain a positive common mode signal and a negative common mode signal; performing differential mode pulse width generation according to the first positive differential mode signal and the first negative differential mode signal to obtain a third positive differential mode signal and a third negative differential mode signal; performing PWM signal generation according to the positive common mode signal, the negative common mode signal, the third positive differential mode signal, the third negative differential mode signal and the delay duration to obtain the PWM positive signal and the PWM negative signal.

18. The circuit of claim 16, wherein, The logic processing unit is configured to perform the following processing: performing logic NOT processing on the second positive signal to obtain a first inverted signal; delaying the second negative signal by the delay duration to obtain a first delayed signal; performing logic OR NOT processing on the first inverted signal and the first delayed signal to obtain the PWM positive signal; performing logic NOT processing on the second negative signal to obtain a second inverted signal; delaying the first positive signal by the delay duration to obtain a second delayed signal; performing logic OR NOT processing on the second inverted signal and the second delayed signal to obtain the PWM negative signal.

19. A signal processing chip, characterized by The signal processing chip is configured to perform the method according to any one of claims 1-14.

20. An electronic device, comprising: The signal processing device comprises: a signal source, a signal receiving end and a signal processing apparatus, wherein the signal processing apparatus comprises the signal processing circuit according to any one of claims 15-18 or the signal processing chip according to claim 19; the signal processing apparatus is connected between the signal source and the signal receiving end; the signal source is configured to transmit an input signal to the signal processing apparatus. The signal receiving end is used for receiving the positive output signal and the negative output signal output by the signal processing device.

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