Signal processing method, circuit and chip, and electronic device

Abstract

Provided in the embodiments of the present application are a signal processing method, circuit and chip, and an electronic device. The signal processing method comprises: performing PWM on an input signal to obtain a PWM positive signal and a PWM negative signal; and outputting a positive output signal and a negative output signal on the basis of the PWM positive signal and the PWM negative signal, wherein in response to the absolute value of the amplitude of the input signal being greater than 0 and less than a first threshold, both the positive output signal and the negative output signal comprise two pulses within one pulse period, and the pulse widths of the pulses included in the positive output signal and the negative output signal are different. The present solution can reduce the frequency requirements of a passive filter for processing positive output signals and negative output signals, thereby reducing the costs of signal processing systems.

Description

Signal processing method, circuit, chip and electronic device TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and in particular to a signal processing method, circuit, chip and electronic device. BACKGROUND

[0002] Pulse-Width Modulation (PWM) is a technology that uses the digital output of a microprocessor to control analog circuits. By modulating the width of the pulse, the required waveform (including shape and amplitude) can be obtained, that is, the voltage and frequency can be adjusted by changing the duty cycle.

[0003] At present, a D-class power amplifier (also known as a digital power amplifier or a switching power amplifier) using PWM technology is used to amplify an audio signal. The D-class power amplifier extracts the output differential component of a comparison unit and sends it to a power output module. The output signal of the power output module drives an audio device through a passive filter.

[0004] The signal frequency supported by the passive filter is inversely related to the cost, that is, the cost of a passive filter supporting a small frequency signal is higher than the cost of a passive filter supporting a large frequency signal. The frequency of the output signal of the power output module in the existing D-class power amplifier is small, and a passive filter supporting a small frequency signal is required, resulting in a high cost of the signal processing system.

[0005] SUMMARY

[0006] In view of this, embodiments of the present application provide a signal processing method, circuit, chip and electronic device to at least partially solve the above problems.

[0007] According to a first aspect of embodiments of the present application, a signal processing method is provided, including: performing PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; and outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an absolute value of an amplitude of the input signal being greater than 0 and less than a first threshold value, the positive output signal and the negative output signal each include 2 pulses in one pulse period, and the pulses included in the positive output signal and the negative output signal have different pulse widths.

[0008] According to a second aspect of the embodiments of the present application, a signal processing circuit is provided, comprising: a modulation module, configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; and a power output module, configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an absolute value of an amplitude of the input signal being greater than 0 and less than a first threshold, the positive output signal and the negative output signal each comprise 2 pulses in a pulse period, and the positive output signal and the negative output signal comprise pulses with different pulse widths.

[0009] According to a third aspect of the embodiments of the present application, a signal processing chip is provided, which is configured to perform the method according to the first aspect.

[0010] According to a fourth aspect of the embodiments of the present application, an electronic device is provided, comprising: a signal source, a signal receiving end and a signal processing apparatus, wherein the signal processing apparatus comprises the signal processing circuit according to the second aspect or the signal processing chip according to the third aspect; the signal processing apparatus is connected between the signal source and the signal receiving end; the signal source is configured to transmit an input signal to the signal processing apparatus; and the signal receiving end is configured to receive a positive output signal and a negative output signal output by the signal processing apparatus.

[0011] According to the scheme of the embodiments of the present application, the input signal is subjected to PWM modulation to obtain a PWM positive signal and a PWM negative signal, and a positive output signal and a negative output signal are output according to the PWM positive signal and the PWM negative signal, and in response to an absolute value of an amplitude of the input signal being greater than 0 and less than a first threshold, the positive output signal and the negative output signal each comprise 2 pulses in a pulse period, and the positive output signal and the negative output signal comprise pulses with different pulse widths. When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold, i.e., when the absolute value of the amplitude of the input signal is small, the positive output signal and the negative output signal output by the power output module each comprise 2 pulses, so that the frequency of the positive output signal and the negative output signal is high, and thus a passive filter supporting a larger signal frequency can be used to process the positive output signal and the negative output signal, and the passive filter supporting a larger signal frequency has a lower cost, so that the cost of the signal processing system can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0013] Figure 1 is a flow chart of a signal processing method according to an embodiment of the present application;

[0014] Figure 2 is a flow chart of a PWM modulation method according to an embodiment of the present application;

[0015] Figure 3 is a schematic diagram of PWM positive signals and PWM negative signals when the amplitude of the input signal is equal to 0 according to an embodiment of the present application;

[0016] Figure 4 is a schematic diagram of PWM positive signals and PWM negative signals when the amplitude of the input signal is equal to 0 according to another embodiment of the present application;

[0017] Figure 5 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is less than a first threshold according to an embodiment of the present application;

[0018] Figure 6 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is less than a first threshold according to another embodiment of the present application;

[0019] Figure 7 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is less than a first threshold according to yet another embodiment of the present application;

[0020] Figure 8 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is less than a first threshold according to still another embodiment of the present application;

[0021] Figure 9 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is greater than a first threshold according to an embodiment of the present application;

[0022] Figure 10 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is greater than a first threshold according to another embodiment of the present application;

[0023] Figure 11 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is greater than a first threshold according to yet another embodiment of the present application;

[0024] Figure 12 is a schematic diagram of PWM positive signals and PWM negative signals when the absolute value of the amplitude of the input signal is greater than a first threshold according to still another embodiment of the present application;

[0025] Figure 13 is a flow chart of a PWM positive signal and PWM negative signal generation method according to an embodiment of the present application;

[0026] Figure 14 is a schematic diagram of a PWM positive signal and PWM negative signal generation process according to an embodiment of the present application;

[0027] Fig. 15 is a schematic diagram of a signal processing circuit according to an embodiment of the present application;

[0028] Fig. 16 is a schematic diagram of a signal processing circuit according to another embodiment of the present application;

[0029] Fig. 17 is a schematic diagram of a signal processing circuit according to yet another embodiment of the present application;

[0030] Fig. 18 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the personnel in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the embodiments of the present application shall belong to the scope of protection of the embodiments of the present application.

[0032] The terms used in the present application are merely for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein means and includes any or all possible combinations of one or more associated listed items.

[0033] It should be understood that although the terms first, second, third, etc. can be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information, without departing from the scope of the present application. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon determination" or "in response to determining".

[0034] In order to make the purposes, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below in combination with the drawings.

[0035] Signal processing method

[0036] Fig. 1 is a flowchart of a signal processing method according to an embodiment of the present application. As shown in Fig. 1, the signal processing method comprises the following steps:

[0037] Step 101, performing PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal.

[0038] The input signal can include a positive input signal and a negative input signal, and the input signal can be an analog signal. The PWM modulation on the input signal can be performed in multiple steps, such as coupling a differential mode signal of the positive input signal and the negative input signal included in the input signal to an input end of the loop filter unit, delivering the filtered signal to the comparison unit and the triangular wave for comparison after the filtering, and performing logical processing on the comparison result to obtain the PWM positive signal and the PWM negative signal.

[0039] The input signal can be an audio signal or other signal requiring PWM modulation.

[0040] In step 102, a positive output signal and a negative output signal are output according to the PWM positive signal and the PWM negative signal.

[0041] After the PWM positive signal and the PWM negative signal are obtained, the PWM positive signal and the PWM negative signal can be processed, such as amplification and inversion, to obtain the positive output signal and the negative output signal, and then the positive output signal and the negative output signal are output. In an example, when the input signal is an audio signal, the output positive output signal and the output negative output signal can be used to drive a loudspeaker after being filtered by a passive filter, such as an LC filter.

[0042] The pulse widths of the PWM positive signal and the PWM negative signal are related to the absolute value of the input signal amplitude, and the positive output signal and the negative output signal are obtained based on the PWM positive signal and the PWM negative signal, so the positive output signal and the negative output signal are related to the absolute value of the input signal amplitude. Specifically, in response to the absolute value of the input signal amplitude being greater than 0 and less than a first threshold, the positive output signal and the negative output signal each include 2 pulses in a pulse period, and the pulse widths of the pulses included in the positive output signal and the negative output signal are different.

[0043] In the embodiments of the present application, the PWM positive signal and the PWM negative signal are obtained by performing PWM modulation on the input signal, and the positive output signal and the negative output signal are output according to the PWM positive signal and the PWM negative signal. When the absolute value of the input signal amplitude is greater than 0 and less than a first threshold, the positive output signal and the negative output signal each include 2 pulses in a pulse period, and the pulse widths of the pulses included in the positive output signal and the negative output signal are different. When the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, i.e., when the absolute value of the input signal amplitude is small, the positive output signal and the negative output signal output by the power output module each include 2 pulses, so that the frequencies of the positive output signal and the negative output signal are high, and thus a passive filter supporting a large signal frequency can be used to process the positive output signal and the negative output signal, and the passive filter supporting the large signal frequency has a low cost, thereby reducing the cost of the signal processing system.

[0044] In a possible implementation, in response to the absolute value of the amplitude of any input signal being within the range of (0, the first threshold value), the pulse width of the pulse included in one of the positive output signal and the negative output signal is equal to a preset second threshold value, and the pulse width of the pulse included in the other of the positive output signal and the negative output signal is greater than the second threshold value. That is, for any first input signal and second input signal whose absolute value of the amplitude is greater than 0 and less than the first threshold value, one of the positive output signal and the negative output signal corresponding to the first input signal includes a pulse with a pulse width equal to the second threshold value, and the other includes a pulse with a pulse width greater than the second threshold value, and one of the positive output signal and the negative output signal corresponding to the second input signal also includes a pulse with a pulse width equal to the second threshold value, and the other includes a pulse with a pulse width greater than the second threshold value.

[0045] When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold value, if the positive output signal includes two pulses with a pulse width equal to the second threshold value in a pulse period, the negative output signal includes two pulses with a pulse width greater than the second threshold value in the pulse period, and if the negative output signal includes two pulses with a pulse width equal to the second threshold value in a pulse period, the positive output signal includes two pulses with a pulse width greater than the second threshold value in the pulse period. It should be noted that the two pulses in a pulse period means that there are only two pulses in a pulse period.

[0046] The amplitude of the input signal refers to the amplitude of the differential mode signal of the positive input signal and the negative input signal, and the amplitude of the input signal can be positive, negative or 0. The signal strength of the input signal is positively correlated with the absolute value of the amplitude. It should be noted that, for ease of description, the amplitude of the input signal described in the following refers to the amplitude of the input signal. The first threshold value is greater than 0 and less than the maximum value of the absolute value of the amplitude of the input signal.

[0047] The positive output signal and the negative output signal can be generated by a power output module according to the PWM positive signal and the PWM negative signal. The pulse width of the differential mode signal of the positive output signal and the negative output signal matches the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal. The second threshold value is greater than the minimum pulse width that can be responded by the power output module. The absolute value of the amplitude of the input signal when the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to the minimum pulse width is defined as a critical amplitude, and the first threshold value is greater than or equal to the critical amplitude.

[0048] In one example, when the absolute value of the input signal amplitude is less than the first threshold, the period (frequency) of the positive output signal and the negative output signal is the same as the period (frequency) of the PWM positive signal and the PWM negative signal, and the period (frequency) of the PWM positive signal and the PWM negative signal is the same as the period (frequency) of the triangular wave. When the absolute value of the input signal amplitude is greater than the first threshold, the frequency of the positive output signal or the negative output signal is equal to 0, that is, one of the positive output signal and the negative output signal does not include a pulse.

[0049] In the embodiments of the present application, the input signal is PWM modulated to obtain a PWM positive signal and a PWM negative signal, and the positive output signal and the negative output signal are output according to the PWM positive signal and the PWM negative signal. When the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, the positive output signal and the negative output signal each include 2 pulses in one pulse period, and the pulse width of the pulse included in one of the positive output signal and the negative output signal is equal to the second threshold, and the pulse width of the pulse included in the other of the positive output signal and the negative output signal is greater than the second threshold. That is, for any input signal whose absolute value of the amplitude is greater than 0 and less than the first threshold, there is always one of the corresponding positive output signal and the negative output signal that includes a pulse with a pulse width equal to the second threshold, and the other output signal includes a pulse with a pulse width greater than the second threshold, which ensures that the differential mode signal of the positive output signal and the negative output signal includes a pulse, so that the differential mode signal of the positive output signal and the negative output signal matches the amplitude of the input signal, and ensures the stability and correctness of processing the input signal.

[0050] Since the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is positively correlated with the absolute value of the input signal amplitude, the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is small when the amplitude of the input signal is small. When the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, that is, when the absolute value of the input signal amplitude is small, the power output module can also respond to the differential mode signal of the PWM positive signal and the PWM negative signal to output the positive output signal and the negative output signal each including 2 pulses, which can then be fed back to the loop filter unit, ensuring the suppression effect of the loop on noise and system nonlinearity, thereby ensuring the quality of the processed signal.

[0051] In one possible implementation, when the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, the falling edge of each pulse included in the positive output signal is time-aligned with the falling edge of the corresponding pulse included in the negative output signal, wherein the pulses included in the positive output signal correspond one-to-one to the pulses included in the negative output signal.

[0052] When the absolute value of the input signal amplitude is greater than 0 and less than the first threshold value, the positive output signal includes a first pulse in time sequence in advance and a second pulse in time sequence in the rear in a pulse period, and the negative output signal includes a third pulse in time sequence in advance and a fourth pulse in time sequence in the rear in a pulse period, the falling edges of the first pulse and the third pulse are in time sequence alignment, and the falling edges of the second pulse and the fourth pulse are in time sequence alignment. If the pulse width of the first pulse and the second pulse is greater than the second threshold value, the pulse width of the third pulse and the fourth pulse is equal to the second threshold value, and if the pulse width of the first pulse and the second pulse is equal to the second threshold value, the pulse width of the third pulse and the fourth pulse is greater than the second threshold value.

[0053] The falling edge of each pulse included in the positive output signal is in time sequence alignment with the falling edge of a corresponding pulse in the negative output signal, and the pulses included in the positive output signal correspond to the pulses included in the negative output signal one by one, so the pulse width of two pulse signals included in the common mode signal of the positive output signal and the negative output signal is equal to the second threshold value. For example, when the pulse width of the first pulse and the second pulse in the above example is equal to the second threshold value, the positive output signal is the common mode signal of the positive output signal and the negative output signal, and when the pulse width of the third pulse and the fourth pulse in the above example is equal to the second threshold value, the negative output signal is the common mode signal of the positive output signal and the negative output signal.

[0054] In the embodiments of the present application, when the absolute value of the input signal amplitude is greater than 0 and less than the first threshold value, the pulse width of the pulse included in the differential mode signal of the PWM positive signal and the PWM negative signal is small, in order to enable the power output module to respond to the PWM positive signal and the PWM negative signal, a common mode signal including two pulses with the second threshold value is added to each pulse period of the PWM positive signal and the PWM negative signal, and when the positive output signal and the negative output signal are generated based on the PWM positive signal and the PWM negative signal, the positive output signal and the negative output signal also include the common mode signal, so that the power output module can also respond to the PWM positive signal and the PWM negative signal when the absolute value of the input signal amplitude is small, and the suppression effect of the loop on noise and system nonlinearity is ensured.

[0055] In a possible implementation, when the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in a pulse period, the pulse width of the pulse included in the positive output signal and the negative output signal is equal to the second threshold value, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, that is, the differential mode signal of the positive output signal and the negative output signal does not include any pulse.

[0056] The positive output signal and the negative output signal match the input signal. When the absolute value of the amplitude of the input signal changes, the differential mode signal of the positive output signal and the negative output signal needs to change accordingly, so as to ensure the correctness of signal processing. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in one pulse period, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, so as to ensure that the differential mode signal of the positive output signal and the negative output signal matches the input signal, and ensure the reliability and accuracy of signal processing.

[0057] When the amplitude of the input signal is equal to 0, the pulse width of the pulse included in the positive output signal and the negative output signal is equal to the second threshold value. The second threshold value can be the minimum pulse width that the power output module can output in response to the PWM positive signal and the PWM negative signal. While ensuring that the power output module can output a pulse to ensure the suppression effect of the loop on noise and system nonlinearity, a lower power consumption is ensured in the standby state.

[0058] In the embodiment of the present application, the number and pulse width of the pulse included in the common mode signal of the positive output signal and the negative output signal are negatively related to the efficiency of signal processing, which can indicate power consumption. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse in each pulse period, so that the common mode signal of the positive output signal and the negative output signal includes a smaller number of pulses, ensuring a lower power consumption in the standby state. When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse, ensuring that the feedback loop in the signal processing process can operate normally, thereby ensuring the performance of signal processing. The feedback loop is composed of a loop filter unit, a comparison unit, a logic processing unit and a power output module. The differential mode signal of the positive input signal and the negative input signal is coupled to the input end of the loop filter unit, and is transmitted to the comparison unit and the triangular wave after filtering processing, and then the comparison result is logically processed to obtain the PWM positive signal and the PWM negative signal. The power output module generates the positive output signal and the negative output signal based on the PWM positive signal and the PWM negative signal. The power output module feeds back the positive output signal and the negative output signal to the loop filter unit. The loop filter unit filters the input positive input signal and negative input signal based on the feedback positive output signal and negative output signal.

[0059] In a possible implementation, when the absolute value of the amplitude of the input signal is greater than the first threshold value, one of the positive output signal and the negative output signal does not include a pulse, and the other of the positive output signal and the negative output signal includes two pulses with a pulse width greater than the second threshold value in one pulse period.

[0060] When the absolute value of the amplitude of the input signal is greater than the first threshold, if the positive output signal does not include a pulse, the negative output signal includes 2 pulses in a pulse period, and if the negative output signal does not include a pulse, the positive output signal includes 2 pulses in a pulse period. It should be noted that the 2 pulses in a pulse period means that there are only 2 pulses in a pulse period.

[0061] In the embodiment of the present application, the input signal is PWM modulated to obtain a PWM positive signal and a PWM negative signal, and the positive output signal and the negative output signal are output according to the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than the first threshold, one of the positive output signal and the negative output signal does not include a pulse, and the other includes 2 pulses in a pulse period, that is, there is no common mode component in the positive output signal and the negative output signal, and the differential signal of the positive output signal and the negative output signal is concentrated on a single side, so that the differential mode pulse width of the positive output signal and the negative output signal does not exist. Since the pulses included in the positive output signal and the negative output signal are generated based on the switching of the switch tube in the circuit, only one of the positive output signal and the negative output signal includes a pulse, which reduces the switching times of the switch tube in the process of generating the positive output signal and the negative output signal, thereby improving the output efficiency. In the PWM modulation process, the number of pulse occurrences per unit time is positively correlated with the suppression effect on the loop nonlinearity and noise. When the absolute value of the amplitude of the input signal is greater than the first threshold, one of the positive output signal and the negative output signal includes 2 pulses in a pulse period, so the suppression effect on the loop nonlinearity and noise can be improved when the absolute value of the amplitude of the input signal is large, thereby improving the performance of the output signal.

[0062] In a possible implementation, the pulse width of the differential mode signal of the positive output signal and the negative output signal is positively correlated with the absolute value of the amplitude of the input signal.

[0063] In the embodiment of the present application, when the amplitude of the input signal is equal to 0, the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, when the absolute value of the amplitude of the input signal is greater than 0, the pulse width of the differential mode signal of the positive output signal and the negative output signal is greater than 0, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is positively correlated with the absolute value of the amplitude of the input signal, so that the change of the input signal after processing can be correctly reflected on the differential mode signal of the positive output signal and the negative output signal, thereby ensuring the accuracy and reliability of signal processing.

[0064] In a possible implementation, the processing of the input signal can be based on a preset second threshold value, and according to different absolute values of the amplitude of the input signal, the pulse width of the pulses included in the positive output signal and the negative output signal satisfies the following relationship with the second threshold value:

[0065] (1) When the amplitude of the input signal is equal to 0, the pulse width of the pulses included in the positive output signal and the negative output signal is equal to the second threshold value;

[0066] (2) When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold value, the pulse width of the pulses included in one of the positive output signal and the negative output signal is greater than the second threshold value, and the pulse width of the pulses included in the other of the positive output signal and the negative output signal is equal to the second threshold value;

[0067] (3) When the absolute value of the amplitude of the input signal is greater than the first threshold value, the pulse width of the two pulses included in the positive output signal or the negative output signal is greater than the second threshold value.

[0068] When the amplitude of the input signal is equal to 0, the positive output signal and the negative output signal each include one pulse with a pulse width equal to the second threshold value, and the pulse width of the differential mode signal of the positive output signal and the negative output signal is equal to 0, that is, the rising edge and the falling edge of the pulses included in the positive output signal and the negative output signal are time-aligned, so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, ensuring the accuracy of signal processing.

[0069] When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold value, the positive output signal and the negative output signal each include two pulses. When the pulse width of the two pulses included in the positive output signal is greater than the second threshold value, the pulse width of the two pulses included in the negative output signal is equal to the second threshold value, and when the pulse width of the two pulses included in the negative output signal is greater than the second threshold value, the pulse width of the two pulses included in the positive output signal is equal to the second threshold value. When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold value, the falling edge of each pulse included in the positive output signal is time-aligned with the falling edge of one pulse included in the negative output signal, so that the pulse width of the differential mode signal of the positive output signal and the negative output signal is not equal to 0, and as the absolute value of the amplitude of the input signal increases (decreases), the pulse width of the differential mode signal of the positive output signal and the negative output signal correspondingly increases (decreases), so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, ensuring the accuracy of signal processing.

[0070] When the absolute value of the amplitude of the input signal is greater than the first threshold value, one of the positive output signal and the negative output signal includes two pulses, and the other of the positive output signal and the negative output signal does not include a pulse, and the pulse width of the two pulses included in the output signal including the two pulses is greater than the second threshold value. When the absolute value of the amplitude of the input signal is greater than the first threshold value, if the positive output signal includes two pulses, the pulse width of the two pulses included in the positive output signal is greater than the second threshold value, and if the negative output signal includes two pulses, the pulse width of the two pulses included in the negative output signal is greater than the second threshold value. When the absolute value of the amplitude of the input signal is greater than the first threshold value, as the absolute value of the amplitude of the input signal increases (decreases), the sum of the pulse widths of the two pulses included in the positive output signal or the negative output signal correspondingly increases (decreases), so that the differential mode signal of the positive output signal and the negative output signal matches the input signal, and the accuracy of signal processing is ensured.

[0071] In the embodiments of the present application, the pulse width of the pulses included in the positive output signal and the negative output signal is related to the preset second threshold value, and the performance of the output signal is related to the pulse width of the pulses included in the positive output signal and the negative output signal. The second threshold value can be set according to the requirement for the performance of the output signal, for example, the second threshold value can be 1 / 40 to 1 / 10 of the period of a triangular wave. On the premise of meeting the requirement for the performance of the output signal, a smaller delay duration is set, so that the pulse width of the pulses included in the positive output signal and the negative output signal is smaller when the amplitude of the input signal is equal to 0, thereby reducing standby power consumption.

[0072] In a possible implementation, when the input signal is PWM modulated, a square wave signal can be generated based on the input signal, and then the PWM positive signal and the PWM negative signal can be generated based on the generated square wave signal and the second threshold value. As shown in the flowchart of the PWM modulation method in FIG. 2, the input signal can be PWM modulated by the method including the following steps:

[0073] In step 201, the input signal is filtered to obtain a first positive signal and a first negative signal.

[0074] The input signal includes a positive input signal and a negative input signal. The first positive signal and the first negative signal can be obtained by filtering the positive input signal and the negative input signal. For example, the differential mode signal of the positive input signal and the negative input signal is coupled to the input end of a loop filter unit, and the first positive signal and the first negative signal can be obtained by filtering the positive input signal and the negative input signal through the loop filter unit.

[0075] In one example, the loop filter unit does not perform reverse processing at its output end, the waveform of the first positive signal matches the waveform of the positive input signal, and the waveform of the first negative signal matches the waveform of the negative input signal.

[0076] In another example, the loop filter unit performs reverse processing at its output end, the waveform of the first positive signal matches the waveform of the negative input signal, and the waveform of the first negative signal matches the waveform of the positive input signal. Wherein, the output end of the loop filter unit outputs the first positive signal and the first negative signal.

[0077] Step 202, compare the first positive signal and the first negative signal with the triangular wave, and generate the second positive signal and the second negative signal according to the comparison result.

[0078] After obtaining the first positive signal and the first negative signal, the first positive signal and the first negative signal can be input into the comparison unit, and the comparison unit compares the first positive signal and the first negative signal with the triangular wave respectively, generates the second positive signal according to the comparison result of the first positive signal and the triangular wave, and generates the second negative signal according to the comparison result of the first negative signal and the triangular wave.

[0079] When the comparison unit compares the first positive signal and the first negative signal with the triangular wave, it determines the second positive signal / second negative signal according to the size relationship between the first positive signal / first negative signal and the triangular wave.

[0080] In one example, as shown in the schematic diagram of the second positive signal and the second negative signal in FIG. 3, the first positive signal IN+ (the first negative signal IN-) is greater than the signal segment of the triangular wave, which corresponds to the high level of the second positive signal CMP+ (the second negative signal CMP-), and the first positive signal IN+ (the first negative signal IN-) is less than the signal segment of the triangular wave, which corresponds to the low level of the second positive signal CMP+ (the second negative signal CMP-).

[0081] In another example, as shown in the schematic diagram of the second positive signal and the second negative signal in FIG. 4, the first positive signal IN+ (the first negative signal IN-) is greater than the signal segment of the triangular wave, which corresponds to the low level of the second positive signal CMP+ (the second negative signal CMP-), and the first positive signal IN+ (the first negative signal IN-) is less than the signal segment of the triangular wave, which corresponds to the high level of the second positive signal CMP+ (the second negative signal CMP-).

[0082] It should be noted that FIG. 3 and FIG. 4 show the triangular waves of two pulse periods. For the convenience of the description, in the subsequent embodiments, the first positive signal is denoted as IN+, the first negative signal is denoted as IN-, the second positive signal is denoted as CMP+, the second negative signal is denoted as CMP-, the PWM positive signal is denoted as PWM+, and the PWM negative signal is denoted as PWM-.

[0083] When the IN+ and IN- signals are compared with the triangular wave to generate the CMP+ and CMP- signals, the reverse processing can be performed or not. In the case where the reverse processing is not performed, the waveforms of the CMP+ and CMP- signals are as shown in FIG. 3, and in the case where the reverse processing is performed, the waveforms of the CMP+ and CMP- signals are as shown in FIG. 4. Whether the reverse processing is performed when the CMP+ and CMP- signals are generated can be set according to the application scene requirement, so as to meet different requirements and improve the applicability of the signal processing method in the embodiments of the present application.

[0084] In step 203, the PWM positive signal and the PWM negative signal are generated according to the second positive signal, the second negative signal, and the second threshold value.

[0085] After the second positive signal and the second negative signal are generated, the second positive signal and the second negative signal can be logically processed based on the second threshold value, and then the PWM positive signal and the PWM negative signal are generated.

[0086] In the embodiments of the present application, the positive output signal and the negative output signal are generated based on the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than the first threshold value and less than the first threshold value, the PWM positive signal and the PWM negative signal are generated based on the second positive signal, the second negative signal, and the second threshold value, without the need to generate the PWM positive signal and the PWM negative signal in a feedback manner through a complex feedback network, so as to make the signal processing simpler and reduce the cost of the signal processing circuit.

[0087] In a possible implementation manner, when the amplitude of the input signal is equal to 0, the PWM positive signal and the PWM negative signal each include one pulse with a pulse width equal to the second threshold value, and the falling edges of the pulses included in the PWM positive signal and the PWM negative signal are each time-aligned with the falling edges of the pulses included in the second positive signal and the second negative signal.

[0088] The pulses included in the second positive signal and the second negative signal can be low level or high level. In the second positive signal and the second negative signal, if the pulse is low level, the leading edge of the pulse is a falling edge, and the trailing edge of the pulse is a rising edge; if the pulse is high level, the leading edge of the pulse is a rising edge, and the trailing edge of the pulse is a falling edge. The following takes the second positive signal (the second negative signal) as an example to describe the PWM positive signal and the PWM negative signal, respectively, when the pulses included in the second positive signal (the second negative signal) are low level and high level.

[0089] When no reverse processing is performed in the generation of the CMP+ and the CMP-, the PWM positive signal and the PWM negative signal are as shown in FIG. 3, the pulses included in the CMP+ and the CMP- are low level, the pulses included in the PWM+ and the PWM- are high level, the differential mode signal Diff of the CMP+ and the CMP- does not include a pulse, the falling edges of the pulses included in the PWM+ and the PWM- are time-aligned with the falling edges (leading edges) of the pulses included in the CMP+ and the CMP-, and the pulse widths of the pulses included in the PWM+ and the PWM- are equal to the second threshold T c .

[0090] When reverse processing is performed in the generation of the CMP+ and the CMP-, the PWM positive signal and the PWM negative signal are as shown in FIG. 4, the pulses included in the CMP+ and the CMP- are high level, the pulses included in the PWM+ and the PWM- are high level, the differential mode signal Diff of the CMP+ and the CMP- does not include a pulse, the falling edges of the pulses included in the PWM+ and the PWM- are time-aligned with the falling edges (trailing edges) of the pulses included in the CMP+ and the CMP-, and the pulse widths of the pulses included in the PWM+ and the PWM- are equal to the second threshold T c .

[0091] It should be noted that FIG. 3 and FIG. 4 show the PWM+ and the PWM- in two pulse periods.

[0092] In the embodiments of the present application, when the amplitude of the input signal is equal to 0, the pulse widths of the pulses included in the PWM positive signal and the PWM negative signal are equal to the second threshold, the falling edges of the pulses included in the PWM positive signal and the PWM negative signal are time-aligned with the falling edges of the pulses included in the second positive signal and the second negative signal, the differential mode signal of the PWM positive signal and the PWM negative signal does not include any pulse, the differential mode signal of the PWM positive signal and the PWM negative signal matches the input signal, and the accuracy of signal processing is ensured. In addition, by setting a small second threshold, the pulse widths of the pulses included in the PWM positive signal and the PWM negative signal when the amplitude of the input signal is equal to 0 can be small, the suppression effect on the loop nonlinearity and noise is ensured, and standby power consumption is reduced.

[0093] In a possible implementation, when the absolute value of the input signal amplitude is greater than 0 and less than the first threshold value, in one pulse period, the PWM positive signal and the PWM negative signal each include two pulses, and the falling edges of the two pulses included in the PWM positive signal are time-aligned with the falling edges of the two pulses included in the PWM negative signal. According to the size relationship between the first positive signal and the first negative signal, the pulse widths of the pulses included in the PWM positive signal and the PWM negative signal are different.

[0094] In the process of generating the CMP+ and the CMP-, no reverse processing is performed, that is, when the pulses included in the CMP+ and the CMP- are low, if the absolute value of the input signal amplitude is greater than 0 and less than the first threshold value, and IN+ is greater than IN-, the PWM+ and the PWM- are as shown in FIG. 5. Referring to FIG. 5, the pulses included in the CMP+ and the CMP- are low, the pulses included in the PWM+ and the PWM- are high, the pulse widths of the two pulses included in the PWM+ are T diff1 +T c and T diff2 +T c , respectively, and the pulse widths of the two pulses included in the PWM- are both T c . The rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM+ is time-aligned with the falling edge of the pulse included in the CMP-, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM+ is time-aligned with the rising edge of the pulse included in the CMP+. The rising edge of the pulse included in the PWM- is time-aligned with the falling edge of the pulse included in the CMP+, and the rising edge of the other pulse included in the PWM- is time-aligned with the rising edge of the pulse included in the CMP-.

[0095] In the process of generating the CMP+ and the CMP-, no reverse processing is performed, that is, when the pulses included in the CMP+ and the CMP- are low, if the absolute value of the input signal amplitude is greater than 0 and less than the first threshold value, and IN+ is less than IN-, the PWM+ and the PWM- are as shown in FIG. 6. Referring to FIG. 6, the pulses included in the CMP+ and the CMP- are low, the pulses included in the PWM+ and the PWM- are high, the pulse widths of the two pulses included in the PWM+ are both T c , respectively, and the pulse widths of the two pulses included in the PWM- are T diff1 +T c and T diff2 +T c , respectively. The rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM- is time-aligned with the falling edge of the pulse included in the CMP+, and the rising edge of the pulse with the pulse width of T diff2 +T cThe rising edge of the pulse is aligned with the rising edge of the pulse included in CMP-. The rising edge of one pulse included in PWM+ is aligned with the falling edge of the pulse included in CMP-, and the rising edge of another pulse included in PWM+ is aligned with the rising edge of the pulse included in CMP+.

[0096] The generation of CMP+ and CMP- is reversed. That is, when the pulses included in CMP+ and CMP- are high-level, if the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, and IN+ is greater than IN-, then PWM+ and PWM- are generated as shown in Figure 7. Referring to Figure 7, the pulses included in CMP+ and CMP- are high-level, the pulses included in PWM+ and PWM- are high-level, and the pulse width of both pulses included in PWM+ is T. c PWM includes two pulses with pulse widths T and T, respectively. diff1 +T c and T diff2 +T c PWM includes pulse widths of T. diff1 +T c The rising edge of the pulse is aligned with the rising edge timing of the pulse included in CMP, and the pulse width included in PWM is T. diff2 +T c The rising edge of the pulse is timed to the falling edge of the pulse included in CMP+. The rising edge of one pulse included in PWM+ is timed to the rising edge of the pulse included in CMP+, and the rising edge of another pulse included in PWM+ is timed to the falling edge of the pulse included in CMP-.

[0097] The generation of CMP+ and CMP- is reversed. That is, when the pulses included in CMP+ and CMP- are high-level, if the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, and IN+ is less than IN-, then PWM+ and PWM- are generated as shown in Figure 8. Referring to Figure 8, the pulses included in CMP+ and CMP- are high-level, and the pulses included in PWM+ and PWM- are also high-level. The pulse widths of the two pulses included in PWM+ are T... diff1 +T c and T diff2 +T c PWM includes two pulses, both with a pulse width of T. c PWM+ includes a pulse width of T. diff1 +T c The rising edge of the pulse is aligned with the rising edge timing of the pulse included in CMP+, and the pulse width included in PWM+ is T. diff2 +T cthe rising edge of one pulse of PWM- is time-aligned with the falling edge of a pulse of CMP-, the rising edge of another pulse of PWM- is time-aligned with the rising edge of a pulse of CMP+.

[0098] It is noted that Figs. 5-8 show two pulse periods of PWM+ and PWM-, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 is used to represent the pulse width of the two pulses of Diff.

[0099] Without inverting the process of generating CMP+ and CMP-, if IN+ is greater than IN- when the absolute value of the input signal amplitude is greater than 0 and less than a first threshold, see Fig. 5, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increase, the pulse width of the pulses of PWM+ starts to increase from T c , the pulse width of the pulses of PWM- remains T c unchanged, and the sum of the pulse widths of the pulses of the differential mode signal of PWM+ and PWM- equals T diff1 + T diff2 .

[0100] Without inverting the process of generating CMP+ and CMP-, if IN+ is less than IN- when the absolute value of the input signal amplitude is greater than 0 and less than a first threshold, see Fig. 6, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increase, the pulse width of the pulses of PWM+ remains T c unchanged, the pulse width of the pulses of PWM- starts to increase from T c , and the sum of the pulse widths of the pulses of the differential mode signal of PWM+ and PWM- equals T diff1 + T diff2 .

[0101] With inverting the process of generating CMP+ and CMP-, if IN+ is greater than IN- when the absolute value of the input signal amplitude is greater than 0 and less than a first threshold, see Fig. 7, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increase, the pulse width of the pulses of PWM+ remains T c unchanged, the pulse width of the pulses of PWM- starts to increase from T c , and the sum of the pulse widths of the pulses of the differential mode signal of PWM+ and PWM- equals T diff1 + T diff2 .

[0102] When the generation of CMP+ and CMP- is reversed, if the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, and if IN+ is less than IN- (see Figure 8), as the absolute value of the input signal amplitude increases, T... diff1 and T diff2 Increase, PWM+ includes pulse width from T C Start increasing, PWM - the pulse width of the included pulse remains T C The sum of the pulse widths of the differential signals in PWM+ and PWM- remains unchanged and equal to T. diff1 +T diff2 .

[0103] In this embodiment, when the absolute value of the input signal amplitude is greater than 0 and less than the first threshold, both PWM+ and PWM- include two pulses, and the sum of the pulse widths of the differential mode signals of PWM+ and PWM- is equal to T. diff1 +T diff2 When the absolute value of the input signal amplitude changes, T diff1 +T diff2 The corresponding changes in the input signal are reflected in the differential signals of PWM+ and PWM-, thus ensuring the accuracy of signal processing. Furthermore, the pulses included in PWM+ and PWM- are both greater than or equal to T. c This enables the power output module to respond to PWM+ and PWM-, thereby ensuring the suppression of loop nonlinearity and noise.

[0104] In one possible implementation, when the absolute value of the input signal amplitude is greater than a first threshold, the pulse widths of the pulses included in the PWM positive signal and the PWM negative signal are different according to the magnitude relationship between the first positive signal and the first negative signal.

[0105] No reverse processing is performed during the generation of CMP+ and CMP-. That is, when the pulses included in CMP+ and CMP- are low level, if the absolute value of the input signal amplitude is greater than the first threshold, and IN+ is greater than IN-, then PWM+ and PWM- are generated as shown in Figure 9. Referring to Figure 9, the pulses included in CMP+ and CMP- are low level, and the pulses included in PWM+ are high level. The pulse widths of the two pulses included in PWM+ are T... diff1 and T diff2 PWM- does not include the pulse. PWM+ includes a pulse width of T. diff1 The rising edge of the pulse is aligned with the falling edge of the pulse included in CMP-, and the pulse width included in PWM+ is T. diff1 The falling edge of the pulse is aligned with the falling edge timing of the pulse included in CMP+. PWM+ includes a pulse width of T. diff2the rising edge of the pulse of CMP+ is time-aligned with the falling edge of the pulse of CMP-, and the pulse width of PWM- is T diff2 the falling edge of the pulse of CMP+ is time-aligned with the rising edge of the pulse of CMP-.

[0106] If the absolute value of the amplitude of the input signal is greater than the first threshold value, and IN+ is less than IN- when the pulses of CMP+ and CMP- are low, PWM+ and PWM- are as shown in Fig. 10. Referring to Fig. 10, the pulses of CMP+ and CMP- are low, the pulse of PWM- is high, and the pulse of PWM+ is absent, and the pulse widths of the two pulses of PWM- are T diff1 and T diff2 , respectively. The pulse width of PWM- is T diff1 the rising edge of the pulse of PWM- is time-aligned with the falling edge of the pulse of CMP+, and the pulse width of PWM- is T diff1 the falling edge of the pulse of PWM- is time-aligned with the falling edge of the pulse of CMP-, and the pulse width of PWM- is T diff2 the rising edge of the pulse of PWM- is time-aligned with the rising edge of the pulse of CMP-, and the pulse width of PWM- is T diff2 the falling edge of the pulse of PWM- is time-aligned with the rising edge of the pulse of CMP+.

[0107] If the absolute value of the amplitude of the input signal is greater than the first threshold value, and IN+ is greater than IN- when the pulses of CMP+ and CMP- are high, PWM+ and PWM- are as shown in Fig. 11. Referring to Fig. 11, the pulses of CMP+ and CMP- are high, the pulse of PWM- is high, and the pulse of PWM+ is absent, and the pulse widths of the two pulses of PWM- are T diff1 and T diff2 , respectively. The pulse width of PWM- is T diff1 the rising edge of the pulse of PWM- is time-aligned with the rising edge of the pulse of CMP-, and the pulse width of PWM- is T diff1 the falling edge of the pulse of PWM- is time-aligned with the rising edge of the pulse of CMP+, and the pulse width of PWM- is T diff2 the rising edge of the pulse of PWM- is time-aligned with the falling edge of the pulse of CMP+, and the pulse width of PWM- is T diff2 the falling edge of the pulse of PWM- is time-aligned with the falling edge of the pulse of CMP-.

[0108] In the generation of CMP+ and CMP-, the reverse processing is performed, that is, if the absolute value of the input signal amplitude is greater than the first threshold value and IN+ is less than IN- when the pulses included in CMP+ and CMP- are high, PWM+ and PWM- are as shown in FIG. 12. Referring to FIG. 12, the pulses included in CMP+ and CMP- are high, the pulses included in PWM+ are high, and PWM- does not include pulses. The pulse width of the two pulses included in PWM+ is T diff1 and T diff2 , respectively. The rising edge of the pulse included in PWM+ with a pulse width of T diff1 is time-aligned with the rising edge of the pulse included in CMP+. The falling edge of the pulse included in PWM+ with a pulse width of T diff1 is time-aligned with the rising edge of the pulse included in CMP-. The rising edge of the pulse included in PWM+ with a pulse width of T diff2 is time-aligned with the falling edge of the pulse included in CMP-. The falling edge of the pulse included in PWM+ with a pulse width of T diff2 is time-aligned with the falling edge of the pulse included in CMP+.

[0109] It should be noted that FIGS. 5-8 show two pulse periods of PWM+ and PWM-, Diff is used to represent the differential mode signal of CMP+ and CMP-, T diff1 and T diff2 are used to represent the pulse width of the two pulses included in Diff. Referring to FIGS. 9-12, when the absolute value of the input signal amplitude is greater than the first threshold value, as the absolute value of the input signal amplitude increases, T diff1 and T diff2 increase, the pulse width of the pulses included in PWM+ or PWM- starts to increase from 2T c , and the sum of the pulse width of the pulses included in the differential mode signal of PWM+ and PWM- is equal to T diff1 + T diff2 .

[0110] In the embodiment of the present application, when the absolute value of the input signal amplitude is greater than the first threshold value, one of the PWM+ and the PWM- includes two pulses, and the other one does not include a pulse. Under the premise that the frequency of the triangular wave is constant, the PWM+ or the PWM- includes two pulses in one pulse period, which improves the suppression effect on the loop nonlinearity and noise, thereby improving the performance of the output signal. One of the PWM+ and the PWM- includes a pulse, and the other one does not include a pulse, that is, there is no common-mode component in the PWM+ and the PWM-, and the differential signal of the PWM+ and the PWM- is concentrated on one side, so that there is no loss in the differential-mode pulse width of the PWM+. Since the pulses included in the positive output signal and the negative output signal are generated based on the switching of the switch tube in the circuit, one of the positive output signal and the negative output signal does not include a pulse in one pulse period, and the other one includes two pulses. Compared with the case where the positive output signal and the negative output signal each include one pulse, the frequency of the pulse is increased, and the number of switching of the switch tube is not increased, thereby improving the performance of the output signal while ensuring the output efficiency. In the PWM modulation process, the number of occurrences of the pulse in a unit time is positively correlated with the suppression effect on the loop nonlinearity and noise. When the absolute value of the input signal amplitude is greater than the first threshold value, one of the positive output signal and the negative output signal includes two pulses in one pulse period, so that the suppression effect on the loop nonlinearity and noise can be improved in the case where the absolute value of the input signal amplitude is large, thereby improving the performance of the output signal.

[0111] In a possible implementation, the CMP+, the CMP-, and the second threshold value T c When the PWM+ and the PWM- are generated, the CMP+ and the CMP- can be subjected to reverse delay processing and then subjected to logic processing to obtain the PWM+ and the PWM-. FIG. 13 shows a flowchart of a method for generating the PWM+ and the PWM- according to an embodiment of the present application. As shown in FIG. 13, the method includes the following steps.

[0112] In step 1301, the second positive signal is subjected to logic non-processing after being delayed for a preset delay time to obtain a first delay reverse signal.

[0113] In step 1302, the first delay reverse signal and the second negative signal are subjected to logic or non-processing to obtain a third positive signal.

[0114] In step 1303, if the pulse width of the pulse included in the third positive signal is greater than the second threshold value, the third positive signal is determined as a fourth positive signal; or if the pulse width of the pulse included in the third positive signal is less than the second threshold value, the pulse width timing of the pulse included in the third positive signal is increased by the second threshold value, to obtain the fourth positive signal.

[0115] Step 1304, performing logical NOT processing on the second negative signal after delaying for a preset delay duration, to obtain a second delayed reverse signal;

[0116] Step 1305, performing logical OR processing on the second delayed reverse signal and the second positive signal, to obtain a third negative signal;

[0117] Step 1306, if the pulse width of the pulse included in the third negative signal is greater than the second threshold value, determining the third negative signal as a fourth negative signal; if the pulse width of the pulse included in the third negative signal is less than the second threshold value, increasing the pulse width timing of the pulse included in the third negative signal by the second threshold value, to obtain the fourth negative signal;

[0118] Step 1307, performing logical OR processing on the fourth positive signal and the fourth negative signal, to obtain a fifth signal;

[0119] Step 1308, performing logical OR processing on the third positive signal and the fifth signal, to obtain a PWM positive signal;

[0120] Step 1309, performing logical OR processing on the third negative signal and the fifth signal, to obtain a PWM negative signal.

[0121] It should be noted that steps 1301 to 1303 are sequentially executed, and steps 1304 to 1306 are sequentially executed, and steps 1301 to 1303 can be executed synchronously with steps 1304 to 1306.

[0122] When the amplitude of the input signal is equal to 0, the differential mode signal of CMP+ and CMP- does not include a pulse, and after performing logical NOT processing on CMP+ and CMP- and delaying for a preset delay duration, a first delayed reverse signal and a second delayed reverse signal are generated, which are trigger signals of the common mode pulse width when the amplitude of the input signal is equal to 0, so that PWM+ and PWM- can include a pulse with a pulse width equal to the second threshold value T c , ensuring that the feedback loop can operate normally in the signal processing process, thereby ensuring the performance of the signal processing.

[0123] When the absolute value of the amplitude of the input signal is greater than 0, the differential mode signal of CMP+ and CMP- includes a pulse, so the setting of the delay duration is to generate the trigger signal of the common mode pulse width when the amplitude of the input signal is equal to 0, and therefore a smaller delay duration can meet the requirements. The delay duration can be in the range of [1ns, 10ns], for example, the delay duration can be set to 5ns, where ns is nanosecond.

[0124] In a possible implementation, Fig. 14 shows a schematic diagram of the PWM+ and PWM- generation process according to an embodiment of the present application. As shown in Fig. 14, the generation of PWM+ and PWM- includes processes such as differential mode pulse width extraction, differential mode pulse width detection, common mode pulse width generation, and output pulse width generation.

[0125] The differential mode pulse width extraction process includes differential mode pulse width extraction on CMP+ and CMP- to obtain a first positive differential mode signal DM+ and a first negative differential mode signal DM-.

[0126] The differential mode pulse width detection process includes differential mode pulse width detection on the first positive differential mode signal DM+ and the first negative differential mode signal DM- to obtain a second positive differential mode signal B+ and a second negative differential mode signal B-.

[0127] The common mode pulse width generation process includes common mode pulse width generation according to the second positive differential mode signal B+ and the second negative differential mode signal B- to obtain a positive common mode signal CM+ and a negative common mode signal CM-.

[0128] The differential mode pulse width generation process includes PWM signal generation according to the first positive differential mode signal DM+, the first negative differential mode signal DM-, the positive common mode signal CM+, the negative common mode signal CM-, and a preset second threshold to obtain PWM+ and PWM-.

[0129] In the embodiments of the present application, differential mode pulse width extraction, differential mode pulse width detection, common mode pulse width generation, and output pulse width generation are performed based on CMP+ and PWM- to obtain PWM+ and PWM-. The pulse widths of CMP+ and CMP- can be determined through differential mode pulse width detection, and PWM+ and PWM- are then generated according to the pulse widths of CMP+ and CMP- without increasing the common mode pulse width or increasing the common mode pulse width by a fixed size, thereby ensuring the quality of signal processing.

[0130] In a possible implementation, the absolute value of the input signal amplitude can be divided into three segments according to a preset first threshold. The amplitude of the input signal equal to 0 is defined as a standby state, the absolute value of the input signal amplitude greater than 0 and less than the first threshold is defined as a small amplitude segment, and the absolute value of the input signal amplitude greater than the first threshold is defined as a large amplitude segment. As described above with reference to Figs. 3-12, the critical condition from the standby state to the small amplitude segment is that the pulse widths of the pulses included in PWM+ and PWM- change from the same to different, and the critical condition from the small amplitude segment to the large amplitude segment is that only one of PWM+ and PWM- includes a pulse. In the small amplitude segment, the pulse widths of the two pulses included in the differential mode signals of CMP+ and CMP- satisfy 0 < T diff1 <T c and 0 < T diff2 <T cIn the large amplitude section, the pulse width of the two pulses included in the differential mode signal of CMP+ and CMP- satisfies T c <T diff1 <T and T c <T diff2 <T.

[0131] The second threshold value T c The value range of the second threshold value T is [T / 40, T / 10], where T is used to represent the time length of the pulse period. For example, the time length of the delay can be T / 40, T / 30, T / 20, T / 10, etc.

[0132] It should be noted that the second threshold value can be a pre-set fixed value, or can be dynamically changed. For example, when the input signal is an analog signal or a digital signal, the second threshold value is a pre-set fixed value, and when the input signal is a digital signal, the second threshold value can be dynamically adjusted according to the power size of the input signal, so as to balance the performance of the output signal and the efficiency of signal processing.

[0133] In one example, the time length of the delay matches the frequency of the triangular wave. For example, when the frequency of the triangular wave is large, a smaller time length of the delay can be set, and when the frequency of the triangular wave is small, a larger time length of the delay can be set.

[0134] In the embodiments of the present application, when the amplitude of the input signal is equal to 0, the pulse width of the pulse included in the common mode signal of PWM+ and PWM- is negatively correlated with the signal processing efficiency, and at the same time, when the pulse width of the pulse included in PWM+ and PWM- is too small, the power output module cannot respond. The pulse width of the pulse included in PWM+ and PWM- when the amplitude of the input signal is equal to 0 is determined by the second threshold value, so the value range of the second threshold value is set to [T / 40, T / 10], so as to ensure that when the amplitude of the input signal is equal to 0, the power output module can respond to the pulse included in PWM+ and PWM- at the same time, and ensure that the power consumption is low in the standby state.

[0135] In a possible implementation, when PWM+ and PWM- output positive and negative output signals, the amplitude of PWM+ can be amplified to obtain the negative output signal, and the amplitude of PWM- can be amplified to obtain the positive output signal, or the amplitude of PWM+ can be amplified to obtain the positive output signal, and the amplitude of PWM- can be amplified to obtain the negative output signal.

[0136] Amplifying the amplitude of PWM+ and PWM- means amplifying the amplitude of the pulse included in PWM+ and PWM-, without changing the number, rising edge position and falling edge position of the pulse included in PWM+ and PWM-. For example, the voltage corresponding to the pulse included in PWM+ is 5V, and by amplifying the amplitude of PWM+ to 20V, the positive or negative output signal is obtained.

[0137] In the process of outputting the positive output signal and the negative output signal according to the PWM+ and the PWM-, the reverse processing can be performed or not. If the reverse processing is performed, the negative output signal is obtained by amplifying the amplitude of the PWM+, and the positive output signal is obtained by amplifying the amplitude of the PWM-. If the reverse processing is not performed, the positive output signal is obtained by amplifying the amplitude of the PWM+, and the negative output signal is obtained by amplifying the amplitude of the PWM-.

[0138] It should be noted that the reverse processing is required in the process of obtaining the positive output signal and the negative output signal by processing the input signal. The reverse processing can be performed in the process of generating the IN+ and the IN- according to the input signal, or in the process of generating the CMP+ and the CMP- according to the IN+ and the IN-, or in the process of generating the PWM+ and the PWM- according to the CMP+ and the CMP-, or in the process of generating the positive output signal and the negative output signal according to the PWM+ and the PWM-. The foregoing embodiments describe the process of performing the reverse processing in the process of generating the CMP+ and the CMP- according to the IN+ and the IN-. The implementation of performing the reverse processing in the process of generating the IN+ and the IN- according to the input signal, in the process of generating the PWM+ and the PWM- according to the CMP+ and the CMP-, or in the process of generating the positive output signal and the negative output signal according to the PWM+ and the PWM- is similar to the process of performing the reverse processing in the process of generating the CMP+ and the CMP- according to the IN+ and the IN-, and is not described herein again.

[0139] In the embodiments of the present application, in the process of outputting the positive output signal and the negative output signal according to the PWM+ and the PWM-, the positive output signal and the negative output signal are obtained by amplifying the amplitudes of the PWM+ and the PWM-, so that the positive output signal and the negative output signal can drive devices such as a loudspeaker. The reverse processing can be performed or not in the process of outputting the positive output signal and the negative output signal according to the PWM+ and the PWM-, so as to meet the requirements of different application scenarios and improve the applicability of the signal processing method in the embodiments of the present application.

[0140] In a possible implementation, the input signal can be an audio signal, and the positive output signal and the negative output signal can be used to drive a loudspeaker. The loudspeaker is used to play the audio signal after signal processing. In an example, the positive output signal can be input to the positive terminal of the loudspeaker, and the negative output signal can be input to the negative terminal of the loudspeaker.

[0141] In the embodiments of the present application, the audio signal is processed by the signal processing method in the foregoing embodiments, so that the efficiency of audio signal processing is relatively high, and the efficiency is improved without using advanced process for the entire audio system. The efficiency of signal processing is improved on the audio system using ordinary process by optimizing the number of switching and the switching mode.

[0142] signal processing circuit

[0143] FIG. 15 shows a schematic diagram of a signal processing circuit according to an embodiment of the present application. As shown in FIG. 15, the signal processing circuit 150 includes a modulation module 151 and a power output module 152. The modulation module 151 is configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal. The power output module 152 is configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal. In response to an absolute value of an amplitude of the input signal being greater than 0 and less than a first threshold, the positive output signal and the negative output signal each include 2 pulses in a pulse period, and the pulse widths of the pulses included in the positive output signal and the negative output signal are different.

[0144] In the embodiments of the present application, the modulation module 151 performs PWM modulation on the input signal to obtain the PWM positive signal and the PWM negative signal, and the power output module 152 outputs the positive output signal and the negative output signal according to the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold, the positive output signal and the negative output signal each include 2 pulses in a pulse period, and the pulse widths of the pulses included in the positive output signal and the negative output signal are different. When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold, i.e., when the absolute value of the amplitude of the input signal is relatively small, the positive output signal and the negative output signal output by the power output module each include 2 pulses, so that the frequencies of the positive output signal and the negative output signal are relatively high. Therefore, a passive filter supporting a relatively large signal frequency can be used to process the positive output signal and the negative output signal, and the passive filter supporting the relatively large signal frequency has a relatively low cost, so that the cost of the signal processing system can be reduced.

[0145] In a possible implementation, in response to an input signal with an absolute value of any amplitude within the range of (0, the first threshold), one of the positive output signal and the negative output signal output by the power output module 152 includes a pulse with a pulse width equal to a second threshold, and the other of the positive output signal and the negative output signal includes a pulse with a pulse width greater than the second threshold.

[0146] In the embodiment of the present application, the modulation module 151 performs PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal, and the power output module 152 outputs a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal. When the absolute value of the amplitude of the input signal is greater than 0 and less than a first threshold, the positive output signal and the negative output signal each include 2 pulses in one pulse period, and the pulse width of the pulse included in one of the positive output signal and the negative output signal is equal to a second threshold, while the pulse width of the pulse included in the other of the positive output signal and the negative output signal is greater than the second threshold. That is, for any input signal whose absolute value of the amplitude is greater than 0 and less than the first threshold, there is always one of the corresponding positive output signal and the negative output signal that includes a pulse with a pulse width equal to the second threshold, and the other output signal includes a pulse with a pulse width greater than the second threshold, which ensures that the differential mode signal of the positive output signal and the negative output signal includes a pulse, so that the differential mode signal of the positive output signal and the negative output signal matches the amplitude of the input signal, and ensures the stability and correctness of processing the input signal.

[0147] Since the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is positively correlated with the absolute value of the amplitude of the input signal, the pulse width of the differential mode signal of the PWM positive signal and the PWM negative signal is small when the absolute value of the amplitude of the input signal is small. When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold, that is, when the absolute value of the amplitude of the input signal is small, the power output module can also respond to the differential mode signal of the PWM positive signal and the PWM negative signal to output the positive output signal and the negative output signal each including 2 pulses, which can then be fed back to the loop filter unit, ensuring the suppression effect of the loop on noise and system nonlinearity, thereby ensuring the quality of the processed signal.

[0148] In a possible implementation, as shown in FIG. 16, the signal processing circuit 150 includes a loop filter unit 1511, a comparison unit 1512, and a logic processing unit 1513.

[0149] The loop filter unit 1511 is configured to perform filtering processing on the input signal to obtain a first positive signal and a first negative signal.

[0150] The comparison unit 1512 is configured to compare the first positive signal and the first negative signal with a triangular wave signal, and generate a second positive signal and a second negative signal according to the comparison result, wherein the period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals.

[0151] The logic processing unit 1513 is configured to generate a PWM positive signal and a PWM negative signal according to the second positive signal, the second negative signal and the second threshold value.

[0152] The positive output signal and the negative output signal output by the power output module 152 can be fed back to the loop filtering unit 1511, and the loop filtering unit 1511 performs filtering processing on the positive input signal and the negative input signal based on the signal fed back by the power output module 152, so as to realize loop filtering.

[0153] In a possible implementation, as shown in FIG. 17, the signal processing circuit 150 includes a logic processing unit 1513, which includes a differential signal extraction subunit 171, a differential mode pulse width detection subunit 172, a pulse width adjustment subunit 173 and a signal processing subunit 174.

[0154] The differential signal extraction subunit 171 is configured to delay the second positive signal by a preset delay time length after performing logical NOT processing, to obtain a first delay reverse signal, and perform logical OR and NOT processing on the first delay reverse signal and the second negative signal, to obtain a third positive signal, and delay the second negative signal by a preset delay time length after performing logical NOT processing, to obtain a second delay reverse signal, and perform logical OR and NOT processing on the second delay reverse signal and the second positive signal, to obtain a third negative signal.

[0155] The differential mode pulse width detection subunit 172 is configured to detect the pulse width of the pulse included in the third positive signal and the third negative signal.

[0156] The pulse width adjustment subunit 173 is configured to, when the pulse width of the pulse included in the third positive signal is greater than the second threshold value, determine the third positive signal as a fourth positive signal, and when the pulse width of the pulse included in the third positive signal is less than the second threshold value, increase the pulse width timing of the pulse included in the third positive signal backward by the second threshold value, to obtain the fourth positive signal, and when the pulse width of the pulse included in the third negative signal is greater than the second threshold value, determine the third negative signal as a fourth negative signal, and when the pulse width of the pulse included in the third negative signal is less than the second threshold value, increase the pulse width timing of the pulse included in the third negative signal backward by the second threshold value, to obtain the fourth negative signal.

[0157] The signal processing subunit 174 is configured to perform logical OR processing on the fourth positive signal and the fourth negative signal, to obtain a fifth signal, perform logical OR processing on the third positive signal and the fifth signal, to obtain a PWM positive signal, and perform logical OR processing on the third negative signal and the fifth signal, to obtain a PWM negative signal.

[0158] In a possible implementation, the logic processing unit 1513 is configured to perform the following processing:

[0159] performing differential mode pulse width extraction on the second positive direction signal and the second negative direction signal to obtain a first positive direction differential mode signal and a first negative direction differential mode signal;

[0160] performing differential mode pulse width detection on the first positive direction differential mode signal and the first negative direction differential mode signal to obtain a second positive direction differential mode signal and a second negative direction differential mode signal;

[0161] performing common mode pulse width generation according to the second positive direction differential mode signal and the second negative direction differential mode signal to obtain a positive direction common mode signal and a negative direction common mode signal;

[0162] performing PWM signal generation according to the first positive direction differential mode signal, the first negative direction differential mode signal, the positive direction common mode signal, the negative direction common mode signal and a second threshold value to obtain a PWM positive direction signal and a PWM negative direction signal.

[0163] It should be noted that the signal processing circuit in the embodiments of the present application is used to execute the signal processing method in the foregoing embodiments, and is based on the same concept as the foregoing signal processing method embodiments. For specific content and beneficial effects, refer to the description in the foregoing signal processing method embodiments, which will not be repeated here.

[0164] signal processing chip

[0165] An embodiment of the present application provides a signal processing chip, which is used to execute the signal processing method in any of the foregoing embodiments. The signal processing chip can include the signal processing circuit 150 in any of the foregoing embodiments, that is, the signal processing circuit 150 in the foregoing embodiments is packaged in a chip. The signal processing chip can be arranged in an electronic device that has a signal processing requirement such as an audio signal or a power supply signal, and is used for signal processing.

[0166] It should be noted that the signal processing chip in the embodiments of the present application is used to execute the signal processing method in the foregoing embodiments, and is based on the same concept as the foregoing signal processing method embodiments. For specific content and beneficial effects, refer to the description in the foregoing signal processing method embodiments, which will not be repeated here.

[0167] electronic device

[0168] FIG. 18 shows a schematic diagram of an electronic device according to an embodiment of the present application. As shown in FIG. 18, the electronic device 180 includes a signal source 181, a signal receiving end 182 and a signal processing apparatus 183. The signal processing apparatus 183 can include the signal processing circuit 150 or the signal processing chip in any of the foregoing embodiments.

[0169] The signal processing device 183 is connected between the signal source 181 and the signal receiving end 182, the signal source 181 is configured to transmit an input signal to the signal processing device 183, and the signal receiving end 182 is configured to receive forward output signals and negative output signals output by the signal processing device 183.

[0170] The input signal transmitted by the signal source 181 to the signal processing device 183 can be an audio signal. After receiving the forward output signals and the negative output signals, the signal receiving end 182 can perform LC filtering on the forward output signals and the negative output signals and then transmit the filtered signals to a loudspeaker to drive the loudspeaker to produce sound.

[0171] It should be noted that the electronic device in the embodiments of the present application is implemented based on the signal processing circuit 150 or the signal processing chip in the foregoing embodiments. For specific applications of the signal processing circuit 150 and the signal processing chip in the foregoing embodiments, refer to the descriptions in the foregoing signal processing unit embodiments and signal processing chip embodiments for specific contents and beneficial effects, which will not be described here.

[0172] It should be understood that each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the device and system embodiments, the description is relatively simple, and the relevant parts can refer to the part of the description of other embodiments.

[0173] It should be understood that the above describes specific embodiments of the present application. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0174] It should be understood that the elements described herein in the singular or shown in the drawings in the singular do not represent the quantity of the elements limited to one. In addition, the modules or elements described or shown herein as separate can be combined into a single module or element, and the modules or elements described or shown herein as single can be split into multiple modules or elements.

[0175] It is also to be understood that the terminology and phraseology employed herein is for the purpose of description and the specification one or more embodiments of the present application should not be limited to the terms used. The use of such terms and expressions does not therefore admit of any limitation on the scope of the application, it being recognized that the various needs, modifications and equivalents will be apparent to the skilled person and are to be included within the scope of a claim. Other modifications, variations and alternatives are also possible. Accordingly, the claims should be regarded as encompassing all such equivalents.

Claims

1. A signal processing method, characterized by, The method comprises: performing PWM modulation on the input signal to obtain a PWM positive signal and a PWM negative signal; outputting a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein, in response to an absolute value of an amplitude of the input signal being greater than 0 and less than a first threshold value, the positive output signal and the negative output signal each comprise 2 pulses in one pulse period, and the positive output signal and the negative output signal comprise pulses with different pulse widths.

2. The method of claim 1, wherein, in response to the input signal with any amplitude whose absolute value is within the range of (0, the first threshold value), a pulse width of a pulse included in one of the positive output signal and the negative output signal is equal to a preset second threshold value, and a pulse width of a pulse included in the other of the positive output signal and the negative output signal is greater than the second threshold value.

3. The method of claim 2, wherein, When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold value, a falling edge of a pulse included in the positive output signal is time-aligned with a falling edge of a pulse included in the negative output signal.

4. The method of claim 2, wherein, in response to the amplitude of the input signal being equal to 0, the positive output signal and the negative output signal each comprise 1 pulse in one pulse period, a pulse width of a pulse included in the positive output signal and the negative output signal is equal to the second threshold value, and a differential mode pulse width of the positive output signal and the negative output signal is equal to 0.

5. The method of claim 2, wherein, in response to the absolute value of the amplitude of the input signal being greater than the first threshold value, one of the positive output signal and the negative output signal does not comprise a pulse, and the other of the positive output signal and the negative output signal comprises 2 pulses with pulse widths greater than the second threshold value in one pulse period.

6. The method of claim 2, wherein, The method further comprises: performing filtering processing on the input signal to obtain a first positive signal and a first negative signal; comparing the first positive signal and the first negative signal with a triangular wave signal to generate a second positive signal and a second negative signal according to a comparison result, wherein a period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals; generating the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal, and the second threshold value.

7. The method of claim 6, wherein, When the amplitude of the input signal is equal to 0, the PWM positive signal and the PWM negative signal each comprise 1 pulse with a pulse width equal to the second threshold value, and a falling edge of a pulse included in the PWM positive signal and the PWM negative signal is time-aligned with a falling edge of a pulse included in the second positive signal and the second negative signal.

8. The method of claim 6, wherein, When the absolute value of the amplitude of the input signal is greater than 0 and less than the first threshold value, the PWM positive signal and the PWM negative signal each include two pulses, and the falling edges of the two pulses included in the PWM positive signal are time-aligned with the falling edges of the two pulses included in the PWM negative signal; If the pulse included in the second positive signal and the second negative signal is low, the PWM positive signal and the PWM negative signal satisfy: if the first positive signal is greater than the first negative signal, the pulse width of two pulses included in the PWM positive signal is T diff1 +T c and T diff2 +T c respectively, the pulse width of two pulses included in the PWM negative signal is T c , the rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM positive signal is time-aligned with the falling edge of the pulse included in the second negative signal, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second positive signal; if the first positive signal is less than the first negative signal, the pulse width of two pulses included in the PWM negative signal is T diff1 +T c and T diff2 +T c respectively, the pulse width of two pulses included in the PWM positive signal is T c , the rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM negative signal is time-aligned with the falling edge of the pulse included in the second positive signal, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal. If the pulse included in the second positive signal and the second negative signal is high level, the PWM positive signal and the PWM negative signal satisfy: if the first positive signal is greater than the first negative signal, the pulse width of two pulses included in the PWM negative signal is T diff1 +T c respectively, the pulse width of two pulses included in the PWM positive signal is T diff2 +T c respectively, the rising edge of the pulse with the pulse width of T c +T diff1 included in the PWM negative signal is time-aligned with the rising edge of the pulse included in the second negative signal, and the rising edge of the pulse with the pulse width of T c +T diff2 included in the PWM positive signal is time-aligned with the falling edge of the pulse included in the second positive signal; if the first positive signal is less than the first negative signal, the pulse width of two pulses included in the PWM positive signal is T c +T diff1 and T c +T diff2 respectively, the pulse width of two pulses included in the PWM negative signal is T c +T c respectively, the rising edge of the pulse with the pulse width of T diff1 +T c included in the PWM positive signal is time-aligned with the rising edge of the pulse included in the second negative signal, and the rising edge of the pulse with the pulse width of T diff2 +T c included in the PWM negative signal is time-aligned with the falling edge of the pulse included in the second positive signal. wherein said T diff1 and T diff2 for characterizing a pulse width of 2 pulses comprising a differential mode signal of said second positive signal and said second negative signal, said T c for characterizing said second threshold value.

9. The method of claim 6, wherein, When the absolute value of the amplitude of the input signal is greater than the first threshold value, If the pulses included in the second positive signal and the second negative signal are low, the PWM positive signal and the PWM negative signal Satisfy the following condition: If the first positive signal is greater than the first negative signal, the PWM positive signal includes pulse widths T... diff1 and T diff2 The two pulses, the negative PWM signal does not include pulses, and the positive PWM signal includes a pulse width of T. diff1 The rising edge of the pulse is aligned with the falling edge of the pulse included in the second negative signal, and the pulse width of the PWM positive signal is T. diff2 The falling edge of the pulse is aligned with the rising edge of the pulse included in the second negative signal; if the first positive signal is smaller than the first negative signal, the PWM negative signal includes pulses with widths T... diff1 and T diff2 The two pulses, the positive PWM signal does not include pulses, and the negative PWM signal includes a pulse width of T. diff1 The rising edge of the pulse is aligned with the falling edge of the pulse included in the second positive signal, and the pulse width of the PWM negative signal is T. diff2 The falling edge of the pulse is time-aligned with the rising edge of the pulse included in the second positive signal; If the pulses included in the second positive signal and the second negative signal are high, the PWM positive signal and the PWM negative signal satisfy: if the first positive signal is greater than the first negative signal, the PWM negative signal includes a pulse with a pulse width of T diff1 whose rising edge is time-aligned with the rising edge of the pulse included in the second negative signal, the PWM negative signal includes a pulse with a pulse width of T diff1 whose falling edge is time-aligned with the rising edge of the pulse included in the second positive signal, the PWM negative signal includes a pulse with a pulse width of T diff2 whose rising edge is time-aligned with the falling edge of the pulse included in the second positive signal, the PWM negative signal includes a pulse with a pulse width of T diff2 whose falling edge is time-aligned with the falling edge of the pulse included in the second negative signal; if the first positive signal is less than the first negative signal, the PWM positive signal includes two pulses with pulse widths of T diff1 and T diff2 respectively, the PWM negative signal does not include a pulse, and the PWM positive signal includes a pulse with a pulse width of T diff1 whose rising edge is time-aligned with the rising edge of the pulse included in the second positive signal, the PWM positive signal includes a pulse with a pulse width of T diff1 whose falling edge is time-aligned with the rising edge of the pulse included in the second negative signal, the PWM positive signal includes a pulse with a pulse width of T diff2 whose rising edge is time-aligned with the falling edge of the pulse included in the second negative signal, the PWM positive signal includes a pulse with a pulse width of T diff2 whose falling edge is time-aligned with the falling edge of the pulse included in the second positive signal. wherein said T diff1 and T diff2 a pulse width of 2 pulses comprising a differential mode signal of said second positive signal and said second negative signal, said T c for characterizing said second threshold value.

10. The method of claim 6, wherein, The generating of the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and the second threshold value comprises: performing logical NOT processing on the second positive signal after delaying the second positive signal by a preset delay duration to obtain a first delay reverse signal; performing logical OR and NOT processing on the first delay reverse signal and the second negative signal to obtain a third positive signal; if the pulse width of the pulse included in the third positive signal is greater than the second threshold value, determining the third positive signal as a fourth positive signal, and if the pulse width of the pulse included in the third positive signal is less than the second threshold value, increasing the pulse width of the pulse included in the third positive signal by the second threshold value in time sequence to obtain a fourth positive signal; performing logical NOT processing on the second negative signal after delaying the second negative signal by the delay duration to obtain a second delay reverse signal; performing logical OR and NOT processing on the second delay reverse signal and the second positive signal to obtain a third negative signal; if the pulse width of the pulse included in the third negative signal is greater than the second threshold value, determining the third negative signal as a fourth negative signal, and if the pulse width of the pulse included in the third negative signal is less than the second threshold value, increasing the pulse width of the pulse included in the third negative signal by the second threshold value in time sequence to obtain a fourth negative signal; performing logical OR processing on the fourth positive signal and the fourth negative signal to obtain a fifth signal; performing logical OR processing on the third positive signal and the fifth signal to obtain the PWM positive signal; performing logical OR processing on the third negative signal and the fifth signal to obtain the PWM negative signal.

11. The method of claim 6, wherein, The generating of the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and the second threshold value comprises: performing differential-mode pulse width extraction on the second positive signal and the second negative signal to obtain a first positive differential-mode signal and a first negative differential-mode signal; performing differential-mode pulse width detection on the first positive differential-mode signal and the first negative differential-mode signal to obtain a second positive differential-mode signal and a second negative differential-mode signal; performing common-mode pulse width generation according to the second positive differential-mode signal and the second negative differential-mode signal to obtain a positive common-mode signal and a negative common-mode signal; performing PWM signal generation according to the first positive differential-mode signal, the first negative differential-mode signal, the positive common-mode signal, the negative common-mode signal and the second threshold value to obtain the PWM positive signal and the PWM negative signal.

12. The method of any one of claims 2-11, wherein, The second threshold value ranges from T / 40 to T / 10, and T represents a time length of the pulse period.

13. The method of any one of claims 6-11, wherein, The outputting of the positive output signal and the negative output signal according to the PWM positive signal and the PWM negative signal comprises: amplifying the amplitude of the PWM positive signal to obtain the negative output signal, and amplifying the amplitude of the PWM negative signal to obtain the positive output signal; or amplifying the amplitude of the PWM positive signal to obtain the positive output signal, and amplifying the amplitude of the PWM negative signal to obtain the negative output signal.

14. The method of any one of claims 1-11, wherein, The input signal is an audio signal, and the positive output signal and the negative output signal are used to drive a loudspeaker, and the loudspeaker is used to play the audio signal after signal processing.

15. A signal processing circuit, characterized by comprising: comprise: a modulation module, configured to perform PWM modulation on an input signal to obtain a PWM positive signal and a PWM negative signal; a power output module, configured to output a positive output signal and a negative output signal according to the PWM positive signal and the PWM negative signal; wherein in response to an absolute value of the amplitude of the input signal being greater than 0 and less than a first threshold value, the positive output signal and the negative output signal each comprise 2 pulses in one pulse period, and the positive output signal and the negative output signal comprise pulses with different pulse widths.

16. The circuit of claim 15, wherein, in response to an input signal with an absolute value of any amplitude within the range of (0, the first threshold value), one of the positive output signal and the negative output signal comprises pulses with a pulse width equal to a preset second threshold value, and the other of the positive output signal and the negative output signal comprises pulses with a pulse width greater than the second threshold value.

17. The circuit of claim 16, wherein, The modulation module comprises a loop filter unit, a comparison unit and a logic processing unit. The loop filter unit is configured to perform filtering processing on the input signal to obtain a first positive signal and a first negative signal. The comparison unit is configured to compare the first positive signal and the first negative signal with a triangular wave signal to generate a second positive signal and a second negative signal according to a comparison result, wherein a period of the triangular wave is equal to the pulse period, and the second positive signal and the second negative signal are both square wave signals. The logic processing unit is configured to generate the PWM positive signal and the PWM negative signal according to the second positive signal, the second negative signal and the second threshold value.

18. The circuit of claim 17, wherein, The logic processing unit comprises a differential signal extraction subunit, a differential mode pulse width detection subunit, a pulse width adjustment subunit and a signal processing subunit. The differential signal extraction subunit is configured to perform logical NOT processing on the second forward signal, delay the second forward signal by a preset delay time, obtain a first delay reverse signal, perform logical OR processing on the first delay reverse signal and the second reverse signal, obtain a third forward signal, perform logical NOT processing on the second reverse signal, delay the second reverse signal by the delay time, obtain a second delay reverse signal, and perform logical OR processing on the second delay reverse signal and the second forward signal, to obtain a third reverse signal. The differential mode pulse width detection subunit is configured to detect pulse widths of pulses included in the third forward signal and the third reverse signal. The pulse width adjustment subunit is configured to, when the pulse width of the pulse included in the third forward signal is greater than the second threshold value, determine the third forward signal as a fourth forward signal, when the pulse width of the pulse included in the third forward signal is less than the second threshold value, increase the pulse width of the pulse included in the third forward signal by the second threshold value in time sequence, to obtain a fourth forward signal, when the pulse width of the pulse included in the third reverse signal is greater than the second threshold value, determine the third reverse signal as a fourth reverse signal, and when the pulse width of the pulse included in the third reverse signal is less than the second threshold value, increase the pulse width of the pulse included in the third reverse signal by the second threshold value in time sequence, to obtain a fourth reverse signal. The signal processing subunit is configured to perform logical OR processing on the fourth forward signal and the fourth reverse signal, to obtain a fifth signal, perform logical OR processing on the third forward signal and the fifth signal, to obtain the PWM forward signal, and perform logical OR processing on the third reverse signal and the fifth signal, to obtain the PWM reverse signal.

19. The circuit of claim 17, wherein, The logic processing unit is configured to perform the following processing: performing differential mode pulse width extraction on the second forward signal and the second reverse signal, to obtain a first forward differential mode signal and a first reverse differential mode signal; performing differential mode pulse width detection on the first forward differential mode signal and the first reverse differential mode signal, to obtain a second forward differential mode signal and a second reverse differential mode signal; performing common mode pulse width generation according to the second forward differential mode signal and the second reverse differential mode signal, to obtain a forward common mode signal and a reverse common mode signal; performing PWM signal generation according to the first forward differential mode signal, the first reverse differential mode signal, the forward common mode signal, the reverse common mode signal, and the second threshold value, to obtain the PWM forward signal and the PWM reverse signal.

20. A signal processing chip, characterized by The signal processing chip is configured to perform the method in any one of claims 1-14.

21. An electronic device, comprising: The signal processing chip comprises: a signal source, a signal receiving end, and a signal processing device, wherein the signal processing device comprises the signal processing circuit in any one of claims 15-19 or the signal processing chip in claim 20; the signal processing device is connected between the signal source and the signal receiving end; the signal source is configured to transmit an input signal to the signal processing device; the signal receiving end is configured to receive a forward output signal and a reverse output signal output by the signal processing device.

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