Display apparatus and drive method therefor

Abstract

A display apparatus (100) and a drive method therefor. In a pixel circuit (20) of the display apparatus (100), a data writing transistor (T2) first transmits to a gate electrode of a drive transistor (T1) a first reset signal (Vini) generated by a voltage generation unit (102); a compensation transistor (T4) is turned on; the drive transistor (T1) then receives a first voltage signal (Vdd), and the drive transistor (T1) is turned on, such that the potential (Vg) at the gate electrode of the drive transistor (T1) rises or falls until the drive transistor (T1) is turned off; and a measurement unit (101) then acquires the potential (Vg) at the gate electrode of the drive transistor (T1) by means of the data writing transistor (T2), so as to generate a compensation voltage signal (Vb).

Description

Display device and driving method thereof

[0001] This application claims priority to Chinese Patent Application No. 202411362239.3, filed on September 27, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a driving method thereof. BACKGROUND

[0003] In the current self-luminous display product, a large number of transistors need to be set in the pixel circuit to realize threshold voltage compensation and other functions, which is not conducive to the development of high-resolution display products. SUMMARY

[0004] The purpose of the present application is to provide a display device and a driving method thereof to improve the problem that a large number of transistors in the existing pixel circuit is not conducive to the development of high-resolution display products.

[0005] In a first aspect, the present application provides a display device, comprising a plurality of control circuits and a plurality of corresponding pixel circuits, the control circuit comprising a detection unit and a voltage generation unit corresponding to the pixel circuit, the pixel circuit comprising:

[0006] a light emitting element;

[0007] a data writing transistor, one of the source and the drain of the data writing transistor being electrically connected to the corresponding detection unit and the corresponding voltage generation unit;

[0008] a driving transistor, the gate of the driving transistor being electrically connected to the data writing transistor, one of the source and the drain of the driving transistor being electrically connected to one end of the light emitting element;

[0009] a compensation transistor, electrically connected between one of the source and the drain of the driving transistor and the gate of the driving transistor;

[0010] In a first time period, the data writing transistor is used to transmit a first reset signal generated by the voltage generation unit to the gate of the driving transistor, and the compensation transistor is used to transmit the first reset signal to one of the source and the drain of the driving transistor;

[0011] In a second time period after the first time period, the driving transistor is used to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is turned on under the action of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off.

[0012] In a third period after the second period, the detection unit is configured to obtain a potential of a gate of the driving transistor through the data writing transistor, and the control circuit is configured to generate a compensation voltage signal according to the potential of the gate of the driving transistor.

[0013] The pixel circuit further comprises:

[0014] The light emitting control transistor has one of a source and a drain electrically connected to the first voltage line, and the other of the source and the drain electrically connected to the other of the source and the drain of the driving transistor.

[0015] At least in the second period, the light emitting control transistor is configured to transmit the first voltage signal to the other of the source and the drain of the driving transistor.

[0016] The other end of the light emitting element is electrically connected to a second voltage line configured to transmit a second voltage signal.

[0017] In the first period, the second period and the third period, an absolute value of a difference between an amplitude of the first reset signal and an amplitude of the second voltage signal is less than a turn-on voltage of the light emitting element, and an absolute value of a difference between the amplitude of the second voltage signal and an amplitude of the first voltage signal is less than an absolute value of a difference between the turn-on voltage of the light emitting element and the driving transistor.

[0018] In a second aspect, the present application provides a display panel, comprising a plurality of control circuits and a plurality of pixel circuits corresponding to the control circuits, the control circuit comprising a detection unit corresponding to the pixel circuit and a voltage generation unit, and the pixel circuit comprising:

[0019] A light emitting element;

[0020] A data writing transistor, one of a source and a drain of the data writing transistor being electrically connected to the corresponding detection unit and the corresponding voltage generation unit;

[0021] A driving transistor, a gate of the driving transistor being electrically connected to the data writing transistor, and one of a source and a drain of the driving transistor being electrically connected to one end of the light emitting element.

[0022] A compensation transistor, electrically connected between one of the source and the drain of the driving transistor and the gate of the driving transistor.

[0023] In a first period, the data writing transistor is used to transmit a first reset signal generated by the voltage generating unit to the gate of the driving transistor, and the compensation transistor is used to transmit the first reset signal to one of the source and the drain of the driving transistor;

[0024] In a second period after the first period, the driving transistor is used to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is turned on under the actions of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off;

[0025] In a third period after the second period, the detection unit is used to obtain the potential of the gate of the driving transistor through the data writing transistor, and the control circuit is used to generate a compensation voltage signal according to the potential of the gate of the driving transistor.

[0026] In a third aspect, the present application also provides a driving method of a display device, the display device comprising a plurality of control circuits and a plurality of corresponding pixel circuits, the control circuit comprising a detection unit and a voltage generating unit corresponding to the pixel circuit, and the pixel circuit comprising:

[0027] a light emitting element;

[0028] a data writing transistor, one of the source and the drain of the data writing transistor being electrically connected to the corresponding detection unit and the corresponding voltage generating unit;

[0029] a driving transistor, the gate of the driving transistor being electrically connected to the data writing transistor, and one of the source and the drain of the driving transistor being electrically connected to one end of the light emitting element;

[0030] a compensation transistor, electrically connected between one of the source and the drain of the driving transistor and the gate of the driving transistor;

[0031] The driving method of the display device comprises:

[0032] In a first period, the data writing transistor is used to transmit a first reset signal generated by the voltage generating unit to the gate of the driving transistor, and the compensation transistor is used to transmit the first reset signal to one of the source and the drain of the driving transistor;

[0033] In a second period after the first period, another one of the source and the drain of the driving transistor is controlled to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is controlled to be turned on under the actions of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off.

[0034] In a third period after the second period, the detection unit is controlled to obtain the potential of the gate of the driving transistor through the data writing transistor, and the control circuit is controlled to generate a compensation voltage signal according to the potential of the gate of the driving transistor.

[0035] Beneficial effects: The display device and the driving method thereof provided by the present application include a plurality of control circuits and corresponding pixel circuits, the control circuit includes a detection unit and a voltage generation unit corresponding to the pixel circuit, in a first period, another one of the source and the drain of the driving transistor is used to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is turned on under the actions of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off, in a second period, another one of the source and the drain of the driving transistor is used to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is turned on under the actions of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off, only through the data writing transistor, the potential of the gate of the driving transistor is detected and reset in time, and more transistors are avoided to be set for internal compensation, the number of transistors is further saved, and the development of high-resolution display products is also beneficial. BRIEF DESCRIPTION OF DRAWINGS

[0036] The present application will be further described below by means of the accompanying drawings. It should be noted that the accompanying drawings in the following description are only used to explain some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of the drawings.

[0037] FIG. 1 is a circuit diagram of a pixel circuit provided by an embodiment of the present application.

[0038] FIG. 2 and FIG. 3 are timing diagrams corresponding to FIG. 1 provided by an embodiment of the present application.

[0039] FIG. 4 is a circuit diagram of another pixel circuit provided by an embodiment of the present application.

[0040] FIG. 5 and FIG. 6 are timing diagrams corresponding to FIG. 4, according to embodiments of the present application.

[0041] FIG. 7 is a flow chart of a driving method of a display device, according to embodiments of the present application. Embodiments of the present application

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0043] In the description of the present application, it should be understood that the terms "first", "second" and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited, and "electrically connected" means that the two are conductive, without limiting whether they are directly connected or indirectly connected.

[0044] In addition, it should be noted that the drawings provided only structures and steps closely related to the present application, and some details not closely related to the application are omitted, the purpose is to simplify the drawings, make the application points clear at a glance, and not as the actual device is exactly the same as the drawing, not as a limitation of the actual device.

[0045] The present application provides a display panel, which can include but is not limited to the following embodiments and combinations of the following embodiments.

[0046] The present application provides a display device, which can include but is not limited to the following embodiments and combinations of the following embodiments.

[0047] In some embodiments, as shown in FIG. 1 and FIG. 4, the display device 100 includes a plurality of control circuits 10 and a corresponding plurality of pixel circuits 20, the control circuit 10 includes a detection unit 101 and a voltage generation unit 102 corresponding to the pixel circuit 20, the pixel circuit 20 includes: a light emitting element D; a data writing transistor T2, one of the source and drain of the data writing transistor T2 is electrically connected to the corresponding detection unit 101 and the corresponding voltage generation unit 102; a drive transistor T1, the gate of the drive transistor T1 is electrically connected to the data writing transistor T2, one of the source and drain of the drive transistor T1 is electrically connected to one end of the light emitting element D; a compensation transistor T4, electrically connected between one of the source and drain of the drive transistor T1 and the gate of the drive transistor T1; as shown in FIG. 2 and FIG. 5, which are the corresponding timing diagrams of FIG. 1 and FIG. 4, respectively, in a first time period t1, the data writing transistor T2 is used to transmit the first reset signal Vini generated by the voltage generation unit 102 to the gate of the drive transistor T1, and the compensation transistor T4 is used to transmit the first reset signal Vini to one of the source and drain of the drive transistor T1; in a second time period t2 after the first time period t1, the drive transistor T1 is used to receive the first voltage signal Vdd transmitted by the first voltage line, and the drive transistor T1 is turned on under the action of the first reset signal Vini, the first voltage signal Vdd and the turned-on compensation transistor T4, so that the potential Vg of the gate of the drive transistor T1 rises or falls until the drive transistor T1 is turned off; in a third time period t3 after the second time period t2, the detection unit 101 is used to obtain the potential Vg of the gate of the drive transistor T1 through the data writing transistor T2, and the control circuit 10 is used to generate a compensation voltage signal Vb according to the potential Vg of the gate of the drive transistor T1.

[0048] Among them, the display device 100 can include a display panel, a driver and the above-mentioned power manager, the display panel can include a plurality of the above-mentioned pixel circuits 20, the power manager can provide corresponding voltage signals to the plurality of pixel circuits and the driver respectively, the driver can generate control signals and data signals Vdata acting on the pixel circuit 20 according to the corresponding voltage signals, and the plurality of pixel circuits 20 control a plurality of light emitting elements D therein to emit light under the action of the control signals, the data signals and the corresponding voltage signals, thereby presenting a display picture.

[0049] Specifically, the driver can include a gate driver (not shown, which can be integrated in the display panel or arranged independently of the display panel) and a source driver (not shown). Here, taking the display panel including N (N is a positive integer) rows of pixel circuits 20 as an example, the gate driver can generate N first gate signals Scan respectively transmitted to the N rows of pixel circuits 20, and the source driver can generate a plurality of data signals Vdata respectively transmitted to a plurality of columns of pixel circuits 20. Each data signal Vdata can include a plurality of data voltages corresponding to a plurality of pixel circuits 20 in the column. The N gate pulses in the N first gate signals Scan are arranged in time sequence on the time axis, for controlling the N rows of pixel circuits 20 to be opened in turn. Correspondingly, in the period when each row of pixel circuits 20 is opened, the plurality of data signals Vdata output by the source driver are a plurality of data voltages corresponding to a plurality of pixel circuits 20 in the row, so as to enable the plurality of pixel circuits 20 in the row to load the corresponding plurality of data voltages respectively.

[0050] Specifically, the plurality of detection units 101 can be included in the driver, and the plurality of voltage generation units 102 can be included in the power manager and the source driver Source in the driver. It can be considered that the driver can determine at least one compensation voltage signal Vb according to the potentials Vg of the gates of the plurality of drive transistors T1 respectively detected by the plurality of detection units 101. For example, the display panel can be divided into a plurality of regions, and the driver can calculate an average value, a mode or other calculation method to obtain one compensation voltage signal Vb suitable for each region according to the potentials Vg of the gates of the corresponding plurality of drive transistors T1 in each region. For another example, the driver can calculate an average value, a mode or other calculation method to obtain one compensation voltage signal Vb suitable for the display panel according to the potentials Vg of the gates of all the drive transistors T1. Further, the voltage generation unit 102 can generate a subsequent data signal Vdata acting on the pixel circuit 20 according to at least the current compensation voltage signal Vb, that is, the data signal Vdata at this time can be considered to have compensated the pixel circuit 20.

[0051] It can be understood that, in the embodiment, by arranging the detection unit 101 and the voltage generating unit 102 which are electrically connected to one of the source and the drain of the data writing transistor T2, the potential Vg of the gate of the driving transistor T1 can be detected and reset by the data writing transistor T2 in time, so as to avoid arranging two or more transistors to respectively realize the above two functions, save the number of transistors, and be beneficial to the development of high-resolution display products; and the detection unit 101 can obtain the potential Vg of the gate of the driving transistor T1 through the data writing transistor T2, and the control circuit 10 can generate a compensation voltage signal Vb according to the potential Vg of the gate of the driving transistor T1, so as to subsequently externally compensate the pixel circuit 20, and also avoid arranging more transistors to internally compensate, further save the number of transistors, and be beneficial to the development of high-resolution display products.

[0052] Further, in the first time period t1 in the detection stage of the potential Vg of the gate of the driving transistor T1, since the compensation transistor T4 is also arranged to be turned on (the second gate signal En loaded on the gate thereof controls the on-off state thereof), the first reset signal Vini generated by the voltage generating unit 102 can be transmitted to the gate of the driving transistor T1 to reset the same, and the first reset signal Vini can also be transmitted to one of the source and the drain of the driving transistor T1 through the compensation transistor T4 to reset the same, that is, an additional transistor can be avoided to reset one of the source and the drain of the driving transistor T1; meanwhile, in the second time period t2 in the detection stage of the potential Vg of the gate of the driving transistor T1, the other one of the source and the drain of the driving transistor T1 is used to receive the first voltage signal Vdd to make the driving transistor T1 turned on, and the compensation transistor T4 is still arranged to be turned on at this time, at this time, the potential Vg of the gate of the driving transistor T1 rises or falls until it is cut off, and considering that the compensation transistor T4 has been arranged to be turned on in the first time period t1 before the second time period t2, the starting point of the potential Vg of the gate of the driving transistor T1 in the second time period t2 is higher, which can accelerate the time when the driving transistor T1 reaches the cut-off state, so as to shorten the time length of the whole detection stage of the potential Vg of the gate of the driving transistor T1, and improve the detection efficiency of the display device 100.

[0053] In some embodiments, as shown in FIG. 1 and FIG. 4, the pixel circuit 20 further comprises a light emitting control transistor T3, one of the source and drain of the light emitting control transistor T3 is electrically connected to the first voltage line (for transmitting the first voltage signal Vdd), and the other of the source and drain of the light emitting control transistor T3 is electrically connected to the other of the source and drain of the driving transistor T1; as shown in FIG. 2 and FIG. 5, at least in the second time period t2, the light emitting control transistor T3 is used to transmit the first voltage signal Vdd to the other of the source and drain of the driving transistor T1.

[0054] As discussed above, in the second time period t2, the other of the source and drain of the driving transistor T1 needs to receive the first voltage signal Vdd transmitted by the first voltage line to control the driving transistor T1 to be turned on, therefore, as described in the embodiment, the light emitting control transistor T3 is arranged between the first voltage line and the other of the source and drain of the driving transistor T1, and the on-off state of the light emitting control transistor T3 is controlled by the third gate signal Em loaded to the gate of the light emitting control transistor T3, so as to control whether a current path is formed between the first voltage line and the other of the source and drain of the driving transistor T1, thereby controlling whether the potential Vs of the other of the source and drain of the driving transistor T1 is equal to the first voltage signal Vdd or the other of the source and drain of the driving transistor T1 is in a floating state (the potential Vs of the other of the source and drain of the driving transistor T1 is unstable).

[0055] Further, as shown in FIG. 1, FIG. 2, FIG. 4 and FIG. 5, in the first time period t1 and the third time period t3, the light emitting control transistor T3 is used to transmit the first voltage signal Vdd to the other of the source and drain of the driving transistor T1. It can be understood that the light emitting control transistor T3 is turned on in the first time period t1 before the second time period t2, so that the starting point of the potential Vs of the other of the source and drain of the driving transistor T1 in the second time period t2 is higher, which can accelerate the speed of the driving transistor T1 from being turned off to being turned on, and the light emitting control transistor T3 is turned on in the third time period t3 after the second time period t2, which can maintain the state of the driving transistor T1 being turned off in the second time period t2, so as to avoid the change of the potential of the other of the source and drain of the driving transistor T1 due to the floating of the potential Vs of the other of the source and drain of the driving transistor T1, thereby affecting the potential Vg of the gate of the driving transistor T1 obtained by the detection unit 101.

[0056] In some embodiments, as shown in FIG. 1, FIG. 2, FIG. 4 and FIG. 5, the other end of the light emitting element D is electrically connected to a second voltage line for transmitting a second voltage signal VSS; during the first time period t1, the second time period t2 and the third time period t3, the absolute value of the difference between the amplitude of the first reset signal Vini and the amplitude of the second voltage signal VSS is less than the turn-on voltage of the light emitting element D, and the absolute value of the difference between the amplitude of the second voltage signal VSS and the amplitude of the first voltage signal Vdd is less than the absolute value of the difference between the turn-on voltage of the light emitting element D and the driving transistor T1.

[0057] It should be noted that, since one of the source and the drain of the driving transistor T1 is electrically connected to one end of the light emitting element D, and as discussed above, during the first time period t1, one of the source and the drain of the driving transistor T1 is reset by the first reset signal Vini, in order to avoid the light emitting element D emitting light, the absolute value of the difference between the amplitude of the first reset signal Vini and the amplitude of the second voltage signal VSS should be less than the turn-on voltage of the light emitting element D; during the second time period t2, the potential Vg of the gate of the driving transistor T1 rises or falls until the driving transistor T1 is turned off, at which time Vd=Vg=Vdd+Vth, where Vth is the threshold voltage of the driving transistor T1, at this time, in order to avoid the light emitting element D emitting light, Vdd+Vth-VSS should be less than the turn-on voltage of the light emitting element D, that is, the absolute value of the difference between the amplitude of the second voltage signal VSS and the amplitude of the first voltage signal Vdd should be less than the absolute value of the difference between the turn-on voltage of the light emitting element D and the driving transistor T1.

[0058] In some embodiments, as shown in FIG. 1 and FIG. 2, the pixel circuit 20 further comprises a capacitor C electrically connected between the gate of the driving transistor T1 and the first voltage line, and the first voltage signal Vdd transmitted by the first voltage line is a constant voltage signal. It can be understood that, in the present embodiment, one end of the capacitor C is connected to the first voltage line with a constant potential, and when the gate of the driving transistor T1 electrically connected to the other end of the capacitor C is in a floating state, the stable potential can be maintained by the voltage stabilizing property of the capacitor C, for example, after the potential Vg of the gate of the driving transistor T1 rises or falls until the driving transistor T1 is turned off, as discussed above, the potential Vg of the gate of the driving transistor T1 (that is, Vdd+Vth) can be maintained unchanged, so that the detection unit 101 detects the potential thereof, thereby generating a compensation voltage signal Vb, which can be considered as Vb=Vth=Vg-Vdd.

[0059] In some embodiments, as shown in FIGS. 1-3, in a fourth period t4 after the third period t3, the data write transistor T2 is configured to transmit the first reset signal Vini generated by the voltage generation unit 102 to the gate of the driving transistor T1, the compensation transistor T4 is configured to transmit the first reset signal Vini to one of the source and the drain of the driving transistor T1, and the light emitting control transistor T3 is configured to control the formation of a current break between the first voltage line (for transmitting the first voltage signal Vdd) and the other of the source and the drain of the driving transistor T1.

[0060] It should be noted that the first period t1 to the third period t3 above all belong to the "detection stage of the potential Vg of the gate of the driving transistor T1", and after each detection, the "light emitting stage of the pixel circuit 20" can be performed. The fourth period t4 here can be understood as the first stage of the "light emitting stage of the pixel circuit 20", i.e., in the "light emitting stage of the pixel circuit 20", the data write transistor T2 and the compensation transistor T4 still need to be turned on to reset the potential Vg of the gate of the driving transistor T1 and the potential Vg of one of the source and the drain of the driving transistor T1 through the first reset signal Vini. At the same time, in order to avoid the light emitting element D from emitting light, and at this time, the driving transistor T1 does not need to be turned on, so unlike the first period t1, the light emitting control transistor T3 can be controlled to be turned off in the fourth period t4 to avoid the formation of a path between the first voltage line and the other of the source and the drain of the driving transistor T1, and thus avoid the formation of a path between the first voltage line and the other end of the light emitting element D.

[0061] In some embodiments, as shown in FIGS. 1-3, in a fifth period t5 after the fourth period t4, the data write transistor T2 is configured to transmit a target data signal Data generated by the voltage generation unit 102 to the gate of the driving transistor T1, the compensation transistor T4 is configured to control the formation of a current break between one of the source and the drain of the driving transistor T1 and the gate of the driving transistor T1, and the light emitting control transistor T3 is configured to control the formation of a current break between the first voltage line and the other of the source and the drain of the driving transistor T1; wherein the control circuit 10 is configured to generate the target data signal Data according to the compensation voltage signal Vb and a data signal Vdata, and the data signal Vdata is configured to be determined according to a corresponding gray scale value.

[0062] It can be known from the above description that the compensation voltage signal Vb can be generated in the detection stage of the potential Vg of the gate of the driving transistor T1, and each pixel circuit has a corresponding gray scale value in each frame, and each gray scale value also has a corresponding data voltage, so that the data signal Vdata can be determined, and the target data signal Data containing compensation information can be obtained by superimposing the compensation voltage signal Vb on the data signal Vdata.

[0063] After the potential Vg of the gate of the driving transistor T1 and the potential Vg of one of the source and the drain of the driving transistor T1 are reset, the target data signal Data generated by the control circuit 10 can be transmitted to the gate of the driving transistor T1 through the data writing transistor T2 in the fourth period t4. At this time, since the compensation transistor T4 and the light emitting control transistor T3 are both cut off, the source and the drain of the driving transistor T1 are both in a suspended state, and the driving transistor T1 is not turned on temporarily.

[0064] In some embodiments, in combination with FIGS. 1 to 3, in a sixth period t6 after the fifth period t5, the light emitting control transistor T3 is used to control the formation of a current path between the first voltage line and the other one of the source and the drain of the driving transistor T1, and the driving transistor T1 is used to generate a driving current according to the target data signal Data to drive the light emitting element D to emit light.

[0065] It can be known from the above description that Vb=Vth, and Data=Vdata+Vb. In the sixth period t6, since the first voltage signal Vdd is transmitted to the other one of the source and the drain of the driving transistor T1, and the potential Vg of the driving transistor T1 is maintained as Data, the gate-source voltage difference of the driving transistor T1 can be considered as Vgs=Vdata+Vb-Vdd. According to the formula for generating a driving current by a transistor, the driving current I=K(Vgs-Vth)2=K(Vdata+Vb-Vdd-Vth) 2 =K(Vdata+Vb-Vdd-Vth) 2= K(Vdata-Vdd) 2 .

[0066] It can be understood that the compensation voltage signal Vb determined by the detection stage of the potential Vg of the gate of the driving transistor T1 acts on the pixel circuit 20 in the subsequent light emitting stage of the pixel circuit 20, and can offset the influence of the threshold voltage of the current driving transistor T1 on the brightness of the light emitting element D.

[0067] In some embodiments, as shown in FIGS. 4-6, based on the architecture of the circuit shown in FIG. 1, the pixel circuit 20 further comprises: a first reset transistor T6, one of the source and drain of the first reset transistor T6 is electrically connected to one end of the light emitting element D and one of the source and drain of the driving transistor T1, and the other of the source and drain of the first reset transistor T6 is electrically connected to a reset line for transmitting a second reset signal Vini_2; in the fourth time period t4 after the third time period t3, the data write transistor T2 is used to transmit the first reset signal Vini generated by the voltage generation unit 102 to the gate of the driving transistor T1, the compensation transistor T4 is used to electrically disconnect one of the source and drain of the driving transistor T1 and the gate of the driving transistor T1, and the first reset transistor T6 is used to transmit the second reset signal Vini_2 to one of the source and drain of the driving transistor T1; in the fifth time period t5 after the fourth time period t4, the data write transistor T2 is used to transmit the target data signal Data generated by the voltage generation unit 102 to the gate of the driving transistor T1, the compensation transistor T4 is used to control the formation of a current break between one of the source and drain of the driving transistor T1 and the gate of the driving transistor T1, the light emitting control transistor T3 is used to control the formation of a current break between the first voltage line and the other of the source and drain of the driving transistor T1, and the first reset transistor T6 is used to transmit the second reset signal Vini_2 to one of the source and drain of the driving transistor T1; wherein the control circuit 10 is used to generate the target data signal Data according to the compensation voltage signal Vb and the data signal Vdata, and the data signal Vdata is used to be determined according to the corresponding gray scale value.

[0068] In particular, the difference between the circuit of FIG. 4 in the present embodiment and the circuit of FIG. 1 above is that the first reset transistor T6 electrically connected to one end of the light emitting element D is further provided, and in terms of timing, as shown in FIG. 5, in the “detection stage of the potential Vg of the gate of the driving transistor T1”, the fourth gate signal Sini loaded on the gate of the first reset transistor T6 controls the first reset transistor T6 to be cut off, and the waveforms of other signals loaded in the pixel circuit 20 are the same as the waveforms of signals loaded in the circuit of FIG. 1, that is, the “detection stage of the potential Vg of the gate of the driving transistor T1” of FIGS. 2 and 1 is the same.

[0069] As shown in FIG. 6, in the fourth period t4 (i.e., the first stage of the "light-emitting stage of the pixel circuit 20"), the potential Vg of the gate of the driving transistor T1 is still reset by the first reset signal Vini via the current path formed by the data writing transistor T2, but at this time, the compensation transistor T4 is used to electrically disconnect one of the source and drain of the driving transistor T1 and the gate of the driving transistor T1, i.e., the potential Vd of one of the source and drain of the driving transistor T1 is no longer equal to Vg, but is transmitted to one of the source and drain of the driving transistor T1 by the first reset transistor T6 to reset the potential Vg of one of the source and drain of the driving transistor T1.

[0070] As can be understood, in the present embodiment, since the potential Vd of one of the source and drain of the driving transistor T1 is reset by the first reset transistor T6, in the fifth period t5, unlike the circuit shown in FIG. 1 in which the data writing transistor T2 is used to reset Vd, even if the data writing transistor T2 has been used to transmit the target data signal Data to the gate of the driving transistor T1, at this time, the first reset transistor T6 can still be used to transmit the second reset signal Vini_2 to one of the source and drain of the driving transistor T1 to continue to reset the potential Vg of one of the source and drain of the driving transistor T1, and the reset time can be prolonged to sufficiently reset the potential Vg of one of the source and drain of the driving transistor T1 to avoid the potential Vg of one of the source and drain of the driving transistor T1 being suspended, so as to affect the brightness of the light-emitting element D in the later light-emitting stage.

[0071] In some embodiments, in combination with FIGS. 4 to 6, on the basis of the architecture of the circuit shown in FIG. 1, the pixel circuit 20 further comprises: a second reset transistor T5, one of the source and drain of the second reset transistor T5 is electrically connected to the other one of the source and drain of the driving transistor T1 and the other one of the source and drain of the light-emitting control transistor T3, and the other one of the source and drain of the second reset transistor T5 is electrically connected to the reset line (for transmitting the second reset signal Vini_2); in the fourth period t4 and the fifth period t5, the second reset transistor T5 is used to transmit the second reset signal Vini_2 to the other one of the source and drain of the driving transistor T1.

[0072] As can be understood, the difference between the circuit of FIG. 4 in the present embodiment and the circuit of FIG. 1 above is at least that the second reset transistor T5 electrically connected to the other one of the source and drain of the driving transistor T1 is additionally provided, and in terms of timing, as shown in FIG. 5, in the "detection stage of the potential Vg of the gate of the driving transistor T1", the second reset transistor T5 is also cut off, i.e., the "detection stage of the potential Vg of the gate of the driving transistor T1" of FIG. 2 and FIG. 1 is the same.

[0073] Different from the above, as shown in FIG. 6, in the fourth period t4 (i.e. the first stage of the "light emitting stage of the pixel circuit 20"), due to the second reset transistor T5, the second reset signal Vini_2 can be transmitted to the other of the source and the drain of the driving transistor T1 by turning on the second reset transistor T5 to reset the potential Vs of the other of the source and the drain of the driving transistor T1. Similarly, in the fifth period t5 after the fourth period t4, the second reset transistor T5 is still controlled to be turned on to continue to reset the potential Vs of the other of the source and the drain of the driving transistor T1, so as to avoid the potential Vs of the other of the source and the drain of the driving transistor T1 being unstable due to being suspended in the fourth period t4 and the fifth period t5.

[0074] When the pixel circuit 20 simultaneously includes the first reset transistor T6 and the second reset transistor T5, the other of the source and the drain of the two can be electrically connected to the reset line to receive the second reset signal Vini_2, and the two can also be electrically connected to the same gate line to receive the fourth gate signal Sini, so as to reduce the number of signal lines and signal types.

[0075] Similarly, in combination with FIGS. 4 to 6, on the basis of at least one of the first reset transistor T6 and the second reset transistor T5 being provided, in the sixth period t6 after the fifth period t5, the light emitting control transistor T3 is used to control the current path formed between the first voltage line and the other of the source and the drain of the driving transistor T1, and the driving transistor T1 is used to generate a driving current according to the target data signal to drive the light emitting element D to emit light. The specific content can be referred to the related description of the circuit shown in FIG. 1 above.

[0076] It should be noted that the voltage generating unit 102 involved in the above can include a first switching element S1, and the detection unit 101 can include a second switching element S2. The first switching element S1 and the second switching element S2 are composed of transistors. The first switching element S1 can control whether the voltage generating unit 102 outputs the first reset signal Vini or the target data signal Data to the data writing transistor T2, and the second switching element S2 can control whether the detection unit 101 can obtain the potential Vg of the gate of the driving transistor T1 through the data writing transistor T2. The detection unit 101 can be, but is not limited to, an analog-to-digital converter.

[0077] In order to better illustrate the working principle of the circuit diagrams shown in FIGS. 1 and 2, in this application, the driving transistor T1 is taken as a P-type transistor, and the other transistors are taken as N-type transistors as an example, and the working stages of the two are described as follows.

[0078] As shown in FIG. 2, the "detection stage of the potential Vg of the gate of the driving transistor T1" in the circuit diagram shown in FIG. 1 can include the following time periods:

[0079] The first time period t1, the first gate signal Scan, the second gate signal En and the third gate signal Em are all high potentials, so the data writing transistor T2, the compensation transistor T4 and the light emitting control transistor T3 are all turned on, the first switch element S1 is turned on, the second switch element S2 is turned off, and the voltage generating unit 102 generates the first reset signal Vini, so the first reset signal Vini is transmitted to one of the source and the drain of the gate of the driving transistor T1, the first voltage signal Vdd is transmitted to the other one of the source and the drain of the gate of the driving transistor T1, Vg = Vd = Vini, Vs = Vdd, and at this time the second voltage signal VSS is a corresponding high potential, and Vini-VSS < Voled needs to be met to ensure that the light emitting element D does not emit light, and Voled is the turn-on voltage of the light emitting element D;

[0080] The second time period t2, the first gate signal Scan, the second gate signal En and the third gate signal Em are all maintained as high potentials, and the first switch element S1 and the second switch element S2 are both turned off, since Vg = Vd = Vini and Vs = Vdd, the driving transistor T1 is turned on, the first voltage signal Vdd is transmitted to one of the source and the drain of the gate of the driving transistor T1 and the gate, Vg is raised until Vg = Vd = Vdd + Vth when the driving transistor T1 is turned off, Vth is the threshold voltage of the driving transistor T1, and at this time the second voltage signal VSS is still a corresponding high potential, and Vdd + Vth-VSS < Voled needs to be met to ensure that the light emitting element D does not emit light;

[0081] The third time period t3, the first gate signal Scan, the second gate signal En and the third gate signal Em are all maintained as high potentials, the first switch element S1 is turned off, the second switch element S2 is turned on, and the detection unit 101 detects Vg, according to Vg = Vdd + Vth when the driving transistor T1 is turned off, since the first voltage signal Vdd is known, the threshold voltage Vth of the driving transistor T1 can be calculated.

[0082] As shown in FIG. 3, the "detection stage of the potential Vg of the gate of the driving transistor T1" in the circuit diagram shown in FIG. 1 can include the following time periods:

[0083] In the fourth time period t4, the first gate signal Scan and the second gate signal En are high, the third gate signal Em is low, the data writing transistor T2 and the compensation transistor T4 are turned on, the first switch element S1 is turned on and the second switch element S2 is turned off (the signal timing diagram is not shown), the first reset signal Vini generated by the voltage generating unit 102 is transmitted to the gate and one of the source and the drain of the driving transistor T1, Vg=Vd=Vini, and Vg and Vd are reset;

[0084] In the fifth time period t5, the first gate signal Scan is high, the second gate signal En and the third gate signal Em are low, the data writing transistor T2 is turned on, the first switch element S1 is turned on and the second switch element S2 is turned off (the signal timing diagram is not shown), the first switch element S1 is turned on and the second switch element S2 is turned off (the signal diagram is not shown), the target data signal Data (equal to Vdata+Vth) generated by the voltage generating unit 102 is transmitted to the gate of the driving transistor T1, Vg=Vdata+Vth, the light emitting control transistor T3 and the compensation transistor T4 are turned off to avoid affecting Vd and Vg;

[0085] In the sixth time period t6, the first gate signal Scan and the second gate signal En are low, the third gate signal Em is high, the first switch element S1 and the second switch element S2 are both turned off, the light emitting control transistor T3 is turned on to form a driving current I=K(Vgs-Vth)2=K(Vdata+Vb-Vdd-Vth) 2 =K(Vdata+Vb-Vdd-Vth) 2= K(Vdata-Vdd) 2 , and the light emitting element D emits light, and at this time, the brightness is not affected by the threshold voltage Vth.

[0086] Wherein, by adjusting the proportion of the high potential of the third gate signal Em, the proportion of the light emitting time of the light emitting element D in a frame can be adjusted.

[0087] As shown in FIG. 5, the “detection stage of the potential Vg of the gate of the driving transistor T1” in the circuit diagram shown in FIG. 4 can also include the first time period t1 to the third time period t3, although the first reset transistor T6 and the second reset transistor T5 are newly added compared with the circuit diagram shown in FIG. 1, but in the first time period t1 to the third time period t3 in the whole FIG. 5, the fourth gate signal Sini is corresponding low potential VGL, so that the first reset transistor T6 and the second reset transistor T5 are both turned off, so the working condition of the circuit diagram shown in FIG. 4 in the first time period t1 to the third time period t3 is the same as that of the circuit diagram shown in FIG. 1 in the first time period t1 to the third time period t3.

[0088] As shown in FIG. 6, the "potential Vg detection stage of the gate of the driving transistor T1" in the circuit diagram shown in FIG. 4 can include the following time periods:

[0089] The fourth time period t4, the first gate signal Scan and the fourth gate signal Sini are high potentials, the second gate signal En and the third gate signal Em are low potentials, the data writing transistor T2, the first reset transistor T6 and the second reset transistor T5 are all turned on, the first switch element S1 is turned on and the second switch element S2 is turned off (the signal timing diagram is not shown), and the difference from the fourth time period t4 of the circuit diagram shown in FIG. 1 is that, at this time, the Vs and Vd are reset by the second reset signal Vini_2 transmitted to the source and the drain of the driving transistor T1, instead of resetting the Vd by the first reset signal Vini, and the amplitude of the first reset signal Vini, the amplitude of the second reset signal Vini_2 and the amplitude of the second voltage signal VSS during this period need to be reasonably set to avoid the light-emitting element D from emitting light;

[0090] The fifth time period t5, the difference from the fourth time period t4 is that the voltage generating unit 102 generates the target data signal Data (equal to Vdata+Vth) transmitted to the gate of the driving transistor T1, and at this time, the Vs and Vd are still reset by the second reset signal Vini_2 transmitted to the source and the drain of the driving transistor T1, so that the Vs and Vd of all the pixel circuits 20 are reset to the same voltage value, and the residual image caused by the different gate-source voltages Vgs of the driving transistors T1 of all the pixel circuits 20 is eliminated.

[0091] The sixth time period t6, the first gate signal Scan, the second gate signal En and the fourth gate signal Sini are all low potentials, the third gate signal Em is a high potential, and the first switch element S1 and the second switch element S2 are both turned off, and this process can refer to the sixth time period t6 of the circuit diagram shown in FIG. 1.

[0092] Similarly, by adjusting the proportion of the high potential of the third gate signal Em, the proportion of the light-emitting time of the light-emitting element D in a frame can be adjusted. At the same time, the second gate signal En is at the corresponding low potential VGL during the fourth time period t4 to the sixth time period t6, that is, the compensation transistor T4 does not need to play a role.

[0093] The embodiment of the present application also provides a driving method of a display device, which is applied to a display device including the control circuit and the pixel circuit as described in any of the above embodiments; as shown in FIG. 7, the driving method of the display device includes but is not limited to the following steps.

[0094] S1, in a first time period, controlling the data write transistor to transmit a first reset signal generated by the voltage generation unit to the gate of the driving transistor, and controlling the compensation transistor to transmit the first reset signal to one of the source and the drain of the driving transistor.

[0095] As can be known from the above description, no matter for the circuit diagram as shown in FIG. 1 or FIG. 4, at this time, the first switch element S1 is turned on, the data write transistor T2 and the compensation transistor T4 are turned on, and the first reset signal Vini generated by the voltage generation unit 102 is transmitted to the gate of the driving transistor T1 and one of the source and the drain of the driving transistor T1. For specific details, reference can be made to the related description of the first time period t1 above.

[0096] S2, in a second time period after the first time period, controlling the other of the source and the drain of the driving transistor to receive a first voltage signal transmitted by a first voltage line, and controlling the driving transistor to be turned on under the actions of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off.

[0097] As can be known from the above description, no matter for the circuit diagram as shown in FIG. 1 or FIG. 4, at this time, the first switch element S1 and the second switch element S2 are both turned off, the driving transistor T1 is turned on, the first voltage signal Vdd is transmitted to one of the source and the drain and the gate of the driving transistor T1, Vg rises or falls until Vg = Vd = Vdd + Vth, and the driving transistor T1 is turned off. For specific details, reference can be made to the related description of the second time period t2 above.

[0098] S3, in a third time period after the second time period, controlling the detection unit to acquire the potential of the gate of the driving transistor through the data write transistor, and controlling the control circuit to generate a compensation voltage signal according to the potential of the gate of the driving transistor.

[0099] As can be known from the above description, no matter for the circuit diagram as shown in FIG. 1 or FIG. 4, the first switch element S1 is turned off, the second switch element S2 is turned on, the detection unit 101 detects Vg, according to Vg = Vdd + Vth when the driving transistor T1 is turned off, and since the first voltage signal Vdd is known, the threshold voltage Vth of the driving transistor T1 can be calculated. For specific details, reference can be made to the related description of the third time period t3 above.

[0100] The structure of the display device and the driving method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced equivalently, and these modifications or replacements do not cause the nature of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0101] It should be noted that the control circuit 10, the pixel circuit 20 and the like mentioned in the present application can be essentially composed of at least one transistor device, and can also include at least one of a capacitor and a resistor, and a wire electrically connected between different devices. The specific composition can be referred to the above description.

[0102] The display panel and the driving method thereof provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core ideas thereof. It should be understood by those skilled in the art that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features thereof can be replaced equivalently, and these modifications or replacements do not cause the nature of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, wherein, The pixel circuit comprises a light emitting element, a data write transistor, a driving transistor, and a compensation transistor. The data write transistor has one of its source and drain electrically connected to the detection unit and the voltage generation unit. The driving transistor has its gate electrically connected to the data write transistor, and one of its source and drain electrically connected to one end of the light emitting element. The compensation transistor is electrically connected between one of the source and drain of the driving transistor and the gate of the driving transistor. In a first time period, the data write transistor is used to transmit a first reset signal generated by the voltage generation unit to the gate of the driving transistor, and the compensation transistor is used to transmit the first reset signal to one of the source and drain of the driving transistor. In a second time period after the first time period, the driving transistor is used to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is turned on under the actions of the first reset signal, the first voltage signal, and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off. In a third time period after the second time period, the detection unit is used to obtain the potential of the gate of the driving transistor through the data write transistor, and the control circuit is used to generate a compensation voltage signal according to the potential of the gate of the driving transistor. The pixel circuit further comprises a light emitting control transistor. The light emitting control transistor has one of its source and drain electrically connected to the first voltage line, and the other of its source and drain electrically connected to the other of the source and drain of the driving transistor. In at least the second time period, the light emitting control transistor is used to transmit the first voltage signal to the other of the source and drain of the driving transistor. The other end of the light emitting element is electrically connected to a second voltage line for transmitting a second voltage signal. In the first time period, the second time period, and the third time period, the absolute value of the difference between the amplitude of the first reset signal and the amplitude of the second voltage signal is less than the turn-on voltage of the light emitting element, and the absolute value of the difference between the amplitude of the second voltage signal and the amplitude of the first voltage signal is less than the absolute value of the difference between the turn-on voltage of the light emitting element and the driving transistor. In the first time period and the third time period, the light emitting control transistor is used to transmit the first voltage signal to the other of the source and drain of the driving transistor.

2. The display device of claim 1, wherein, ​ 3. The display device according to claim 1 or 2, wherein In a fourth period after the third period, the data write transistor is configured to transmit the first reset signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to transmit the first reset signal to one of the source and the drain of the driving transistor, and the light emitting control transistor is configured to control the first voltage line to form a current break with the other one of the source and the drain of the driving transistor.

4. The display device of claim 3, wherein, In a fifth period after the fourth period, the data write transistor is configured to transmit a target data signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to control one of the source and the drain of the driving transistor to form a current break with the gate of the driving transistor, and the light emitting control transistor is configured to control the first voltage line to form a current break with the other one of the source and the drain of the driving transistor. The control circuit is configured to generate the target data signal according to the compensation voltage signal and a data signal, and the data signal is generated according to a corresponding gray scale value.

5. The display device of claim 4, wherein, In a sixth period after the fifth period, the light emitting control transistor is configured to control the first voltage line to form a current path with the other one of the source and the drain of the driving transistor, and the driving transistor is configured to generate a driving current according to the target data signal to drive the light emitting element to emit light.

6. The display device according to claim 1 or 2, wherein The pixel circuit further comprises: a first reset transistor, one of the source and the drain of the first reset transistor is electrically connected to one end of the light emitting element and one of the source and the drain of the driving transistor, and the other one of the source and the drain of the first reset transistor is electrically connected to a reset line for transmitting a second reset signal; In a fourth period after the third period, the data write transistor is configured to transmit the first reset signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to electrically disconnect one of the source and the drain of the driving transistor from the gate of the driving transistor, and the first reset transistor is configured to transmit the second reset signal to one of the source and the drain of the driving transistor. In a fifth period after the fourth period, the data write transistor is configured to transmit a target data signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to control one of the source and the drain of the driving transistor to form a current break with the gate of the driving transistor, the light emitting control transistor is configured to control the first voltage line to form a current break with the other one of the source and the drain of the driving transistor, and the first reset transistor is configured to transmit the second reset signal to one of the source and the drain of the driving transistor. The control circuit is configured to generate the target data signal according to the compensation voltage signal and a data signal, and the data signal is generated according to a corresponding gray scale value.

7. The display device of claim 6, wherein, The pixel circuit further comprises: a second reset transistor, one of a source and a drain of the second reset transistor being electrically connected to the other one of the source and the drain of the driving transistor and the other one of the source and the drain of the light emitting control transistor, the other one of the source and the drain of the second reset transistor being electrically connected to the reset line; in the fourth period and the fifth period, the second reset transistor is configured to transmit the second reset signal to the other one of the source and the drain of the driving transistor.

8. The display device of claim 7, wherein, in a sixth period after the fifth period, the light emitting control transistor is configured to control a current path between the first voltage line and the other one of the source and the drain of the driving transistor, and the driving transistor is configured to generate a driving current according to the target data signal to drive the light emitting element to emit light.

9. A display device, wherein, a plurality of control circuits and a plurality of pixel circuits corresponding to the control circuits, the control circuit comprising a detection unit and a voltage generation unit corresponding to the pixel circuit, the pixel circuit comprising: a light emitting element; a data write transistor, one of a source and a drain of the data write transistor being electrically connected to the detection unit and the voltage generation unit corresponding to the pixel circuit; a driving transistor, a gate of the driving transistor being electrically connected to the data write transistor, one of a source and a drain of the driving transistor being electrically connected to one end of the light emitting element; a compensation transistor, being electrically connected between the other one of the source and the drain of the driving transistor and the gate of the driving transistor; in a first period, the data write transistor is configured to transmit a first reset signal generated by the voltage generation unit to the gate of the driving transistor, and the compensation transistor is configured to transmit the first reset signal to one of the source and the drain of the driving transistor; in a second period after the first period, the driving transistor is configured to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is turned on under the action of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off; in a third period after the second period, the detection unit is configured to obtain the potential of the gate of the driving transistor through the data write transistor, and the control circuit is configured to generate a compensation voltage signal according to the potential of the gate of the driving transistor.

10. The display device of claim 9, wherein, the pixel circuit further comprises: a light emitting control transistor, one of a source and a drain of the light emitting control transistor being electrically connected to the first voltage line, the other one of the source and the drain of the light emitting control transistor being electrically connected to the other one of the source and the drain of the driving transistor; in at least the second period, the light emitting control transistor is configured to transmit the first voltage signal to the other one of the source and the drain of the driving transistor.

11. The display device of claim 10, wherein, in the first period and the third period, the light emitting control transistor is configured to transmit the first voltage signal to the other one of the source and the drain of the driving transistor.

12. The display device of claim 9, wherein, Another end of the light emitting element is electrically connected to a second voltage line for transmitting a second voltage signal; In the first time period, the second time period and the third time period, an absolute value of a difference between an amplitude of the first reset signal and an amplitude of the second voltage signal is less than a turn-on voltage of the light emitting element, and an absolute value of a difference between the amplitude of the second voltage signal and an amplitude of the first voltage signal is less than an absolute value of a difference between the turn-on voltage of the light emitting element and the driving transistor.

13. A display device as claimed in any one of claims 10 to 12, wherein, In a fourth time period after the third time period, the data write transistor is configured to transmit the first reset signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to transmit the first reset signal to one of the source and the drain of the driving transistor, and the light emitting control transistor is configured to control a current circuit between the first voltage line and the other of the source and the drain of the driving transistor.

14. The display device of claim 13, wherein, In a fifth time period after the fourth time period, the data write transistor is configured to transmit a target data signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to control a current circuit between the one of the source and the drain of the driving transistor and the gate of the driving transistor, and the light emitting control transistor is configured to control a current circuit between the first voltage line and the other of the source and the drain of the driving transistor. The control circuit is configured to generate the target data signal according to the compensation voltage signal and a data signal, and the data signal is configured to be generated according to a corresponding gray scale value.

15. The display device of claim 14, wherein, In a sixth time period after the fifth time period, the light emitting control transistor is configured to control a current circuit between the first voltage line and the other of the source and the drain of the driving transistor, and the driving transistor is configured to generate a driving current according to the target data signal to drive the light emitting element to emit light.

16. The display device of any of claims 10 to 12, wherein, The pixel circuit further comprises: a first reset transistor, one of a source and a drain of the first reset transistor is electrically connected to one end of the light emitting element and one of a source and a drain of the driving transistor, and the other of the source and the drain of the first reset transistor is electrically connected to a reset line for transmitting a second reset signal; In a fourth time period after the third time period, the data write transistor is configured to transmit the first reset signal generated by the voltage generation unit to the gate of the driving transistor, the compensation transistor is configured to electrically disconnect the one of the source and the drain of the driving transistor and the gate of the driving transistor, and the first reset transistor is configured to transmit the second reset signal to the one of the source and the drain of the driving transistor. In a fifth period after the fourth period, the data write transistor is configured to transmit a target data signal generated by the voltage generation unit to a gate of the driving transistor, the compensation transistor is configured to control a current break between one of a source and a drain of the driving transistor and the gate of the driving transistor, the light emitting control transistor is configured to control a current break between the first voltage line and the other of the source and the drain of the driving transistor, and the first reset transistor is configured to transmit the second reset signal to the one of the source and the drain of the driving transistor. The control circuit is configured to generate the target data signal according to the compensation voltage signal and a data signal generated according to a corresponding gray scale value.

17. The display device of claim 16, wherein, The pixel circuit further comprises: a second reset transistor, one of a source and a drain of the second reset transistor is electrically connected to the other of the source and the drain of the driving transistor and the other of a source and a drain of the light emitting control transistor, and the other of the source and the drain of the second reset transistor is electrically connected to the reset line. In the fourth period and the fifth period, the second reset transistor is configured to transmit the second reset signal to the other of the source and the drain of the driving transistor.

18. The display device of claim 17, wherein, In a sixth period after the fifth period, the light emitting control transistor is configured to control a current pass between the first voltage line and the other of the source and the drain of the driving transistor, and the driving transistor is configured to generate a driving current according to the target data signal to drive the light emitting element to emit light.

19. The display device of any of claims 9 to 12, 14 to 15, 17 to 18, wherein, The pixel circuit further comprises: a capacitor electrically connected between the gate of the driving transistor and the first voltage line, and the first voltage signal transmitted by the first voltage line is a constant voltage signal.

20. A driving method of a display device, wherein, The display device comprises a plurality of control circuits and a plurality of corresponding pixel circuits, each of the control circuits comprises a detection unit and a voltage generation unit corresponding to the pixel circuit, and each of the pixel circuits comprises: a light emitting element; a data write transistor, one of a source and a drain of the data write transistor is electrically connected to the corresponding detection unit and the corresponding voltage generation unit; a driving transistor, a gate of the driving transistor is electrically connected to the data write transistor, and one of a source and a drain of the driving transistor is electrically connected to one end of the light emitting element; a compensation transistor, electrically connected between one of the source and the drain of the driving transistor and the gate of the driving transistor; a driving method of the display device comprises: in a first period, controlling the data write transistor to transmit a first reset signal generated by the voltage generation unit to the gate of the driving transistor, and controlling the compensation transistor to transmit the first reset signal to one of the source and the drain of the driving transistor; In a second period after the first period, another one of the source and the drain of the driving transistor is controlled to receive a first voltage signal transmitted by a first voltage line, and the driving transistor is controlled to be turned on under the actions of the first reset signal, the first voltage signal and the turned-on compensation transistor, so that the potential of the gate of the driving transistor rises or falls until the driving transistor is turned off; In a third period after the second period, the detection unit is controlled to obtain the potential of the gate of the driving transistor through the data writing transistor, and the control circuit is controlled to generate a compensation voltage signal according to the potential of the gate of the driving transistor.

Images