Dedicated management network port connection system, physical layer chip management method, device, product, and medium

Abstract

The present application relates to the technical field of computers, and discloses a dedicated management network port connection system, a physical layer chip management method, a device, a product, and a medium. The system comprises: a secure control module board and a mainboard provided with a first connector, wherein the secure control module board is provided with a management device and a first physical layer chip connected to the management device. In addition, the system further comprises an input / output board mounted on a front panel of a server chassis, wherein the input / output board is provided with a target jack of a dedicated management network port of the management device, a second physical layer chip, and a second connector. The first physical layer chip is connected in series to the second physical layer chip on the input / output board through the connectors in sequence by means of a serial communication bus; and the management device on the secure control module board controls the first physical layer chip and the second physical layer chip by means of a plurality of management buses. By means of the technical solution of the present application, the problem that some existing jacks do not conform to circuit design specifications can be solved.

Description

Special management network port connection system, physical layer chip management method, device, product and medium

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to the Chinese patent application No. 202411367333.8, filed on September 29, 2024, and entitled "Special management network port connection system, physical layer chip management method, device, product and medium", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of computer technology, and in particular, to a special management network port connection system, a physical layer chip management method, a device, a product and a medium. BACKGROUND

[0004] The BMC (Baseboard Management Controller) special management network port refers to the network interface specially provided for the BMC on the server motherboard, which is used for remote monitoring and management of the server hardware state. This special management network port is usually independent of the main network interface of the server, so that even if the server operating system crashes or is not started, the administrator can still remotely access the server through the BMC special management network port for management and troubleshooting.

[0005] The BMC special management network port relies on the PHY (Physical Layer) chip to realize the function of its physical layer, to ensure the effective transmission of data and the smooth operation of management. As shown in FIG. 1, it is a hardware design schematic diagram for managing the PHY chip through the BMC. Usually, the RJ45 socket of the special management network port is placed on the SCM (Secure Control Module) board to be directly connected with the PHY chip. However, the RJ45 may cause electromagnetic interference to the circuit, and since the hardware circuit requirements of some GPU (Graphics Processing Unit) manufacturers are relatively high, it cannot meet the hardware design standards thereof. Therefore, how to provide a solution to the above technical problems is a problem that the person skilled in the art needs to solve at present. SUMMARY

[0006] Therefore, the purpose of the present application is to provide a special management network port connection system, a physical layer chip management method, a device, a product and a medium, which can solve the problem of not meeting the circuit design specification caused by some sockets of the special management network port. The specific scheme is as follows:

[0007] In a first aspect, the application discloses a special management network port connection system, which comprises a security control module board and a mainboard provided with a first connector, the security control module board is provided with a management device and a first physical layer chip connected with the management device; and the special management network port connection system further comprises:

[0008] An input / output board is installed on the front panel of the server case, and the input / output board is provided with a target socket of the special management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected with the second physical layer chip on the input / output board in series through the first connector and the second connector by using a serial communication bus; the first connector and the second connector are connectors supporting preset high-density storage connection; and the target socket is a socket capable of generating electromagnetic interference on the security control module board.

[0009] Furthermore, the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management buses.

[0010] In some embodiments of the application, the management device on the security control module board is connected with the first physical layer chip through a reduced gigabit media independent interface bus.

[0011] In some embodiments of the application, the first physical layer chip on the security control module board is connected with the second physical layer chip on the input / output board in series through the first connector and the second connector by using a serial gigabit media independent interface bus.

[0012] In some embodiments of the application, the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management data input / output buses.

[0013] In some embodiments of the application, the management device is used to control the transmission rate of the first physical layer chip and the second physical layer chip.

[0014] In some embodiments of the application, the management device is used to set the first physical layer chip and the second physical layer chip to a rate self-matching mode by using the management bus, so as to realize the control of the transmission rate.

[0015] In some embodiments of the application, the management device is used to obtain the transmission rate setting parameter of the second physical layer chip, and set the transmission rate setting parameter as the transmission rate of the first physical layer chip by using the management bus, so as to realize the control of the transmission rate.

[0016] In some embodiments of the present application, the management device is connected with the first physical layer chip by using a first management bus, and is connected with the second physical layer chip by using a second management bus and sequentially through the first connector and the second connector; wherein the first management bus and the second management bus are connected based on the multiplexing resistance of the multifunctional board.

[0017] The first target position is reserved without resistance based on the multiplexing resistance of the multifunctional board, so that the link between the management device and the second physical layer chip is in a disconnected state; wherein when the physical layer chips are controlled, the management device sends a first control command to the first physical layer chip through the first management bus, and sends a second control command to the second physical layer chip through the first management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip respectively based on different control commands through one management bus.

[0018] In some embodiments of the present application, the management device is connected with the first physical layer chip by using a third management bus, and is connected with the second physical layer chip by using a fourth management bus and sequentially through the first connector and the second connector; wherein the third management bus and the fourth management bus are connected based on the multiplexing resistance of the multifunctional board.

[0019] The second target position is reserved without resistance based on the multiplexing resistance of the multifunctional board, so that the link between the management device and the second physical layer chip is in a connected state; wherein when the physical layer chips are controlled, the management device sends a third control command to the first physical layer chip through the third management bus, and sends a fourth control command to the second physical layer chip through the fourth management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip respectively based on different control commands through two management buses.

[0020] In some embodiments of the present application, the management device is connected with the first physical layer chip by using a fifth management bus.

[0021] The first physical layer chip is connected with the second physical layer chip by using the fifth management bus and sequentially through the first connector and the second connector; wherein when the physical layer chips are controlled, the management device sends a fifth control command to the first physical layer chip through the fifth management bus, and the first physical layer chip sends the fifth control command to the second physical layer chip through the fifth management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip based on the same control command.

[0022] In some embodiments of the present application, the first physical layer chip is connected with the second physical layer chip through the sixth management bus, the first connector and the second connector in sequence, and the management device is connected with the first connector through the seventh management bus; wherein, when the physical layer chips are controlled, the management device sends the sixth control command to the second physical layer chip through the seventh management bus, and the second physical layer chip sends the sixth control command to the first physical layer chip through the sixth management bus, so as to realize the control of the management device on the first physical layer chip and the second physical layer chip based on the same control command.

[0023] In a second aspect, the present application discloses a physical layer chip management method, applied to the special management network port connection system as mentioned above; wherein, the method comprises:

[0024] determining the control link between the management device on the security control module board and each physical layer chip in the server; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses, and each physical layer chip includes the first physical layer chip on the security control module board and the second physical layer chip on the input / output board in the special management network port connection system;

[0025] sending the control command to the first physical layer chip and the second physical layer chip through the management device and using the control link, so as to realize the control of the first physical layer chip and the second physical layer chip.

[0026] In a third aspect, the present application discloses an electronic device, comprising:

[0027] a memory for storing a computer program;

[0028] a processor for loading and executing the computer program to realize the aforementioned physical layer chip management method.

[0029] In a fourth aspect, the present application discloses a computer program product, comprising computer programs / instructions, which realize the steps of the aforementioned physical layer chip management method when executed by a processor.

[0030] In a fifth aspect, the present application discloses a computer non-volatile storage medium for storing a computer program; wherein the computer program realizes the aforementioned physical layer chip management method when executed by a processor.

[0031] The application provides a special management network port connection system, which comprises a security control module board and a mainboard provided with a first connector, the security control module board is provided with a management device and a first physical layer chip connected with the management device; and the special management network port connection system further comprises: an input and output board installed on the front panel of a server case, the input and output board is provided with a target socket of the special management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected with the second physical layer chip on the input and output board in series by using a serial communication bus and sequentially through the first connector and the second connector; the first connector and the second connector are connectors supporting preset high-density storage connection; the target socket is a socket capable of generating electromagnetic interference to the security control module board; and the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management buses.

[0032] The application has the beneficial technical effects that: by placing two physical layer chips on the security control module board and the input and output board installed on the front panel of the server case, and connecting the physical layer chip far away from the main circuit position with the target socket of the special management network port, since the target socket can generate electromagnetic interference to the security control module board, the physical layer chip far away from the main circuit can prevent some hardware adaptation caused by electromagnetic interference and the like from not meeting the standard, and the problem that some sockets of the special management network port can cause the circuit design specification not to be met is solved. When the management device on the security control module board in the server manages the physical layer chip, the physical layer chip can be managed by using a plurality of management buses through the connector supporting preset high-density storage connection, not only the transmission wiring distance problem between the mainboard and the input and output board is solved, but also the data transmission capacity and transmission quality are ensured, and the management of the management device to the physical layer chip is realized.

[0033] In addition, the physical layer chip management method, device, program product and medium provided by the application correspond to the above-mentioned special management network port connection system and have the same effects. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in some embodiments of the application or related technical solutions, the following will briefly introduce the drawings needed to be used in some embodiments or related technical solution descriptions. Obviously, the drawings in the following description are only some embodiments of the application, and those skilled in the art can obtain other drawings according to the provided drawings without any creative effort.

[0035] Fig. 1 is a schematic diagram of an exemplary hardware design of the current BMC managing the PHY chip;

[0036] Fig. 2 is a schematic diagram of a special management network port connection system structure disclosed by the application;

[0037] Fig. 3 is a system architecture diagram for managing a PHY chip based on a multi-functional single board multiplexed resistor according to the present disclosure;

[0038] Fig. 4 is a system architecture diagram for controlling two PHY chips respectively through one management bus according to the present disclosure;

[0039] Fig. 5 is a simplified architecture diagram for controlling two PHY chips respectively through one management bus according to the present disclosure;

[0040] Fig. 6 is a system architecture diagram for controlling two PHY chips respectively through two management buses according to the present disclosure;

[0041] Fig. 7 is a simplified architecture diagram for controlling two PHY chips respectively through two management buses according to the present disclosure;

[0042] Fig. 8 is a system architecture diagram for controlling two PHY chips simultaneously through one communication link of one management bus according to the present disclosure;

[0043] Fig. 9 is a system architecture diagram for controlling two PHY chips simultaneously through one communication link of one management bus according to the present disclosure;

[0044] Fig. 10 is a flow chart of a physical layer chip management method according to the present disclosure;

[0045] Fig. 11 is a structure diagram of a physical layer chip management device according to the present disclosure;

[0046] Fig. 12 is a structure diagram of an electronic device according to the present disclosure. DETAILED DESCRIPTION

[0047] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in some embodiments of the present disclosure. Obviously, some described embodiments are only some of the embodiments of the present disclosure, not all the embodiments. Based on some embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present disclosure.

[0048] Currently, due to the high requirements of the hardware circuit of some GPU manufacturers, placing the RJ45 socket of the BMC dedicated management network port directly on the SCM board to connect with the PHY chip will cause electromagnetic interference to the circuit, which cannot meet the hardware design standard. Therefore, the present disclosure provides a dedicated management network port connection system, which can solve the problem that some sockets of the current dedicated management network port do not meet the circuit design specification, and at the same time, manage the PHY chip.

[0049] Some embodiments of the present application disclose a special management network port connection system, as shown in FIG. 2, the system comprises a security control module board 11 and a mainboard 21 provided with a first connector 211, the security control module board 11 is provided with a management device 111 and a first physical layer chip 112 connected with the management device 111; and the special management network port connection system further comprises:

[0050] An input / output board 31 is installed on the front panel of the server case, the input / output board 31 is provided with a target socket 313 of the special management network port of the management device 111, a second physical layer chip 312 and a second connector 311; wherein the first physical layer chip 112 on the security control module board 11 is connected in series with the second physical layer chip 312 on the input / output board 31 through the first connector 211 and the second connector 311 by using a serial communication bus; the first connector 211 and the second connector 311 are connectors supporting preset high-density storage connection; and the target socket is a socket capable of generating electromagnetic interference to the security control module board;

[0051] Further, the management device 111 on the security control module board 11 controls the first physical layer chip 112 and the second physical layer chip 312 through a plurality of management buses.

[0052] In some embodiments of the present application, a special management network port connection system is designed, which can be applied to a GPU server. Further, for the GPU server, in a specific embodiment, the management device 111 is taken as an example of BMC, and the target socket 313 is taken as an example of RJ45 socket. Those skilled in the art can understand that the specific types of the above devices are only illustrative and do not limit the technology. In some embodiments below, BMC and RJ45 socket are taken as examples for illustration, and the following will not be described in detail.

[0053] It can be understood that, due to the requirements of GPU manufacturers for hardware design standards, the RJ45 socket of the BMC special network port cannot be placed on the SCM board together with the BMC chip. Therefore, in the present application, the RJ45 socket of the BMC special management network port is placed on the IO (Input / output) board, and then the IO board is placed on the front of the server case to obtain a Front IO Board, that is, the input / output board 31 in FIG. 2. In this way, the RJ45 socket is placed away from the main circuit of the SCM board and the mainboard, which can avoid the standards of the GPU manufacturers and avoid electromagnetic and optical wave interference.

[0054] Generally, the BMC special management network port corresponds to an Ethernet PHY chip at the physical layer and a MAC controller of a BMC chip at the MAC (Media Access Control) layer. The MAC layer performs data transmission with the Ethernet PHY chip at the physical layer through an RGMII (Reduced Gigabit Media Independent Interface) bus, the MAC chip is responsible for processing data frames, and the PHY chip converts the data frames into electrical signals for transmission through a network cable. An MDIO (Management Data Input / output) bus is usually used to configure and monitor the PHY chip, and the BMC accesses the management registers of the PHY chip through the MDIO bus to configure the behavior of the PHY chip and monitor the status thereof.

[0055] Therefore, in some embodiments of the present application, the management device 111 on the security control module board 11 is connected to the first physical layer chip 112 through an RGMII bus. The management device 111 on the security control module board 11 controls the physical layer chip through an MDIO bus.

[0056] It should be noted that the RGMII is used to connect the MAC (Media Access Control layer) and the PHY chip, reduces the number of pins, and is suitable for gigabit Ethernet. When the BMC performs connection management of the PHY chip, a simple solution is to directly connect the RJ45 and the first physical layer chip PHY1 on the SCM board through a cable. However, since the wiring distance is too long and the connection cable can cause electromagnetic interference to the circuit, the RJ45 cannot span the IO board and the mainboard and be directly connected to the PHY1 on the SCM board through a long cable. Therefore, in order to solve this problem, a second physical layer chip PHY2 is placed on the IO board in some embodiments of the present application, which is connected to the PHY1 on the SCM board through an SGMII (SerDes Gigabit Media Independent Interface) bus. At the same time, the BMC needs to manage the two physical layer chips through an MDIO bus.

[0057] The SGMII bus is an interface standard for connecting computers and peripheral devices (such as hard drives, tape drives, scanners, printers, etc.) for high-speed data transmission. Because the transmission capacity of the SGMII bus is relatively strong, and the wiring distance can be relatively long, using two PHY chips in series and converting RGMII transmission into SGMII transmission can not only meet the design of the BMC dedicated management network port, but also overcome the limitations of RGMII wiring distance, transmission capacity, and the inability to achieve long-distance wiring.

[0058] Further, in order to ensure data transmission capacity and transmission quality, a first connector 211 and a second connector 311 supporting a pre-set high-density storage connection are respectively placed on the mainboard 21 and the input / output board 31. In a specific embodiment, the connector can be connected using a Slim Line (SASx8) cable to efficiently and high-quality long-distance transmit data from the SGMII bus. The SASx8 (Serial Attached SCSI) device is a compact design solution that supports high-density storage connections, suitable for high-performance storage needs in servers and storage systems. By providing 8 SAS ports, efficient data storage and management can be achieved in limited space. In this way, the problem of short SGMII / MDIO bus transmission and wiring distance is further solved, and the data transmission capacity and transmission quality are guaranteed.

[0059] That is, the first physical layer chip 112 on the security control module board 11 uses the serial gigabit media independent interface bus and is connected in series with the second physical layer chip 312 on the input / output board 31 through the first connector 211 and the second connector 311.

[0060] In addition, for the SCM board, the mainboard, and the IO board in the dedicated management network port connection system architecture, the positions of the SCM board, the mainboard, and the IO board in the server chassis can also be reasonably designed to save the main space occupied by the dedicated management network port connection system, make full use of the chassis position to reserve enough space, and then set as many other boards as possible. Without increasing the product size, optimizing the space design can provide favorable conditions for functional expansion and performance improvement.

[0061] The application provides a special management network port connection system, which comprises a security control module board and a mainboard provided with a first connector, the security control module board is provided with a management device and a first physical layer chip connected with the management device; and the special management network port connection system further comprises: an input and output board installed on the front panel of a server case, the input and output board is provided with a target socket of a special management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected with the second physical layer chip on the input and output board in series by using a serial communication bus and sequentially through the first connector and the second connector; the first connector and the second connector are connectors supporting preset high-density storage connection; the target socket is a socket capable of generating electromagnetic interference to the security control module board; and the management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management buses.

[0062] The application has the beneficial technical effects that: two physical layer chips are placed on the security control module board and the input and output board installed on the front panel of the server case, and the physical layer chip far away from the main circuit position is connected with the target socket of the special management network port, since the target socket can generate electromagnetic interference to the security control module board, the physical layer chip far away from the main circuit can prevent some hardware adaptation caused by electromagnetic interference and the like from not meeting the standards, and the problem that some sockets of the special management network port can cause the circuit design specification not to be met is solved. When the management device on the security control module board in the server manages the physical layer chip, the physical layer chip can be managed by using a plurality of management buses through the connector supporting the preset high-density storage connection, not only the transmission wiring distance problem between the mainboard and the input and output board is solved, but also the data transmission capacity and transmission quality are ensured, and the management of the management device to the physical layer chip is realized.

[0063] In the application, the management device 111 on the security control module board 11 needs to control the first physical layer chip 112 and the second physical layer chip 312 through a plurality of management buses to realize the management of the management device to the physical layer chip. As shown in FIG. 3, an example driving scheme diagram capable of realizing that the BMC manages two PHY chips through one or two MDIO buses is provided. A multifunctional single board multiplexing resistor 113Colay is arranged on the security control module.

[0064] In circuit design, the Colay resistance is a technology for realizing multi-functional single-board multiplexing through specific wiring structure and resistance layout. Specifically, by reasonably placing the Colay resistance on a PCB (Printed Circuit Board) board and setting corresponding vias and signal lines, multiple functional application scenarios can be compatible on the same board card, without the need to develop a new board card for each function, thereby saving cost and improving design efficiency.

[0065] Based on some of the above embodiments, in a feasible implementation, as shown in FIG. 4, a schematic diagram of a driving scheme for the BMC to manage two PHY chips through one MDIO bus is shown.

[0066] Specifically, the management device 111 is connected with the first physical layer chip 112 through a first management bus, and is connected with the second physical layer chip 312 through a second management bus and in sequence through the first connector 211 and the second connector 311; wherein the first management bus and the second management bus are connected based on the multi-functional single-board multiplexing resistance 113.

[0067] Based on the multi-functional single-board multiplexing resistance 113, the first target position R2 is not reserved with resistance, so that the link between the management device 111 and the second physical layer chip 312 is in a disconnected state; wherein when controlling the physical layer chip, the management device 111 sends a first control command to the first physical layer chip 112 through the first management bus, and sends a second control command to the second physical layer chip 312 through the first management bus, so as to realize that the management device 111 controls the first physical layer chip 112 and the second physical layer chip 312 based on different control commands through one management bus.

[0068] In some embodiments of the present application, at the hardware link level, the resistance R2 position is not reserved with resistance. In this way, the MDC2 (Management Data Clock, bus clock signal) / MDIO2 link between the BMC and the second physical layer chip 312 on the IO board is in a disconnected state. Therefore, the BMC is connected to the first physical layer chip 112 on the SCM board and the second physical layer chip 312 on the IO board through the MDC1 / MDIO1 bus at the same time, thereby forming a scheme for the BMC to control two PHYs through one MDIO bus.

[0069] That is, in Figure 4, the final hardware link corresponds to: (1) the BMC on the SCM board is connected to the PHY1 (first physical layer chip) through the RGMII bus, and the PHY1 is connected to the Slim Line SASx8 interface on the mainboard through the SGMII bus; (2) the MDIO bus of the BMC on the SCM board is connected to the PHY1 and the Slim Line SASx8 interface on the mainboard, respectively; (3) the PHY2 (second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (4) finally, the Slim Line SASx8 interface on the mainboard and the Slim Line SASx8 interface on the IO board are connected through the Slim Line SASx8 cable. The corresponding architecture simplified diagram is shown in Figure 5.

[0070] It should be noted that the kernel of the BMC driver binds mdio1 with PHY1 and PHY2, and because PHY2 is connected to the RJ45 socket, the outside world accesses the dedicated management network of the BMC through PHY2, so mac2 is bound with PHY2. Since PHY1 is a relay chip, it does not need to be bound with mac. When the BMC kernel starts, it initializes the configuration (such as data transmission rate, duplex mode, medium type, etc.) of the PHY1 and PHY2 chips through mdio1. The BMC communicates with PHY1 and PHY2 through mdio1 by sending control commands to the PHY1 and PHY2 chips, so the BMC needs to carry the address of the PHY chip when sending commands, for example, the address of PHY1 is 0x0, and the address of PHY2 is 0x1. Further, according to the control command, the BMC realizes the driving scheme of managing two PHY chips through one MDIO bus.

[0071] In addition, in some embodiments of the present application, in order to prevent the transmission rate of PHY1 and PHY2 from being inconsistent and causing the transmission speed to decrease, the management device controls the transmission rate of the first physical layer chip and the second physical layer chip, so that PHY1 follows PHY2 to maintain consistent transmission rate.

[0072] In a first specific embodiment, the management device sets the first physical layer chip and the second physical layer chip to a rate self-matching mode through the management bus to realize the control of the transmission rate. That is, the BMC sets PHY1 / PHY2 to the rate self-matching mode through mdio1, so that it can automatically negotiate the best transmission rate and mode with the connected device, ensuring the compatibility and best performance between the two. And automatically adjust the data transmission rate under different network conditions, improve the communication efficiency and stability.

[0073] In the second specific embodiment, the management device acquires the transmission rate setting parameter of the second physical layer chip, and sets the transmission rate setting parameter as the transmission rate of the first physical layer chip by using the management bus, so as to realize the control of the transmission rate. That is, the BMC acquires the setting parameter of PHY2, and then sets it to PHY1 through mdio1.

[0074] Based on the above some embodiments, in a feasible embodiment, as shown in FIG. 6, it is a schematic diagram of the driving scheme of the BMC for managing two PHY chips through two MDIO buses.

[0075] Specifically, the management device 111 is connected with the first physical layer chip 112 by using the third management bus, and is connected with the second physical layer chip 312 by using the fourth management bus and sequentially through the first connector 211 and the second connector 311; wherein the third management bus and the fourth management bus are connected based on the multifunctional single board multiplexing resistor 113.

[0076] Based on the multifunctional single board multiplexing resistor 113, the second target position R1 is not reserved with a resistor, so that the link between the management device 111 and the second physical layer chip 312 is in a connected state; wherein when the physical layer chip is controlled, the management device 111 sends a third control command to the first physical layer chip 112 through the third management bus, and sends a fourth control command to the second physical layer chip 312 through the fourth management bus, so as to realize that the management device 111 controls the first physical layer chip 112 and the second physical layer chip 312 respectively by using two management buses and based on different control commands.

[0077] In some embodiments of the present application, at the hardware link level, the resistor R1 position is not reserved with a resistor. In this way, the MDC2 / MDIO2 link between the BMC and the second physical layer chip 312 on the IO board is in a connected state. Therefore, the BMC is connected to the first physical layer chip 112 on the SCM board through the MDC1 / MDIO1 bus, and is connected to the second physical layer chip 312 on the IO board through the MDC2 / MDIO2 bus, so as to form a scheme of the BMC for controlling two PHYs through two MDIO buses.

[0078] That is, in Figure 6, the final hardware link corresponds to: (1) the BMC on the SCM board is connected with the PHY1 (first physical layer chip) through the RGMII bus, and the PHY1 is connected to the Slim Line SASx8 interface on the mainboard through the SGMII bus; (2) the MDIO bus of the BMC on the SCM board is connected to the PHY1 and the Slim Line SASx8 interface on the mainboard respectively; (3) the PHY2 (second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (4) finally, the Slim Line SASx8 interface on the mainboard and the Slim Line SASx8 interface on the IO board are connected through the Slim Line SASx8 cable. The corresponding architecture simplified diagram is shown in Figure 7.

[0079] It should be noted that, in the driver level, the kernel of the BMC binds mdio1 with the PHY1, binds mdio2 with the PHY2, and binds mac2 with the PHY2 at the same time, because the PHY2 is connected with the RJ45 socket, and the outside accesses the special management network of the BMC through the PHY2. Since the PHY1 is a relay chip, it does not need to bind mac. When the BMC kernel starts, it initializes the configuration (such as data transmission rate, duplex mode, medium type, etc.) of the PHY1 and the PHY2 chips through mdio1 and mdio2 respectively.

[0080] Similarly, in some embodiments of the present application, in order to prevent the transmission speed from being reduced due to the inconsistent transmission rates of the PHY1 and the PHY2, it is necessary to require the PHY1 to keep consistent transmission rate with the PHY2. Therefore, the BMC sets the PHY1 / PHY2 into the rate self-matching mode through mdio1, or the BMC obtains the setting parameters of the PHY2 and then sets them to the PHY1 through mdio1.

[0081] Further, as shown in Figures 8 and 9, an exemplary driving scheme diagram is provided, which can realize that the BMC controls two PHY chips through only one MDIO bus.

[0082] In a specific embodiment, as shown in Figure 8, specifically, the manager device 111 is connected with the first physical layer chip 112 through the fifth management bus;

[0083] The first physical layer chip 112 is connected with the second physical layer chip 312 through the fifth management bus, the first connector 211 and the second connector 311 in sequence; wherein, when the physical layer chips are controlled, the management device 111 sends a fifth control command to the first physical layer chip 112 through the fifth management bus, and the first physical layer chip 112 sends the fifth control command to the second physical layer chip 312 through the fifth management bus, so as to realize that the management device controls the first physical layer chip 112 and the second physical layer chip 312 based on the same control command.

[0084] The corresponding hardware links in some embodiments of the application are as follows: (1) the BMC on the SCM board is connected with the PHY1 (first physical layer chip) through the RGMII bus, and the PHY1 is connected to the Slim Line SASx8 interface on the mainboard through the SGMII bus; (2) the MDIO bus of the BMC on the SCM board is connected to the PHY1; (3) the PHY1 on the SCM board is connected to the Slim Line SASx8 interface on the mainboard through the MDIO bus; (4) the PHY2 (second physical layer chip) on the IO board is connected to its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (5) finally, the Slim Line SASx8 interface on the mainboard is connected with the Slim Line SASx8 interface on the IO board through the Slim Line SASx8 cable.

[0085] It should be noted that the kernel of the BMC binds the mdio1 with the PHY1 at the driver level, and because the PHY2 is connected with the RJ45 socket, the outside accesses the special management network of the BMC through the PHY2, so the mac2 is bound with the PHY2. Because the PHY1 is a relay chip, it is not necessary to bind the mac. When the BMC kernel is started, the PHY1 is initialized through the mdio1, the control command is sent to the PHY1 through the mdio1 bus, and then the PHY1 sends the same control command to the PHY2 through the MDIO bus, so as to complete the control and management of the BMC to the PHY1 and the PHY2.

[0086] In another specific embodiment, as shown in FIG. 9, specifically, the first physical layer chip 112 is connected with the second physical layer chip 312 through the sixth management bus and sequentially through the first connector 211 and the second connector 311, and the management device 111 is connected with the first connector 211 through the seventh management bus; wherein, when controlling the physical layer chips, the management device 111 sends the sixth control command to the second physical layer chip 312 through the seventh management bus, and the second physical layer chip 312 sends the sixth control command to the first physical layer chip 112 through the sixth management bus, so as to realize the control of the management device 111 on the first physical layer chip 112 and the second physical layer chip 312 based on the same control command.

[0087] The corresponding hardware links in some embodiments of the application are as follows: (1) the BMC on the SCM board is connected with the PHY1 (first physical layer chip) through the RGMII bus, and the PHY1 is connected with the Slim Line SASx8 interface on the mainboard through the SGMII bus; (2) the MDIO bus of the BMC on the SCM board is connected with the Slim Line SASx8 interface on the mainboard; (3) the PHY1 on the SCM board is connected with the Slim Line SASx8 interface on the mainboard through the MDIO bus; (4) the PHY2 (second physical layer chip) on the IO board is connected with its Slim Line SASx8 interface through the SGMII bus and the MDIO bus; (5) finally, the Slim Line SASx8 interface on the mainboard is connected with the Slim Line SASx8 interface on the IO board through the Slim Line SASx8 cable.

[0088] It should be noted that the kernel of the BMC binds the mdio2 with the PHY2 at the driver level, and because the PHY2 is connected with the RJ45 socket, the outside accesses the special management network of the BMC through the PHY2, so the mac2 is bound with the PHY2. Because the PHY1 is a relay chip, the mac does not need to be bound. When the kernel of the BMC is started, the PHY2 is initialized through the mdio2, the control command is sent to the PHY2 through the mdio2 bus, and then the PHY2 sends the same control command to the PHY1 through the MDIO, so as to complete the control and management of the BMC on the PHY1 and the PHY2.

[0089] Some embodiments of the application disclose a physical layer chip management method, which is applied to the special management network port connection system disclosed in the foregoing embodiments; as shown in FIG. 10, the method comprises the following steps:

[0090] Step S11: determining a control link between the management device on the security control module board of the dedicated management network port connection system and each physical layer chip in the server; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses, and each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on an input / output board in the dedicated management network port connection system.

[0091] Step S12: sending a control command to the first physical layer chip and the second physical layer chip through the management device and using the control link to achieve control of the first physical layer chip and the second physical layer chip.

[0092] In some embodiments of the present application, the problem that some sockets of the dedicated management network port of the management device do not meet the circuit design specification is solved by placing two physical layer chips. Therefore, when applied to the dedicated management network port connection system designed in the present application, the control link between the management device on the security control module board of the dedicated management network port connection system and each physical layer chip in the server is determined, data transmission is further implemented according to the control link, and the management of the management device to the physical layer chip is implemented through the control command. The more specific processing process of the above steps can be referred to the corresponding content disclosed in the foregoing embodiments, and will not be described here.

[0093] In some embodiments of the present application, a physical layer chip management method is provided, which is applied to a dedicated management network port connection system and includes: determining a control link between a management device on a security control module board of the dedicated management network port connection system and each physical layer chip in the server; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses, and each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on an input / output board in the dedicated management network port connection system; and sending a control command to the first physical layer chip and the second physical layer chip through the management device and using the control link to achieve control of the first physical layer chip and the second physical layer chip.

[0094] The beneficial technical effects of the present application are as follows: by placing two physical layer chips on the security control module board and the input / output board installed on the front panel of the server case, and connecting the physical layer chip far away from the main circuit to the target socket of the special management network port, since the target socket can generate electromagnetic interference to the security control module board, the electromagnetic interference and other factors can be prevented from causing some hardware adaptation to be non-compliant with the standard, and the problem that some sockets of the special management network port can cause non-compliance with the circuit design specification is solved. When the management device on the security control module board in the server manages the physical layer chip, the management device can manage the physical layer chip by supporting the connector of the preset high-density storage connection and using a plurality of management buses, which not only solves the transmission wiring distance problem between the mainboard and the input / output board, but also ensures the data transmission capacity and transmission quality, and realizes the management of the management device to the physical layer chip.

[0095] Correspondingly, some embodiments of the present application also disclose a physical layer chip management device, as shown in FIG. 11, which comprises:

[0096] A link determination module 51 is configured to determine a control link between the management device on the security control module board in the special management network port connection system in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses; each physical layer chip comprises a first physical layer chip on the security control module board and a second physical layer chip on the input / output board in the special management network port connection system.

[0097] A chip control module 52 is configured to send a control command to the first physical layer chip and the second physical layer chip through the management device and using the control link, so as to control the first physical layer chip and the second physical layer chip.

[0098] Wherein, the more specific working process of each module can refer to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

[0099] Therefore, by the above scheme of some embodiments of the present application, the special management network port connection system is applied, comprising: determining a control link between the management device on the security control module board in the special management network port connection system in the server and each physical layer chip; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses; each physical layer chip comprises a first physical layer chip on the security control module board and a second physical layer chip on the input / output board in the special management network port connection system; a control command is sent to the first physical layer chip and the second physical layer chip through the management device and using the control link, so as to control the first physical layer chip and the second physical layer chip.

[0100] The beneficial technical effects of the present application are: by placing two physical layer chips on the security control module board and the input / output board installed on the front panel of the server case, and connecting the physical layer chip far away from the main circuit position with the target socket of the special management network port, since the target socket can generate electromagnetic interference to the security control module board, the physical layer chip far away from the main circuit can prevent some hardware adaptation from not meeting the standard caused by electromagnetic interference, and the problem that some sockets of the special management network port can cause non-compliance with the circuit design specification is solved. When the management device on the security control module board in the server manages the physical layer chip, the management device can manage the physical layer chip through the connector supporting the preset high-density storage connection and using several management buses, which not only solves the transmission wiring distance problem between the mainboard and the input / output board, but also ensures the data transmission capacity and transmission quality, and realizes the management of the physical layer chip by the management device.

[0101] Further, some embodiments of the present application also disclose an electronic device, and FIG. 12 is a structural diagram of an electronic device 60 according to some example embodiments, and the content in the figure should not be considered as any limitation on the use range of the present application.

[0102] FIG. 12 is a structural schematic diagram of an electronic device 60 according to some embodiments of the present application. The electronic device 60 can specifically include at least one processor 61, at least one memory 62, a power supply 63, a communication interface 64, an input / output interface 65 and a communication bus 66. The memory 62 is used to store a computer program, which is loaded and executed by the processor 61 to implement the related steps in the physical layer chip management method disclosed in some embodiments described above. In addition, the electronic device 60 in some embodiments of the present application can be a server.

[0103] In some embodiments of the present application, the power supply 63 is used to provide working voltage for each hardware device on the electronic device 60; the communication interface 64 can create a data transmission channel between the electronic device 60 and external devices, and the communication protocol followed by the communication interface 64 can be any communication protocol applicable to the technical solution of the present application, which is not limited here; the input / output interface 65 is used to obtain external input data or output data to the outside world, and the specific interface type can be selected according to the specific application needs, which is not limited here.

[0104] In addition, the memory 62 as a carrier of resource storage can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 621, a computer program 622 and data 623, etc., and the data 623 can include various data. The storage mode can be temporary storage or permanent storage.

[0105] The operating system 621 is used for managing and controlling the various hardware devices and computer programs 622 on the electronic device 60, and can be Windows Server (Microsoft server operating system), Netware (network operating system), Unix (operating system), Linux (operating system), etc. The computer programs 622 can further include computer programs capable of performing other specific work in addition to the computer programs capable of performing the physical layer chip management method executed by the electronic device 60 disclosed in some embodiments.

[0106] Further, some embodiments of the present application further disclose a computer nonvolatile storage medium, which includes Random Access Memory (RAM), memory, Read-Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, magnetic disk or optical disk, or any other form of storage medium known in the technical field. The computer program is executed by the processor to implement the aforementioned physical layer chip management method. The specific steps of the method can refer to the corresponding content disclosed in some embodiments, and will not be described here.

[0107] Further, some embodiments of the present application further provide a computer program product, which includes computer programs / instructions, and the computer programs / instructions are executed by the processor to implement any one of the aforementioned physical layer chip management methods.

[0108] Some embodiments in the specification are described in a progressive manner, and some embodiments mainly explain the differences from other embodiments. The same or similar parts between some embodiments can refer to each other. For the apparatus disclosed in some embodiments, since it corresponds to the method disclosed in some embodiments, the description is relatively simple, and the relevant part can refer to the method part.

[0109] The steps of the physical layer chip management method or algorithm described in combination with some embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the technical field.

[0110] Finally, it needs to be pointed out that in this article, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or equipment including the element.

[0111] The above provides a detailed introduction to a special management network port connection system, a physical layer chip management method, equipment, products and media provided by the present application. In this article, specific examples are applied to explain the principles and implementation modes of the present application. The above description of some embodiments is only used to help understand the method and core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed; in conclusion, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A dedicated management network port connection system, characterized by, The system comprises a security control module board and a main board provided with a first connector, the security control module board is provided with a management device and a first physical layer chip connected with the management device; and the system further comprises: An input / output board installed on the front panel of the server case, the input / output board is provided with a target socket of the special management network port of the management device, a second physical layer chip and a second connector; wherein the first physical layer chip on the security control module board is connected with the second physical layer chip on the input / output board in series through the first connector and the second connector by using a serial communication bus; the first connector and the second connector are connectors supporting preset high-density storage connection; the target socket is a socket capable of generating electromagnetic interference to the security control module board; The management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management buses.

2. The dedicated management network port connection system of claim 1, wherein, The management device on the security control module board is connected with the first physical layer chip through a reduced gigabit media independent interface bus.

3. The dedicated management network port connection system of claim 1, wherein, The first physical layer chip on the security control module board is connected with the second physical layer chip on the input / output board in series through the first connector and the second connector by using a serial gigabit media independent interface bus.

4. The dedicated management network port connection system of claim 1, wherein, The management device on the security control module board controls the first physical layer chip and the second physical layer chip through a plurality of management data input / output buses.

5. The dedicated management network port connection system of claim 1, wherein, The management device is configured to control the transmission rate of the first physical layer chip and the second physical layer chip.

6. The dedicated management network port connection system of claim 5, wherein, The management device is configured to set the first physical layer chip and the second physical layer chip to a rate self-matching mode by using the management bus to realize control of the transmission rate.

7. The dedicated management network port connection system of claim 5, wherein, The management device is configured to obtain the transmission rate setting parameter of the second physical layer chip, and set the transmission rate setting parameter as the transmission rate of the first physical layer chip by using the management bus to realize control of the transmission rate.

8. The dedicated management network interface connection system of claim 1, wherein, The first connector and the second connector are connected through a serial connection SCSI interface.

9. The private management network interface system of claim 1, wherein, The management device on the security control module board accesses the management registers of the first physical layer chip and the second physical layer chip through a plurality of management data input / output buses to monitor the states of the first physical layer chip and the second physical layer chip.

10. The dedicated management network port connection system of claim 1, wherein, The second physical layer chip is connected with the target socket; the first physical layer chip is a transit chip.

11. The dedicated management network port connection system of claim 1, wherein, The media access control sublayer protocol is bound with the second physical layer chip, and the media access control layer is not bound with the first physical layer chip.

12. The dedicated management network port connection system of claim 1, wherein, The management device on the security control module board initializes the configuration of the second connector and the second physical layer chip through a management data input / output bus.

13. The dedicated management network interface connection system according to any of claims 1 to 12, characterized in that, The management device is connected with the first physical layer chip by using a first management bus, and is connected with the second physical layer chip by using a second management bus and sequentially through the first connector and the second connector; wherein the first management bus and the second management bus are connected based on a multifunctional single board multiplexing resistor; A first target position is reserved without resistor based on the multifunctional single board multiplexing resistor, so that a link between the management device and the second physical layer chip is in a disconnected state; wherein when the physical layer chips are controlled, the management device sends a first control command to the first physical layer chip through the first management bus, and sends a second control command to the second physical layer chip through the first management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip respectively based on different control commands through one management bus.

14. The dedicated management network interface connection system according to any of claims 1 to 12, characterized in that, The management device is connected with the first physical layer chip by using a third management bus, and is connected with the second physical layer chip by using a fourth management bus and sequentially through the first connector and the second connector; wherein the third management bus and the fourth management bus are connected based on a multifunctional single board multiplexing resistor; A second target position is reserved without resistor based on the multifunctional single board multiplexing resistor, so that a link between the management device and the second physical layer chip is in a connected state; wherein when the physical layer chips are controlled, the management device sends a third control command to the first physical layer chip through the third management bus, and sends a fourth control command to the second physical layer chip through the fourth management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip respectively based on different control commands through two management buses.

15. The dedicated management network interface connection system according to any of claims 1 to 12, characterized in that, The management device is connected with the first physical layer chip by using a fifth management bus; The first physical layer chip is connected with the second physical layer chip by using the fifth management bus and sequentially through the first connector and the second connector; wherein when the physical layer chips are controlled, the management device sends a fifth control command to the first physical layer chip through the fifth management bus, and the first physical layer chip sends the fifth control command to the second physical layer chip through the fifth management bus, so as to realize that the management device controls the first physical layer chip and the second physical layer chip based on the same control command.

16. The dedicated management network port connection system of any of claims 1 to 12, wherein, The first physical layer chip is connected with the second physical layer chip through the sixth management bus, the first connector and the second connector in sequence, and the management device is connected with the first connector through a seventh management bus; wherein, when controlling the physical layer chips, the management device sends a sixth control command to the second physical layer chip through the seventh management bus, and the second physical layer chip sends the sixth control command to the first physical layer chip through the sixth management bus, so as to realize the control of the first physical layer chip and the second physical layer chip by the management device based on the same control command.

17. A physical layer chip management method, comprising: The application is applied to the special management network port connection system as claimed in any one of claims 1 to 16; wherein, the method comprises: determining a control link between a management device on a security control module board of the special management network port connection system and each physical layer chip in the server; the control link is a communication link created between the management device and each physical layer chip based on a plurality of management buses, and the each physical layer chip includes a first physical layer chip on the security control module board and a second physical layer chip on an input / output board in the special management network port connection system; sending a control command to the first physical layer chip and the second physical layer chip through the management device and using the control link, so as to realize the control of the first physical layer chip and the second physical layer chip.

18. An electronic device, comprising: comprise: a memory configured to store a computer program; a processor configured to load and execute the computer program to realize the physical layer chip management method as claimed in claim 17.

19. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to realize the steps of the physical layer chip management method as claimed in claim 17.

20. A computer non-volatile storage medium, characterized by configured to store a computer program; wherein the computer program is executed by the processor to realize the physical layer chip management method as claimed in claim 17.

Images