Computer system, signal processing method, device, medium and product

Abstract

The present application relates to the technical field of computers. Provided are a computer system, a signal processing method, a device, a medium and a product. The system comprises a target main control board, a pull-up circuit, a first logic controller, an image processing module and a switch module, wherein the pull-up circuit is connected to a target general-purpose input / output port in the target main control board, and the pull-up circuit is used for generating a corresponding port signal on the basis of a port state of the target general-purpose input / output port; and the first logic controller is connected to the target main control board, the pull-up circuit, the image processing module and the switch module, and the first logic controller is used for: on the basis of the port signal transmitted by the pull-up circuit, acquiring a platform type corresponding to the target main control board, and on the basis of the platform type and a target reset signal transmitted by the target main control board, executing a corresponding reset control operation for the image processing module and the switch module. The present application reduces the development cost and adapts to compatibility requirements of different chip combinations.

Description

Computer system, signal processing method, device, medium and product

[0001] Cross-reference to related applications

[0002] This application claims priority to the Chinese patent application No. 202411357320.2, filed on September 27, 2024, and entitled "Computer system, signal processing method, device, medium and product", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of computer, and in particular, to a computer system, a signal processing method, a device, a medium and a product. BACKGROUND

[0004] With the rapid development of cloud computing, big data and artificial intelligence technologies, the performance, stability and compatibility requirements of computer systems as the core support platform of these technologies are increasingly improving. When users build computer systems, they often choose different manufacturers of central processing units (CPUs), peripheral component interconnect express switch (PCIE Switch) chips and graphics processing units (GPUs) for flexible collocation based on diversified application scenarios and cost-benefit considerations to achieve efficient signal processing.

[0005] However, due to the design differences of different CPU manufacturers, PCIE Switch chip manufacturers and GPU manufacturers in the initialization efficiency, initialization process and global reset function of PCIE controllers based on the Peripheral Component Interconnect Express (PCIE) protocol specification, compatibility problems may occur when these chips or components from different manufacturers are combined together.

[0006] For downstream computer system manufacturers, such compatibility problems increase the complexity and uncertainty of product development. In order to solve these problems, some manufacturers have to adopt multiple sets of system logic control boards or customized firmware to adapt to the compatibility requirements of different chip combinations. However, this one-to-one development configuration for chips or components from different manufacturers increases the development cost. SUMMARY

[0007] The application provides a computer system, a signal processing method, equipment, a medium and a product, to solve the defects of increasing development cost caused by configuring multiple sets of system boards or customized firmware to adapt to the compatibility requirements of different chip combinations, and to realize adapting to the compatibility requirements of different chip combinations while reducing development cost.

[0008] The application provides a computer system, comprising:

[0009] A target main control board;

[0010] A pull-up circuit, the pull-up circuit being connected with a target general-purpose input / output port in the target main control board, and the pull-up circuit being used for generating a corresponding port signal according to a port state of the target general-purpose input / output port;

[0011] A first logic controller, an image processing module and a switching module, the first logic controller being connected with the target main control board, the pull-up circuit, the image processing module and the switching module, the first logic controller being used for receiving the port signal transmitted by the pull-up circuit, acquiring a platform type corresponding to the target main control board according to the port signal, and performing a corresponding reset control operation on the image processing module and the switching module according to the platform type and a target reset signal transmitted by the target main control board.

[0012] According to the computer system provided by the application, the first logic controller is further used for:

[0013] Judging whether the platform type is a first platform type;

[0014] In a case where the platform type is the first platform type, acquiring a current reset task required to be executed by the first logic controller according to level change information of the target reset signal;

[0015] Performing a corresponding reset control operation on the image processing module and the switching module according to time sequence signal change information of the current reset task.

[0016] According to the computer system provided by the application, the first logic controller is further used for:

[0017] According to the level change information of the target reset signal, judging whether a falling edge of the target reset signal is detected, to obtain a first judgment result;

[0018] According to the first judgment result, acquiring the current reset task required to be executed by the first logic controller.

[0019] According to the computer system provided by the application, the first logic controller is further used for:

[0020] In a case where it is known from the first judgment result that the falling edge of the target reset signal is detected, determining that the current reset task is a cold reset task or a hot reset task.

[0021] In a case where it is learned from the first judgment result that the falling edge of the target reset signal is not detected, the current reset task is determined as the AC-DC power cycle task.

[0022] According to the computer system provided in the application, the first logic controller is further configured to:

[0023] In a case where it is learned that the current reset task is the cold reset task or the hot reset task, a first target delay time is obtained according to the timing signal change information of the cold reset task or the hot reset task;

[0024] After delaying for the first target delay time, the reset signals at the input ends of the image processing module and the switching module are pulled high, and the image processing module and the switching module are de-reset according to the reset signals after the pulling high.

[0025] According to the computer system provided in the application, the first logic controller is further configured to:

[0026] In a case where it is learned that the current reset task is the AC-DC power cycle task, a second judgment result is obtained by judging whether the target indication signal of the last power is detected; the target indication signal is used to indicate that the power is in a normal operation state;

[0027] According to the second judgment result and the timing signal change information of the AC-DC power cycle task, corresponding reset control operations are performed on the image processing module and the switching module.

[0028] According to the computer system provided in the application, the first logic controller is further configured to:

[0029] In a case where it is learned from the second judgment result that the target indication signal of the last power is not detected, the step of judging whether the target indication signal of the last power is detected is returned to until it is learned that the target indication signal of the last power is detected.

[0030] According to the computer system provided in the application, the first logic controller is further configured to:

[0031] In a case where it is learned from the second judgment result that the target indication signal of the last power is detected, a second target delay time is obtained according to the timing signal change information of the AC-DC power cycle task;

[0032] After delaying for the second target delay time, the reset signals at the input ends of the image processing module and the switching module are pulled high, and the image processing module and the switching module are de-reset according to the reset signals after the pulling high.

[0033] According to the computer system provided in the application, the switching module is connected with the central processing unit and the image processing module in the target main control board;

[0034] The switching module is used for performing high-speed serial computer expansion bus link training with the central processing unit and the image processing module in the target main control board, in the case that the image processing module and the switching module respectively complete the execution of the corresponding de-reset operation.

[0035] According to the computer system provided in the application, the first logic controller is further used for:

[0036] In the case that the high-speed serial computer expansion bus link training between the switching module and the central processing unit and the image processing module in the target main control board is determined to be completed, the step of returning to the step of judging whether the platform type is the first platform type is performed, and the next reset task is executed.

[0037] According to the computer system provided in the application, the first logic controller is further used for:

[0038] The level corresponding to the port signal is matched with the preset level corresponding to the general input and output port in the main control board of each preset platform type;

[0039] According to the matching result, the preset level matched with the level corresponding to the port signal is obtained;

[0040] According to the preset platform type corresponding to the matched preset level, the platform type corresponding to the target main control board is obtained.

[0041] According to the computer system provided in the application, the pull-up circuit comprises a pull-up resistor and a pull-up power supply;

[0042] The first end of the pull-up resistor is connected with the pull-up power supply, the second end of the pull-up resistor is connected with the target general input and output port, and the third end of the pull-up resistor is connected with the first logic controller.

[0043] According to the computer system provided in the application, in the case that the target main control board is the first platform type, the target main control board comprises a plurality of central processing units and a second logic controller;

[0044] The plurality of central processing units are connected through an interconnection interface;

[0045] At least one central processing unit is connected with the second logic controller, and the second logic controller is connected with the first logic controller.

[0046] According to the computer system provided in the application, in the case that the platform type is the first platform type, the target reset signal is a global reset signal emitted by at least one central processing unit of the target main control board through the second logic controller of the target main control board.

[0047] According to the computer system provided in the application, when the target main control board is of the second platform type, the target main control board comprises a plurality of central processing units, a south bridge chip and a second logic controller;

[0048] The plurality of central processing units are connected through an interconnection interface;

[0049] At least one of the central processing units is connected with the south bridge chip, the south bridge chip is connected with the second logic controller, and the second logic controller is connected with the first logic controller.

[0050] According to the computer system provided in the application, when the platform type is the second platform type, the target reset signal is a global reset signal emitted by at least one of the central processing units of the target main control board in sequence through the south bridge chip and the second logic controller.

[0051] The application further provides a signal processing method, the method being applied to any one of the computer systems, and the method comprising:

[0052] According to the port signal transmitted by the pull-up circuit, the platform type corresponding to the target main control board is acquired; the port signal is generated by the pull-up circuit according to the port state of a target general-purpose input / output port in the target main control board;

[0053] According to the platform type and the target reset signal transmitted by the target main control board, corresponding reset control operations are performed on the image processing module and the switching module.

[0054] The application further provides an electronic device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements any one of the signal processing methods when executing the program.

[0055] The application further provides a non-volatile computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement any one of the signal processing methods.

[0056] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement any one of the signal processing methods.

[0057] The computer system, signal processing method, device, medium and product provided by the application realize the compatibility requirement of a set of universal architecture for a plurality of platform type main control board combinations by real-time monitoring of the port state of the general input and output port of the target main control board by the pull-up circuit, generating and transmitting corresponding port signals to the first logic controller, so that the first logic controller quickly identifies the platform type of the target main control board according to the signals, and flexibly adjusts the reset control operation of the image processing module and the switching module according to the target reset signal from the target main control board, thereby eliminating the PCIE compatibility problems of different platform CPUs matched with different platform PCIE switch chips and different manufacturer GPU modules, simplifying the compatibility processing flow of diversified chip combinations, avoiding the high development cost of traditional multiple system logic control boards or customized firmware, and significantly improving the stability and reliability of the computer system under different hardware combinations, thereby effectively reducing the complexity and uncertainty of product development, and providing a more efficient and economical solution for downstream computer system manufacturers. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0059] Fig. 1 is a structural schematic diagram of a computer system provided by the application.

[0060] Fig. 2 is a structural schematic diagram of a computer system provided by the application.

[0061] Fig. 3 is a structural schematic diagram of a computer system provided by the application.

[0062] Fig. 4 is a timing signal change diagram corresponding to an AC-DC power supply cycle task provided by the application.

[0063] Fig. 5 is a timing signal change diagram corresponding to a hot reset task provided by the application.

[0064] Fig. 6 is a timing signal change diagram corresponding to a cold reset task provided by the application.

[0065] Fig. 7 is a flowchart of a signal processing step provided by the application.

[0066] Fig. 8 is a flowchart of a signal processing method provided by the application.

[0067] Fig. 9 is a structural schematic diagram of an electronic device provided by the present application.

[0068] Reference signs: 10: switching board; 11: first logic controller; 12: image processing module; 13: switching module; 20: pull-up circuit; 30: target main control board. DETAILED DESCRIPTION

[0069] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the accompanying drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present application.

[0070] The computer system provided by the embodiments of the present application can be an artificial intelligence server, a data center device, etc., which is not specifically limited in the embodiments of the present application, and the following will be described taking the computer system as an artificial intelligence server as an example.

[0071] In recent years, as an important hardware basis for the development of artificial intelligence technology, the development trend of artificial intelligence (AI) servers mainly has the following aspects: 1. Market demand growth: With the wide application of artificial intelligence technology, especially in natural language processing, image recognition, autonomous driving and other fields, the market demand for AI servers continues to grow. Due to the powerful computing and storage capabilities of AI servers, they can handle massive data and complex algorithms, and AI servers use efficient cooling design and energy-saving technology to effectively ensure stable operation under high load and reduce energy consumption. In addition, AI servers support multiple AI frameworks and algorithm libraries, making it easy for users to quickly build AI applications. Therefore, the market size of AI servers continues to expand, with a high annual compound growth rate. 2. Technological progress: AI servers need to handle massive data and complex algorithms, so they have high requirements for computing power, storage capacity and energy efficiency. With the progress of chip technology, heterogeneous computing and other technologies, the performance of AI servers continues to improve. 3. Industry chain development: The upstream of the AI server industry chain includes chips, printed circuit boards (PCB), etc., the midstream includes server brand manufacturers and original equipment manufacturers (OEM) or original design manufacturers (ODM), and the downstream is Internet vendors, cloud service providers, etc. The perfection and development of the industry chain will promote the maturity of the AI server market. 4. Application expansion: The application scenarios of AI servers are expanding from centralized AI services to edge AI services, and the development of AI personal computers (PCs) and other terminal devices driven by AI server infrastructure, which will bring new growth points to the AI server market. 5. Market participants competition: There are many designers and manufacturers of AI servers, which have significant advantages in market share, technological innovation, etc. By continuously launching high-performance AI chips and system integration solutions, they can promote the development of the market. 6. Green computing: With the popularization of the concept of sustainable development, AI servers pay more and more attention to energy efficiency in design. By optimizing algorithms and hardware design, energy consumption can be reduced and resource utilization efficiency can be improved, thereby promoting the development of green computing.

[0072] Based on the above market background and development trend, when users build a computer system, they often choose different manufacturers' CPUs to match different manufacturers' PCIE Switch chips based on diverse application scenarios and cost-effectiveness considerations, and then mount different manufacturers' GPU configurations under the PCIE Switch chip. For example, an Intel / AMD / NVDIA CPU is matched with a PCIE Switch chip from a supplier such as Broadcom / Microchip, and the PCIE Switch chip is then mounted with a GPU configuration from a platform such as NVDIA.

[0073] However, under the premise of complying with the PCIE protocol specification, different CPU manufacturers or PCIE Switch chip manufacturers or GPU manufacturers run different PCIE design topologies under different PCIE Switch chips, combined with the differences in the characteristics of the uplink CPU platform PCIE controller and the time difference of the global Reset issued by different CPU platforms or the differences in the CPU's own initialization process, so that each chip manufacturer will have differences in the initialization efficiency, initialization process, and global Reset (or Reset) functions of the PCIE controller.

[0074] Therefore, after different functional chips or component manufacturers are matched together, there will be compatibility problems such as card loss, loss of PCIe Switch key components, and reduction of PCIe bus bandwidth. This problem brings certain challenges to downstream server system solution manufacturers. Further, in order to solve these problems, some manufacturers have to adopt multiple sets of system logic control boards, such as Complex Programmable Logic Device (CPLD), or customized Firmware (FW), such as Basic Input Output System Firmware (BIOS) FW, to adapt to the compatibility requirements of different chip combinations. However, this one-to-one development and configuration method for different manufacturers' chips or components increases the development cost. For example, in order to solve the compatibility problems such as card loss, loss of Switch, and reduction of PCIe bus bandwidth caused by the combination of two different platform CPUs with the same manufacturer's PCIE Switch and GPU, two sets of PCIE exchange boards are needed to adapt to different platform CPUs, so that different processing methods are adopted for the global Reset from different platform CPUs, thereby increasing the development and design cost of the server.

[0075] To solve the compatibility problem and the high development and design cost in the prior art, the embodiments of the present application provide a computer system supporting homology and non-homology, which only needs to be designed by a set of universal architecture combined with corresponding logic code design, so as to eliminate the compatibility problem of different CPU platforms matching different PCIE Switch chips and GPU components, thereby realizing low-cost solution to compatibility problems such as card loss, switch loss and PCIE bus bandwidth reduction through a simple and flexible architecture.

[0076] FIG. 1 is a structural schematic diagram of a computer system provided by the present application; as shown in FIG. 1, the system comprises a pull-up circuit 20, a first logic controller 11, an image processing module 12, a switching module 13 and a target main control board 30. The first logic controller 11, the image processing module 12 and the switching module 13 can be configured in a switching board 10, which can be a PCIE switching board (or PCIE Switch board).

[0077] The pull-up circuit 20 can be implemented by a low-power logic gate circuit or a dedicated interface chip, which is used to output different port signals according to the port state of the target general input / output port of the main control board of different platform types, so as to identify the platform type information of the different main control boards.

[0078] The first logic controller here is a controller that can be used to implement various logic controls, such as a Field-Programmable Gate Array (FPGA), etc., which is not specifically limited in the embodiments, and the following will be described by taking the first logic controller as an FPGA as an example.

[0079] The image processing module 12 here comprises a plurality of image processors, such as 10 image processors including GPU0 to GPU9.

[0080] The switching module 13 here comprises a plurality of PCIE switching chips (or switching chips, or PCIE Switch chips), such as PCIE switching chip A (or PCIE Switch chip A) and PCIE switching chip B (or PCIE Switch chip B).

[0081] The pull-up circuit is connected with the target general input / output port in the target main control board, and the pull-up circuit is used to generate corresponding port signals according to the port state of the target general input / output port.

[0082] Optionally, the input end of the pull-up circuit 20 is connected with a target general-purpose input / output port of a target CPU (such as CPU0) in the target main control board 30, and the output end of the pull-up circuit 20 is connected with the first logic controller 11. The specific connection mode can be adaptively determined according to the topology of the pull-up circuit.

[0083] For example, in some embodiments, the pull-up circuit 20 includes a pull-up resistor and a pull-up power supply; the first end of the pull-up resistor is connected with the pull-up power supply, the second end of the pull-up resistor is connected with the target general-purpose input / output port, and the third end of the pull-up resistor is connected with the first logic controller.

[0084] As shown in FIG. 1, the pull-up circuit includes a pull-up resistor and a pull-up power supply (or referred to as Resistor). In some embodiments, the pull-up power supply here can be a 3.3-volt power supply (or referred to as P3V3_STBY). The first end of the pull-up resistor is connected to the pull-up power supply, the second end of the pull-up resistor is connected to the target general-purpose input / output port of the target CPU (such as CPU0) in the target main control board, and the third end of the pull-up resistor is connected to the input pin of the first logic controller, so as to provide a stable reference voltage for the first logic controller, which helps to ensure the integrity and reliability of the signal. When the first logic controller receives the port state information output from the target general-purpose input / output port (GPIO) through the pull-up resistor and outputs the corresponding port signal, the first logic controller can accurately identify the platform type of the target main control board according to the resistance voltage division principle, so as to provide a basis for subsequent execution of different signal processing logics for different platforms.

[0085] The default port state of the target GPIO in the target main control board in the CPU inside the platform type to which it belongs is different from the default port state of the GPIO in the main control board of other platform types. For example, the default port state of the GPIO in the CPU inside the main control board of a platform type is a pull-down state, the default port state of the GPIO in the CPU inside the main control board of another platform type is a pull-up state or a suspended state.

[0086] Optionally, the pull-up circuit can obtain the port state of the target GPIO of the target main control board, and generate a corresponding port signal (or CPU_Detect signal) according to the port state of the target GPIO, and transmit the generated port signal to the first logic controller through a connection path between the pull-up circuit and the first logic controller, so that the first logic controller identifies the platform type to which the target main control board belongs according to the corresponding port signal, and calls the logic code corresponding to the platform type to implement corresponding logic signal processing, thereby realizing the compatibility of different CPU platforms with different PCIE switch chips and GPU components through a set of universal architecture, thereby reducing development cost.

[0087] The first logic controller is connected with the target main control board, the pull-up circuit, the image processing module and the switching module. The first logic controller is configured to receive the port signal transmitted by the pull-up circuit, obtain the platform type corresponding to the target main control board according to the port signal, and perform corresponding reset control operation on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board.

[0088] Optionally, the target main control board can include multiple CPUs, such as CPU0 and CPU1.

[0089] The first logic controller is connected with the target main control board, the pull-up circuit, the image processing module and the switching module. The first logic controller is configured to receive the port signal transmitted by the pull-up circuit, obtain the platform type corresponding to the target main control board according to the port signal, and perform corresponding reset control operation on the image processing module and the switching module according to the platform type and the target reset signal transmitted by the target main control board.

[0090] Exemplarily, as shown in FIG. 1, when the first logic controller is FPGA1, the image processing module includes GPU0-GPU9, the switching module includes PCIE switching chip A and PCIE switching chip B, and the target main control board contains CPU0 and CPU1, FPGA1 can be connected with 10 image processors including GPU0-GPU9, and FPGA1 can be connected with the control port S6 in PCIE switching chip A; GPU0 can be connected with the control port S1 in PCIE switching chip A through a PCIE link, GPU1 can be connected with the control port S2 in PCIE switching chip A through a PCIE link, GPU2 can be connected with the control port S5 in PCIE switching chip A through a PCIE link, GPU3 can be connected with the control port S7 in PCIE switching chip A through a PCIE link, GPU4 can be connected with the control port S8 in PCIE switching chip A through a PCIE link, GPU5 can be connected with the control port S1 in PCIE switching chip B through a PCIE link, GPU6 can be connected with the control port S5 in PCIE switching chip B through a PCIE link, GPU7 can be connected with the control port S6 in PCIE switching chip B through a PCIE link, GPU8 can be connected with the control port S7 in PCIE switching chip B through a PCIE link, GPU9 can be connected with the control port S8 in PCIE switching chip B through a PCIE link, and the control port S0 in PCIE switching chip A can be connected with CPU0 through a PCIE link, and the control port S0 in PCIE switching chip B can be connected with CPU1 through a PCIE link.

[0091] It should be noted that, since the customer has different requirements for the size of the case and the number of GPUs matched, the number of PCIE switching chips in the switching module can be set according to specific requirements, such as 2 PCIE switching chips, or 4 PCIE switching chips, etc.; similarly, the number of GPUs in the image processing module can also be set according to specific requirements, such as 10 GPUs, or more GPUs; in addition, due to the difference in the size of the case, the shape of the PCIE switching chip will be different, and due to the requirements of PCIE wiring and signal integrity (SI) parameters during PCB design, the resource allocation of S0 / S1 / S5 / S6 / S7 / S8 of each PCIE switching chip, i.e., the design topology, may be different, such as the control port S0 of PCIE switching chip A being connected with CPU0, and the control port S0 of PCIE switching chip B being connected with CPU1, i.e., the design topology of 2 or 4 PCIE switching chips on the same PCIE switching board may be inconsistent, in order to reduce the manufacturing cost, the FW of 2 or 4 PCIE switching chips on the same PCIE switching board can be configured in the same way.

[0092] Optionally, in the signal processing process, the first logic controller can identify the corresponding platform type of the target main control board connected to the switching board in uplink according to the port signal received by the pull-up circuit.

[0093] The corresponding platform type of the target main control board here can be achieved by the first logic controller according to the logical judgment of the port signal, or can be obtained by inputting the port signal into a recognition model obtained by supervised training with a sample port signal as a sample and a sample platform type label as a label, and the embodiment does not make specific limitation thereto.

[0094] Exemplarily, in some embodiments, the first logic controller can specifically perform the following steps for platform type identification:

[0095] matching the level grade corresponding to the port signal with the preset level grade corresponding to the general input and output port in the main control board of each preset platform type;

[0096] obtaining the preset level grade matched with the level grade corresponding to the port signal according to the matching result;

[0097] obtaining the platform type corresponding to the target main control board according to the preset platform type corresponding to the matched preset level grade.

[0098] Optionally, the first logic controller can perform the following steps to achieve the identification of the platform type corresponding to the target main control board:

[0099] The first logic controller can read the port signal sent by the pull-up circuit and determine the level grade corresponding to the port signal. Then, the corresponding relationship table of the preset level grade corresponding to the general input and output port in the main control board of different platform types is traversed, and the level grade corresponding to the port signal is compared with the preset level grade corresponding to the general input and output port in the main control board of each preset platform type in the corresponding relationship table to find the matching item. Once the matching level grade is found, the platform type of the target main control board can be determined according to the preset platform type corresponding to the matching level grade, so as to efficiently and accurately identify the platform type of the target main control board connected to the switching board in uplink, thereby facilitating to improve the compatibility and flexible configuration of the main control boards of different platform types, and further improving the scalability and ease of use of the computer system.

[0100] For example, it is assumed that the preset level corresponding to the general input and output port in the main control board of the first platform type is the first level (such as high level), and the preset level corresponding to the general input and output port in the main control board of the second platform type is the second level (such as low level). Thus, when the CPU_Detect signal obtained from the pull-up circuit is a high level signal (or H signal), it is determined that the target main control board connected by the exchange board is of the first platform type, and when the CPU_Detect signal obtained from the pull-up circuit is a low level signal (or L signal), it is determined that the target main control board connected by the exchange board is of the second platform type, so that the exchange board can accurately identify the platform type of the main control board connected by the exchange board by the high and low levels of the CPU_Detect signal transmitted by the pull-up circuit when connecting the main control boards of different platform types.

[0101] Optionally, after obtaining the corresponding platform type of the target main control board connected by the exchange board, the first logic controller can obtain the target reset signal transmitted by the target main control board in real time.

[0102] The target reset signal herein is transmitted to the first logic controller by the target main control board according to the transmission path corresponding to the topology of the platform type.

[0103] Fig. 2 is a second structural schematic diagram of the computer system provided by the present application.

[0104] Exemplarily, as shown in FIG. 2, in the case where the target main control board is of the first platform type, the target main control board comprises a plurality of central processing units and a second logic controller; the plurality of central processing units are connected through an interconnection interface; at least one of the central processing units is connected with the second logic controller, and the second logic controller is connected with the first logic controller; and a target general input / output port in the at least one central processing unit is connected with the pull-up circuit. For example, assuming that, in the first platform type, the target main control board contains CPU0 and CPU1 as the CPUs, and contains FPGA0 as the second logic controller; wherein, the CPU0 and the CPU1 are interconnected through an interconnection interface, such as a 10Gigabit Media Independent Interface (XGMII), to meet the data interaction requirement between the two different CPUs. The CPU0 is connected with the second logic controller (i.e., FPGA0). The second logic controller is connected with the first logic controller. Accordingly, in the case where the platform type is the first platform type, the target reset signal is a global reset signal sent by at least one central processing unit of the target main control board through the second logic controller of the target main control board, i.e., in the reset task processing flow, the target main control board under the first platform type first sends a global reset signal to the second logic controller through a target central processing unit (such as CPU0), and then the second logic controller sends the global reset signal to the first logic controller, thereby realizing the transmission of the target reset signal.

[0105] FIG. 3 is a third structural schematic diagram of a computer system provided by the present application.

[0106] Exemplarily, as shown in FIG. 3, in the case where the target main control board is of the second platform type, the target main control board comprises a plurality of central processing units, a south bridge chip and a second logic controller; the plurality of central processing units are connected through an interconnection interface; at least one of the central processing units is connected with the south bridge chip, the south bridge chip is connected with the second logic controller, and the second logic controller is connected with the first logic controller; and a target general input / output port in the at least one of the central processing units is connected with the pull-up circuit. For example, it is assumed that, in the second platform type, the target main control board contains a CPU0 and a CPU1 as the CPUs, and contains an FPGA0 as the second logic controller, wherein the CPU0 and the CPU1 are interconnected through a high-speed bus of an interconnection interface such as an Ultra Path Interconnect (UPI) to meet the data interaction requirement between the two different CPUs. The CPU0 is connected with a south bridge chip such as a Platform Controller Hub (PCH) through a Direct Media Interface (DMI) bus; the south bridge chip is connected with the second logic controller (i.e., the FPGA0), and the second logic controller is connected with the first logic controller. Accordingly, in the case where the platform type is the second platform type, the target reset signal is a global reset signal emitted by the at least one central processing unit of the target main control board in sequence through the south bridge chip and the second logic controller, i.e., in the reset task processing flow, the target main control board of the second platform type first emits the global reset signal to the south bridge chip through the target central processing unit (e.g., the CPU0), the south bridge chip then issues the global reset signal to the second logic controller, and the second logic controller then issues the global reset signal to the first logic controller, thereby realizing the transmission of the target reset signal.

[0107] Optionally, after the target reset signal transmitted by the target main control board is acquired, the first logic controller can call a corresponding signal processing logic according to the target reset signal and the platform type transmitted by the target main control board, to perform a corresponding reset control operation on the image processing module and the switching module.

[0108] The system provided by the embodiment integrates the pull-up circuit, the first logic controller, the image processing module and the switching module, uses the pull-up circuit to monitor the port state of the general input and output port of the target main control panel in real time, generates and transmits corresponding port signals to the first logic controller, so that the first logic controller can quickly identify the platform type of the target main control panel according to the signals, and flexibly adjust the reset control operation on the image processing module and the switching module according to the target reset signal from the target main control panel. Thus, the compatibility requirement of the main control panel combination of multiple platform types can be met through a set of general architecture, so as to eliminate the PCIE compatibility problems of the CPU of different platforms matched with the PCIE switch chip of different platforms and the GPU module of different manufacturers. Not only is the compatibility processing flow of diversified chip combinations simplified, and the high development cost of traditional multiple system logic control panels or customized firmware is avoided, but also the stability and reliability of the computer system under different hardware combinations are significantly improved, thereby effectively reducing the complexity and uncertainty of product development, and providing a more efficient and economical solution for downstream computer system manufacturers.

[0109] In order to more clearly describe the processing logic of the interaction board when performing different reset tasks, the timing signal change diagram corresponding to different reset tasks is described here.

[0110] FIG. 4 is a timing signal change diagram corresponding to an AC / DC cycle task provided by the present application. As shown in FIG. 4, for the AC / DC cycle task, after the power (or Power) is turned on (that is, the rising edge of the power signal appears), the 100Mhz clock appears next. After the 100Mhz clock is stable, the reset signal (or Reset signal) is pulled high. That is, from the rising edge of the power signal to the rising edge of the reset signal is the boot action performed by the hardware when the AC / DC cycle task is performed for the first time. Next, the shutdown action is performed, that is, from the falling edge of the reset signal, the 100Mhz clock is pulled low and invalid, and then the falling edge of the power signal appears. After a period of time, the rising edge of the power signal appears. From the rising edge of the power signal to the rising edge of the reset signal is the cold restart action performed by the hardware again. Thus, the AC / DC power reset task of one cycle is completed.

[0111] FIG. 5 is a timing signal change diagram corresponding to a warm reset task provided by the present application. As shown in FIG. 5, for the warm reset task (or Warm Reset task), the difference from the timing signal change diagram of the AC cycle task shown in FIG. 4 is that the power signal does not appear the falling edge when the warm reset task is performed, and the 100Mhz clock is continuously output during the execution of the warm reset task and does not become invalid.

[0112] FIG. 6 is a timing signal change diagram corresponding to a cold reset task provided by the present application. As shown in FIG. 6, for the cold reset task (or Cold Reset task), compared with the Warm Reset task shown in FIG. 5, there is a process of pulling down the 100Mhz Clock to make the clock invalid and then output the valid clock when the Cold Reset task is executed.

[0113] In some embodiments, the first logic controller is further configured to:

[0114] determine whether the platform type is a first platform type;

[0115] in a case where the platform type is the first platform type, obtain, according to the level change information of the target reset signal, a current reset task required to be executed by the first logic controller;

[0116] perform, according to the timing signal change information of the current reset task, a corresponding reset control operation on the image processing module and the switching module.

[0117] Optionally, the first logic controller can perform the following steps to implement the reset control:

[0118] The first logic controller first determines whether the platform type of the target main control board is the first platform type according to the port signal generated by the pull-up circuit according to the port state of the target general input / output port of the target main control board. In some embodiments, the first platform type here can be an AMD platform type.

[0119] When it is determined that the platform type of the target main control board is not the first platform type but a second platform type, it is indicated that the target main control board matched with the switching board is loaded with a CPU of the second platform type. At this time, the reset control strategy can be dynamically adjusted according to the signal processing logic corresponding to the second platform type, so as to ensure that the system under different chip combinations can be initialized smoothly and run stably. The signal processing logic corresponding to the second platform type is as follows:

[0120] The first logic controller executes hardware startup actions according to a normal timing sequence. The timing sequence can be a startup action corresponding to an AC / DC Cycle task, a startup action corresponding to a Warm Reset task, or a startup action corresponding to a Cold Reset task. After the startup sequence is executed, each switch chip (such as PCIE switch chip A and PCIE switch chip B) in the switch module respectively performs high-speed serial computer expansion bus link training (or PCIE Link Training) with each CPU (such as CPU0 and CPU1) in the target main control board and each GPU (such as GPU0-GPU9) in the image processing module. After the training is completed, the next startup action corresponding to the AC / DC Cycle task, the startup action corresponding to the Warm Reset task, the startup action corresponding to the Cold Reset task, or a direct end signal processing sequence can be executed.

[0121] When it is determined that the platform type of the target main control board is the first platform type, it is indicated that the target main control board matched with the switch board is loaded with a CPU of the first platform type. At this time, the reset control strategy can be dynamically adjusted according to the signal processing logic corresponding to the first platform type, so as to ensure that the system under different chip combinations can be successfully initialized and stably operated. The signal processing logic corresponding to the first platform type is as follows:

[0122] The first logic controller pushes up the power supply of the switch board according to the power-on timing sequence, and identifies the reset task currently required to be executed by the first logic controller, that is, the current reset task, by using the received level change information of the target reset signal. Different reset tasks correspond to different level change information. Specifically, the correspondence between different reset tasks and different level change information can be determined according to the timing signal change information corresponding to different reset tasks.

[0123] Then, the first logic controller executes corresponding reset control operations on each GPU in the image processing module and each PCIE switch chip in the switch module according to the timing signal change information of the current reset task. In this way, by dynamically adjusting the timing and parameters of the reset operation, it is ensured that all components can complete the initialization process in the correct order and state, thereby avoiding system abnormalities caused by compatibility problems, on the basis of fully considering the differences in initialization efficiency, process, and global reset function of different chips or components.

[0124] The timing signal change information includes, but is not limited to, power signal timing change information, clock signal timing change information, and reset signal timing change information, which are not specifically limited in the present embodiment.

[0125] In some embodiments, the implementation of the reset control operation can be that the multi-dimensional timing signal change information of the current reset task is subjected to multiple logical judgments or model prediction to obtain a corresponding reset control strategy, and then the corresponding reset control process is performed on the image processing module and the switching module at the corresponding reset operation trigger time based on the corresponding reset control strategy, so that the reset control operation on the image processing module and the switching module is realized. The reset control strategy herein includes but is not limited to the reset operation process and the reset operation trigger time, which are not specifically limited in the embodiment.

[0126] The system provided by the embodiment intelligently judges the platform type by integrating the first logic controller, dynamically adjusts the reset control strategy according to the platform characteristics, and solves the compatibility problem caused by the design differences of different CPUs, PCIE switch chips and GPU manufacturers by configuring a set of general architecture and corresponding logic controller processing logic, thereby reducing the development cost, improving the product universality and stability, and avoiding the complexity and uncertainty brought by the traditional multiple system logic control boards or customized firmware.

[0127] In some embodiments, the first logic controller is further configured to:

[0128] determine whether a falling edge of the target reset signal is detected according to the level change information of the target reset signal, and obtain a first judgment result;

[0129] obtain a current reset task to be executed by the first logic controller according to the first judgment result.

[0130] Optionally, the first logic controller can implement the identification of the current reset task by performing the following steps:

[0131] The first logic controller can determine whether a falling edge of the target reset signal is currently detected according to the level change information of the target reset signal, so as to identify the current reset task to be executed by the first logic controller according to the corresponding judgment result, thereby accurately identifying and triggering the required current reset task by monitoring the falling edge of the target reset signal, so as to realize accurate control and timely response of the reset operation, and improve the stability and efficiency of the system.

[0132] In some embodiments, the first logic controller is further configured to:

[0133] in a case where it is known from the first judgment result that the falling edge of the target reset signal is detected, determine that the current reset task is a cold reset task or a hot reset task;

[0134] in a case where it is known from the first judgment result that the falling edge of the target reset signal is not detected, determine that the current reset task is an AC / DC power supply cycle task.

[0135] In some embodiments, the first logic controller is further configured to:

[0136] In the case of knowing that the current reset task is a cold reset task or a warm reset task, the first target delay time is obtained according to the timing signal change information of the cold reset task or the warm reset task.

[0137] After delaying for the first target delay time, the reset signals at the input ends of the image processing module and the switching module are pulled high, and the image processing module and the switching module are reset according to the reset signals after the pulling high.

[0138] Optionally, the first logic controller can further implement signal processing by performing the following steps:

[0139] In the case of knowing that the current reset task is a cold reset task or a warm reset task according to the first determination result, the first target delay time is obtained according to the timing signal change information of the cold reset task or the warm reset task. After delaying for the first target delay time when the falling edge of the target reset signal is detected, the reset signals at the input ends of the image processing module and the switching module are pulled high, and the image processing module and the switching module are reset according to the reset signals after the pulling high. After the respective reset of the image processing module and the switching module is completed, the switching module can perform PCIE Link Training with the CPU in the target main control board and each GPU in the image processing module, respectively, and enter the operating system (OS) of the server after the PCIE Link Training is completed, so as to iteratively perform the next Warm Reset task or Cold Reset task or other tasks.

[0140] It should be noted that the first target delay time is an uncertain value, which can be measured by an oscilloscope according to the timing signal change information of the cold reset task or the warm reset task. Specifically, different reset tasks need to be measured by different measurement methods, and the measured values can be different, such as 2s delay time or other delay time, which is not limited in the embodiment. In the process of obtaining the first target delay time, the reset signals at the input ends of the image processing module and the switching module are reset after 2s or other measured delay time, and the power-on timing sequence of the image processing module and the switching module satisfies the timing signal change condition of the warm reset task as shown in FIG. 5 or the timing signal change condition of the cold reset task as shown in FIG. 6.

[0141] To sum up, the system provided by the embodiment optimizes the reset operation of the image processing module and the switching module and the PCIE Link Training by intelligently identifying the reset task type and accurately controlling the delay time according to different reset task types, thereby effectively improving the operation stability and energy efficiency ratio of the server.

[0142] In some embodiments, the first logic controller is further configured to:

[0143] In a case where it is learned from the first determination result that the falling edge of the target reset signal is not detected, it is determined that the current reset task is an AC-DC power cycle task.

[0144] In a case where it is learned that the current reset task is the AC-DC power cycle task, it is determined whether the target indication signal of the last power is detected, and a second determination result is obtained; the target indication signal is used to indicate that the power is in a normal operation state.

[0145] According to the second determination result and the timing signal change information of the AC-DC power cycle task, corresponding reset control operations are performed on the image processing module and the switching module.

[0146] Optionally, the first logic controller can further implement signal processing by performing the following steps:

[0147] In a case where it is learned from the first determination result that the falling edge of the target reset signal is not detected, the first logic controller determines that the current reset task is the AC-DC power cycle task. At this time, it can be further determined whether the target indication signal (or Power Good signal) of the last power indicating that the power is in a normal operation state is detected, and a second determination result is obtained.

[0148] Subsequently, the first logic controller performs multiple logic determinations or model predictions according to the second determination result and the timing signal change information of the AC-DC power cycle task, obtains a corresponding reset control strategy, and thereby performs corresponding reset control operations on the image processing module and the switching module based on the corresponding reset control strategy.

[0149] Exemplarily, in some embodiments, the first logic controller can implement the reset control operation by the following logic determination:

[0150] In a case where it is learned from the second determination result that the target indication signal of the last power is detected, a second target delay time is obtained according to the timing signal change information of the AC-DC power cycle task.

[0151] After delaying for the second target delay time, the reset signals of the input ends of the image processing module and the switching module are pulled high, and the image processing module and the switching module are reset according to the reset signals after the pulling high.

[0152] Optionally, the first logic controller, in the case of knowing that the target indication signal of the last power supply of the switching board is currently detected according to the second judgment result, obtains the second target delay time according to the time sequence signal change information of the AC / DC power supply cycle task, so as to pull high the reset signals of the input ends of the image processing module and the switching module after delaying for the second target delay time, and reset the image processing module and the switching module according to the reset signals after the pulling high.

[0153] It should be noted that the second target delay time here is an uncertain value, which can be obtained by an oscilloscope according to the time sequence signal change information of the AC / DC power supply cycle task. Specifically, different tasks need to be measured by different measurement methods, and the measured values may be different, such as 200 ms delay time or other delay time, which is not limited in the embodiment. However, in the process of obtaining the second target delay time, it is necessary to ensure that the power-on time sequence of the image processing module and the switching module satisfies the time sequence signal change condition of the AC / DC power supply cycle task shown in FIG. 4 after the reset signals of the input ends of the image processing module and the switching module are reset after delaying for 200 ms or other measured delay time.

[0154] For example, in some embodiments, the first logic controller can realize the reset control operation through the following logical judgment:

[0155] The first logic controller, in the case of knowing that the target indication signal of the last power supply is not detected according to the second judgment result, returns to the step of judging whether the target indication signal of the last power supply is detected, until it is known that the target indication signal of the last power supply is detected.

[0156] Optionally, the first logic controller, in the case of knowing that the target indication signal of the last power supply is not currently detected according to the second judgment result, returns to the step of judging whether the target indication signal of the last power supply is detected, and continues to monitor the power supply of the switching board until it is known that the target indication signal of the last power supply is currently detected, and then obtains the second target delay time according to the time sequence signal change information of the AC / DC power supply cycle task, so as to pull high the reset signals of the input ends of the image processing module and the switching module after delaying for the second target delay time, and reset the image processing module and the switching module according to the reset signals after the pulling high.

[0157] The system provided by the embodiment can dynamically adjust the reset control strategy by detecting the falling edge of the target reset signal, the target indication signal and the change information of the task timing signal, and can realize efficient and accurate reset control of the image processing module and the switching module.

[0158] In some embodiments, the switching module is connected with the central processing unit in the target main control board and the image processing module.

[0159] The switching module is configured to, in a case where the reset operation of the image processing module and the switching module is completed, perform high-speed serial computer extended bus link training with the central processing unit in the target main control board and the image processing module.

[0160] The switching module is connected with the central processing unit in the target main control board and the image processing module, and the specific connection mode can be set according to actual requirements. For example, assuming that the switching module includes a PCIE switching chip A and a PCIE switching chip B, the target main control board includes CPU0 and CPU1, and the image processing module includes GPU0-GPU9, the PCIE switching chip A can be connected with GPU0-GPU4 through a PCIE link and can be connected with CPU0 through a PCIE link; and the PCIE switching chip B can be connected with GPU5-GPU9 through a PCIE link and can be connected with CPU1 through a PCIE link.

[0161] Optionally, in a case where the reset operation of the image processing module and the switching module is completed, each switching chip in the switching module can perform PCIE Link Training with the CPU and the GPU connected therewith, respectively, so that each switching chip in the switching module can quickly perform efficient PCIE Link Training with the CPU and the GPU connected therewith after the reset operation of the image processing module and the switching module is completed, thereby significantly improving the stability and efficiency of system data transmission.

[0162] In some embodiments, the first logic controller is further configured to:

[0163] In a case where the high-speed serial computer extended bus link training between the switching module and the central processing unit in the target main control board and the image processing module is completed, the first logic controller returns to the step of judging whether the platform type is the first platform type, and performs the next reset task.

[0164] Optionally, the first logic controller, in the case of determining that the high-speed serial computer expansion bus link training between the switch module and the central processing unit in the target main control board and the image processing module is completed, can return to the step of judging whether the platform type is the first platform type, to iteratively perform the next reset task, such as the boot action corresponding to the AC / DC Cycle task, the boot action corresponding to the Warm Reset task, the boot action corresponding to the Cold Reset task, or directly end the signal processing procedure, thereby realizing the automation and flexibility of the system reset procedure after the high-speed serial computer expansion bus link training is completed, and ensuring the stability and efficiency of the computer system.

[0165] The following takes the first logic controller as FPGA1 and the second logic controller as FPGA0 as an example to specifically describe the signal processing steps performed by the computer system provided in the embodiments of the present application.

[0166] FIG. 7 is a flowchart of the signal processing steps provided in the present application; as shown in FIG. 7, the signal processing logic of the firmware in the first logic controller is specifically as follows:

[0167] After the server is powered on, the FPGA1 loads the code from the internal configuration flash memory (CFM) module for running, and after the code loading is completed, the FPGA1 senses the high and low level states of the port signal of the CPU0 transmitted by the pull-up circuit, to determine the platform type to which the target main control board currently carried by the server belongs from the high and low level states of the port signal of the CPU0.

[0168] When it is determined that the target main control board currently carried by the server is the second platform type (such as the Intel platform type), the FPGA1 performs the hardware boot action according to the normal timing procedure according to the target reset signal transmitted by the target main control board; the timing procedure here can be the hardware boot action corresponding to the AC / DC Cycle task, the hardware boot action corresponding to the Warm Reset task, or the hardware boot action corresponding to the Cold Reset task; in addition, after the boot procedure is completed, the switch chips (such as switch chip A and switch chip B) in the switch module respectively perform the PCIE Link Training with the CPUs (such as CPU0 and CPU1) in the main control board under the second platform type, and the image processors (such as GPU0-GPU9) in the image processing module, and after the training is completed, the next hardware boot action corresponding to the AC / DC Cycle task, the hardware boot action corresponding to the Warm Reset task, or the hardware boot action corresponding to the Cold Reset task can be performed or directly ended.

[0169] When it is determined that the target main control board currently loaded on the server is of the first platform type (e.g., AMD platform type), the FPGA1 of the switchboard pushes up the power (or Power) of the switchboard according to the power-on sequence, and determines whether a falling edge of a target reset signal from the CPU (e.g., CPU0) of the target main control board of the first platform type is currently detected.

[0170] If the FPGA1 does not detect the falling edge of the target reset signal, it means that the server is currently performing an AC Cycle task. Next, the FPGA1 determines whether a Power Good signal of the last Power of the switchboard is currently detected. If the Power Good signal is detected, the FPGA1 pulls up the reset signals (or Reset signals) of the switch chips (e.g., switch chip A and switch chip B) in the switch module and the image processors (e.g., GPU0-GPU9) in the image processing module after a second delay time (e.g., 200 ms) to perform a reset action. If the Power Good signal of the last Power of the switchboard is not detected, the FPGA1 returns to the step of determining whether the Power Good signal of the last Power of the switchboard is currently detected, and continues to monitor until the Power Good signal of the last Power of the switchboard is detected. After the second delay time, the FPGA1 pulls up the reset signals of the switch chips (e.g., switch chip A and switch chip B) in the switch module and the image processors (e.g., GPU0-GPU9) in the image processing module to perform a reset action. After the reset action is completed, the switch chips (e.g., switch chip A and switch chip B) in the switch module can perform PCIE Link Training with the CPUs (e.g., CPU0 and CPU1) of the target main control board of the first platform type and the image processors (e.g., GPU0-GPU9) in the image processing module, and after the PCIE Link Training is completed, perform a hardware boot action corresponding to the next Warm Reset task or Cold Reset task or other actions.

[0171] If the FPGA1 currently detects the falling edge of the target reset signal, it indicates that the server is currently performing a Warm Reset task and a Cold Reset task. Next, after detecting the falling edge of the target reset signal for a first target delay time (e.g., 2s), the reset signals (or Reset signals) of the switching chips (e.g., switching chip A and switching chip B) in the switching module and the image processors (e.g., GPU0-GPU9) in the image processing module are pulled high to perform a reset action. After the reset of the image processing module and the switching module is completed, the switching chips (e.g., switching chip A and switching chip B) in the switching module can respectively perform PCIE Link Training with the CPUs (e.g., CPU0 and CPU1) of the target main control board under the first platform type and the image processors (e.g., GPU0-GPU9) in the image processing module, and after the PCIE Link Training is completed, the server enters the OS and performs the next Warm / Cold Reset task corresponding to the hardware boot action or other action.

[0172] It should be noted that the logic of the FW of the FPGA1 can be implemented based on Verilog language or other languages, which is not limited in the embodiment.

[0173] In summary, the computer system provided by the embodiment can solve the compatibility problem of different platform CPUs, PCIE switching chips and GPUs through a general architecture design, reduce development cost, improve universality, and the specific effects are as follows:

[0174] Firstly, the differences in initialization efficiency, initialization process and global reset of different CPU manufacturers, PCIE switch chip manufacturers and GPU manufacturers under the PCIE controller can be eliminated, and the compatibility problems such as card loss, switch loss and PCIE bus bandwidth reduction after different functional chip or component manufacturers are matched together can be solved, and the PCIE compatibility problem of different platform CPUs matched with different platform PCIE switching chips and different manufacturer GPU modules can be completely eliminated.

[0175] Secondly, by increasing the pull-up circuit and optimizing the firmware processing logic of the logic controller, the PCIE compatibility problem of different platform CPUs matched with different platform PCIE switching chips and different manufacturer GPU modules can be eliminated, the hardware architecture is simple, the maintenance and repair cost is low, the development cost is low, the reliability is high, and the problem of high cost of developing multiple system boards or multiple CPLD / BIOS FW in the traditional solution is effectively avoided, and the whole system development cost is effectively reduced.

[0176] Third, it has strong versatility and can be used to compatible with various platforms of CPU and various PCIE Switch manufacturers and GPU manufacturers, thus having high market value.

[0177] The signal processing method provided in the present application is described below. The signal processing method described below can be mutually referenced with the computer system described above.

[0178] FIG. 8 is a flowchart of the signal processing method provided in the present application. As shown in FIG. 8, the method is implemented by the first logic controller in the computer system provided in each of the embodiments. The method includes steps 810 and 820.

[0179] In step 810, the platform type corresponding to the target main control board is obtained according to the port signal transmitted by the pull-up circuit. The port signal is generated by the pull-up circuit according to the port state of the target GPIO in the target main control board.

[0180] In step 820, the image processing module and the switching module are subjected to corresponding reset control operations according to the platform type and the target reset signal transmitted by the target main control board.

[0181] Optionally, the pull-up circuit can obtain the port state of the target GPIO of the target main control board, and generate a corresponding port signal (or CPU_Detect signal) according to the port state of the target GPIO. The generated port signal is transmitted to the first logic controller through the connection path between the pull-up circuit and the first logic controller, so that the first logic controller can identify the platform type to which the target main control board belongs according to the corresponding port signal, and call the logic code corresponding to the platform type to implement corresponding logic signal processing. In this way, the compatibility problem of different CPU platforms matched with different PCIE Switch chips and GPU components can be solved by using a universal architecture, thereby reducing the development cost.

[0182] Optionally, in the signal processing process, the first logic controller can identify the corresponding platform type of the target main control board connected to the switching board in an upward direction according to the port signal transmitted by the pull-up circuit.

[0183] For example, the first logic controller can implement the identification of the platform type corresponding to the target main control board by performing the following steps:

[0184] The first logic controller can read the port signal sent by the pull-up circuit and determine the level corresponding to the port signal. Then, a correspondence table of preset level corresponding to the general input and output port of the main control board of different platform types is traversed, and the level corresponding to the port signal is compared with the preset level corresponding to the general input and output port of the main control board of each preset platform type in the correspondence table, to find a matching item. Once the matching level is found, the platform type of the target main control board can be determined according to the preset platform type corresponding to the matching level, so that the platform type of the target main control board connected to the switching board in the uplink is efficiently and accurately identified, thereby facilitating to improve the compatibility and flexible configuration of the main control board of different platform types, and further improving the scalability and ease of use of the computer system.

[0185] Optionally, after obtaining the corresponding platform type of the target main control board connected to the switching board in the uplink, the first logic controller can obtain the target reset signal transmitted by the target main control board in real time.

[0186] After obtaining the target reset signal transmitted by the target main control board, the first logic controller can call the corresponding signal processing logic according to the target reset signal and the platform type of the target main control board, to perform corresponding reset control operation on the image processing module and the switching module.

[0187] The method provided in the embodiment integrates the pull-up circuit, the first logic controller, the image processing module and the switching module, uses the pull-up circuit to monitor the port state of the general input and output port of the target main control board in real time, generates and transmits the corresponding port signal to the first logic controller, so that the first logic controller can quickly identify the platform type of the target main control board according to the signal, and flexibly adjust the reset control operation on the image processing module and the switching module according to the target reset signal from the target main control board, thereby realizing the compatibility requirement of the combination of the main control board of multiple platform types through a set of general architecture, eliminating the PCIE compatibility problem of the CPU of different platforms matched with the PCIE Switch chip of different platforms and the GPU module of different manufacturers, not only simplifying the compatibility processing flow of diversified chip combinations, avoiding the high development cost of traditional multiple system logic control boards or customized firmware, but also significantly improving the stability and reliability of the computer system under different hardware combinations, thereby effectively reducing the complexity and uncertainty of product development, and providing a more efficient and economical solution for downstream computer system manufacturers.

[0188] The computer system provided in the present application is used to execute the above-mentioned method embodiments, and the specific flow and detailed content are referred to the above-mentioned embodiments, which will not be described here.

[0189] Fig. 9 illustrates an entity structure diagram of an electronic device, as shown in Fig. 9, the electronic device can include: a processor 910, a communications interface 920, a memory 930 and a communications bus 940, wherein the processor 910, the communications interface 920, the memory 930 complete the communication between each other through the communications bus 940. The processor 910 can call the logic instructions in the memory 930 to execute the signal processing method, the method comprising: obtaining the platform type corresponding to the target main control panel according to the port signal transmitted by the pull-up circuit; the port signal is generated by the pull-up circuit according to the port state of the target general input and output port in the target main control panel; according to the platform type, and the target reset signal transmitted by the target main control panel, the corresponding reset control operation is performed on the image processing module and the switching module.

[0190] In addition, the logic instructions in the memory 930 described above can be implemented in the form of a software function unit and sold or used as an independent product, which can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the embodiments of the method of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0191] On the other hand, the present application also provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-volatile computer readable storage medium, when the computer program is executed by the processor, the computer can execute the signal processing method provided by the above-mentioned method, the method comprises: obtaining the platform type corresponding to the target main control panel according to the port signal transmitted by the pull-up circuit; the port signal is generated by the pull-up circuit according to the port state of the target general input and output port in the target main control panel; according to the platform type, and the target reset signal transmitted by the target main control panel, the corresponding reset control operation is performed on the image processing module and the switching module.

[0192] In yet another aspect, the present application provides a non-volatile computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a signal processing method provided by any of the above methods, the method comprising: obtaining a platform type corresponding to a target main control board according to a port signal transmitted by a pull-up circuit; the port signal being generated by the pull-up circuit according to a port state of a target general-purpose input / output port in the target main control board; and performing a corresponding reset control operation on an image processing module and a switching module according to the platform type and a target reset signal transmitted by the target main control board.

[0193] The system embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., may be located in one place, or may be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0194] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary universal hardware platforms, and of course can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods of the various embodiments or some parts of the embodiments.

[0195] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A computer system, characterized by The application relates to a target main control board, an up-pull circuit connected with a target general input-output port in the target main control board, a first logic controller, an image processing module and a switching module, and a reset control method. The application relates to a target main control board, an up-pull circuit connected with a target general input-output port in the target main control board, a first logic controller, an image processing module and a switching module, and a reset control method. The first logic controller is further used for judging whether the platform type is a first platform type, obtaining a current reset task required by the first logic controller according to level change information of the target reset signal when the platform type is the first platform type, and executing corresponding reset control operations on the image processing module and the switching module according to time sequence signal change information of the current reset task. The first logic controller is further used for judging whether a falling edge of the target reset signal is detected according to the level change information of the target reset signal to obtain a first judgment result, and obtaining the current reset task required by the first logic controller according to the first judgment result.

2. The computer system of claim 1, wherein, The first logic controller is further used for determining that the current reset task is a cold reset task or a hot reset task when it is learned from the first judgment result that the falling edge of the target reset signal is detected, and determining that the current reset task is an AC-DC power supply cycle task when it is learned from the first judgment result that the falling edge of the target reset signal is not detected. The first logic controller is further used for obtaining a first target delay time according to time sequence signal change information of the cold reset task or the hot reset task when it is learned that the current reset task is the cold reset task or the hot reset task, pulling up reset signals of an input end of the image processing module and an input end of the switching module after delaying for the first target delay time, and performing a reset release operation on the image processing module and the switching module according to the pulled-up reset signals. The first logic controller is further used for judging whether a target indication signal of a last power supply is detected to obtain a second judgment result when it is learned that the current reset task is the AC-DC power supply cycle task, the target indication signal being used for indicating that the power supply is in a normal operation state, and executing corresponding reset control operations on the image processing module and the switching module according to the second judgment result and time sequence signal change information of the AC-DC power supply cycle task. The first logic controller is further used for 3. The computer system of claim 2, wherein, ​ ​ ​ 4. The computer system of claim 3, wherein, ​ ​ ​ 5. The computer system of claim 4, wherein, ​ ​ ​ 6. The computer system of claim 4, wherein, ​ ​ ​ 7. The computer system of claim 6, wherein, ​ If the last power supply target indication signal is not detected according to the second determination result, return to the step of determining whether the last power supply target indication signal is detected until the last power supply target indication signal is determined to be detected.

8. The computer system of claim 6, wherein, The first logic controller is further configured to: If the last power supply target indication signal is detected according to the second determination result, obtain a second target delay time according to the timing signal change information of the AC / DC power supply cycle task; After delaying for the second target delay time, pull high the reset signals of the input end of the image processing module and the input end of the switching module, and perform a reset operation on the image processing module and the switching module according to the reset signals after the pull high operation.

9. The computer system of claim 8, wherein, The switching module is connected with the central processing unit in the target main control board and the image processing module; If the reset operations of the image processing module and the switching module are both completed, the switching module performs a high-speed serial computer expansion bus link training with the central processing unit in the target main control board and the image processing module.

10. The computer system of claim 9, wherein, The first logic controller is further configured to: If the high-speed serial computer expansion bus link training between the switching module and the central processing unit in the target main control board and the image processing module is completed, return to the step of determining whether the platform type is the first platform type, and perform a next reset task.

11. The computer system of any of claims 1-10, wherein, The first logic controller is further configured to: Match the level corresponding to the port signal with the preset level corresponding to the general input / output port in the main control board of each preset platform type; According to the matching result, obtain the preset level matched with the level corresponding to the port signal; According to the preset platform type corresponding to the matched preset level, obtain the platform type corresponding to the target main control board.

12. The computer system of any of claims 1-10, wherein, The pull-up circuit includes a pull-up resistor and a pull-up power supply; The first end of the pull-up resistor is connected with the pull-up power supply, the second end of the pull-up resistor is connected with the target general input / output port, and the third end of the pull-up resistor is connected with the first logic controller.

13. The computer system of any of claims 1-10, wherein, If the target main control board is the first platform type, the target main control board includes a plurality of central processing units and a second logic controller; The plurality of central processing units are connected through an interconnection interface; At least one of the central processing units is connected with the second logic controller, and the second logic controller is connected with the first logic controller.

14. The computer system of claim 13, wherein, If the platform type is the first platform type, the target reset signal is a global reset signal sent by at least one of the central processing units of the target main control board through the second logic controller of the target main control board.

15. The computer system of any of claims 1-10, wherein, If the target main control board is the second platform type, the target main control board includes a plurality of central processing units, a south bridge chip and a second logic controller; The plurality of central processing units are connected through an interconnection interface; At least one of the central processing units is connected with the south bridge chip, the south bridge chip is connected with the second logic controller, and the second logic controller is connected with the first logic controller.

16. The computer system of claim 15, wherein, In the case that the platform type is a second platform type, the target reset signal is a global reset signal sent by at least one of the central processing units of the target main control board through the south bridge chip and the second logic controller in sequence.

17. The computer system of claim 2, wherein, The level change information corresponding to different reset tasks is different, and the correspondence between different reset tasks and different level change information is determined according to the time sequence signal change information corresponding to each reset task; the time sequence signal change information includes power signal time sequence change information, clock signal time sequence change information and reset signal time sequence change information. The reset control operation corresponding to the current reset task is executed on the image processing module and the switching module, including: The time sequence signal change information of the current reset task is subjected to multiple logical judgments or model prediction to obtain a corresponding reset control strategy, and based on the corresponding reset control strategy, a corresponding reset control process is executed on the image processing module and the switching module at a corresponding reset operation trigger time; the reset control strategy includes a reset operation process and a reset operation trigger time.

18. A signal processing method characterized by, The method is applied to the computer system as claimed in any one of claims 1 to 17, and the method comprises: According to the port signal transmitted by the pull-up circuit, the platform type corresponding to the target main control board is obtained; the port signal is generated by the pull-up circuit according to the port state of the target general-purpose input and output port in the target main control board; According to the platform type and the target reset signal transmitted by the target main control board, corresponding reset control operations are executed on the image processing module and the switching module.

19. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein, The processor executes the program to realize the signal processing method as claimed in claim 18.

20. A non-transitory computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the signal processing method as claimed in claim 18.

21. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to realize the signal processing method as claimed in claim 18.

Images