Chip system and electronic apparatus

Abstract

The present application relates to the technical field of semiconductors, and provides a chip system and an electronic apparatus, used for improving the clock quality of a chip system having a 3D structure, and improving the chip performance. The chip system comprises a first die and at least one second die; the first die is coupled to the second die by means of an inter-die interconnection interface; and the first die and the second die are each provided with a plurality of timing devices. The chip system further comprises a clock tree; the clock tree is disposed in the first die; and the clock tree can be coupled to clock input ends of the timing devices on the second die by means of the inter-die interconnection interface and interconnection metal lines to provide a clock signal for the timing devices on the second die. In this way, distribution of the clock tree across different dies can be avoided, thereby reducing the effect of cross chip variation on the clock signal of the chip system, improving the clock signal quality of the chip system, and improving the chip performance.

Description

Chip system and electronic device

[0001] This application claims priority to the Chinese patent application No. 202411347328.0, filed on September 25, 2024, and entitled "Chip system and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of semiconductor technology, and in particular, to a chip system and an electronic device. BACKGROUND

[0003] At present, with the increasing demand for chip functions and computing power, a single die has been difficult to meet the growing demand of application scenarios. As a result, chiplet and 3-dimensional (3D) stacking design have become a hot spot in current chip design. Chiplet and 3D stacking can use multiple dies, for example, multiple dies are stacked in 3D to integrate more functions.

[0004] In a digital chip, the data transmission between each unit is synchronously controlled by a clock signal. In a 3D structure chip, since different dies can be made of different wafers or different processes, there can be cross chip variation (CCV) between dies. Cross chip variation refers to the variation between two different dies due to process fluctuations. Cross chip variation causes clock skew on the clock path on different dies, resulting in poor clock quality of the 3D chip and affecting the performance of the chip. SUMMARY

[0005] The present application provides a chip system and an electronic device to improve the clock quality of a 3D structure chip system and improve the performance of the chip.

[0006] In a first aspect, a chip system is provided, the chip system comprising a first die and a second die, the first die and the second die being coupled through an inter-die interconnection interface, a plurality of sequential devices being disposed on the first die and the second die, the sequential devices comprising, for example, registers, flip-flops, static random-access memories (SRAMs), and the like; the chip system further comprising a clock tree, the clock tree being disposed in the first die, the sequential devices of the second die being coupled to the clock tree through the inter-die interconnection interface and an interconnection metal line to obtain a clock signal.

[0007] The chip system provided by the embodiments of the present application comprises a plurality of dies, a clock tree is arranged on a first die, and a timing device on a second die is coupled with the clock tree through an inter-die interconnection interface and an interconnection metal line, so that the clock tree does not need to be arranged on the second die, the clock tree is distributed on different dies is avoided, the interconnection metal line is less affected by cross-die process deviation, and therefore the clock signal quality of the chip system can be improved by arranging the clock tree on the first die, the clock signal quality of the chip system is improved, and the performance of the chip system is improved.

[0008] In a possible implementation, the first die comprises a plurality of timing devices, and clock input ends of the timing devices of the first die are coupled with the clock tree through the interconnection metal line.

[0009] In a possible implementation, the clock tree comprises a plurality of clock drivers, a first clock driver in the plurality of clock drivers is configured to be connected with a clock source, and a last clock driver in the plurality of clock drivers is configured to be coupled with clock input ends of the timing devices of the first die and clock input ends of the timing devices of the second die.

[0010] In a possible implementation, the clock driver comprises an inverter or a buffer.

[0011] In a possible implementation, the chip system further comprises a clock source, the clock source is arranged on the first die, or the clock source is arranged on the second die and is transmitted to the first die through the inter-die interconnection interface and the interconnection metal line, so that the influence of cross-die process deviation on the clock signal quality of the chip system can be reduced.

[0012] In a possible implementation, the clock source is arranged on the first die.

[0013] In a possible implementation, the last clock driver is configured to be coupled with the clock input ends of the timing devices of the second die through the inter-die interconnection interface and the interconnection metal line.

[0014] In a possible implementation, the last clock driver is configured to be coupled with the clock input ends of the timing devices of the first die through the interconnection metal line to output the clock signal to the timing devices of the first die.

[0015] In a possible implementation, the clock source is arranged on the first die.

[0016] In a possible implementation, the clock input end of the timing device of the second die is used to be coupled with the clock driver arranged on the first die through the interconnection metal line and the inter-die interconnection interface, so as to obtain the clock signal provided by the clock driver of the first die.

[0017] In a fourth aspect, an electronic device is provided, which includes a circuit board and the chip system provided in the first aspect and any implementation, and the chip system is arranged on the circuit board. BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a schematic diagram of a general clock circuit;

[0019] FIG. 2 is a schematic diagram of a general 3D chip;

[0020] FIG. 3 is a schematic diagram of an electronic device provided in an embodiment of the present application;

[0021] FIG. 4 is a schematic diagram of a chip system provided in an embodiment of the present application;

[0022] FIG. 5 is a schematic diagram of another chip system provided in an embodiment of the present application;

[0023] FIG. 6 is a schematic diagram of a clock tree of the chip system provided in an embodiment of the present application;

[0024] FIG. 7 is a flowchart of a method for generating a clock tree provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0026] Hereinafter, the terms "first", "second", and the like are only used for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more. For example, multiple processing units refer to two or more processing units.

[0027] In addition, in the embodiments of the present application, "up", "down", "left", and "right" are not limited to be defined according to the relative positions of the components shown in the drawings, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the positions of the components shown in the drawings. In the drawings, the thicknesses of the layers and regions are exaggerated for clarity, and the size ratio relationship between the parts in the drawings does not reflect the actual size ratio relationship.

[0028] In the embodiments of the present application, unless specifically defined and limited otherwise, the term "connection" should be interpreted broadly, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium. In addition, the term "electrical connection" can be direct electrical connection, or indirect electrical connection through intermediate medium.

[0029] In the embodiments of the present application, the term "module" is generally a functional structure divided according to logic, which can be implemented by pure hardware, or by a combination of software and hardware. In the embodiments of the present application, the association relationship of the associated objects is described by "and / or", which means that there can be three kinds of relationships, for example, A and / or B can represent three cases of A alone, B alone, and A and B together.

[0030] In the embodiments of the present application, the words such as "exemplary" or "for example" are used to mean serving as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplary" or "for example" are used in the specific manner to present the relevant concept.

[0031] The chip includes a plurality of functionally different processing units, such as memories, calculators, etc., and each processing unit cooperates to realize the function of the chip, for example, reading data A from the first memory and reading data B from the second memory, and the calculator performs operation on data A and data B. If the two data arrive at the calculator at the same time, the operation can be directly performed, but in most cases, due to different transmission paths and other reasons, the two data cannot arrive at the calculator at the same time, which requires a clock signal to synchronize the operation, for example, in the first clock cycle, data A and data B are read from the memory and latched, at this time, it is not necessary to consider which data arrives first, it is only necessary to ensure that the two data are ready before the next clock cycle arrives; in the next clock cycle, the calculator performs operation on data A and data B, so that the operation result will not be wrong.

[0032] In a chip, data transmission between each unit and state switching of each timing device is synchronously controlled by a clock signal, which is a periodic pulse signal, also known as a system clock or a reference clock, and the unit is hertz (Hz). The chip includes a plurality of timing devices, such as a register, which functions to first latch the incoming data to maintain stability and then release the data when the next clock active edge arrives. If the data is not synchronized, the data that needs to be synchronized for operation cannot be synchronized, and thus the operation result will be incorrect, so the clock signal needs to be used to control the data synchronization operation. Since the clock signal is synchronized, the data can also be synchronized, and the synchronous operation of the data can be achieved, and the operation result will not be incorrect.

[0033] The clock signal in the chip is usually provided by a clock source combined with a clock network. The chip can include a plurality of clock regions located at different positions of the chip. The clock region includes a plurality of registers, flip-flops, static random access memories (SRAMs), and other timing devices. The clock network is a topology structure of the clock circuit inside the chip, which can synchronously transmit the clock signal to the clock regions located at different positions of the chip, such as synchronously transmitting the clock signal to the timing devices located in the central region of the chip and to the timing devices located in the edge region of the chip.

[0034] The clock network is usually implemented in the structure of a clock tree. The clock signal provided by the clock source is propagated to the clock input terminals of all timing circuits in the entire chip through a plurality of inverters or buffers in a one-to-many form. The inverters, buffers, and other units composed of transistors and interconnection structures with specific logic operation functions or data storage functions can be referred to as standard cells, or clock drivers. The structure from the clock source to the timing devices composed of these standard cells and the metal traces between the standard cells is called a clock tree, which plays an important role in the chip.

[0035] FIG. 1 shows a schematic diagram of a clock circuit, as shown in FIG. 1, the clock circuit includes a clock source 110 and a clock tree 120. Among them, the clock source 110 is used to output a clock signal, for example, the clock source 110 can include a phase-locked loop; the clock tree 120 is used to transmit and amplify the clock signal to drive the timing devices in the subsequent circuit. For example, a register 130 in the subsequent circuit. As shown in FIG. 1, the clock tree 120 usually includes multiple levels of clock drivers 121. Each level of clock driver includes one or more clock drivers 121. Among them, the clock driver 121 connected with the clock source 110 can be called the clock master driver, and the last level of clock driver 121 can be used to connect the timing devices such as the register 130.

[0036] With the increasing demand for chip computing power and the arrival of the physical limit of semiconductor device size miniaturization, chips in the form of a single die have been difficult to meet the growing demand of application scenarios. Chiplet technology or three-dimensional (3-dimensional, 3D) stacking design as the main solution to continue Moore's law is rapidly advancing, and more and more research is being conducted in the scientific research community and the industry.

[0037] Chiplet and 3D stacking design can splice multiple dies according to demand to realize 3D stacking, meet different application scenarios, and also improve the yield of chiplets by reasonably controlling the size of the die to reduce production costs. The design difficulty of 3D structure chip is greater than that of single die, especially how to realize the full synchronization of the clock signal, which has always been a difficult problem in the industry.

[0038] A complete 3D structure chip is usually formed by stacking multiple two-dimensional (2-dimensional, 2D) chips. For ease of description, each individual 2D chip is referred to as a die in the following. With the continuous development of integrated circuit industry, device size is continuously shrinking, and integrated circuit manufacturing process fluctuation is also getting bigger and bigger, which brings great challenges to circuit designers. Multiple dies in a 3D structure chip may be made of different wafers and may belong to different process corners, which makes the 3D structure chip have process fluctuations between different dies and wafers, called cross chip variation (CCV). CCV will bring great challenges to the clock tree design of the 3D structure chip.

[0039] As shown in FIG. 2, which shows a schematic diagram of a 3D chip including a first die 210 and a second die 220 stacked, for example, the first die 210 and the second die 220 are stacked in the direction of the thickness of the chip. The first die 210 is coupled with the second die 220 through an inter-die interconnection interface 230. The 3D chip includes a clock tree including a first clock path 211 located on the first die 210 and a second clock path 221 located on the second die 220. In the example of FIG. 2, the first clock path 211 and the second clock path 221 have the same structure and length, for example, including the same number of clock drivers. A clock signal provided by a clock source 240 is transmitted to a timing device 212 on the first die 210 through the first clock path 211. The clock signal provided by the clock source 240 is transmitted to a timing device 222 on the second die 220 through the second clock path 221. The present application is applicable to a clock tree including any clock paths of different lengths. The first clock path 211 and the second clock path 221 have the same length, which is only a specific case for convenience of description. The lengths of the first clock path 211 and the second clock path 221 are the same, so ideally the time for the clock signal to reach the timing device 212 on the first die 210 and the timing device 222 on the second die 220 should be synchronized, but due to the cross-die process variation between the first die 210 and the second die 220, the first clock path 211 and the second clock path 221 can have variations, for example, a clock driver in the first clock path 211 has weaker performance, or a clock driver in the second clock path 221 has stronger performance, which can cause differences in the clock signals transmitted by the first clock path 211 and the second clock path 221, resulting in clock skew. Clock skew refers to the time offset of a clock source reaching the clock input terminals of two different timing devices. Clock skew can be represented as: T skew = T clk2 - T clk1 , where T skew represents clock skew, T clk1 and T clk2 represent the times when the clock source reaches the clock input terminals of the two different timing devices. The cross-die process variation causes the time for the same clock signal to reach the timing devices on the first die 210 and the second die 220 to be inconsistent, affecting the quality of the clock signal and possibly causing the entire 3D chip to malfunction.

[0040] To improve this problem, embodiments of the present application provide a chip system, which can be applied in different devices, such as the electronic device shown in FIG. 3, which is a schematic diagram of an electronic device 30 provided by embodiments of the present application. The electronic device 30 can be a terminal, such as a server 31, a mobile phone terminal 32, a tablet computer 33, a notebook computer 34, a desktop computer 35, an augmented reality (AR) device (not shown in FIG. 3), a virtual reality (VR) device (not shown in FIG. 3), a vehicle-mounted terminal (not shown in FIG. 3), and the like.

[0041] Among them, the chip system includes a plurality of dies with specific functions, which can be modularly assembled with each other, such as dies that can realize functions of data storage, calculation, signal processing, data flow management, and the like. Based on rich intellectual property core (IP) reserves, the chip system proposes the concept of IP chip (IP as a chiplet, IaaC), aiming to realize the "plug and play" of special function IP with dies. For example, for some core processor IP, the die can be a graphics processing unit (GPU) IP, a neural processing unit (NPU) IP, a video processing unit (VPU) IP, a digital signal processing (DSP) IP, an image signal processor (ISP) IP, and a display processor IP, and the like. In addition, the die can also be a digital-analog hybrid IP and a radio frequency IP, and the like.

[0042] The chip system in the present application can also be referred to as a small chip system or a chiplet system, that is, the die can also be referred to as a small chip or a chiplet. For example, the chip system can be applied on a system-on-a-chip (SoC), and the SoC integrates dies with multiple functions.

[0043] FIG. 4 is a structural schematic diagram of a chip system provided by embodiments of the present application. For example, the chip system includes a plurality of dies, such as a first die 410 and a second die 420, which are stacked in the direction of the thickness of the chip, and this stacking mode is referred to as three-dimensional stacking; the first die 410 and the second die 420 can also be other stacking modes, such as 2.5D stacking, and the like. The plurality of stacked dies can be coupled through an inter-die interconnection interface 430.

[0044] The chip system includes a clock circuit, which includes a clock source 440 and a clock tree 450. The clock tree 450 is used to amplify and transmit a clock signal generated by the clock source 440 to registers and other timing devices on any die of the chip system, such as the timing devices on the first die 410 and the timing devices on the second die 420 in the embodiment.

[0045] The clock tree 450 includes multiple stages of clock drivers. A first stage of the clock drivers is used to receive the clock signal, and a last stage of the clock drivers is used to be coupled with clock input terminals of the timing devices to provide the clock signal to the timing devices. In the embodiment, the clock tree 450 is disposed in the first die 410, and thus the first die 410 can be referred to as a clock die, and the second die 420 can be referred to as a non-clock die. The clock tree 450 on the clock die is connected to the timing devices on the non-clock die through an inter-die interconnection interface and interconnection metal lines. For example, a last stage clock driver of the clock tree 450 on the first die 410 is electrically connected to the second die 420 through the inter-die interconnection interface, and the inter-die interconnection interface is connected to clock input terminals of the timing devices (such as registers) on the second die 420 through the interconnection metal lines.

[0046] In the chip system provided by the embodiment, the clock tree 450 is disposed on one of the dies, such as the multiple stages of clock drivers of the clock tree 450 and the interconnection metal lines therebetween are disposed on the first die 410. A last stage clock driver of the multiple stages of clock drivers is connected to clock input terminals of the timing devices on the first die 410 or on the second die 420 through the inter-die interconnection interface and / or the interconnection metal lines. For the timing devices on different dies, most of their clock paths are located on the first die 410, and the clock paths outside the first die 410 only include the inter-die interconnection interface and the interconnection metal lines. Since the electrical characteristics of the interconnection metal lines are not sensitive to process fluctuations relative to the clock drivers (such as inverters, buffers, etc.), that is, the electrical characteristics of the interconnection metal lines are less affected by cross-die process variations, and the interconnection metal lines between the multiple stages of clock drivers of the clock tree 450 and the clock drivers are disposed on the same die, the influence of cross-die process variations on the clock tree can also be avoided. Therefore, the influence of cross-die process variations on the clock signal in the chip system can be reduced, timing degradation can be avoided, and the performance of the 3D structure chip can be improved.

[0047] The clock tree 450 includes multiple levels of clock drivers, for example, the clock tree structure shown in FIG. 1 can be referred to, each level of clock drivers includes one or more clock drivers, and constitutes a multi-level clock buffer structure. Generally, the higher the number of levels of clock buffer structure, the more the number of clock drivers, for example, the number of first level clock drivers is 1, the number of second level clock drivers is 2, the number of third level clock drivers is 2-4, and so on. The first level clock driver is used to connect the clock source 440, and in some cases, the clock driver connected with the clock source 440 is also referred to as the master clock driver. The last level clock driver is used to be coupled with the clock input end of the corresponding timing device to transmit the clock signal to the corresponding timing device. The clock driver in the clock tree 450 can be understood as a node in the clock tree 450, which functions similarly to a clock repeater, and is used to transmit, recover, and enhance the clock signal to drive a larger load. The clock signal path between the clock source 440 and the timing device can be referred to as a clock path, and the driving capability of each clock path is limited. The driving capability of the clock path can be improved by setting clock drivers and other devices, or another clock path can be added to drive more and larger loads.

[0048] In a possible implementation, taking the first timing device 411 located in the first die 410 and the second timing device 421 located in the second die 420 as an example, the last level clock driver in the clock tree 450 includes a first clock driver, which is coupled with the clock input end (indicated as CP in the figure) of the second timing device 421 of the second die 420 through the inter-die interconnection interface 430 and the interconnection metal line. The last level clock driver in the clock tree 450 also includes a second clock driver, which is coupled with the clock input end (indicated as CP in the figure) of the first timing device 411 of the first die 410 through the interconnection metal line.

[0049] For example, in combination with FIG. 4, the clock tree 450 includes a first clock path 451 and a second clock path 452, wherein a last-stage clock driver 4511 in the first clock path 451 is coupled to a clock input terminal of the first timing device 411 to provide a clock signal to the first timing device 411, and a last-stage clock driver 4521 in the second clock path 452 is coupled to a clock input terminal of the second timing device 421 through the inter-die interconnection interface 430 and the interconnection metal line to provide a clock signal to the second timing device 421, and the first clock path 451 and the second clock path 452 have the same length, for example, have the same number of clock drivers. In an embodiment of the present application, for example, the first clock path 451 includes 6-stage clock drivers, and the second clock path 452 also includes 6-stage clock drivers. Since the multiple-stage clock drivers in the first clock path 451 and the second clock path 452 and the interconnection lines therebetween are located on the same die, the first clock path 451 and the second clock path 452 are not affected by the cross-die process fluctuation, and clock skew can be avoided in the clock paths of the same length due to the cross-die process fluctuation when the clock tree 450 is distributed on multiple dies. For the portions of the first clock path 451 and the second clock path 452 that are located outside the non-clock die, only the interconnection metal line exists, and the interconnection metal line is less affected by the cross-die process fluctuation. Therefore, the clock scheme provided in the embodiment of the present application can reduce the influence of the cross-die process fluctuation on the clock signal.

[0050] In addition, since the clock drivers of the multiple stages of the clock tree are all arranged on the same die, for example, the first clock path 451 and the second clock path 452 are both arranged on the first die 410, and the first clock path 451 and the second clock path 452 have the same length, then in the case that the driving capability is strong enough, most of the first clock path 451 and the second clock path 452 can be combined, for example, referring to FIG. 5, only the first clock path 451 is arranged, and the first clock path 451 drives the first sequential device 411 located on the first die 410 and the second sequential device 421 located on the second die 420 at the same time. In this case, the last-stage clock driver 4511 in the first clock path 451 is coupled with the clock input end of the first sequential device 411, and also coupled with the clock input end of the second sequential device 421, for example, the last-stage clock driver 4511 in the first clock path 451 is connected with the clock input end of the first sequential device 411 through the interconnection metal line, and the last-stage clock driver in the first clock path 451 is connected with the clock input end of the second sequential device 421 through the inter-die interconnection interface and the metal interconnection line, so that the common path between the clock path of the first sequential device 411 located on the first die 410 and the clock path of the second sequential device 421 located on the second die 420 reaches the maximum, that is, the part between the clock source 440 and the last-stage clock driver in the first clock path 451, and for the non-common path, only the interconnection metal line exists, so that on the one hand, the structure of the clock tree can be simplified, and on the other hand, the fluctuation of the clock skew between the two sequential devices is reduced in the way that the common path between the clock paths of the two sequential devices is as long as possible, and the influence of the cross-die process deviation on the clock signal quality is reduced.

[0051] In other words, for the clock tree arranged on the first die 410, the last-stage clock drivers are used to connect the clock input ends of the sequential devices of the first die 410 and the clock input ends of the sequential devices of the second die 420, wherein part of the last-stage clock drivers are electrically connected with the clock input ends of the sequential devices of the first die 410, part of the last-stage clock drivers are electrically connected with the clock input ends of the sequential devices of the second die 420, and part of the last-stage clock drivers can be electrically connected with the clock input ends of the sequential devices of the first die 410 and the clock input ends of the sequential devices of the second die 420 at the same time. The chip system further comprises a clock source 440, which is used to output a clock signal to the clock tree, and the clock tree transmits the clock signal after driving and amplifying to the sequential devices on each die in the chip system. In the embodiment of the application, the clock source 440 can be a phase-locked loop, and the clock source 440 can be arranged on the first die 410.

[0052] In some other possible implementation manners, the clock source 440 can also be arranged on other dies, for example, the clock source 440 is arranged on the second die 420, and is propagated to the first die 410 through the inter-die interconnection interface and the interconnection metal line. Since the clock tree is arranged on the first die, the propagation path of the clock source from the second die to the first die is a common path of all clock paths, and the influence of the cross-die process deviation on the clock signal quality of the chip system can also be reduced in the case that the clock tree is arranged on the first die.

[0053] Referring to FIG. 6, the clock scheme provided by the embodiment of the present application arranges the clock tree structures originally distributed on each die on one die of the 3D chip, referred to as a clock die, for example, arranges the clock tree structures originally distributed on different dies on the first die. For the sequential devices on the non-clock die, the clock tree on the clock die drives through the inter-die interconnection interface and the interconnection metal line. Since the in-die process deviation is relatively controllable, the clock skew of the clock signals obtained by the sequential devices on different dies due to process fluctuation is relatively small. For example, a certain clock path is connected to the sequential devices on the clock die and the non-clock die, and the last-stage clock driver in the clock path is connected to the clock input end of the sequential device on the non-clock die through the inter-die interconnection interface and the interconnection metal line. The interconnection metal line is little affected by the process fluctuation, and thus the influence of the cross-die process deviation on the clock signal of the chip system can be reduced.

[0054] For a chip system with a complex structure, it can have more than one clock signal, and thus different clock trees can be arranged, for example, the first clock signal is transmitted through the first clock tree, and the second clock signal is transmitted through the second clock tree. For the first clock signal and the first clock tree, the first clock tree can be arranged on the first die, and the first die is used as the clock die of the first clock signal. For the second clock signal and the second clock tree, if the first clock signal and the second clock signal are not synchronous clocks or there is no sequential path between the two clock signals, the second clock tree can also be arranged on the second die, and the second die is used as the clock die of the second clock signal. Alternatively, in a possible implementation manner, the first clock tree and the second clock tree can also be arranged on the first die, and the first die is used as the clock die of the first clock signal and the second clock signal.

[0055] In the above examples, the chip system is taken as an example of the first die and the second die stacked to form a 3D structure, the first die and the second die can also be arranged in a horizontal direction, or the chip system can include multiple dies arranged in a horizontal direction and multiple dies stacked in a vertical direction, and the clock tree is arranged on one of the dies, so as to reduce the influence of the cross-die process deviation on the clock signal.

[0056] The embodiment of the present application also provides a clock tree generation method. In a chip design, the implementation of the clock tree is referred to as clock tree synthesis (CTS), which is usually performed after placement and before routing. The method provided by the embodiment of the present application is mainly used in this stage.

[0057] Referring to FIG. 7, the method provided by the embodiment of the present application includes the following steps.

[0058] S1: Arranging a timing device.

[0059] In this stage, all standard cells (including combinational logic, timing logic devices, etc.) contained in the initial input are placed on different positions of the die through a line length and timing driving algorithm, so as to ensure better performance and power consumption as much as possible, and then the positions of the standard cells are fine-tuned (legalization) to meet the grid requirements of the process manufacturing.

[0060] S2: Merging a clock input end.

[0061] Since the chip system provided by the present application sets most of the structure of the clock tree on one clock die, after the layout of the standard cells and other devices is completed, the clock input ends of the timing devices on the non-clock die need to be merged to the inter-die interconnection interface between the clock die and the non-clock die, and the inter-die interconnection interface is regarded as a clock tree sink on the clock die. Since there is only an interconnection metal line between the clock input end of the timing device on the non-clock die and the inter-die interconnection interface, the delay of the interconnection metal line can be calculated in advance and used as an input parameter of the clock tree synthesis, which is beneficial to the clock tree of the timing devices between multiple dies.

[0062] S3: Clock tree synthesis.

[0063] The clock tree synthesis is to propagate the clock signal to all the timing devices in the chip in a way that meets the physical design rules by routing and adding buffers, inverters and the like in the clock path. In the embodiments of the present application, the clock input terminals of all the timing devices are combined on one die, or on the inter-die interconnection interface of the die and other dies. The inter-die interconnection interface is also regarded as the terminal point of the clock tree, and the clock tree synthesis is performed uniformly. Therefore, the standard cells and interconnection metal lines used in the clock tree synthesis can be limited to the one die, i.e., the clock die. The clock input terminals of all the timing logic on other dies, i.e., non-clock dies, are connected to the clock die through the interconnection metal lines and the inter-die interconnection interface, and the inter-die interconnection interface includes at least one of the mixed bonding and the through silicon via.

[0064] After the clock tree synthesis is completed, the clock input terminals of the timing devices of the clock die are driven by the clock tree on the clock die, and the clock input terminals of the timing devices on the non-clock die are driven by the clock tree on the clock die, the inter-die interconnection interface and the interconnection metal lines of the non-clock die.

[0065] The embodiments of the present application also provide a die, which can be the first die in the foregoing embodiments. The first die includes a multi-stage clock driver. The multi-stage clock driver can be connected in a tree shape. A first-stage clock driver in the multi-stage clock driver is configured to receive a clock signal. A last-stage clock driver in the multi-stage clock driver is configured to be coupled with a clock input terminal of a timing device to output the clock signal to the timing device. The timing device can be located on the first die, or can also be located outside the first die.

[0066] For example, the last-stage clock driver in the multi-stage clock driver includes a first clock driver. The first clock driver is coupled with the clock input terminal of the timing device on the second die to output the clock signal to the timing device on the second die. For example, the first clock driver is disposed on the first die, and the timing device driven by the first clock driver is located on the second die. The first clock driver can be coupled with the clock input terminal of the timing device on the second die through the inter-die interconnection interface and the interconnection metal lines, for example, through the inter-die interconnection interface of the through silicon via or the mixed bonding and the interconnection metal lines. In this way, the clock tree can be avoided from being dispersed on different dies, and the clock quality can be avoided from being affected by the process deviation across the dies.

[0067] The first die also includes a plurality of timing devices. The first clock driver is also coupled with the clock input terminal of the timing device of the first die to output the clock signal to the timing device of the first die. For example, the first clock driver is coupled with the input terminal of the timing device of the first die through the interconnection metal lines.

[0068] It can be seen that the clock tree is arranged in the first die according to the embodiment of the application, and the clock tree can be coupled to the timing device on the second die directly without passing through other clock drivers, and the clock tree of the first die is connected to the timing device on the second die only through the inter-die interconnection interface and the interconnection metal line, so that the influence of the cross-die process deviation on the clock signal can be reduced.

[0069] The embodiment of the application further provides another kind of die, for example, the second die in the foregoing embodiment, the second die includes a plurality of timing devices, and a clock input end of the timing device is used for being coupled to the clock tree arranged in the first die to receive a clock signal, for example, the clock input end of the timing device on the second die can be coupled to the clock tree arranged in the first die through the interconnection metal line and the inter-die interconnection interface.

[0070] The embodiment of the application further provides an electronic device, which includes a circuit board and the chip system provided by the foregoing embodiment of the application, and the chip system is arranged on the circuit board.

[0071] Among them, the beneficial effects that the first die, the second die and the electronic device provided by the embodiment of the application can achieve can refer to the beneficial effects of the chip system provided by the foregoing embodiment of the application, which will not be described here.

[0072] The above is only a specific embodiment of the application, but the protection scope of the application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A chip system, characterized by The chip system includes a first die and at least one second die, the first die and the second die coupled through an inter-die interconnect interface; The chip system includes a clock tree disposed in the first die, the second die including a plurality of timing devices, clock inputs of the timing devices of the second die coupled through the inter-die interconnect interface and interconnect metal lines to the clock tree.

2. The chip system according to claim 1, characterized by The first die includes a plurality of timing devices, clock inputs of the timing devices of the first die coupled through interconnect metal lines to the clock tree.

3. The chip system according to claim 1 or 2, characterized by The clock tree includes a plurality of clock drivers, a first clock driver of the plurality of clock drivers configured to connect to a clock source, a last clock driver of the plurality of clock drivers configured to couple to clock inputs of the timing devices of the first die and the timing devices of the second die.

4. The chip system according to claim 3, characterized by The clock driver includes an inverter or a buffer.

5. The chip system according to any one of claims 1 to 4, characterized in that Further comprising a clock source, the clock source disposed on the first die or the second die.

6. A first die, characterized by, The first die includes a plurality of clock drivers, a first clock driver of the plurality of clock drivers configured to receive a clock signal, a last clock driver of the plurality of clock drivers configured to couple to clock inputs of the timing devices of the first die and the second die to output the clock signal to the timing devices.

7. The first die of claim 6, wherein, The last clock driver is configured to couple to clock inputs of the timing devices of the second die through the inter-die interconnect interface and interconnect metal lines.

8. The first die of claim 6 or 7, wherein, The last clock driver is configured to couple to clock inputs of the timing devices of the first die through interconnect metal lines to output the clock signal.

9. A second die, wherein: The second die includes a plurality of timing devices, clock inputs of the timing devices configured to couple to a clock tree disposed in the first die to receive a clock signal.

10. The second die of claim 9, wherein, The timing devices are configured to couple to the clock tree disposed in the first die through interconnect metal lines and the inter-die interconnect interface.

11. An electronic device, comprising: A circuit board and a chip system as claimed in any one of claims 1 to 5, the chip system disposed on the circuit board.

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