Semiconductor device and manufacturing method therefor, integrated circuit, and electronic device

Abstract

Embodiments of the present application relate to the technical field of electronics, and provide a semiconductor device and a manufacturing method therefor, an integrated circuit, and an electronic device. The semiconductor device comprises a drift layer, a well layer, an emitter, a gate, a dummy gate, a first insulating film layer, and a second insulating film layer. A first trench and a second trench are formed in the well layer, the first trench and the second trench are spaced apart from each other, the well layer and the portion of the drift layer close to the well layer are arranged around the first trench and the second trench, and the side surface of the emitter close to the first trench serves as the inner wall of the first trench. The gate fills the first trench, and the dummy gate fills the second trench. The first insulating film layer is arranged between the gate and the inner wall of the first trench, and the second insulating film layer is arranged between the dummy gate and the inner wall of the second trench. The thickness of at least a portion of the second insulating film layer is greater than the thickness of the portion of the first insulating film layer in contact with a channel region. The semiconductor device has a small parasitic capacitance, a minimal voltage tailing issue, and low turn-on loss.

Description

Semiconductor device and manufacturing method thereof, integrated circuit, and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411377897.X, filed on September 29, 2024, and entitled "Semiconductor device and manufacturing method thereof, integrated circuit, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, and in particular to a semiconductor device and manufacturing method thereof, an integrated circuit, and an electronic device. BACKGROUND

[0003] An insulated gate bipolar transistor (IGBT) is a composite full-control voltage-driven power semiconductor device composed of a bipolar junction transistor (BJT) and a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0004] IGBTs include planar gate and trench gate types, where the channel in the trench gate IGBT changes from lateral to longitudinal, the carrier concentration on the emitter side is improved, and the hole flow path is optimized, so that the on-state voltage drop of the trench gate IGBT is reduced and the anti-latch-up capability is enhanced, thereby making the trench gate IGBT more and more popular.

[0005] However, with the development of electronic device technology, the size of IGBT is gradually miniaturized, which greatly affects the electrical performance of the trench gate IGBT, and how to improve the electrical performance of the trench gate IGBT has become one of the technical problems to be solved at present. SUMMARY

[0006] The embodiments of the present application provide a semiconductor device and manufacturing method thereof, an integrated circuit, and an electronic device, which aims to reduce the parasitic capacitance generated in the semiconductor device, thereby reducing the turn-on loss of the semiconductor device and improving its electrical performance.

[0007] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a semiconductor device is provided, which includes a drift layer, a well layer, an emitter, a gate and a pseudo gate, a first insulating film layer, and a second insulating film layer.

[0009] The well layer is arranged on the drift layer, the emitter is embedded in the well layer, and the emitter extends from a first surface of the well layer into the well layer, the first surface being a surface of the well layer away from the drift layer; on a side of the first surface of the well layer, a first groove and a second groove are arranged along a direction perpendicular to the first surface, the first groove and the second groove are arranged in a spaced manner, the well layer and a portion of the drift layer close to the well layer are arranged around the first groove and the second groove, and a side of the emitter close to the first groove serves as an inner wall of the first groove. The gate is filled in the first groove, and a first insulating film layer is arranged between the gate and the inner wall of the first groove; and the dummy gate is filled in the second groove, and a second insulating film layer is arranged between the dummy gate and the inner wall of the second groove.

[0010] At least part of the second insulating film layer has a thickness greater than that of a portion of the first insulating film layer in contact with the channel region; the channel region is a portion of the well layer between the emitter and the drift layer.

[0011] In the semiconductor device provided by the embodiments of the present application, the insulating film layer between the gate and the channel region has a relatively thin thickness, so that the channel region can quickly respond to the control of the gate, the turn-on rate and the response speed of the semiconductor device are accelerated, the input impedance is improved, the device loss is reduced, and the electrical performance of the semiconductor device is optimized; meanwhile, at least part of the second insulating film layer has a relatively thick thickness, so that the distance between the dummy gate and the well layer and the distance between the dummy gate and the drift layer are increased, the parasitic capacitance is reduced, the overall parasitic capacitance of the semiconductor device is reduced without affecting the gate control effect of the gate, the tailing effect of the semiconductor device in the turn-on process is reduced, the turn-on loss of the semiconductor device is reduced, and the electrical performance of the semiconductor device is optimized.

[0012] In a possible implementation manner of the first aspect, the thickness of the first insulating film layer is the same at different positions in a cross section of the first insulating film layer perpendicular to a second direction; the second direction is a length extension direction of the first groove and the second groove, and the second direction intersects with the arrangement direction of the first groove and the second groove.

[0013] That is, the thickness of the first insulating film layer is the same at different positions in the same cross section (a cross section perpendicular to the length direction), for example, the thickness of the portion of the first insulating film layer at the bottom of the first groove and the thickness of the portion of the first insulating film layer at the wall of the first groove are the same in the same cross section, so that the distribution of the carriers controlled by the gate near the inner wall of the first groove is more uniform, so that the voltage or other factors (such as parasitic capacitance) borne by the portion of the position are more uniform, so that the controllability of the semiconductor device and the product yield can be improved. In addition, the one-piece forming of the first insulating film layer can be realized, and the preparation difficulty of the semiconductor device is reduced.

[0014] In a possible implementation manner of the first aspect, the average thickness of the second insulating film layer is greater than the average thickness of the first insulating film layer, so that the parasitic capacitance between the pseudo gate and the well layer and between the pseudo gate and the drift layer can also be reduced without affecting the gate control effect of the gate, thereby reducing the overall parasitic capacitance of the semiconductor device, reducing the tailing effect of the semiconductor device in the on process, reducing the on loss of the semiconductor device, and optimizing the electrical performance of the semiconductor device.

[0015] In a possible implementation manner of the first aspect, a plurality of second grooves are arranged at intervals on the side of the first surface of the well layer and are perpendicular to the first surface. The thickness of the first insulating film layer is the same at different positions, and the thickness of the second insulating film layer in the same second groove is the same at different positions.

[0016] That is, the thickness of the first insulating film layer is uniformly arranged, and the thickness of the second insulating film layer is uniformly arranged, which can ensure that the parameters around the gate are uniformly distributed, for example, the carrier distribution is uniform, the voltage received is relatively uniform, and the like, and can also ensure that the parameters around the pseudo gate are uniformly distributed, for example, the parasitic capacitance is uniformly distributed, thereby improving the reliability of the semiconductor device. At the same time, the thickness of the second groove is designed to be greater than the thickness of the first groove, thereby reducing the parasitic capacitance of the semiconductor device.

[0017] In a possible implementation manner of the first aspect, the thickness of the second insulating film layer in each second groove is greater than the thickness of the first insulating film layer, so that the parasitic capacitance between the plurality of pseudo gates and the well layer and between the pseudo gate and the drift layer can be reduced, thereby further optimizing the electrical performance of the semiconductor device.

[0018] In a possible implementation manner of the first aspect, the thickness of the second insulating film layer in the plurality of second grooves is the same, thereby facilitating the synchronous preparation of the second insulating film layer in the plurality of second grooves and reducing the preparation difficulty.

[0019] In a possible implementation manner of the first aspect, the thickness of the second insulating film layer in the second groove adjacent to the first groove is the same as the thickness of the first insulating film layer, and the thickness of the second insulating film layer in the second groove spaced from the first groove by at least one second groove is greater than the thickness of the first insulating film layer.

[0020] That is, the thickness of the second insulating film layer in the second groove near the first groove is small, and only the thickness of the second insulating film layer in the second groove away from the first groove is increased, so that the depth of the part of the well layer that can be controlled by the gate is consistent while reducing the overall parasitic capacitance of the semiconductor device, for example, the depth of the well layer between the first groove and the second groove is relatively uniform, thereby avoiding the influence of the thickening of the second insulating film layer on the gate control effect of the gate and improving the structural reliability of the semiconductor device.

[0021] In a possible implementation manner of the first aspect, the semiconductor device includes a plurality of emitters, the plurality of emitters are sequentially and spaced apart along a second direction, and each of the plurality of emitters is in contact with the first insulating film layer. The first insulating film layer includes a plurality of first sub-layers and a plurality of second sub-layers, the plurality of first sub-layers and the plurality of second sub-layers are alternately arranged along the second direction, and the first sub-layers are in contact with the emitters. The second insulating film layer includes a plurality of third sub-layers and a plurality of fourth sub-layers, the plurality of third sub-layers and the plurality of fourth sub-layers are alternately arranged along the second direction; the third sub-layers are arranged in a first direction together with the first sub-layers, and the fourth sub-layers are arranged in the first direction together with the second sub-layers; and the first direction is the arrangement direction of the first trenches and the second trenches.

[0022] The thickness of the first sub-layers and the third sub-layers is the same, the thickness of the second sub-layers and the fourth sub-layers is the same, and the thickness of the second sub-layers and the fourth sub-layers is greater than the thickness of the first sub-layers and the third sub-layers.

[0023] Through the design, the synchronous preparation of the first sub-layers and the third sub-layers and the synchronous preparation of the second sub-layers and the fourth sub-layers can be facilitated, that is, the insulating material can be sequentially deposited along the second direction to form the first insulating film layer and the second insulating film layer, so that the synchronous preparation of the part of the first insulating film layer that does not participate in gate control and the part of the second insulating film layer that has a relatively large thickness can be simultaneously implemented. In this way, the parasitic capacitance between the gate and the well layer or the parasitic capacitance between the gate and the drift layer can be reduced without affecting the gate control effect of the gate, and the parasitic capacitance of the semiconductor device as a whole can be further reduced, and the electrical performance of the semiconductor device can be optimized.

[0024] In a possible implementation manner of the first aspect, the first insulating film layer includes a plurality of first sub-layers, a plurality of second sub-layers, and a fifth sub-layer, the fifth sub-layer is arranged on the same side of the plurality of first sub-layers and the plurality of second sub-layers along the second direction, and the fifth sub-layer is spaced apart from the first sub-layers by at least one second sub-layer. The second insulating film layer includes a plurality of third sub-layers, a plurality of fourth sub-layers, and a sixth sub-layer, the sixth sub-layer is arranged on the same side of the plurality of third sub-layers and the plurality of fourth sub-layers along the second direction, the sixth sub-layer is spaced apart from the third sub-layers by at least one fourth sub-layer, and the sixth sub-layer and the fifth sub-layer are arranged in the first direction.

[0025] The thickness of the first sub-layers, the second sub-layers, the third sub-layers, and the fourth sub-layers is the same, the thickness of the fifth sub-layer and the sixth sub-layer is the same, and the thickness of the fifth sub-layer and the sixth sub-layer is greater than the thickness of the first sub-layers, the second sub-layers, the third sub-layers, and the fourth sub-layers.

[0026] By the design, the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer can be conveniently prepared synchronously, so that the depths of different positions of the portion of the well layer close to the gate are substantially the same, for example, the depth of the portion of the well layer for forming the channel is substantially the same as the depth of the portions on both sides of the channel region along the second direction, so that the influence on the electrical performance of the channel region caused by the different depths is avoided, meanwhile, the fifth sub-layer and the sixth sub-layer are prepared synchronously, the preparation difficulty is reduced, and the parasitic capacitance between the gate and the well layer or between the gate and the drift layer and the parasitic capacitance between the dummy gate and the well layer or between the dummy gate and the drift layer can be reduced without affecting the gate control effect of the gate, the parasitic capacitance of the whole semiconductor device is further reduced, and the electrical performance thereof is optimized.

[0027] In a possible implementation manner of the first aspect, a thickness of at least part of the second insulating film layer is 1.5 times to 3 times a thickness of the portion of the first insulating film layer in contact with the channel region. By setting the thickness of the portion with a relatively large thickness in the insulating film layers (the first insulating film layer and the second insulating film layer) to be 1.5 times to 3 times the thickness of the portion with a relatively small thickness, the electrical performance of the semiconductor device can be flexibly adjusted.

[0028] In a possible implementation manner of the first aspect, a dielectric constant of the second insulating film layer is less than or equal to a dielectric constant of the first insulating film layer. Thus, the parasitic capacitance generated between the dummy gate and the well layer or between the gate and the drift layer can be further reduced without affecting the gate control performance of the gate, so that the parasitic capacitance of the whole semiconductor device is reduced, the voltage tailing problem is alleviated, and the turn-on loss of the semiconductor device is reduced.

[0029] In a second aspect, a preparation method of a semiconductor device is provided, and the preparation method comprises:

[0030] The first trench and the second trench are formed on one side surface of the semiconductor layer. The first insulating film layer is formed on the inner wall of the first trench, and the second insulating film layer is formed on the inner wall of the second trench. The gate and the dummy gate are formed. The gate is filled in the first trench, and the dummy gate is filled in the second trench. The semiconductor layer is doped to form the drift layer, the well layer and the emitter. The well layer is arranged on the drift layer. The emitter is embedded in the well layer, and the emitter extends from the surface of the well layer away from the drift layer into the well layer. The portions of the well layer and the drift layer close to the well layer are arranged around the first trench and around the second trench, and the side surface of the emitter close to the first trench serves as the inner wall of the first trench.

[0031] In the second aspect, a thickness of at least part of the second insulating film layer is greater than a thickness of the portion of the first insulating film layer in contact with the channel region. The channel region is the portion of the well layer between the emitter and the drift layer.

[0032] The preparation method provided by the embodiment can form a second insulating film layer with a relatively large thickness, so that the parasitic capacitance of the formed semiconductor device in the conduction process is small, and the voltage tailing problem is alleviated, thereby effectively reducing the turn-on loss.

[0033] In a possible implementation of the second aspect, forming the first insulating film layer and the second insulating film layer comprises:

[0034] forming a protection layer on the inner wall of the first trench; forming a first oxide layer on the inner wall of the second trench; removing the protection layer; forming a second oxide layer on the inner wall of the first trench and on the first oxide layer; the part of the second oxide layer on the inner wall of the first trench serves as the first insulating film layer, and the part of the second oxide layer in the second trench serves as the second insulating film layer together with the first oxide layer.

[0035] That is, the embodiment can make the second insulating film layer have two oxide layers (the first oxide layer and the second oxide layer), and the first insulating film layer have only one oxide layer (the second oxide layer), so as to ensure that the thickness of the second insulating film layer is greater than the thickness of the first insulating film layer, so that the first insulating film layer participating in gate control has a relatively thin thickness, thereby guaranteeing the gate control effect, and the second insulating film layer not participating in gate control has a relatively thick thickness, thereby reducing the parasitic capacitance in the semiconductor device and optimizing the electrical performance thereof.

[0036] In a third aspect, an integrated circuit is provided, which comprises an electronic device and the semiconductor device provided in any one of the embodiments of the first aspect, and the electronic device is electrically connected with the semiconductor device.

[0037] In a fourth aspect, an electronic device is provided, which comprises a circuit board and the semiconductor device provided in any one of the embodiments of the first aspect or the integrated circuit provided in the embodiments of the third aspect, and the semiconductor device or the integrated circuit is arranged on the circuit board.

[0038] The technical effects brought by the integrated circuit in the third aspect and the electronic device in the fourth aspect can refer to the technical effects brought by the structural design of the semiconductor device in the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0040] FIG. 2 is another structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0041] FIG. 3 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0042] FIG. 4 is a top view of a semiconductor device according to an embodiment of the present application;

[0043] FIG. 5 is a cross-sectional view along the section line A-A' in FIG. 4;

[0044] FIG. 6 is a cross-sectional view along the section line B-B' in FIG. 4;

[0045] FIG. 7 is another top view of a semiconductor device according to an embodiment of the present application;

[0046] FIG. 8 is a cross-sectional view of the semiconductor device corresponding to FIG. 7;

[0047] FIG. 9 is another top view of a semiconductor device according to an embodiment of the present application;

[0048] FIG. 10 is a cross-sectional view of the semiconductor device corresponding to FIG. 9;

[0049] FIG. 11 is a simulation analysis diagram of a semiconductor device according to an embodiment of the present application;

[0050] FIG. 12 is another simulation analysis diagram of a semiconductor device according to an embodiment of the present application;

[0051] FIG. 13 is another top view of a semiconductor device according to an embodiment of the present application;

[0052] FIG. 14 is a cross-sectional view along the section line C-C' in FIG. 13;

[0053] FIG. 15 is a cross-sectional view along the section line D-D' in FIG. 13;

[0054] FIG. 16 is another top view of a semiconductor device according to an embodiment of the present application;

[0055] FIG. 17 is a cross-sectional view along the section line E-E' in FIG. 16;

[0056] FIG. 18 is a cross-sectional view along the section line F-F' in FIG. 16;

[0057] FIG. 19 is another top view of a semiconductor device according to an embodiment of the present application;

[0058] FIG. 20 is a cross-sectional view along the section line H-H' in FIG. 19;

[0059] FIG. 21 is a cross-sectional view along the section line I-I' in FIG. 19;

[0060] FIGS. 22 and 23 are flow charts of manufacturing a semiconductor device according to an embodiment of the present application;

[0061] FIGS. 24-41 are cross-sectional views corresponding to respective manufacturing steps of a semiconductor device. DETAILED DESCRIPTION

[0062] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0063] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only intended to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0064] Unless otherwise required by the context, the term "comprising" is interpreted to mean "including, but not limited to" throughout the specification and claims. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary", or "some examples" are intended to mean that the particular feature, structure, material, or characteristic being described in connection with this embodiment or example includes at least one embodiment or example of the present application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials, or characteristics can be included in any suitable manner in any one or more embodiments or examples.

[0065] Hereinafter, the terms "first", "second", and the like are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0066] Connection / connection: can refer to a mechanical connection relationship or a physical connection relationship, that is, A and B are connected or A and B are connected, which means that there is a fastening member (such as a screw, a bolt, a rivet, etc.) between A and B, or A and B are in contact with each other and A and B are difficult to separate, wherein A and B can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium.

[0067] Coupled: can be understood as directly coupled and / or indirectly coupled, and "coupled connection" can be understood as directly coupled connection and / or indirectly coupled connection. Directly coupled can also be referred to as "electrically connected", which is understood as that the components are in direct or indirect physical contact and electrically conductive, for example, in the form of connection between different components in a circuit structure through a physical circuit such as copper foil or wire of a printed circuit board (PCB) that can transmit electrical signals; "indirectly coupled" can be understood as that two conductors are electrically conductive through a space / without contact. In an embodiment, indirectly coupled can also be referred to as capacitive coupling, for example, through the coupling between the gap between two conductive parts to form an equivalent capacitor to achieve signal transmission.

[0068] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0069] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0070] As used herein, "parallel", "perpendicular", "equal" include the stated condition and a condition approximately the same as the stated condition, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the error related to the measurement of the specific quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two is less than or equal to 5% of either.

[0071] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0072] In addition, the scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the appearance of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0073] The electronic device provided by the embodiments of the present application may, for example, be a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, or a terminal device of different types of user equipment; the electronic device may, for example, also be a power converter such as a boost-buck converter, an electric energy conversion device such as an uninterruptible power supply, a charging device, or a photovoltaic power conversion device; the electronic device may, for example, also be a network device such as a base station. The embodiments of the present application do not specially limit the specific form of the electronic device.

[0074] FIG. 1 and FIG. 2 are structural schematic diagrams of an electronic device provided by an embodiment of the present application.

[0075] In some embodiments, as shown in FIG. 1, the electronic device 1000 may, for example, include an integrated circuit 100 and a circuit board 200, and the integrated circuit 100 may, for example, be disposed on the circuit board 200.

[0076] For example, the circuit board 200 may, for example, be a printed circuit board (PCB).

[0077] It can be understood that the structure of the electronic device 1000 shown in FIG. 1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may, for example, include more or fewer components than those shown in FIG. 1, or may, for example, combine certain components shown in FIG. 1, or may, for example, be arranged differently from the components shown in FIG. 1.

[0078] The embodiments of the present application also provide an integrated circuit 100.

[0079] For example, as shown in FIG. 1, the integrated circuit 100 may, for example, include a logic circuit 101, an analog circuit 102, a storage circuit 103, and an input-output circuit 104.

[0080] It should be understood that the integrated circuit 100 includes, but is not limited to, the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104. For example, in addition to the aforementioned four circuits, the integrated circuit 100 can also include other types or functions of circuits, or discrete devices.

[0081] In addition, the integrated circuit 100 can include one or more of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104.

[0082] On this basis, the number of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 can include one or more logic circuits 101. The integrated circuit 100 can also include one or more analog circuits 102. The integrated circuit 100 can also include one or more storage circuits 103. The integrated circuit 100 can also include one or more input / output circuits 104.

[0083] As shown in FIG. 1, the integrated circuit 100 can include the semiconductor device 10 and some electronic devices 20. The electronic devices 20 are electrically connected to the semiconductor device 10.

[0084] For example, referring to FIG. 1, the semiconductor device 10 and the electronic devices 20 can be integrated in the logic circuit 101. The semiconductor device 10 and the electronic devices 20 in the logic circuit 101 cooperate with each other to realize the functions such as “and”, “or”, and “not” in the logic circuit 101.

[0085] Alternatively, for example, the semiconductor device 10 can also be integrated in other circuits, such as a power integrated circuit. The present application does not make specific limitations in this regard.

[0086] Alternatively, for example, the semiconductor device 10 can also be provided as a discrete device in the integrated circuit 100, for example, the semiconductor device 10 can be integrated as a power device together with the logic circuit 101, the analog circuit 102, etc. in the integrated circuit 100.

[0087] For example, the electronic devices 20 can be electronic devices such as resistors and capacitors.

[0088] In other embodiments, as shown in FIG. 2, the electronic device 1000 can include the semiconductor device 10 and the circuit board 200, and the semiconductor device 10 is provided on the circuit board 200.

[0089] That is, the semiconductor device 10 can be provided independently as a discrete device on the circuit board 200, or can be integrated in the integrated circuit 100 and then provided on the circuit board 200.

[0090] As an example, referring to FIG. 2, the semiconductor device 10 arranged on the circuit board 200 as a discrete device can also be electrically connected with the plurality of electronic devices 20.

[0091] The embodiment of the present application further provides a semiconductor device 10.

[0092] FIG. 3 is a structural schematic diagram of the semiconductor device 10 provided by the embodiment of the present application, FIG. 4 is a top view of the semiconductor device 10 corresponding to FIG. 3, FIG. 5 is a sectional view along the sectional line A-A' in FIG. 4, and FIG. 6 is a sectional view along the sectional line B-B' in FIG. 4.

[0093] As an example, the semiconductor device 10 can be an IGBT structure, or can be a semiconductor device including an IGBT structure.

[0094] For example, the semiconductor device 10 can be a semiconductor device integrating a diode and an IGBT structure, for example, can be a reverse conduction IGBT (RC-IGBT).

[0095] The diode can include a freewheeling diode (FWD) or a fast recovery diode (FRD).

[0096] As an example, the IGBT structure in the semiconductor device 10 can be a non punch through IGBT (NPT-IGBT), or can be a Field stop IGBT (FS-IGBT).

[0097] As shown in FIG. 3, the semiconductor device 10 can include a drift layer 2C, a well layer 2A, an emitter 2B, a gate 3, a dummy gate 4, a first insulating film layer 51 and a second insulating film layer 52.

[0098] The drift layer 2C is used for passing carriers (holes and electrons), for example, electrons can be emitted by the emitter 2B located on one side of the drift layer 2C, and flow into the drift layer 2C through a channel formed at the interface between the well layer 2A and the first insulating film layer 51, and then diffuse to the injection layer 1 located on the other side of the drift layer 2C (see FIG. 3), to complete the current transmission in the semiconductor device 10. The carriers can also accumulate in the drift layer 2C (as well as the storage region 2E mentioned later), so that the drift layer 2C can participate in the conductance modulation in the conduction process of the semiconductor device 10, and reduce the on-state voltage drop of the semiconductor device 10.

[0099] Exemplarily, the doping type of the drift layer 2C is different from the doping type of the well layer 2A, for example, the drift layer 2C is N-type doped.

[0100] Exemplarily, the doping concentration of the drift layer 2C is less than the doping concentration of the well layer 2A, for example, the doping concentration of the drift layer 2C can be N-.

[0101] Referring to FIG. 3, FIG. 5 and FIG. 6, the well layer 2A can be disposed on the drift layer 2C.

[0102] The well layer 2A is used to form a channel under the control of the gate 3, so as to realize the transmission of carriers between the emitter 2B and the injection layer 1, that is, realize the current transmission of the semiconductor device 10.

[0103] Exemplarily, the doping type of the well layer 2A can be different from the doping type of the drift layer 2C, for example, the well layer 2A can be P-type doped.

[0104] Referring to FIG. 3 and FIG. 5, the emitter 2B is embedded in the well layer 2A, and the emitter 2B extends from a first surface of the well layer 2A into the well layer 2A, wherein the first surface is a surface of the well layer 2A away from the drift layer 2C.

[0105] The emitter 2B is used to generate carriers. For example, when the semiconductor device 10 is turned on, the emitter 2B can generate electrons, and the electrons flow from the emitter 2B through the well layer 2A and the drift layer 2C to the injection layer 1, thereby generating a current.

[0106] Exemplarily, the emitter 2B can be formed by locally implanting impurities (for example, N-type impurities) into the well layer 2A by ion implantation.

[0107] Exemplarily, the doping type of the emitter 2B is different from the doping type of the well layer 2A, for example, the emitter 2B can be N-type doped.

[0108] Exemplarily, the doping concentration of the emitter 2B is greater than the doping concentration of the well layer 2A, for example, the doping concentration of the emitter 2B can be N+.

[0109] Exemplarily, embodiments of the present application do not limit the position of the emitter 2B embedded in the well layer 2A, for example, referring to FIG. 5, the emitter 2B can be embedded only in the part of the well layer 2A close to the first trench U1, or for example, referring to FIG. 8, the emitter 2B can also extend from the first trench U1 to the second trench U2.

[0110] Exemplarily, the drift layer 2C, the well layer 2A and the emitter 2B can be integrally arranged, for example, referring to FIG. 3, the drift layer 2C, the well layer 2A and the emitter 2B can be different portions of a semiconductor layer 2, for example, ion implantation can be performed on different positions of the semiconductor layer 2 to obtain the drift layer 2C, the well layer 2A and the emitter 2B.

[0111] Exemplarily, referring to FIG. 3, the semiconductor layer 2 is arranged on the implanted layer 1.

[0112] Exemplarily, the material of the semiconductor layer 2 is a semiconductor material.

[0113] Exemplarily, the method of forming the semiconductor layer 2 can include, for example, a Metal-Organic Chemical Vapor Deposition (MOCVD) growth method or a Molecular Beam Epitaxy (MBE) growth method, etc.

[0114] Exemplarily, the semiconductor layer 2 can be directly grown on the implanted layer 1, or the semiconductor layer 2 can be first formed on a substrate, then the substrate is thinned and the implanted layer 1 is formed by implanting impurities, or other implementation manners can be used, which are not limited in the present application.

[0115] On the basis of the semiconductor layer 2 including the drift layer 2C, the well layer 2A and the emitter 2B, the semiconductor layer 2 can further include other regions to achieve excellent current transmission of the semiconductor device 10.

[0116] Exemplarily, referring to FIG. 3, FIG. 5 and FIG. 6, the semiconductor layer 2 can further include a buffer region 2D between the drift layer 2C and the implanted layer 1, which buffers the carriers flowing through the drift layer 2C, and is beneficial to reduce the on-state voltage drop and power consumption of the semiconductor device 10.

[0117] Exemplarily, the buffer region 2D has the same doping type as the drift layer 2C.

[0118] Exemplarily, the doping concentration of the buffer region 2D is greater than the doping concentration of the drift layer 2C. For example, the doping concentration of the buffer region 2D can be N.

[0119] Exemplarily, referring to FIG. 3, FIG. 5 and FIG. 6, the semiconductor layer 2 can further include a storage region 2E arranged between the well layer 2A and the drift layer 2C, the N-type doped storage region 2E is used to form a hole barrier to block holes from being quickly extracted by the emitter electrode 7 (see FIG. 8) when the semiconductor device 10 is turned on, and to improve the injection efficiency of the side of the drift layer 2C close to the emitter electrode 7.

[0120] Exemplarily, the doping type of the storage region 2E is the same as the doping type of the drift layer 2C.

[0121] Exemplarily, the doping concentration of the storage region 2E is greater than the doping concentration of the drift layer 2C. For example, the doping concentration of the storage region 2E can be N.

[0122] Exemplarily, referring to FIG. 3, FIG. 5 and FIG. 6, the semiconductor device 10 can further include an injection layer 1 disposed at a side of the drift layer 2C away from the well layer 2A.

[0123] The injection layer 1 is configured to generate carriers. For example, when the semiconductor device 10 is turned on, the injection layer 1 can generate holes, which flow from the injection layer 1 to a side of the drift layer 2C away from the injection layer 1 in the semiconductor device 10, thereby generating a current.

[0124] Exemplarily, the material of the injection layer 1 is a semiconductor material.

[0125] Exemplarily, the doping type of the injection layer 1 is different from the doping type of the drift layer 2C, so as to form a PN junction between the injection layer 1 and the drift layer 2C. For example, the injection layer 1 can be P-type doped.

[0126] Exemplarily, the doping concentration of the injection layer 1 is greater than the doping concentration of the drift layer 2C, thereby facilitating the flow of carriers (e.g. holes) from the injection layer 1 to the drift layer 2C. For example, the doping concentration of the injection layer 1 can be P, or can be P+.

[0127] In the embodiments of the present application, P or P+ means that holes are majority carriers, N-, N+ or N++ means that electrons are majority carriers. In addition, "+" marked on N or P means that the doping concentration is higher than that of the structure without the "+" mark, and "-" marked on N or P means that the doping concentration is lower than that of the structure without the "-" mark. It can be understood that the more "+" marks, the higher the doping concentration, and the more "-" marks, the lower the doping concentration.

[0128] FIG. 7 is another top view of the semiconductor device 10 according to an embodiment of the present application, FIG. 8 is a sectional view of the semiconductor device 10 corresponding to FIG. 7, FIG. 9 is another top view of the semiconductor device 10 according to an embodiment of the present application, and FIG. 10 is a sectional view of the semiconductor device 10 corresponding to FIG. 9.

[0129] As an example, referring to FIG. 8 and FIG. 10, the semiconductor device 10 can further include a collector electrode 6 disposed on the side of the injection layer 1 away from the drift layer 2C and in contact with the injection layer 1, which serves as one of the conductive terminals of the semiconductor device 10 for connecting to an external power source, and which can collect the carriers (e.g. electrons) in the semiconductor device 10 so as to enable the semiconductor device 10 to participate in the current transmission process.

[0130] The injection layer 1 with a higher doping concentration can form a good ohmic contact with the collector electrode 6, thereby reducing the turn-on loss of the semiconductor device 10 and improving the electrical performance of the semiconductor device 10.

[0131] As an example, referring to FIG. 8 and FIG. 10, the semiconductor device 10 can further include an emitter electrode 7 disposed on the side of the semiconductor layer 2 away from the injection layer 1 and in contact with the emitter 2B. The emitter electrode 7 serves as another conductive terminal of the semiconductor device 10 for connecting to an external power source so as to excite the emitter 2B to generate electrons, thereby forming a current path between the emitter 2B and the collector electrode 6 in the semiconductor device 10 and realizing the current transmission of the semiconductor device 10.

[0132] The emitter 2B with a higher doping concentration can form a good ohmic contact with the emitter electrode 7, thereby reducing the turn-on loss of the semiconductor device 10 and improving the electrical performance of the semiconductor device 10.

[0133] As an example, the emitter electrode 7 can be in a planar contact with the semiconductor layer 2 (e.g. the well layer 2A in the semiconductor layer 2), for example, similar to the contact between the injection layer 1 and the semiconductor layer 2, the emitter electrode 7 can be laid on the surface of the semiconductor layer 2 so as to be in contact with the emitter 2B in the semiconductor layer 2.

[0134] Alternatively, as an example, referring to FIG. 8 and FIG. 10, the emitter electrode 7 can also be embedded in the semiconductor layer 2 (e.g. the well layer 2A in the semiconductor layer 2) and in contact with the semiconductor layer 2, for example, referring to FIG. 8 and FIG. 10, a groove K can be formed on the side surface of the semiconductor layer 2 where the emitter 2B is located, the groove K exposes at least the side surface of the emitter 2B and part of the surface of the well layer 2A, and at least part of the emitter electrode 7 is embedded in the groove K so as to be in contact with the emitter 2B and the well layer 2A.

[0135] Exemplarily, the emitter electrode 7 can be arranged on a part of the surface of the semiconductor layer 2, for example, the emitter electrode 7 can be arranged only on the region where the emitter 2B of the semiconductor layer 2 is located, or exemplarily, referring to FIG. 8 and FIG. 10, the emitter electrode 7 can also completely cover the surface (for example, the upper surface in FIG. 8) of the semiconductor layer 2, any arrangement mode capable of realizing the contact between the emitter electrode 7 and the emitter 2B is within the protection scope of the embodiments of the present application, and the embodiments of the present application do not limit this.

[0136] Exemplarily, referring to FIG. 8 and FIG. 10, the emitter electrode 7 also contacts the well layer 2A in the semiconductor layer 2, so that the holes in the well layer 2A can be led out from the emitter electrode 7 during the off process of the semiconductor device 10.

[0137] Exemplarily, referring to FIG. 7, FIG. 8, FIG. 9 and FIG. 10, the well layer 2A can also include a contact region 2A', the doping type of the contact region 2A' is the same as that of the well layer 2A, and the doping concentration of the contact region 2A' is greater than that of the well layer 2A, for example, the doping concentration of the well layer 2A can be P, and the doping concentration of the contact region 2A' can be P+.

[0138] Referring to FIG. 8 and FIG. 10, the well layer 2A contacts the emitter electrode 7 through the contact region 2A', and by arranging the contact region 2A' with high doping concentration, an ohmic contact can be formed between the well layer 2A and the emitter electrode 7, so that the holes gathered in the well layer 2A can be quickly led out through the emitter electrode 7 during the off process of the semiconductor device 10.

[0139] Exemplarily, referring to FIG. 8 and FIG. 10, in the case that the recess K is arranged on the semiconductor layer 2, the contact region 2A' can be arranged on the inner wall of the recess K.

[0140] Exemplarily, referring to FIG. 7 and FIG. 8, the recess K is arranged at least between the first trench U1 and the second trench U2 arranged adjacent to the first trench U1, and the recess K exposes the side surface of the emitter 2B, the contact region 2A' can be arranged on the bottom of the recess K, and at least part of the emitter electrode 7 is filled in the recess K and contacts the side surface of the emitter 2B and the contact region 2A' on the bottom of the recess K, respectively.

[0141] Or exemplarily, referring to FIG. 9 and FIG. 10, the recess K can also be arranged on both sides of the second trench U2, in the semiconductor device 10 with high integration density, the recess K can be etched to form the recess K with the side surface of the second trench U2 as the boundary, so that the width of the recess K can be reduced, and the emitter 2B near the first trench U1 can have sufficient area.

[0142] Exemplarily, referring to FIG. 8 and FIG. 10, the semiconductor device 10 can further comprise a dielectric layer 8, which is arranged at least between the gate 3 and the emitter electrode 7, so as to avoid the problem that the same potential of the gate 3 and the emitter electrode 7 (i.e. the potential of the emitter 2B) leads to the failure of conduction.

[0143] Exemplarily, referring to FIG. 10, the dielectric layer 8 can also be arranged between the dummy gate 4 and the emitter electrode 7, so as to realize the electrical insulation between the dummy gate 4 and the emitter electrode 7.

[0144] Referring to FIG. 3, on the side of the first surface of the well layer 2A, a first trench U1 and a second trench U2 are arranged along the direction perpendicular to the first surface, and the first trench U1 and the second trench U2 are arranged in a spaced manner.

[0145] Wherein, referring to FIG. 3, FIG. 4, FIG. 5 and FIG. 6, the first trench U1 and the second trench U2 are arranged in a spaced manner along a first direction X, and the first direction X is parallel to the injection layer 1.

[0146] Exemplarily, referring to FIG. 3, FIG. 4, FIG. 5 and FIG. 6, the first trench U1 and the second trench U2 can each be in a strip shape, and the length thereof extends along a second direction Y, the second direction Y is parallel to the injection layer 1, and the first direction X and the second direction Y intersect each other, for example, perpendicular to each other.

[0147] Exemplarily, referring to FIG. 3, FIG. 4, FIG. 5 and FIG. 6, the depth direction of the first trench U1 and the second trench U2 is a third direction Z, and the third direction Z can be perpendicular to each of the first direction X and the second direction Y.

[0148] Referring to FIG. 3 and FIG. 5, the part of the well layer 2A and the drift layer 2C close to the well layer 2A is arranged around the first trench U1 and the second trench U2, and the side of the emitter 2B close to the first trench U1 serves as the inner wall of the first trench U1.

[0149] That is, the first trench U1 penetrates the emitter 2B and the well layer 2A, and further penetrates the inside of the drift layer 2C, and the second trench U2 penetrates the well layer 2A, and further penetrates the inside of the drift layer 2C.

[0150] Referring to FIG. 3 and FIG. 5, at least part of the side wall of the first trench U1 belongs to the emitter 2B, and at least part of the side wall of the first trench U1 belongs to the well layer 2A, so as to facilitate the formation of a channel near the side wall of the first trench U1, and at least part of the side wall of the second trench U2 belongs to the well layer 2A, but the second trench U2 does not necessarily need to penetrate the emitter 2B, that is, there is no need to form a channel near the side wall of the second trench U2.

[0151] That is, the first trench U1 is used to form a transistor structure, and the second trench U2 does not form a transistor structure, for example, the second trench U2 can be used to form an isolation structure, so as to realize the isolation between two adjacent transistor structures.

[0152] Exemplarily, the semiconductor device 10 can also be provided with a plurality of first trenches U1 so as to form a plurality of transistor structures.

[0153] Exemplarily, among the plurality of first trenches U1, at least one pair of first trenches U1 arranged adjacently can be provided with at least one second trench U2, so that the transistor structures formed by the at least one pair of first trenches U1 can be separated by the isolation structure formed by the second trench U2, thereby reducing the distribution density of the first trenches U1 (or transistors) and enhancing the short-circuit characteristic of the semiconductor device 10.

[0154] It can be understood that, in the drawings corresponding to the embodiments of the present application, only the structure of one first trench U1 and two second trenches U2 is exemplarily illustrated for the structure of the semiconductor device 10, and the number of the first trenches U1 and the number of the second trenches U2 in the semiconductor device 10 are not limited.

[0155] Referring to FIGS. 3, 4, 5 and 6, the gate 3 is filled in the first trench U1, and the dummy gate 4 is filled in the second trench U2.

[0156] The gate 3 serves as a control terminal of the semiconductor device 10, and is used to transmit a gate signal to the semiconductor device 10 so as to control the formation of a channel near the sidewall of the first trench U1 (for example, in the part of the well layer 2A belonging to the sidewall of the first trench U1), thereby realizing the conduction between the emitter electrode 7 and the collector 6, i.e., realizing the circuit conduction of the semiconductor device 10.

[0157] It can be understood that the part of the well layer 2A between the emitter 2B and the drift layer 2C and close to the gate 3 can form a channel under the control of the gate 3, i.e., the part can serve as a channel region 2' of the semiconductor device 10.

[0158] The dummy gate 4 is filled in the second trench U2, but cannot control the formation of a channel in the well layer 2A.

[0159] Exemplarily, the materials of the gate 3 and the dummy gate 4 can both be metal or alloy materials.

[0160] Exemplarily, the gate 3 and the dummy gate 4 can be integrally formed, and the materials of the two can be the same.

[0161] Exemplarily, the dummy gate 4 can be conductive, for example, the dummy gate 4 can be electrically connected with the emitter electrode 7 (not shown in the figure), for example, no dielectric layer 8 can be arranged between the dummy gate 4 and the emitter electrode 7, or the emitter electrode 7 can be electrically connected with the dummy gate 4 after penetrating through the dielectric layer 8, so that the dummy gate 4 and the emitter electrode 7 have the same potential and serve as a fixed potential.

[0162] Alternatively, for example, the dummy gate 4 can also be electrically connected with the gate 3 (not shown in the figure) so as to adjust the gate junction capacitance of the semiconductor device 10.

[0163] Exemplarily, in the case where the dummy gate 4 is electrically connected with the emitter electrode 7, the second trench U2 can also pass through the emitter 2B (see FIG. 7 and FIG. 8, the emitter 2B is also arranged around the dummy gate 4).

[0164] In the case where the dummy gate 4 is electrically connected with the emitter electrode 7, the dummy gate 4 and the emitter electrode 7 have the same electric potential, thus no voltage difference is generated between the dummy gate 4 and the emitter electrode 7, i.e. no channel is formed in the well layer 2A around the dummy gate 4, thus the dummy gate 4 does not form a transistor whether or not the emitter 2B is arranged around the dummy gate 4, thus in this embodiment, the second trench U2 can pass through the emitter 2B.

[0165] Exemplarily, in the case where the dummy gate 4 is electrically connected with the gate 3, the second trench U2 only passes through the well layer 2A, i.e. the emitter 2B is arranged away from the dummy gate 4 (see FIG. 5, the emitter 2B is not arranged around the dummy gate 4).

[0166] In the case where the dummy gate 4 is electrically connected with the gate 3, the dummy gate 4 shares the gate electric potential, and has a voltage difference with the emitter electrode 7, if the emitter 2B is arranged on the sidewall of the second trench U2, the emitter 2B electrically connected with the emitter electrode 7 forms a voltage difference with the dummy gate 4, which causes the well layer 2A to form a channel under the influence of the dummy gate 4 and the emitter 2B, thus the dummy gate 4 functions as the gate 3, and cannot reduce the distribution density of the transistor structure, thus in this embodiment, the emitter 2B is arranged away from the dummy gate 4.

[0167] Referring to FIG. 3, FIG. 4, FIG. 5 and FIG. 6, the first insulating film layer 51 is arranged between the gate 3 and the inner wall of the first trench U1, and the second insulating film layer 52 is arranged between the dummy gate 4 and the inner wall of the second trench U2.

[0168] The first insulating film layer 51 is used to realize the electrical insulation between the gate 3 and the semiconductor layer 2 (for example, between the gate 3 and the well layer 2A, and between the gate 3 and the emitter 2B, and between the gate 3 and the drift layer 2C), so as to avoid the direct electrical conduction between the gate 3 and the semiconductor layer 2, so that the gate 3 can control the formation of the channel in the well layer 2A.

[0169] The second insulating film layer 52 is used to realize the electrical insulation between the dummy gate 4 and the semiconductor layer 2 (for example, between the dummy gate 4 and the well layer 2A, and between the dummy gate 4 and the drift layer 2C), so as to avoid the electrical connection between the conductive dummy gate 4 and the semiconductor layer 2, which affects the control of the gate 3.

[0170] Exemplarily, the material of the first insulating film layer 51 and the second insulating film layer 52 both has electrical insulation, for example, the material of both can include an oxide with insulation, or can also include a material with high dielectric constant.

[0171] At least part of the second insulating film layer 52 has a thickness greater than that of the part of the first insulating film layer 51 in contact with the channel region 2'.

[0172] That is, the insulating film layer between at least the gate 3 and the channel region 2' has a relatively thin thickness, and part or even all of the second insulating film layer 52 has a relatively thick thickness.

[0173] The thickness of the first insulating film layer 51 is the size of the first insulating film layer 51 in the direction perpendicular to the inner wall of the first trench U1, and the thickness of the second insulating film layer 52 is the size of the second insulating film layer 52 in the direction perpendicular to the inner wall of the second trench U2, that is, the insulating film layer (the first insulating film layer 51 and the second insulating film layer 52) is in a film shape, the insulating film layer is laid along the inner wall of the trench (the first trench U1 and the second trench U2), and the thickness of the target part of the insulating film layer is the size of the insulating film layer in the direction perpendicular to the inner wall of the trench where the target part is arranged, for example, the thickness of the part of the first insulating film layer 51 in contact with the channel region 2' can be the size of the first insulating film layer 51 in the direction perpendicular to the part of the inner wall of the first trench U1 formed by the channel region 2'.

[0174] In the semiconductor device 10 provided by the embodiments of the present application, by arranging the insulating film layer between at least the gate 3 and the channel region 2' to have a relatively thin or normal thickness, the channel region 2' of the well layer 2A can quickly respond to the control of the gate 3, and the turn-on speed and response speed of the semiconductor device 10 can be accelerated or maintained, thereby reducing the device loss and optimizing the electrical performance of the semiconductor device 10, while at the same time, by arranging at least part of the second insulating film layer 52 to have a relatively thick thickness, the distance between the pseudo gate 4 and the semiconductor layer 2 can be increased, and the parasitic capacitance between the gate and the pseudo gate (emitter) and between the collector and the pseudo gate can be reduced, thereby increasing the gate control effect of the gate 3 while reducing the overall parasitic capacitance of the semiconductor device 10, reducing the tailing effect of the semiconductor device 10 in the turn-on process, thereby reducing the turn-on loss of the semiconductor device 10 and optimizing its electrical performance.

[0175] The electrical performance of the semiconductor device 10 provided by the embodiments of the present application is analyzed as follows.

[0176] FIGS. 11 and 12 are simulation analysis diagrams of the semiconductor device 10 provided by the embodiments of the present application, and Table 1 is a summary of the simulation results of the semiconductor device 10.

[0177] Table 1:

[0178] In FIG. 11, VGE refers to the voltage between the gate 3 and the emitter electrode 7, Ig refers to the current of the gate 3, I (pseudo gate) refers to the current flowing through the pseudo gate 4 in the process of turning on the semiconductor device 10, ICE refers to the current between the collector 6 and the emitter electrode 7, and VCE refers to the voltage between the collector 6 and the emitter electrode 7. Referring to FIG. 11, the t0 stage is the charging period of the gate 3, and the variation of the charging charge of the pseudo gate 4 at this stage can be obtained according to the I (pseudo gate) curve, and the charging charge of the capacitor formed between the collector 6 and the pseudo gate 4 can be reflected at the t1 stage.

[0179] As shown in FIG. 12, with the thickening of the second insulating film layer 52 in the semiconductor device 10 (100 nm→400 nm) according to the embodiments of the present application, the slope of the curve corresponding to the voltage between the collector 6 and the emitter electrode 7 (VCE in FIG. 12) of the semiconductor device 10 gradually increases, that is, the VCE curve gradually approaches the ideal curve in FIG. 11, effectively alleviating the voltage tailing problem in the semiconductor device 10. Referring to FIG. 12, with the increase of the thickness of the second insulating film layer 52, the curve of the current between the collector 6 and the emitter electrode 7 (ICE in FIG. 12) and the curve of the voltage between the gate 3 and the emitter electrode 7 (VGE in FIG. 12) are all corrected, that is, these values gradually tend to be ideal, effectively improving the electrical performance of the semiconductor device 10.

[0180] As shown in Table 1, corresponding to the simulation curves in FIG. 12, with the thickening of the second insulating film layer 52, the amount of charge between the collector 6 and the pseudo gate 4 gradually decreases, that is, the parasitic capacitance gradually decreases, thereby gradually reducing the turn-on loss of the semiconductor device 10, reducing the Eon ratio, that is, increasing the performance and efficiency of the semiconductor device 10.

[0181] In some embodiments, as shown in FIGS. 3, 5 and 6, the thickness of the first insulating film layer 51 at different positions in the cross section perpendicular to the second direction Y (i.e., the X-Z cross section) is the same.

[0182] That is, the thickness of the first insulating film layer 51 at different positions in the same cross section (X-Z cross section) is the same, for example, the thickness of the first insulating film layer 51 at the bottom of the first trench U1 and the thickness of the first insulating film layer 51 at the wall of the first trench U1 in one X-Z cross section are the same, so that the distribution of the carriers controlled by the gate 3 near the inner wall of the first trench U1 is more uniform, so that the voltage or other factors (such as parasitic capacitance, etc.) borne by this part of the position are more uniform, so that the controllability and product yield of the semiconductor device 10 can be improved. In addition, the one-piece forming of the first insulating film layer 51 can also be realized, and the difficulty of manufacturing the semiconductor device 10 is reduced.

[0183] FIG. 13 is another top view of the semiconductor device 10 provided by the embodiments of the present application, FIG. 14 is a cross-sectional view along the cross-sectional line C-C' in FIG. 13, and FIG. 15 is a cross-sectional view along the cross-sectional line D-D' in FIG. 13.

[0184] In some embodiments, as shown in FIGS. 4, 5, 6, 13, 14 and 15, the average thickness of the second insulating film layer 52 is greater than the average thickness of the first insulating film layer 51, so that the parasitic capacitance between the pseudo gate 4 and the semiconductor layer 2 or the implanted layer 1 can also be reduced without affecting the gate control effect of the gate 3, so that the overall parasitic capacitance of the semiconductor device 10 is reduced, the tailing effect of the semiconductor device 10 in the on process is reduced, the turn-on loss of the semiconductor device 10 is reduced, and the electrical performance of the semiconductor device 10 is optimized.

[0185] For example, the thickness of the first insulating film layer 51 at different positions can not be uniformly set, and the thickness of the second insulating film layer 52 at different positions can also not be uniformly set, but the average thickness of the second insulating film layer 52 is greater than the average thickness of the first insulating film layer 51, so that the parasitic capacitance between the pseudo gate 4 and the semiconductor layer 2 is reduced without affecting the gate control effect of the gate 3, the overall parasitic capacitance of the semiconductor device 10 is reduced, and the electrical performance of the semiconductor device 10 is optimized.

[0186] Or for example, referring to FIGS. 4, 5, 6, 13, 14 and 15, the thickness of the first insulating film layer 51 at different positions is the same, the thickness of the second insulating film layer 52 at different positions in the same second trench U2 is the same, and the thickness of the second trench U2 is greater than the thickness of the first trench U1.

[0187] That is, the thickness of the first insulating film layer 51 is uniformly set, and the thickness of the second insulating film layer 52 is uniformly set, so that the parameters around the gate 3, such as uniform distribution of carriers and uniform voltage, can be uniformly distributed, and the parameters around the dummy gate 4, such as uniform distribution of parasitic capacitance, can be uniformly distributed, thereby improving the reliability of the semiconductor device 10. At the same time, the thickness of the second trench U2 is designed to be greater than the thickness of the first trench U1, thereby reducing the parasitic capacitance of the semiconductor device 10.

[0188] In some embodiments, referring to FIGS. 4, 5, 6, 13, 14 and 15, the semiconductor device 10 includes a plurality of dummy gates 4, that is, a plurality of second trenches U2 are arranged at intervals on the first surface side of the well layer 2A in a direction perpendicular to the first surface, and the second insulating film layer 52 is arranged on the inner wall of the plurality of second trenches U2.

[0189] Exemplarily, as shown in FIGS. 4, 5 and 6, the thickness of the second insulating film layer 52 in each second trench U2 is greater than the thickness of the first insulating film layer 51, so that the parasitic capacitance between the plurality of dummy gates 4 and the semiconductor layer 2 can be reduced, and the electrical performance of the semiconductor device 10 is further optimized.

[0190] Exemplarily, as shown in FIGS. 4, 5 and 6, the thickness of the second insulating film layer 52 in the plurality of second trenches U2 is the same, so that the synchronous preparation of the second insulating film layer 52 in the plurality of second trenches U2 is facilitated, and the preparation difficulty is reduced.

[0191] Exemplarily, as shown in FIGS. 13, 14 and 15, the thickness of the second insulating film layer 52 in the second trench U2 adjacent to the first trench U1 is the same as the thickness of the first insulating film layer 51, and the thickness of the second insulating film layer 52 in the second trench U2 spaced apart from the first trench U1 by at least one second trench U2 is greater than the thickness of the first insulating film layer 51.

[0192] That is, the thickness of the second insulating film layer 52 in the second trench U2 near the first trench U1 is small, and only the thickness of the second insulating film layer 52 in the second trench U2 away from the first trench U1 is increased, so that the depth of each region in the part of the semiconductor layer 2 controlled by the gate 3 (for example, the part of the semiconductor layer 2 between the first trench U1 and the second trench U2) is the same, for example, the depth of the well layer 2A is uniform, thereby avoiding the influence of the thickening of the second insulating film layer 52 on the gate control effect of the gate 3, and improving the structural reliability of the semiconductor device 10.

[0193] Fig. 16 is another top view of the semiconductor device 10 according to an embodiment of the present application, Fig. 17 is a sectional view along the section line E-E' in Fig. 16, and Fig. 18 is a sectional view along the section line F-F' in Fig. 16.

[0194] In some embodiments, as shown in Fig. 16, the semiconductor device 10 includes a plurality of emitters 2B, which are arranged in sequence along the second direction Y and each of which is in contact with the first insulating film layer 51.

[0195] Each of the emitters 2B can correspond to a transistor structure.

[0196] It can be understood that the portion of the well layer 2A between the adjacent emitters 2B does not belong to the channel region 2' and does not generate a channel, and thus does not participate in the current transmission process of the semiconductor device 10.

[0197] Referring to Fig. 16, the first insulating film layer 51 includes a plurality of first sub-layers 511 and a plurality of second sub-layers 512, which are arranged alternately along the second direction Y, the first sub-layers 511 are in contact with the emitters 2B, i.e., the first sub-layers 511 are the portions of the first insulating film layer 51 corresponding to the channel regions 2', and the second sub-layers 512 are the portions of the first insulating film layer 51 that do not participate in the current transmission.

[0198] For example, referring to Fig. 16, the thickness of the second sub-layers 512 can be greater than the thickness of the first sub-layers 511, i.e., the thickness of the portion of the first insulating film layer 51 that participates in the gate control is relatively thin, and the thickness of the portion of the first insulating film layer 51 that does not participate in the gate control is relatively thick. In this way, the parasitic capacitance between the gate 3 and the semiconductor layer 2 or between the gate 3 and the implanted layer 1 can be reduced without affecting the gate control effect of the gate 3, thereby reducing the overall parasitic capacitance of the semiconductor device 10, reducing the tailing effect of the semiconductor device 10 in the on process, and thus reducing the on loss of the semiconductor device 10 and optimizing the electrical performance thereof.

[0199] Referring to Fig. 16, the second insulating film layer 52 includes a plurality of third sub-layers 521 and a plurality of fourth sub-layers 522, which are arranged alternately along the second direction Y, the third sub-layers 521 are arranged in the first direction X with the first sub-layers 511, and the fourth sub-layers 522 are arranged in the first direction X with the second sub-layers 512.

[0200] That is, the third sub-layers 521 are the portions of the second insulating film layer 52 corresponding to the first sub-layers 511 of the first insulating film layer 51, and the fourth sub-layers 522 are the portions of the second insulating film layer 52 corresponding to the second sub-layers 512 of the first insulating film layer 51.

[0201] Exemplarily, referring to FIG. 17, the first sub-layer 511 and the third sub-layer 521 have the same thickness, referring to FIG. 18, the second sub-layer 512 and the fourth sub-layer 522 have the same thickness, referring to FIG. 16, or referring to FIG. 17 and FIG. 18, the second sub-layer 512 and the fourth sub-layer 522 have a thickness greater than the thickness of the first sub-layer 511 and the third sub-layer 521.

[0202] Through the design, the synchronous preparation of the first sub-layer 511 and the third sub-layer 521 can be facilitated, and the synchronous preparation of the second sub-layer 512 and the fourth sub-layer 522 can be facilitated, that is, the insulating material can be sequentially deposited along the second direction Y to form the first insulating film layer 51 and the second insulating film layer 52, so that the synchronous preparation of the part of the first insulating film layer 51 that does not participate in the gate control and the part of the second insulating film layer 52 that has a relatively large thickness can be simultaneously achieved. At the same time, without affecting the gate control effect of the gate 3, the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the injection layer 1 can be reduced, and the parasitic capacitance between the pseudo gate 4 and the semiconductor layer 2 or the injection layer 1 can be reduced, further reducing the overall parasitic capacitance of the semiconductor device 10 and optimizing the electrical performance thereof.

[0203] FIG. 19 is another top view of the semiconductor device 10 provided by an embodiment of the present application, FIG. 20 is a sectional view along the section line H-H’ in FIG. 19, and FIG. 21 is a sectional view along the section line I-I’ in FIG. 19.

[0204] The sectional view along the section line G-G’ in FIG. 19 can refer to the aforementioned FIG. 17.

[0205] In some embodiments, as shown in FIG. 19, the first insulating film layer 51 includes a plurality of first sub-layers 511, a plurality of second sub-layers 512, and a fifth sub-layer 515. The fifth sub-layer 515 is disposed on the same side of the plurality of first sub-layers 511 and the plurality of second sub-layers 512 along the second direction Y, and the fifth sub-layer 515 is spaced apart from the first sub-layer 511 by at least one second sub-layer 512.

[0206] Referring to FIG. 19, the first sub-layer 511 can be understood as the part of the first insulating film layer 51 that participates in the gate control, for example, the first sub-layer 511 includes the part of the first insulating film layer 51 that contacts the channel region 2’, and the part of the first insulating film layer 51 that contacts the emitter 2B.

[0207] Referring to FIG. 19, the second sub-layer 512 and the fifth sub-layer 515 are both parts of the first insulating film layer 51 that do not participate in the gate control.

[0208] As shown in FIG. 19, the second sub-layer 512 can be understood as a portion of the first insulating film layer 51 that is not involved in the gate control and is adjacent to the first sub-layer 511 and has a preset length (a size in the second direction Y). The preset length (i.e., the length of the second sub-layer 512) can be the distance between two adjacent emitter electrodes 2B in the second direction Y.

[0209] For example, the second sub-layer 512 can include a portion of the first insulating film layer 51 between two adjacent emitter electrodes 2B in the second direction Y, and can also include a portion of the first insulating film layer 51 on both sides of the first sub-layer 511 and within the preset length.

[0210] As shown in FIG. 19, the fifth sub-layer 515 can be understood as a portion of the first insulating film layer 51 that is away from the first sub-layer 511. For example, the fifth sub-layer 515 can be a portion of the first insulating film layer 51 that is not involved in the gate control and is spaced apart from the first sub-layer 511 by the aforementioned preset length. For example, the fifth sub-layer 515 can be a portion above the first second sub-layer 512 from top to bottom in FIG. 19, so that the fifth sub-layer 515 is arranged away from the first sub-layer 511 relative to the second sub-layer 512.

[0211] It can be understood that the fifth sub-layer 515 can also be arranged below in FIG. 19. FIG. 19 is exemplary and does not limit the number and size of the fifth sub-layer 515.

[0212] For example, the thickness of the second sub-layer 512 can be the same as the thickness of the first sub-layer 511. The thickness of the fifth sub-layer 515 can be greater than the thickness of the first sub-layer 511 and the second sub-layer 512. That is, in the first insulating film layer 51, the thickness of the portion involved in the gate control is thin, and the thickness of the portion around the first sub-layer 511 in the portion not involved in the gate control is also thin. Only the thickness of the portion not involved in the gate control and away from the first sub-layer 511 is thick. The thickness of the second sub-layer 512 is the same as the thickness of the first sub-layer 511, which can ensure that the depths of the various regions in the portion of the semiconductor layer 2 close to the gate 3 are substantially the same. For example, the depth of the portion of the well layer 2A for forming the channel (i.e., the portion of the well layer 2A in contact with the first sub-layer 511) is substantially the same as the depth of the portion on both sides of the channel region 2’ in the second direction Y (i.e., the portion of the well layer 2A in contact with the second sub-layer 512), thereby avoiding the influence of different depths on the electrical performance of the channel region 2’. Only the thickness of the fifth sub-layer 515 away from the gate control region (e.g., the channel region 2’) is thickened to reduce the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the injection layer 1, thereby reducing the overall parasitic capacitance of the semiconductor device 10 and reducing the tailing effect of the semiconductor device 10 in the on process.

[0213] As shown in FIG. 19, the second insulating film layer 52 includes a plurality of third sub-layers 521, a plurality of fourth sub-layers 522, and a sixth sub-layer 526, the sixth sub-layer 526 is arranged on the same side of the plurality of third sub-layers 521 and the plurality of fourth sub-layers 522 along the second direction Y, at least one fourth sub-layer 522 is arranged between the sixth sub-layer 526 and the third sub-layers 521, and the sixth sub-layer 526 and the fifth sub-layer 515 are arranged along the first direction X.

[0214] That is, the sixth sub-layer 526 is a part of the second insulating film layer 52 corresponding to the fifth sub-layer 515 of the first insulating film layer 51.

[0215] For example, referring to FIG. 19, FIG. 17, and FIG. 20, the thicknesses of the first sub-layer 511, the second sub-layer 512, the third sub-layer 521, and the fourth sub-layer 522 are the same, referring to FIG. 21, the thicknesses of the fifth sub-layer 515 and the sixth sub-layer 526 are the same, and referring to FIG. 19, or comparing FIG. 17, FIG. 20, and FIG. 21, the thicknesses of the fifth sub-layer 515 and the sixth sub-layer 526 are greater than the thicknesses of the first sub-layer 511, the second sub-layer 512, the third sub-layer 521, and the fourth sub-layer 522.

[0216] Through the design, the synchronous preparation of the first sub-layer 511, the second sub-layer 512, the third sub-layer 521, and the fourth sub-layer 522 can be facilitated, and the synchronous preparation of the fifth sub-layer 515 and the sixth sub-layer 526 can be facilitated, thereby reducing the preparation difficulty, and at the same time, without affecting the gate control effect of the gate 3, the parasitic capacitance between the gate 3 and the semiconductor layer 2 or the parasitic capacitance between the gate 3 and the injection layer 1 can be reduced, and the parasitic capacitance between the pseudo gate 4 and the semiconductor layer 2 or the parasitic capacitance between the pseudo gate 4 and the injection layer 1 can be reduced, thereby further reducing the overall parasitic capacitance of the semiconductor device 10 and optimizing the electrical performance thereof.

[0217] In some embodiments, the thickness of at least part of the second insulating film layer 52 is 1.5 times to 3 times the thickness d1 of the part of the first insulating film layer 51 in contact with the channel region 2'.

[0218] For example, it can be 1.5 times, 2 times, 2.75 times, or 3 times.

[0219] For example, in the case where the thickness of the first insulating film layer 51 is uniformly arranged and the thickness of the second insulating film layer 52 is uniformly arranged, the thickness of the second insulating film layer 52 can be 1.5 times to 3 times the thickness of the first insulating film layer 51.

[0220] For example, the average thickness of the second insulating film layer 52 can be 1.5 times to 3 times the average thickness of the first insulating film layer 51.

[0221] Exemplarily, referring to FIGS. 16-21, the thickness of the thicker portion (e.g., the fifth sub-layer 515) of the first insulating film layer 51 can be 1.5-3 times the thickness of the thinner portion (e.g., the first sub-layer 511) of the first insulating film layer 51, and the second insulating film layer 52 is the same.

[0222] By setting the thickness of the thicker portion of the insulating film layer (the first insulating film layer 51 and the second insulating film layer 52) to be 1.5-3 times the thickness of the thinner portion, flexible regulation of the electrical properties of the semiconductor device 10 can be achieved.

[0223] In some embodiments, the dielectric constant of the second insulating film layer 52 can be less than or equal to the dielectric constant of the first insulating film layer 51, so that the parasitic capacitance generated between the pseudo gate 4 and the semiconductor layer 2 or between the pseudo gate 4 and the injection layer 1 can be further reduced without affecting the gate control performance of the gate 3, thereby reducing the overall parasitic capacitance of the semiconductor device 10, alleviating the voltage tail problem, and reducing the turn-on loss of the semiconductor device 10.

[0224] For example, the dielectric constant of the material of the second insulating film layer 52 can be approximately 3.9, and the dielectric constant of the material of the first insulating film layer 51 can be approximately 7.5, or in the case where the material of the first insulating film layer 51 includes high dielectric constant materials such as hafnium oxide, the dielectric constant can even reach 25.

[0225] Exemplarily, the first insulating film layer 51 and / or the second insulating film layer 52 can also be a multi-layer composite structure, and the materials of different layers can be different.

[0226] The application also provides a preparation method of the semiconductor device 10.

[0227] FIG. 22 is a preparation flowchart of the semiconductor device 10 according to an embodiment of the application, FIG. 23 is another preparation flowchart of the semiconductor device 10 according to an embodiment of the application, and FIGS. 24-41 are cross-sectional views corresponding to each preparation step of the semiconductor device 10.

[0228] In some embodiments, as shown in FIG. 21, the preparation method includes the following steps S1-S4:

[0229] S1: Referring to FIG. 25, first and second trenches U1 and U2 are formed in the semiconductor layer 2.

[0230] Exemplarily, referring to FIGS. 24 and 25, the first and second trenches U1 and U2 can be etched in alignment by a hard mask M.

[0231] Referring to FIG. 25, the first and second trenches U1 and U2 are arranged at intervals.

[0232] Exemplarily, referring to FIG. 25, the first trench U1 and the second trench U2 both extend into the semiconductor layer 2.

[0233] Exemplarily, referring to FIG. 26, before the step S3, the hard mask M needs to be removed to avoid affecting subsequent preparation steps.

[0234] S2: forming a first insulating film layer 51 and a second insulating film layer 52.

[0235] Referring to FIG. 30, the first insulating film layer 51 is located on the inner wall of the first trench U1, and the second insulating film layer 52 is located on the inner wall of the second trench U2.

[0236] Wherein, referring to FIG. 30, at least part of the thickness of the second insulating film layer 52 is greater than the thickness of the first insulating film layer 51.

[0237] The preparation method provided by the embodiment can form a second insulating film layer 52 with a relatively thick thickness, so that the parasitic capacitance of the semiconductor device 10 formed in the conduction process is small, and the voltage tail problem is alleviated, thereby effectively reducing the turn-on loss.

[0238] Exemplarily, as shown in FIG. 23, the step S2 can include the following steps S21-S24:

[0239] S21: referring to FIG. 27, forming a protective layer A1 on the inner wall of the first trench U1.

[0240] The protective layer A1 is used to cover the first trench U1 to avoid damage to the inner wall of the first trench U1 in subsequent steps.

[0241] Exemplarily, the material of the protective layer A1 can include oxide or silicon nitride.

[0242] In some embodiments, referring to FIG. 27, the protective layer A1 can also cover the second trench U2, and the part of the protective layer A1 covering the second trench U2 can be used for subsequent oxidation to form a first oxide layer B1 (see FIG. 28).

[0243] S22: referring to FIG. 28, forming a first oxide layer B1 on the inner wall of the second trench U2.

[0244] Exemplarily, in the case where the protective layer A1 only covers the first trench U1, the protective layer A1 can be used to avoid oxidation of the inner wall of the first trench U1 to form an oxide layer, and only the inner wall of the second trench U2 forms the first oxide layer B1.

[0245] Alternatively, refer to FIG. 27 and FIG. 28, in the case that the protective layer A1 covers both the first trench U1 and the second trench U2, a mask (not shown in the middle) can be used to cover the first trench U1 and the protective layer A1 in the first trench U1, and then the protective layer A1 on the inner wall of the second trench U2 can be oxidized to form the first oxide layer B1.

[0246] S23: refer to FIG. 29, the protective layer A1 is removed.

[0247] After the protective layer A1 is removed, the inner wall of the first trench U1 is exposed, and at this time, the inner wall of the second trench U2 already has a layer of the first oxide layer B1.

[0248] S24: refer to FIG. 30, the second oxide layer B2 is formed on the inner wall of the first trench U1 and the first oxide layer B1.

[0249] As can be understood from FIG. 30, at this time, the inner wall of the first trench U1 only has a layer of the second oxide layer B2, and the inner wall of the second trench U2 has a layer of the first oxide layer B1 and a layer of the second oxide layer B2.

[0250] The part of the second oxide layer B2 on the inner wall of the first trench U1 serves as the first insulating film layer 51, and the part of the second oxide layer B2 in the second trench U2, together with the first oxide layer B1, serves as the second insulating film layer 52.

[0251] That is, the second insulating film layer 52 has two layers of oxide layers (the first oxide layer B1 and the second oxide layer B2), and the first insulating film layer 51 only has one layer of oxide layer (the second oxide layer B2), so as to ensure that the thickness of the second insulating film layer 52 is greater than the thickness of the first insulating film layer 51, so that the first insulating film layer 51 participating in the gate control has a relatively thin thickness, thereby ensuring the gate control effect, and the second insulating film layer 52 not participating in the gate control has a relatively thick thickness, thereby reducing the parasitic capacitance in the semiconductor device 10 and optimizing the electrical performance.

[0252] In some embodiments, it can be understood that referring to the aforementioned variations of the structure of the semiconductor device 10, the preparation steps can be correspondingly adjusted, for example, the size of the area where the protective layer A1 is located can be correspondingly adjusted, etc. For example, the protective layer A1 can be formed at the position where a relatively thin insulating film layer is needed, for example, the protective layer can be formed only on the part of the inner wall of the first trench U1 corresponding to the channel region 2', so that the thickness of the part of the first insulating film layer 51 participating in the gate control (i.e. the part corresponding to the channel region 2') is relatively thin, and the thickness of the part of the first insulating film layer 51 not participating in the gate control (i.e. the part between two adjacent channel regions 2' along the second direction Y) is relatively thick. The same applies to the second insulating film layer 52.

[0253] S3: Referring to FIG. 31, the gate 3 and the dummy gate 4 are formed.

[0254] Referring to FIG. 31, the gate 3 is filled in the first trench U1, and the dummy gate 4 is filled in the second trench U2.

[0255] It can be understood that after the gate 3 is filled in the first trench U1, the first insulating film layer 51 can be arranged between the inner wall of the first trench U1 and the gate 3, so as to realize the electrical insulation between the semiconductor layer 2 and the gate 3.

[0256] Similarly, after the dummy gate 4 is filled in the second trench U2, the second insulating film layer 52 can be arranged between the inner wall of the second trench U2 and the dummy gate 4, so as to realize the electrical connection between the semiconductor layer 2 and the dummy gate 4.

[0257] Exemplarily, referring to FIG. 31, in this step, the top of the gate 3 and / or the dummy gate 4 can also be partially etched, so as to reserve a space for preparing the intermediate layer 81 (see FIG. 32).

[0258] S4: The semiconductor layer 2 is doped to form a drift layer 2C, a well layer 2A and an emitter 2B.

[0259] Exemplarily, referring to FIGS. 32 and 33, the step S4 can include:

[0260] S41: Referring to FIG. 32, the side surface of the semiconductor layer 2, which is opened by the first trench U1 and the second trench U2, is ion implanted to form the well layer 2A.

[0261] Referring to FIG. 32, in this step, the part of the semiconductor layer 2 around the slot of the first trench U1 and the slot of the second trench U2 can be prepared as the well layer 2A, that is, the first trench U1 and the second trench U2 can penetrate through the well layer 2A.

[0262] Exemplarily, the step S41 can be located before the foregoing step S3, or can also be located after the foregoing step S3. The embodiments of the present application only take the case that the step S41 is located after the step S3 as an example to illustratively describe the preparation method, and do not limit the sequence of the preparation method.

[0263] Exemplarily, referring to FIG. 32, in the case that the step S41 is located after the step S3, before ion implantation, an intermediate layer 81 can be arranged on the exposed surface of the gate 3 and the dummy gate 4. The intermediate layer 81 has insulation property, and is used to protect the gate 3 and the dummy gate 4 from the influence of ion implantation.

[0264] Exemplarily, referring to FIG. 32, in this step, part of the semiconductor layer 2 can also be doped to form a storage region 2E.

[0265] S42: Referring to FIG. 33, ion implantation is performed on one side surface of the well layer 2A to form the emitter 2B.

[0266] Referring to FIG. 33, the emitter 2B is embedded in the well layer 2A, and the emitter 2B extends from the surface of the well layer 2A into the well layer 2A.

[0267] Exemplarily, referring to FIG. 33, the part where the emitter 2B is not needed can be covered by the first shielding layer N1 first, for example, the first shielding layer N1 covers the dummy gate 4 and the well layer 2A around the dummy gate 4, only exposing the well layer 2A around the gate 3, so as to form the emitter 2B only around the gate 3.

[0268] Exemplarily, in other embodiments, the well layer 2A around the dummy gate 4 can also be exposed, so as to form the emitter 2B also around the dummy gate 4, reducing the fineness in preparing the emitter 2B, but it needs to be noted that in this case, the dummy gate 4 cannot be connected to the gate signal, avoiding the dummy gate 4 also playing a role of gate control under the influence of the surrounding emitter 2B.

[0269] Referring to FIG. 33, the part of the semiconductor layer 2 other than the well layer 2A (and the storage region 2E) can be used as a drift layer 2C.

[0270] Referring to FIG. 33, the well layer 2A is arranged on the drift layer 2C.

[0271] Referring to FIG. 33, after step S4, the well layer 2A and the part of the drift layer 2C close to the well layer 2A are arranged around the first trench U1 and around the second trench U2, and the side of the emitter 2B close to the first trench U1 is used as the inner wall of the first trench U1, that is, the first trench U1 penetrates the emitter 2B and the well layer 2A and extends to the drift layer 2C, and the second trench U2 at least penetrates the well layer 2A and extends to the drift layer 2C.

[0272] Referring to FIG. 33, after the foregoing steps S1-S4, at least part of the second insulating film layer 52 can have a thickness greater than that of the part of the first insulating film layer 51 in contact with the channel region 2', which is the part of the well layer 2A between the emitter 2B and the drift layer 2C.

[0273] Exemplarily, referring to FIGS. 34-41, the preparation method can further include the following other steps.

[0274] Referring to FIG. 34, the second shielding layer N2 can be covered on the gate 3 and the side of the emitter 2B away from the drift layer 2C, and the dummy gate 4 and the structure near the dummy gate 4 are annealed or subjected to other treatments.

[0275] Referring to Fig. 35, the dielectric layer 8 can be provided on the same side of the gate 3 and the dummy gate 4 and the semiconductor layer 2, so as to realize the electrical insulation of the gate 3 and other conductive structures and realize the electrical insulation of the dummy gate 4 and other conductive structures.

[0276] Referring to Fig. 36, the dielectric layer 8 is cut by using the third shielding layer N3, so as to expose at least part of the emitter 2B and at least part of the well layer 2A, so as to facilitate the electrical connection of the emitter 2B and the well layer 2A with the emitter electrode 7 formed later.

[0277] Exemplarily, referring to Fig. 36, in this step, the portions of the first insulating film layer 51 and the second insulating film layer 52 on the side surface of the well layer 2A away from the drift layer 2C can also be removed synchronously, so as to expose the emitter 2B and the well layer 2A.

[0278] Referring to Fig. 37, the emitter electrode 7 can be formed, so as to realize the input and output of electrical signals.

[0279] Referring to Fig. 38, the semiconductor layer 2 (the side of the drift layer 2C away from the well layer 2A) can be doped to form the buffer region 2D and the injection layer 1.

[0280] Exemplarily, this step can have various preparation methods, for example, the semiconductor layer 2 can be grown on the injection layer 1 before the step S1, or the semiconductor layer 2 can be epitaxially grown on the substrate first, then the substrate is removed and the semiconductor layer 2 is ion implanted to form the injection layer 1, or the semiconductor layer 2 is directly doped to form the injection layer 1, and the preparation sequence or preparation method of the two is not limited in the embodiments of the present application, and any preparation process capable of realizing the stacked arrangement of the injection layer 1 and the semiconductor layer 2 is within the protection scope of the embodiments of the present application.

[0281] Referring to Fig. 38, the collector 6 can be formed on the side of the injection layer 1 away from the drift layer 2C after the injection layer 1 is formed.

[0282] The preparation method can also be deformed, for example, referring to Figs. 39, 40 and 41, in the process of cutting the dielectric layer 8, the dielectric layer 8 on the well layer 2A (for example, the well layer 2A on the right side of the rightmost second groove U2 in Figs. 39, 40 and 41) of at least one side of at least one second groove U2 can be reserved, so that the part of the well layer 2A does not come into electrical contact with the emitter electrode 7 (referring to Fig. 41), so as to realize the electrical floating of the part of the well layer 2A.

[0283] The following provides an embodiment for preparing the semiconductor device 10:

[0284] (a) photolithography and dry etching of an oxide mask on the semiconductor layer.

[0285] (b) trench etch, damage removal (e.g. etch oxide, CDE etch away a thickness of silicon).

[0286] (c) oxide removal, cleaning, sacrificial oxidation and its removal.

[0287] (d) deposition of thermal liner oxide (30 nm) and silicon nitride.

[0288] (e) photolithography and etching of silicon nitride, and selective oxidation to form thick oxide (200 nm thickness).

[0289] (f) removal of silicon nitride (Si3N4) and liner oxide.

[0290] (g) gate oxidation, formation of gate oxide and dummy trench oxide.

[0291] (h) doped polysilicon or amorphous silicon trench fill and etch back.

[0292] (i) subsequent process steps to form an IGBT semiconductor device.

[0293] According to a specific process integration scheme, process steps (d) to (f) can also be replaced by the following sequence:

[0294] 1) deposition of high temperature oxide (HTO) with thickness of 150 nm to 300 nm and densification.

[0295] 2) photolithography and etching of HTO.

[0296] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of the changes or replacements within the technical range disclosed by the present application, which shall be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a drift layer; a well layer disposed on the drift layer; an emitter embedded in the well layer, and the emitter extends into the well layer from a first surface of the well layer, the first surface being a surface of the well layer away from the drift layer; a first trench and a second trench are formed on a side of the first surface of the well layer in a direction perpendicular to the first surface, the first trench and the second trench are disposed in a spaced manner, a portion of the well layer and the drift layer close to the well layer is disposed around the first trench and around the second trench, and a side of the emitter close to the first trench serves as an inner wall of the first trench; a gate filled in the first trench, and a first insulating film layer is disposed between the gate and the inner wall of the first trench; and a dummy gate filled in the second trench, and a second insulating film layer is disposed between the dummy gate and the inner wall of the second trench; wherein the thickness of at least part of the second insulating film layer is greater than the thickness of a portion of the first insulating film layer in contact with a channel region, the channel region being a portion of the well layer between the emitter and the drift layer. The thickness of the first insulating film layer is the same at different positions in a cross section perpendicular to a second direction, the second direction being a length extension direction of the first trench and the second trench, and the second direction intersects with an arrangement direction of the first trench and the second trench.

2. The semiconductor device according to claim 1, wherein The average thickness of the second insulating film layer is greater than the average thickness of the first insulating film layer.

3. The semiconductor device according to claim 1 or 2, wherein A plurality of second trenches are formed on a side of the first surface of the well layer in a direction perpendicular to the first surface, and the second trenches are disposed in a spaced manner; 4. The semiconductor device according to any one of Claims 1 to 3, wherein The thickness of the first insulating film layer is the same at different positions, and the thickness of the second insulating film layer is the same at different positions in the same second trench. The thickness of the second insulating film layer in each second trench is greater than the thickness of the first insulating film layer.

5. The semiconductor device of claim 4, wherein, The thickness of the second insulating film layer is the same in a plurality of second trenches.

6. The semiconductor device of claim 5, wherein, The thickness of the second insulating film layer in a second trench adjacent to the first trench is the same as the thickness of the first insulating film layer in the first trench; 7. The semiconductor device of claim 4, wherein The thickness of the second insulating film layer in a second trench spaced from the first trench is greater than the thickness of the first insulating film layer. The semiconductor device comprises a plurality of emitters, the plurality of emitters are sequentially and spacedly disposed in a second direction, and the plurality of emitters are in contact with the first insulating film layer; 8. The semiconductor device according to claim 1 or 2, wherein The first insulating film layer comprises a plurality of first sub-layers and a plurality of second sub-layers, the plurality of first sub-layers and the plurality of second sub-layers are alternately disposed in the second direction, and the first sub-layers are in contact with the emitters; ​ The second insulating film layer comprises a plurality of third sub-layers and a plurality of fourth sub-layers, the plurality of third sub-layers and the plurality of fourth sub-layers are arranged alternately along the second direction; the third sub-layers are arranged in the first direction with the first sub-layers, and the fourth sub-layers are arranged in the first direction with the second sub-layers; the first direction is the arrangement direction of the first trench and the second trench; The thickness of the first sub-layers is the same as that of the third sub-layers, and the thickness of the second sub-layers is the same as that of the fourth sub-layers; the thickness of the second sub-layers and the fourth sub-layers is greater than that of the first sub-layers and the third sub-layers.

9. The semiconductor device according to claim 1 or 2, wherein The first insulating film layer comprises a plurality of first sub-layers, a plurality of second sub-layers and a fifth sub-layer, the fifth sub-layer is arranged on the same side of the plurality of first sub-layers and the plurality of second sub-layers along the second direction, and the fifth sub-layer is separated from the first sub-layers by at least one second sub-layer; The second insulating film layer comprises a plurality of third sub-layers, a plurality of fourth sub-layers and a sixth sub-layer, the sixth sub-layer is arranged on the same side of the plurality of third sub-layers and the plurality of fourth sub-layers along the second direction, and the sixth sub-layer is separated from the third sub-layers by at least one fourth sub-layer, and the sixth sub-layer is arranged in the first direction with the fifth sub-layer; The thickness of the first sub-layers, the second sub-layers, the third sub-layers and the fourth sub-layers is the same, the thickness of the fifth sub-layer and the sixth sub-layer is the same, and the thickness of the fifth sub-layer and the sixth sub-layer is greater than that of the first sub-layers, the second sub-layers, the third sub-layers and the fourth sub-layers.

10. The semiconductor device according to any one of Claims 1 to 9, wherein The thickness of at least part of the second insulating film layer is 1.5 to 3 times the thickness of the part of the first insulating film layer in contact with the channel region.

11. The semiconductor device according to any one of Claims 1 to 10, wherein The dielectric constant of the second insulating film layer is less than or equal to the dielectric constant of the first insulating film layer.

12. A method of manufacturing a semiconductor device, characterized by, Comprising: A first trench and a second trench are opened on one side surface of a semiconductor layer; The first trench and the second trench are arranged separately; A first insulating film layer and a second insulating film layer are formed; the first insulating film layer is located on the inner wall of the first trench, and the second insulating film layer is located on the inner wall of the second trench; A gate and a dummy gate are formed; the gate is filled in the first trench, and the dummy gate is filled in the second trench; The semiconductor layer is doped to form a drift layer, a well layer and an emitter; the well layer is arranged on the drift layer; The emitter is embedded in the well layer, and the emitter extends into the well layer from the surface of the well layer away from the drift layer; The well layer and the part of the drift layer close to the well layer are arranged around the first trench and around the second trench, and the side of the emitter close to the first trench serves as the inner wall of the first trench; The thickness of at least part of the second insulating film layer is greater than the thickness of the part of the first insulating film layer in contact with the channel region; The channel region is the part of the well layer between the emitter and the drift layer.

13. The method of claim 12, wherein, The formation of the first insulating film layer and the second insulating film layer comprises: forming a protective layer on the inner wall of the first trench; forming a first oxide layer on the inner wall of the second trench; removing the protective layer; forming a second oxide layer on the inner wall of the first trench and on the first oxide layer; the portion of the second oxide layer on the inner wall of the first trench serving as a first insulating film layer, and the portion of the second oxide layer in the second trench serving as the second insulating film layer together with the first oxide layer.

14. An integrated circuit, characterized by comprising: the semiconductor device according to any one of claims 1 to 11; an electronic device electrically connected to the semiconductor device.

15. An electronic device, comprising: comprising: the semiconductor device according to any one of claims 1 to 11, or the integrated circuit according to claim 14; a circuit board on which the semiconductor device or the integrated circuit is disposed.

Images