Driving circuit and half-bridge driving circuit

Abstract

Provided in the disclosure of the present invention are a driving circuit and a half-bridge driving circuit. The driving circuit is used for driving a target power transistor, and the driving circuit comprises: floating rail circuits, which are connected between a first node and a second node, and are used for generating a floating voltage and a clamp voltage; a control signal generation circuit, which is connected between the first node and the floating voltage, and generates control signals on the basis of a PWM signal; and a gate driving circuit, which is connected between the first node and the second node, is connected to the clamp voltage, and is used for generating a target driving signal on the basis of several control signals, so as to drive a target power transistor. In the present invention, a floating voltage is generated by means of a floating rail circuit, such that a control signal generation circuit operates in a floating voltage domain, thereby avoiding the risk of breakdown of a high-voltage transistor; a clamp voltage is generated by means of a floating rail circuit, such that a low-voltage transistor can be used as an output transistor of a gate driving circuit, thereby improving the response speed of the gate driving circuit; and half-bridge driving can be realized on the basis of two sets of floating rail circuits, thereby reducing the area of circuits.

Description

Driving circuit and half-bridge driving circuit

[0001] The present application claims priority to the Chinese patent application No. 202411364777.6, filed on September 27, 2024, and entitled "Driving circuit and half-bridge driving circuit", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of integrated circuits, and more particularly, to a driving circuit and a half-bridge driving circuit. BACKGROUND

[0003] As shown in FIG. 1, a half-bridge driving circuit in the prior art is shown, in which the driving voltage PVCC is high voltage (for example, 7.5V), and the high-voltage process does not support thick gate oxide, i.e., the V GS ≤5V, a low-voltage (for example, 5V) internal floating drive needs to be made to ensure that the V GS of the high-voltage tube will not be broken down.

[0004] As shown in FIG. 2, a floating rail circuit in the prior art is shown, in which a floating voltage is generated by a driving tube and a stabilizing capacitor. For example, on the PMOS driving side, a floating voltage of PVCC-5V (or BST-5V) is generated; and on the NMOS driving side, a floating voltage of PGND+5V (or SW+5V) is generated.

[0005] The prior art has the following disadvantages: the driving tube and the stabilizing capacitor of the floating rail circuit occupy a large circuit area. As shown in FIG. 3, for a half-bridge driving circuit, in order to obtain sufficient driving capability and stable driving voltage, four floating voltages (PVCC-5V, BST-5V, PGND+5V, and SW+5V) need to be generated by four groups of floating rail circuits, thus occupying a larger circuit area.

[0006] Therefore, in view of the above technical problems, it is necessary to provide a driving circuit and a half-bridge driving circuit. SUMMARY

[0007] The present application aims to provide a driving circuit and a half-bridge driving circuit, which can generate a floating voltage domain with a small circuit area to adapt to a thin gate process for high-voltage driving.

[0008] To achieve the above-mentioned purpose, a technical solution provided by an embodiment of the present application is as follows:

[0009] A driving circuit for driving a target power tube, the driving circuit comprising:

[0010] A floating rail circuit connected between the first node and the second node, configured to generate a floating voltage based on the voltage on the first node and a clamping voltage based on the voltage on the second node, the floating voltage being less than the voltage on the first node, and the clamping voltage being greater than the voltage on the second node;

[0011] A control signal generation circuit connected between the first node and the floating voltage, configured to generate a plurality of control signals based on the PWM signal;

[0012] A gate drive circuit connected between the first node and the second node and connected to the clamping voltage, the gate drive circuit being a multi-stage structure, each stage of the gate drive circuit corresponding to at least one control signal, the gate drive circuit being configured to generate a target drive signal based on the plurality of control signals to drive a target power tube.

[0013] In one or more embodiments of the present application, the floating rail circuit includes a first Zener diode, a first resistor, a second resistor, a first MOS tube, a third resistor, and a second Zener diode; wherein the first end of the first Zener diode is connected to the first end of the first resistor, the second end of the first Zener diode is connected to the first node, and the second end of the first resistor is connected to the second node; the first end of the second resistor is connected to the first node, the second end of the second resistor is connected to the floating voltage, the first end of the first MOS tube is connected to the floating voltage, the second end of the first MOS tube is connected to the second node, and the control end of the first MOS tube is connected to the first end of the first Zener diode; the first end of the third resistor is connected to the first node, the second end of the third resistor is connected to the clamping voltage, the first end of the second Zener diode is connected to the second node, and the second end of the second Zener diode is connected to the clamping voltage.

[0014] In one or more embodiments of the present application, the floating rail circuit further includes:

[0015] A first capacitor, the first end of the first capacitor being connected to the first node, and the second end of the first capacitor being connected to the floating voltage;

[0016] A second capacitor, the first end of the second capacitor being connected to the clamping voltage, and the second end of the second capacitor being connected to the second node.

[0017] In one or more embodiments of the present application, the gate drive circuit comprises a latch unit, a first drive unit, a second drive unit, a first power tube and a second power tube; wherein the latch unit is connected with a control signal generation circuit, the latch unit generates a latch signal based on a first control signal and a second control signal, the first control signal and the second control signal are opposite in phase; the first drive unit is connected with the control signal generation circuit and the latch unit, the first drive unit is used for generating a first drive signal based on the latch signal and the second control signal; the second drive unit is connected with the first drive unit, the second drive unit is used for generating a power tube drive signal based on the first drive signal and a third control signal.

[0018] The first end of the first power tube is connected with a first node, the control end of the first power tube receives a fourth control signal, and the second end of the first power tube is connected with the control end of a target power tube; the first end of the second power tube is connected with a second node, the control end of the second power tube is connected with the second drive unit and receives the power tube drive signal, and the second end of the second power tube is connected with the control end of the target power tube.

[0019] In one or more embodiments of the present application, the first drive unit comprises a third input tube, a third clamping tube and a third output tube; wherein the first end of the third input tube is connected with the first node, the second end of the third input tube is connected with the second end of the third clamping tube, and the control end of the third input tube receives the second control signal; the control end of the third clamping tube is connected with a clamping voltage, the first end of the third clamping tube is connected with the second end of the third output tube; the control end of the third output tube is connected with the latch unit and receives the latch signal, the first end of the third output tube is connected with the second node, and the second end of the third output tube is connected with the second drive unit and generates the first drive signal.

[0020] In one or more embodiments of the present application, the second drive unit comprises a fourth input tube, a fourth clamping tube and a fourth output tube; wherein the first end of the fourth input tube is connected with the first node, the second end of the fourth input tube is connected with the second end of the fourth clamping tube, and the control end of the fourth input tube receives the third control signal; the control end of the fourth clamping tube is connected with the clamping voltage, the first end of the fourth clamping tube is connected with the second end of the fourth output tube; the control end of the fourth output tube is connected with the first drive unit and receives the first drive signal, the first end of the fourth output tube is connected with the second node, and the second end of the fourth output tube is connected with the control end of the second power tube and generates the power tube drive signal.

[0021] In one or more embodiments of the present application, the control signal generation circuit includes a plurality of connected inverters, the plurality of inverters being configured to invert and delay the PWM signal to generate a first control signal, a second control signal, a third control signal, and a fourth control signal; wherein,

[0022] the first control signal is in phase with the PWM signal; the second control signal is inverted from the PWM signal, and the second control signal is delayed from the first control signal; the third control signal is in phase with the PWM signal, and the third control signal is delayed from the second control signal; and the fourth control signal is inverted from the PWM signal, and the fourth control signal is delayed from the third control signal.

[0023] In one or more embodiments of the present application, the latch unit includes a first input transistor, a second input transistor, a first clamp transistor, a second clamp transistor, a first output transistor, and a second output transistor; wherein a first end of the first input transistor is connected to a first node, a second end of the first input transistor is directly or indirectly connected to a second end of the first clamp transistor, and a control end of the first input transistor receives the second control signal; a first end of the second input transistor is connected to the first node, a second end of the second input transistor is directly or indirectly connected to a second end of the second clamp transistor, and a control end of the second input transistor receives the first control signal;

[0024] control ends of the first clamp transistor and the second clamp transistor are connected to a clamp voltage, a first end of the first clamp transistor is directly or indirectly connected to a second end of the first output transistor, and a first end of the second clamp transistor is directly or indirectly connected to a second end of the second output transistor; a first end of the first output transistor is connected to a second node, and a control end of the first output transistor is connected to the first end of the second clamp transistor; and a first end of the second output transistor is connected to the second node, and a control end of the second output transistor is connected to the first end of the first clamp transistor.

[0025] In one or more embodiments of the present application, the latch unit further includes a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; wherein a first end of the fourth resistor is connected to the second end of the first input transistor, and a second end of the fourth resistor is connected to the second end of the first clamp transistor; a first end of the fifth resistor is connected to the second end of the second input transistor, and a second end of the fifth resistor is connected to the second end of the second clamp transistor; a first end of the sixth resistor is connected to the first end of the first clamp transistor, and a second end of the sixth resistor is connected to the second end of the first output transistor; and a first end of the seventh resistor is connected to the first end of the second clamp transistor, and a second end of the seventh resistor is connected to the second end of the second output transistor.

[0026] In one or more embodiments of the present application, the first node is connected with a BST pin in the driving circuit, the second node is connected with a SW pin in the driving circuit, and the target power tube is a high-voltage side power tube.

[0027] In one or more embodiments of the present application, the first node is connected with a power supply voltage, the second node is connected with a ground potential, and the target power tube is a low-voltage side power tube.

[0028] Another specific embodiment of the present application provides a half-bridge driving circuit, which comprises a first driving circuit and a second driving circuit; wherein the first driving circuit is the driving circuit described above; and the second driving circuit is the driving circuit described above.

[0029] Another specific embodiment of the present application provides a half-bridge driving circuit, which comprises a first driving circuit and a second driving circuit; wherein the first driving circuit is the driving circuit described above.

[0030] Another specific embodiment of the present application provides a half-bridge driving circuit, which comprises a first driving circuit and a second driving circuit; wherein the second driving circuit is the driving circuit described above.

[0031] Compared with the prior art, the driving circuit and the half-bridge driving circuit of the present application generate a floating voltage through a floating circuit, so that the control signal generation circuit works in a floating voltage domain, and then the control signals are all signals in the floating voltage domain, and the input tube in the gate driving circuit works in a floating voltage domain of about 5V, thereby preventing the input tube in the gate driving circuit from being broken down.

[0032] The floating voltage generated by the floating circuit enables the output tube in the gate driving circuit to use a low-voltage tube, and prevents the output tube in the gate driving circuit from being broken down, thereby improving the response speed of the gate driving circuit and reducing power consumption.

[0033] The gate driving circuit adopts a push-pull stage structure, and generates a target driving signal meeting a target driving capability and being stable through step-by-step driving.

[0034] For the half-bridge driving circuit, only two groups of floating circuits are needed to obtain sufficient driving capability and stable driving voltage, thereby saving circuit area. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0036] Fig. 1 is a schematic diagram of a half-bridge drive circuit in the prior art;

[0037] Fig. 2 is a schematic diagram of a floating track circuit in the prior art;

[0038] Fig. 3 is a schematic diagram of a half-bridge drive circuit in the prior art;

[0039] Fig. 4 is a schematic diagram of a drive circuit in Embodiment 1 of the present application;

[0040] Fig. 5 is a schematic diagram of a floating track circuit of the drive circuit in Embodiment 1 of the present application;

[0041] Fig. 6 is a schematic diagram of a control signal generation circuit of the drive circuit in Embodiment 1 of the present application;

[0042] Fig. 7 is a schematic diagram of a gate drive circuit of the drive circuit in Embodiment 1 of the present application;

[0043] Fig. 8 is a schematic diagram of a drive circuit in Embodiment 2 of the present application;

[0044] Fig. 9 is a schematic diagram of a half-bridge drive circuit in Embodiment 3 of the present application. DETAILED DESCRIPTION

[0045] In order to make the person in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person in the art without creative labor should belong to the scope of protection of the present application.

[0046] In the specification, "coupling" or "connection" or "linking" includes both direct connection and indirect connection. Indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have a parasitic inductance or a parasitic capacitance; indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through circuits or components such as switches, follower circuits, etc. In addition, in the present application, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0047] Embodiment 1:

[0048] As shown in Fig. 4, the drive circuit in an embodiment is used to drive a target power tube, and the drive circuit includes a floating track circuit 10, a control signal generation circuit 20 and a gate drive circuit 30.

[0049] The floating circuit 10 is connected between the first node and the second node, and is configured to generate a floating voltage VFLOAT based on the voltage on the first node, and generate a clamping voltage VCLAMP based on the voltage on the second node. The floating voltage VFLOAT is less than the voltage on the first node, and the clamping voltage VCLAMP is greater than the voltage on the second node.

[0050] In an embodiment, the target power tube is a high-voltage side power tube, and thus the first node is connected to a BST pin of the driving circuit, and the second node is connected to a SW pin of the driving circuit. The difference between the voltage on the BST pin and the voltage on the SW pin is about 7.5V. For convenience of distinction, the first node is referred to as BST, and the second node is referred to as SW in an embodiment.

[0051] The control signal generation circuit 20 is connected between the first node BST and the floating voltage VFLOAT, and is configured to generate a plurality of control signals based on the PWM signal.

[0052] The gate driving circuit 30 is connected between the first node BST and the second node SW, and is connected to the clamping voltage VCLAMP. The gate driving circuit 30 is of a multi-stage structure, each stage of the gate driving circuit 30 corresponds to at least one control signal, and the gate driving circuit 30 is configured to generate a target driving signal HO based on the plurality of control signals to drive the target power tube.

[0053] As shown in FIG. 5, the floating circuit 10 in an embodiment includes a first Zener diode D1, a first resistor R1, a second resistor R2, a first MOS tube M1, a third resistor R3, a second Zener diode D2, a first capacitor C1, and a second capacitor C2.

[0054] Specifically, the first end of the first Zener diode D1 is connected to the first end of the first resistor R1, the second end of the first Zener diode D1 is connected to the first node BST, and the second end of the first resistor R1 is connected to the second node SW.

[0055] The first end of the second resistor R2 is connected to the first node BST, the second end of the second resistor R2 is connected to the floating voltage VFLOAT, the first end of the first MOS tube M1 is connected to the floating voltage VFLOAT, the second end of the first MOS tube M1 is connected to the second node SW, and the control end of the first MOS tube M1 is connected to the first end of the first Zener diode D1. In this embodiment, the first MOS tube M1 is a high-voltage PMOS, the first end of the first MOS tube M1 is the source, the second end is the drain, and the control end is the gate.

[0056] The first end of the third resistor R3 is connected with the first node BST, and the second end of the third resistor R3 is connected with the clamping voltage VCLAMP. The first end of the second Zener diode D2 is connected with the second node SW, and the second end of the second Zener diode D2 is connected with the clamping voltage VCLAMP.

[0057] The first end of the first capacitor C1 is connected with the first node BST, and the second end of the first capacitor C1 is connected with the floating voltage VFLOAT. The first end of the second capacitor C2 is connected with the clamping voltage VCLAMP, and the second end of the second capacitor C2 is connected with the second node SW.

[0058] As shown in FIG. 5, the floating circuit 10 generates the floating voltage VFLOAT and the clamping voltage VCLAMP by using the reverse breakdown voltage Vzener (about 6V) of the first Zener diode D1 and the second Zener diode D2 to realize voltage stabilization. Wherein, the floating voltage VFLOAT equals to BST-Vzener+VGS M1 , and the clamping voltage VCLAMP=SW+Vzener.

[0059] Specifically, the control end potential of the first MOS transistor M1 is clamped to BST-Vzener by the first Zener diode D1, and the floating voltage VFLOAT equals to BST-Vzener+VGS M1 , and thus the floating voltage domain BST-VFLOAT between the first node BST and the floating voltage VFLOAT is Vzener-VGS M1 , and the floating voltage domain BST-VFLOAT ranges about 5V, which can prevent the high-voltage transistor under the thin gate process from being broken down.

[0060] As shown in FIG. 6, the control signal generating circuit 20 includes multiple levels of inverters connected in sequence, and each level of inverter works in the floating voltage domain BST-VFLOAT.

[0061] As shown in FIG. 7, the gate drive circuit 30 of the embodiment includes a latch unit 31, a first drive unit 32, a second drive unit 33, a first power transistor HV_PMOS and a second power transistor HV_NMOS. It can be understood that the gate drive circuit 30 is a multi-level structure, wherein the latch unit 31 can be regarded as a first level structure, the first drive unit 32 can be regarded as a second level structure, the second drive unit 33 can be regarded as a third level structure, and the first power transistor HV_PMOS and the second power transistor HV_NMOS can be regarded as an output level structure.

[0062] The latch unit 31 is connected with the control signal generating circuit 20, and the latch unit 31 generates a latch signal based on a first control signal A1 and a second control signal A2, and the first control signal A1 and the second control signal A2 are opposite in phase. It can be understood that the latch signal is the potential of point B2 shown in FIG. 7.

[0063] The first driving unit 32 is connected with the control signal generating circuit 20 and the latch unit 31, and is configured to generate the first driving signal B3 based on the latch signal and the second control signal A2.

[0064] The second driving unit 33 is connected with the first driving unit 32, and is configured to generate the power tube driving signal NGATE based on the first driving signal B3 and the third control signal A3. It can be understood that the power tube driving signal is the NGATE point potential shown in FIG. 7.

[0065] The first power tube HV_PMOS and the second power tube HV_NMOS constitute an output stage, the second end of the first power tube HV_PMOS is connected with the second end of the second power tube HV_NMOS, and the control end of the target power tube, and generates the target driving signal HO to the control end of the target power tube. The first power tube HV_PMOS and the second power tube HV_NMOS in an embodiment are both high-voltage tubes.

[0066] Specifically, the first end of the first power tube HV_PMOS is connected with the first node BST, the control end of the first power tube HV_PMOS receives the fourth control signal A4, and the second end of the first power tube HV_PMOS is connected with the control end of the target power tube. The first end of the second power tube HV_NMOS is connected with the second node SW, the control end of the second power tube HV_NMOS is connected with the second driving unit 33 and receives the power tube driving signal NGATE, and the second end of the second power tube HV_NMOS is connected with the control end of the target power tube.

[0067] It can be understood that the latch unit 31, the first driving unit 32 and the second driving unit 33 each include a corresponding input tube, a clamping tube and an output tube. The input tube is connected with the first node BST, the second end of the input tube is directly or indirectly connected with the second end of the clamping tube, and the control end of the input tube receives the corresponding control signal. The control end of the clamping tube is connected with the clamping voltage VCLAMP, and the first end of the clamping tube is directly or indirectly connected with the second end of the output tube. The first end of the output tube is connected with the second node SW.

[0068] Further, the input tubes of the latch unit 31, the first driving unit 32 and the second driving unit 33 are all high-voltage tubes, as can be known from the above analysis, the control signal generating circuit 20 is connected between the first node BST and the floating voltage VFLOAT, and the control signals generated thereby are all signals in the floating voltage domain BST-VFLOAT, so the V GS of the input tubes of the latch unit 31, the first driving unit 32 and the second driving unit 33 are all in the range of Vzener-V GS (about 5V), and will not be high-voltage breakdown.

[0069] The clamp tubes of the latch unit 31, the first driving unit 32 and the second driving unit 33 are high-voltage tubes, and the clamp tubes can be considered to be always in the on state. The output tubes of the latch unit 31, the first driving unit 32 and the second driving unit 33 are low-voltage tubes, and the first end voltage of the clamp tube, i.e. the source voltage of the clamp tube, is clamped to VCLAMP-V GS Therefore, the output tubes work in a voltage range of about 5V. Specifically, the B1 node is clamped to VCLAMP-VGS Q3 , the B2 node is clamped to VCLAMP-VGS Q4 , the B3 node is clamped to VCLAMP-VGS Q8 , and the NGATE node is clamped to VCLAMP-VGS Q11 .

[0070] It can be understood that the control end voltage of the second power tube HV_NMOS is about SW+5V, and the control end voltage of the first power tube HV_PMOS is about BST-5V, i.e. the driving circuit in an embodiment realizes generation of two floating voltages (SW+5V and BST-5V) through a floating rail circuit.

[0071] Specifically, the latch unit 31 includes a first input tube Q1, a second input tube Q2, a first clamp tube Q3, a second clamp tube Q4, a first output tube Q5 and a second output tube Q6. The first input tube Q1 and the second input tube Q2 are high-voltage PMOS, the first clamp tube Q3 and the second clamp tube Q4 are high-voltage NMOS, and the first output tube Q5 and the second output tube Q6 are low-voltage NMOS.

[0072] The first end of the first input tube Q1 is connected with the first node BST, the second end of the first input tube Q1 is directly or indirectly connected with the second end of the first clamp tube Q3, and the control end of the first input tube Q1 receives a second control signal A2.

[0073] The first end of the second input tube Q2 is connected with the first node BST, the second end of the second input tube Q2 is directly or indirectly connected with the second end of the second clamp tube Q4, and the control end of the second input tube Q2 receives a first control signal A1.

[0074] The control ends of the first clamp tube Q3 and the second clamp tube Q4 are connected with a clamp voltage VCLAMP, the first end of the first clamp tube Q3 is directly or indirectly connected with the second end of the first output tube Q5, and the first end of the second clamp tube Q4 is directly or indirectly connected with the second end of the second output tube Q6.

[0075] The first end of the first output tube Q5 is connected with the second node SW, and the control end of the first output tube Q5 is connected with the first end of the second clamp tube Q4. The first end of the second output tube Q6 is connected with the second node SW, and the control end of the second output tube Q6 is connected with the first end of the first clamp tube Q3.

[0076] Further, the latch unit 31 in an embodiment further comprises a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7. The first end of the fourth resistor R4 is connected with the second end of the first input tube Q1, and the second end of the fourth resistor R4 is connected with the second end of the first clamp tube Q3. The first end of the fifth resistor R5 is connected with the second end of the second input tube Q2, and the second end of the fifth resistor R5 is connected with the second end of the second clamp tube Q4. The first end of the sixth resistor R6 is connected with the first end of the first clamp tube Q3, and the second end of the sixth resistor R6 is connected with the second end of the first output tube Q5. The first end of the seventh resistor R7 is connected with the first end of the second clamp tube Q4, and the second end of the seventh resistor R7 is connected with the second end of the second output tube Q6.

[0077] As shown in FIG. 7, the first driving unit 32 in an embodiment comprises a third input tube Q7, a third clamp tube Q8 and a third output tube Q9. The third input tube Q7 is a high-voltage PMOS tube, the third clamp tube Q8 is a high-voltage NMOS tube, and the third output tube Q9 is a low-voltage NMOS tube.

[0078] The first end of the third input tube Q7 is connected with the first node BST, the second end of the third input tube Q7 is connected with the second end of the third clamp tube Q8, and the control end of the third input tube Q7 receives the second control signal A2.

[0079] The control end of the third clamp tube Q8 is connected with the clamp voltage VCLAMP, and the first end of the third clamp tube Q8 is connected with the second end of the third output tube Q9.

[0080] The control end of the third output tube Q9 is connected with the latch unit 31 and receives the latch signal, the first end of the third output tube Q9 is connected with the second node SW, and the second end of the third output tube Q9 generates the first driving signal B3.

[0081] As shown in FIG. 7, the second driving unit 33 in an embodiment comprises a fourth input tube Q10, a fourth clamp tube Q11 and a fourth output tube Q12. The fourth input tube Q10 is a high-voltage PMOS tube, the fourth clamp tube Q11 is a high-voltage NMOS tube, and the fourth output tube Q12 is a low-voltage NMOS tube.

[0082] The first end of the fourth input tube Q10 is connected with the first node BST, the second end of the fourth input tube Q10 is connected with the second end of the fourth clamp tube Q11, and the control end of the fourth input tube Q10 receives the third control signal A3.

[0083] The control end of the fourth clamp tube Q11 is connected with the clamp voltage VCLAMP, and the first end of the fourth clamp tube Q11 is connected with the second end of the fourth output tube Q12.

[0084] The control end of the fourth output tube Q12 is connected with the second end of the third output tube Q9 of the first driving unit 32 and receives the first driving signal B3, the first end of the fourth output tube Q12 is connected with the second node SW, and the second end of the fourth output tube Q12 is connected with the control end of the second power tube HV_NMOS and generates the power tube driving signal NGATE.

[0085] As shown in FIGS. 6 and 7, the control signal generating circuit 20 is used to cooperate with the gate driving circuit 30 to enable the gate driving circuit 30 to realize step-by-step driving. Therefore, for the gate driving circuit 30 shown in FIG. 7, the control signal generating circuit 20 needs to generate four control signals, which are the first control signal A1, the second control signal A2, the third control signal A3, and the fourth control signal A4.

[0086] Further, the driving capabilities of the first control signal A1, the second control signal A2, the third control signal A3, and the first control signal A4 are gradually enhanced, and the phases are gradually delayed, so that the input tube of the latch unit 31 of the gate driving circuit 30, the input tube of the first driving unit 32, the input tube of the second driving unit 33, and the first power tube HV_PMOS start to conduct step by step.

[0087] Specifically, the first control signal A1 is in phase with the PWM signal; the second control signal A2 is opposite to the PWM signal, and the second control signal A2 is delayed from the first control signal A1; the third control signal A3 is in phase with the PWM signal, and the third control signal A3 is delayed from the second control signal A2; the fourth control signal A4 is opposite to the PWM signal, and the fourth control signal A4 is delayed from the third control signal A3.

[0088] As shown in FIG. 6, the control signal generating circuit 20 in an embodiment includes multiple-stage connected inverters, each of which includes an NMOS tube and a PMOS tube. Among them, the first end of the PMOS tube is connected with the first node BST, the second end of the PMOS tube is connected with the second end of the NMOS tube, the control end of the PMOS tube is connected with the control end of the NMOS tube and serves as the input end of the inverter, the first end of the NMOS tube is connected with the floating voltage VFLOAT, and the second end of the NMOS tube is connected with the second end of the PMOS tube and serves as the output end of the inverter. The input end of the first inverter receives the PWM signal, the output end of the first inverter is connected with the input end of the next inverter, and so on. The corresponding control signals are obtained through the output ends of different inverters.

[0089] Specifically, the PWM signal in one embodiment passes through two inverters to generate a first control signal A1, which is in phase with the PWM signal. The first control signal A1 passes through one inverter to generate a second control signal A2, which is opposite to the first control signal A1. The second control signal A2 passes through three inverters to generate a third control signal A3, which is opposite to the second control signal A2. The first control signal A1 passes through five inverters to generate a fourth control signal A4, which is opposite to the first control signal A1.

[0090] When the PWM signal is high, the first control signal A1 is high, the second control signal A2 is low, the third control signal A3 is high, the fourth control signal A4 is low, the first input tube Q1 is turned on, the second input tube Q2 is turned off, the B1 node is pulled up, and thus the second output tube Q6 is turned on, the B2 node is pulled down, and the third output tube Q9 is turned off. Since the third input tube Q7 is turned on, the B3 node is pulled up, the fourth output tube Q12 is turned on, the fourth input tube Q10 is turned off, the power tube driving signal (i.e., the NGATE node voltage) is pulled down, the second power tube HV_NMOS is turned off, the first power tube HV_PMOS is turned on, and the target driving signal HO is pulled up.

[0091] When the PWM signal is low, the first control signal A1 is low, the second control signal A2 is high, the third control signal A3 is low, the fourth control signal A4 is high, the first input tube Q1 is turned off, the second input tube Q2 is turned on, the B2 node is pulled up, and thus the first output tube Q5 is turned on, the B1 node is pulled down, and the third output tube Q9 is turned on. Since the third input tube Q7 is turned off, the B3 node is pulled down, the fourth output tube Q12 is turned off, the fourth input tube Q10 is turned on, the power tube driving signal (i.e., the NGATE node voltage) is pulled up, the second power tube HV_NMOS is turned on, the first power tube HV_PMOS is turned off, and the target driving signal HO is pulled down.

[0092] The voltage range of the target driving signal HO is between the voltage on the first node BST and the voltage on the second node SW, but other MOS tubes in the driving unit 32 work in a voltage domain of about 5V under the action of the clamping voltage VCLAMP, avoiding being broken down.

[0093] Further, by setting the phase of the first control signal A1, the second control signal A2, the third control signal A3 to the first control signal A4 gradually delayed, the step-by-step starting of the gate drive circuit 30 is realized. And the first power tube HV PMOS and the second power tube HV NMOS are not turned on or turned off at the same time, and after the on or off state of the second power tube HV NMOS is determined, the first power tube HV PMOS is turned on or turned off, avoiding the harm of large current to the circuit.

[0094] Embodiment 2

[0095] As shown in FIG. 8, the driving circuit in an embodiment is used to drive the target power tube, and the driving circuit comprises the floating track circuit 10, the control signal generation circuit 20 and the gate drive circuit 30.

[0096] It can be understood that the specific circuit structure of the driving circuit in an embodiment is consistent with that of Embodiment 1, and the difference lies in that the target power tube in an embodiment is a low-voltage side power tube, and the gate drive circuit 30 generates the target driving signal LO to realize the control of the low-voltage side power tube. Therefore, the first node in the embodiment is connected with the power supply voltage PVCC, and the second node is connected with the ground potential PGND. The difference between the power supply voltage PVCC and the ground potential PGND is about 7.5V.

[0097] The floating track circuit 10 uses the reverse breakdown voltage Vzener (about 6V) of the first Zener diode D1 and the second Zener diode D2 to generate the floating voltage VFLOAT and the clamping voltage VCLAMP to realize voltage stabilization. The floating voltage VFLOAT=PVCC-Vzener+V GS , and the clamping voltage VCLAMP=PGND+Vzener.

[0098] Specifically, the control end node of the first MOS tube M1 is clamped to PVCC-Vzener by the first Zener diode D1, and therefore the floating voltage domain PVCC-VFLOAT between the first node and the floating voltage VFLOAT is Vzener-V GS , and the value of the floating voltage domain PVCC-VFLOAT is about 5V, which can ensure that the high-voltage tube under the thin gate process will not be broken down.

[0099] The working principle of the embodiment is similar to that of Embodiment 1, which will not be described here.

[0100] Embodiment 3

[0101] As shown in Fig. 9, a half-bridge driving circuit in an embodiment includes a first driving circuit 41 and a second driving circuit 42. The first driving circuit 41 is the driving circuit in Embodiment 1, the first node is connected to the BST pin in the half-bridge driving circuit, and the second node is connected to the SW pin in the half-bridge driving circuit, for driving the high-voltage side power tube.

[0102] The second driving circuit 42 is the driving circuit in Embodiment 2, the first node is connected to the power supply voltage PVCC, and the second node is connected to the ground potential PVCC, for driving the low-voltage side power tube.

[0103] The output end of the first driving circuit 41 (i.e. the second end of the first power tube HV_PMOS and the second end of the second power tube HV_NMOS) is connected to the logic combination unit of the second driving circuit 42 through a level conversion unit LVL_H2L, and the logic combination unit of the second driving circuit 42 is used for receiving a corresponding PWM signal, and the output end thereof is connected to a corresponding control signal generation circuit.

[0104] The output end of the second driving circuit 42 (i.e. the second end of the first power tube HV_PMOS and the second end of the second power tube HV_NMOS) is connected to the logic combination unit of the first driving circuit 41 through a level conversion unit LVL_H2L, and the logic combination unit of the first driving circuit 41 is used for receiving a corresponding PWM signal, and the output end thereof is connected to a corresponding control signal generation circuit.

[0105] From the above technical solutions, the present application has the following beneficial effects:

[0106] The present application can be applied to a high-voltage driving circuit, and the high-voltage process does not have a thick gate oxide and does not support a high-voltage V GS The floating voltage is generated by the floating circuit, the control signal generation circuit works in the floating voltage domain, i.e. the control signals are signals generated in the floating voltage domain BST-VFLOAT, and therefore the V GS of the input tube in the gate driving circuit works in the range of Vzener-V GS (about 5V), preventing the input tube from being broken down.

[0107] The clamping voltage is generated by the floating circuit, so that the output tube in the gate driving circuit can use a low-voltage tube and will not be broken down by high voltage, improving the response speed of the gate driving circuit and reducing power consumption.

[0108] The gate drive circuit of the present application adopts the structure of push-pull stage, and generates the target drive signal meeting certain drive capacity and stability through step-by-step driving, for a drive circuit, only one set of floating track circuit is needed to make the voltage variation range of the target drive signal between the voltage on the first node and the voltage on the second node.

[0109] The half-bridge drive circuit of the present application adopts the symmetrical structure, and when the target drive signal generated under the low-voltage domain PVCC-PGND is switched to the high-voltage domain BST-SW quickly, the instantaneous change speed of the DC current is avoided to affect the generation of the floating domain.

[0110] It is apparent for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.

[0111] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments that those skilled in the art can understand.

Claims

1. A drive circuit for driving a target power transistor, characterized by, The driving circuit comprises: a floating circuit connected between the first node and the second node, configured to generate a floating voltage based on the voltage on the first node and a clamping voltage based on the voltage on the second node, the floating voltage being less than the voltage on the first node, and the clamping voltage being greater than the voltage on the second node; a control signal generation circuit connected between the first node and the floating voltage, configured to generate a plurality of control signals based on a PWM signal; a gate driving circuit connected between the first node and the second node and connected to the clamping voltage, the gate driving circuit being of a multi-stage structure, each stage of the gate driving circuit corresponding to at least one control signal, and the gate driving circuit being configured to generate a target driving signal based on the plurality of control signals to drive a target power tube.

2. The drive circuit according to claim 1, characterized by The floating circuit comprises a first Zener diode, a first resistor, a second resistor, a first MOS tube, a third resistor, and a second Zener diode; wherein a first end of the first Zener diode is connected to a first end of the first resistor, a second end of the first Zener diode is connected to the first node, and a second end of the first resistor is connected to the second node; a first end of the second resistor is connected to the first node, a second end of the second resistor is connected to the floating voltage, a first end of the first MOS tube is connected to the floating voltage, a second end of the first MOS tube is connected to the second node, and a control end of the first MOS tube is connected to a first end of the first Zener diode; a first end of the third resistor is connected to the first node, a second end of the third resistor is connected to the clamping voltage, a first end of the second Zener diode is connected to the second node, and a second end of the second Zener diode is connected to the clamping voltage.

3. The drive circuit according to claim 2, characterized in that, The floating circuit further comprises: a first capacitor, a first end of the first capacitor being connected to the first node, and a second end of the first capacitor being connected to the floating voltage; a second capacitor, a first end of the second capacitor being connected to the clamping voltage, and a second end of the second capacitor being connected to the second node.

4. The drive circuit according to claim 1, characterized by The gate driving circuit comprises a latch unit, a first driving unit, a second driving unit, a first power tube, and a second power tube; wherein the latch unit is connected to the control signal generation circuit, and is configured to generate a latch signal based on a first control signal and a second control signal, the first control signal and the second control signal being opposite in phase; the first driving unit is connected to the control signal generation circuit and the latch unit, and is configured to generate a first driving signal based on the latch signal and the second control signal; the second driving unit is connected to the first driving unit, and is configured to generate a power tube driving signal based on the first driving signal and a third control signal; a first end of the first power tube is connected to the first node, a control end of the first power tube receives a fourth control signal, and a second end of the first power tube is connected to a control end of the target power tube; a first end of the second power tube is connected to the second node, a control end of the second power tube is connected to the second driving unit and receives the power tube driving signal, and a second end of the second power tube is connected to the control end of the target power tube.

5. The drive circuit according to claim 4, characterized in that, The first driving unit comprises a third input transistor, a third clamp transistor and a third output transistor; wherein a first end of the third input transistor is connected with the first node, a second end of the third input transistor is connected with a second end of the third clamp transistor, and a control end of the third input transistor receives a second control signal; a control end of the third clamp transistor is connected with a clamp voltage, a first end of the third clamp transistor is connected with a second end of the third output transistor; a control end of the third output transistor is connected with the latch unit and receives a latch signal, a first end of the third output transistor is connected with the second node, and a second end of the third output transistor is connected with the second driving unit and generates a first driving signal.

6. The drive circuit according to claim 4, characterized by The second driving unit comprises a fourth input transistor, a fourth clamp transistor and a fourth output transistor; wherein a first end of the fourth input transistor is connected with the first node, a second end of the fourth input transistor is connected with a second end of the fourth clamp transistor, and a control end of the fourth input transistor receives a third control signal; a control end of the fourth clamp transistor is connected with the clamp voltage, a first end of the fourth clamp transistor is connected with a second end of the fourth output transistor; a control end of the fourth output transistor is connected with the first driving unit and receives the first driving signal, a first end of the fourth output transistor is connected with the second node, and a second end of the fourth output transistor is connected with a control end of the second power transistor and generates a power transistor driving signal.

7. The drive circuit according to claim 4, characterized by The control signal generating circuit comprises a plurality of connected inverters, and the plurality of inverters are used for inverting and delaying the PWM signal to generate the first control signal, the second control signal, the third control signal and the fourth control signal; wherein the first control signal is in phase with the PWM signal; the second control signal is opposite to the PWM signal, and the second control signal is delayed from the first control signal; the third control signal is in phase with the PWM signal, and the third control signal is delayed from the second control signal; the fourth control signal is opposite to the PWM signal, and the fourth control signal is delayed from the third control signal.

8. The drive circuit of claim 4, wherein, The latch unit comprises a first input transistor, a second input transistor, a first clamp transistor, a second clamp transistor, a first output transistor and a second output transistor; wherein a first end of the first input transistor is connected with the first node, a second end of the first input transistor is directly or indirectly connected with a second end of the first clamp transistor, and a control end of the first input transistor receives the second control signal; a first end of the second input transistor is connected with the first node, a second end of the second input transistor is directly or indirectly connected with a second end of the second clamp transistor, and a control end of the second input transistor receives the first control signal; control ends of the first clamp transistor and the second clamp transistor are connected with the clamp voltage, a first end of the first clamp transistor is directly or indirectly connected with a second end of the first output transistor, and a first end of the second clamp transistor is directly or indirectly connected with a second end of the second output transistor; a first end of the first output transistor is connected with the second node, and a control end of the first output transistor is connected with the first end of the second clamp transistor; a first end of the second output transistor is connected with the second node, and a control end of the second output transistor is connected with the first end of the first clamp transistor.

9. The drive circuit according to claim 8, characterized in that, The latch unit further comprises a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; wherein, a first end of the fourth resistor is connected with a second end of the first input tube, and a second end of the fourth resistor is connected with a second end of the first clamping tube; a first end of the fifth resistor is connected with a second end of the second input tube, and a second end of the fifth resistor is connected with a second end of the second clamping tube; a first end of the sixth resistor is connected with a first end of the first clamping tube, and a second end of the sixth resistor is connected with a second end of the first output tube; a first end of the seventh resistor is connected with a first end of the second clamping tube, and a second end of the seventh resistor is connected with a second end of the second output tube.

10. The drive circuit of claim 1, wherein, The first node is connected with a BST pin in the driving circuit, the second node is connected with a SW pin in the driving circuit, and the target power tube is a high-voltage side power tube.

11. The drive circuit of claim 1, wherein, The first node is connected with a power supply voltage, the second node is connected with a ground potential, and the target power tube is a low-voltage side power tube.

12. A half bridge drive circuit, characterized by The half-bridge driving circuit comprises a first driving circuit and a second driving circuit; wherein, The first driving circuit is the driving circuit in any one of claims 1-10. The second driving circuit is the driving circuit in any one of claims 1-9 or 11.

13. A half bridge drive circuit, characterized by The half-bridge driving circuit comprises a first driving circuit and a second driving circuit, and the first driving circuit is the driving circuit in any one of claims 1-10.

14. A half bridge drive circuit, characterized by The half-bridge driving circuit comprises a first driving circuit and a second driving circuit, and the second driving circuit is the driving circuit in any one of claims 1-9 or 11.

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