Display substrate, manufacturing method therefor, and display apparatus

Abstract

The present disclosure belongs the technical field of display, and provides a display substrate, a manufacturing method therefor and a display apparatus. The display substrate comprises: a substrate, comprising a display region and a peripheral region surrounding the display region, the peripheral region comprising a binding region located on a side of the display region; a plurality of sub-pixels, located on a side of the substrate and in the display region; a plurality of data lines, located in the display region and extending to the binding region, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of first contact pads, located in the binding region and connected to the plurality of data lines; a plurality of second contact pads, located in the binding region and on the sides of the plurality of first contact pads away from the display region, the plurality of first contact pads and the plurality of second contact pads being configured to be bound to a driving chip; and a plurality of virtual wires, located on the sides of the plurality of first contact pads close to the display region and on at least one side of the plurality of data lines in a first direction. The present disclosure can improve the display effect.

Description

Display substrate, manufacturing method thereof and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202411388611.8, filed on September 30, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and particularly refers to a display substrate, a manufacturing method thereof, and a display device. BACKGROUND

[0004] OLED (Organic Light-Emitting Diode) display devices have been listed as the next generation display technology with great development prospects due to their advantages such as thinness, lightness, wide viewing angle, active light-emitting, continuous adjustable light-emitting color, low cost, fast response speed, small energy consumption, low driving voltage, wide operating temperature range, simple production process, high light-emitting efficiency, and flexible display. SUMMARY

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate, a manufacturing method thereof, and a display device, which can improve the display effect of the display device.

[0006] To solve the above technical problems, the embodiments of the present disclosure provide the technical solutions as follows:

[0007] In one aspect, a display substrate is provided, comprising:

[0008] a substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a binding area located at one side of the display area;

[0009] a plurality of sub-pixels located at one side of the substrate and in the display area;

[0010] a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0011] a plurality of first contact pads located in the binding area and connected to the plurality of data lines;

[0012] a plurality of second contact pads located in the binding area and located at one side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound with a driving chip;

[0013] A plurality of virtual traces are located on at least one side of the plurality of data lines along the first direction and are located on one side of the plurality of first contact pads close to the display area.

[0014] In some embodiments, the plurality of data lines comprises a first group of data lines and a second group of data lines arranged along the first direction, and the plurality of virtual traces are located on at least one side of the first group of data lines along the first direction and / or are located on at least one side of the second group of data lines along the first direction.

[0015] In some embodiments, the plurality of virtual traces are located on both sides of the first group of data lines along the first direction and on both sides of the second group of data lines along the first direction.

[0016] In some embodiments, the display substrate further comprises virtual data lines located on both sides of the first group of data lines along the first direction and on both sides of the second group of data lines, and arranged one by one with the plurality of virtual traces along a second direction intersecting the first direction.

[0017] In some embodiments, the plurality of first contact pads comprises a first group of contact pads and a second group of contact pads arranged along the first direction, the first group of data lines are connected with the first group of contact pads, and the second group of data lines are connected with the second group of contact pads.

[0018] In some embodiments, the connection between the virtual traces and the first contact pads is disconnected.

[0019] In some embodiments, the extension direction of the virtual traces between the first group of data lines and the second group of data lines is parallel to the extension direction of at least part of the data lines.

[0020] In some embodiments, the virtual traces between the first group of data lines and the second group of data lines are parallel to the first direction.

[0021] In some embodiments, the virtual traces between the first group of data lines and the second group of data lines are in block shape and arranged in an array between the first group of data lines and the second group of data lines.

[0022] In some embodiments, the virtual traces extend to between a plurality of the first contact pads.

[0023] In some embodiments, the display substrate comprises a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer, a first source-drain metal layer, a third insulating layer, a second source-drain metal layer, and a fourth insulating layer arranged in sequence on the substrate.

[0024] The data line and the virtual trace are made of the first gate metal layer.

[0025] In some embodiments, the display substrate further comprises:

[0026] a binding area interlayer insulating layer located in the binding area and between the plurality of first contact pads and the data line;

[0027] a binding area first gate insulating layer located in the binding area and on a side of the binding area interlayer insulating layer close to the base; and

[0028] a binding area second gate insulating layer located in the binding area and between the binding area first gate insulating layer and the binding area interlayer insulating layer, and stacked with the binding area interlayer insulating layer;

[0029] The binding area second gate insulating layer comprises a first contact pad via hole, the binding area interlayer insulating layer comprises a second contact pad via hole, and at least one of the plurality of data lines is electrically connected to the first contact pad through the first contact pad via hole and the second contact pad via hole.

[0030] In some embodiments, the display substrate further comprises a binding area third insulating layer,

[0031] The binding area third insulating layer is located in the binding area and is arranged on a side of the first contact pad away from the base to cover the first contact pad.

[0032] The binding area third insulating layer has a third contact pad via hole to expose a surface of the first contact pad.

[0033] In some embodiments, the display substrate further comprises an auxiliary conductive layer,

[0034] The auxiliary conductive layer is located in the binding area and is arranged on a side of the binding area third insulating layer away from the base.

[0035] The auxiliary conductive layer comprises a second transfer electrode pattern located in the binding area.

[0036] The second transfer electrode pattern is electrically connected to the first contact pad through the third contact pad via hole.

[0037] Embodiments of the present disclosure also provide a display device comprising the display substrate as described above.

[0038] Embodiments of the present disclosure also provide a manufacturing method of a display substrate, comprising:

[0039] A substrate is provided, which includes a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located at one side of the display area;

[0040] A plurality of sub-pixels are formed on the substrate, the sub-pixels being located in the display area;

[0041] A plurality of data lines are formed on the substrate, the data lines being located in the display area and extending to the binding area, the plurality of data lines being electrically connected with the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0042] A plurality of first contact pads are formed on the substrate, the first contact pads being located in the binding area and connected with the plurality of data lines;

[0043] A plurality of second contact pads are formed on the substrate, the second contact pads being located in the binding area and located at one side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound with a driving chip;

[0044] A plurality of virtual traces are formed on the substrate, the virtual traces being located at one side of the plurality of first contact pads close to the display area and located on at least one side of the plurality of data lines along a first direction.

[0045] Embodiments of the present disclosure have the following beneficial effects:

[0046] In the above scheme, the virtual traces are arranged at one side of the plurality of first contact pads close to the display area, and the virtual traces are located on at least one side of the data lines. The stress of the edge area of the data lines and the stress of the central area of the data lines are uniform through the virtual traces, so that the heat dissipation of the edge area of the data lines and the heat dissipation of the central area of the data lines are uniform. The deformation of the display substrate in the area where the plurality of contact pads are located is avoided, and the cracks or film peeling of the local film layer is avoided, thereby improving the display effect of the display device. BRIEF DESCRIPTION OF DRAWINGS

[0047] FIG. 1A is a structural schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0048] FIG. 1B is a structural schematic diagram of another display substrate according to an embodiment of the present disclosure;

[0049] FIG. 2 is a partial schematic diagram of a first signal access area according to an embodiment of the present disclosure;

[0050] FIG. 3 is a detailed enlarged view of the area S in FIG. 2;

[0051] FIG. 4 is a cross-sectional schematic diagram of the display area of the display substrate shown in FIG. 1A along the line aa';

[0052] FIG. 5 is an enlarged schematic view of the S1 region in FIGS. 1A and 1B;

[0053] FIG. 6 is an enlarged schematic view of the S2 region in FIGS. 1A and 1B;

[0054] FIG. 7 is an enlarged schematic view of the S3 region in FIGS. 1A and 1B;

[0055] FIG. 8 is an enlarged schematic view of the S4 region in FIGS. 1A and 1B;

[0056] FIG. 9 is a partial schematic view of a peripheral region of a display substrate;

[0057] FIG. 10 is a partial schematic view of a peripheral region of a display substrate according to an embodiment of the present disclosure;

[0058] FIG. 11 is a partial schematic view of a peripheral region of a display substrate according to another embodiment of the present disclosure;

[0059] FIG. 12 is a partial schematic view of a peripheral region of a display substrate according to yet another embodiment of the present disclosure;

[0060] FIG. 13 is a partial schematic view of a peripheral region of a display substrate according to still another embodiment of the present disclosure;

[0061] FIG. 14 is a partial schematic view of a peripheral region of a display substrate according to yet another embodiment of the present disclosure;

[0062] FIG. 15 is a cross-sectional schematic view of a contact pad according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present disclosure.

[0064] It can be understood that the drawings in the embodiments of the present disclosure are only used to schematically show the connection relationship between the components, the sizes of the components in the drawings are not drawn according to the proportion, and their relative positional relationship does not necessarily correspond to the actual position completely.

[0065] In the present disclosure, unless specifically defined and limited otherwise, the terms "mounting", "connecting", "connecting", "fixing" and the like should be broadly interpreted, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances

[0066] In the present disclosure, "electrically connected" includes the case where elements are connected together through elements having certain electrical effects. "Elements having certain electrical effects" are not particularly limited as long as they can perform the transmission of electrical signals between the constituent elements to be connected. Examples of "elements having certain electrical effects" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0067] In the present disclosure, "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced by "conductive film". Similarly, "insulating film" can sometimes be replaced by "insulating layer".

[0068] The "patterning process" in the present disclosure includes processes such as deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist. Deposition can use any one or more selected from sputtering, evaporation, and chemical vapor deposition, coating can use any one or more selected from spraying and spin coating, and etching can use any one or more selected from dry etching and wet etching. "Thin film" refers to a thin film of a certain material made on a substrate using deposition or coating process. If the "thin film" does not require a patterning process throughout the entire manufacturing process, the "thin film" can also be referred to as a "layer". When the "thin film" still requires a patterning process throughout the entire manufacturing process, it is referred to as a "thin film" before the patterning process, and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

[0069] FIG. 1A is a schematic view of a display substrate according to an embodiment of the present disclosure. FIG. 1B is another schematic view of a display substrate according to an embodiment of the present disclosure. Both FIG. 1A and FIG. 1B are planar schematic views of the display substrate before the bending process.

[0070] In some examples, as shown in FIGS. 1A and 1B, the display substrate can include a display area AA and a peripheral area BB surrounding the display area AA periphery. For example, the peripheral area BB can include a first border area B1 located at one side of the display area AA, and border areas (e.g., which can include a second border area B2, a third border area B3, and a fourth border area B4) located at other sides of the display area AA. For example, the first border area B1 can be a lower border of the display panel, the second border area B2 can be an upper border of the display panel, the third border area B3 can be a left border of the display panel, and the fourth border area B4 can be a right border of the display panel.

[0071] In some examples, as shown in FIGS. 1A and 1B, the display area AA can be a flat area including a plurality of sub-pixels PX constituting a pixel array, and the plurality of sub-pixels PX can be configured to display dynamic pictures or still images. The display area AA can be referred to as an active area. In some examples, the display area AA can be rectangular. However, the present embodiments are not limited thereto. For example, the display area AA can be circular or elliptical or other shapes. In some examples, the display panel can be a flexible panel, and thus the display panel can be deformable, such as being rolled, bent, folded, or rolled up.

[0072] In some examples, as shown in FIGS. 1A and 1B, the display area AA can include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL can extend along a first direction X, and the plurality of data lines DL can extend along a second direction Y. The orthogonal projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate can cross to form a plurality of sub-pixel regions, and one sub-pixel PX can be disposed in each sub-pixel region. The plurality of data lines DL can be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL can be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL can be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL can be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals can include scan signals and light-emitting control signals, or can include scan signals, or can include scan signals, reset control signals, and light-emitting control signals.

[0073] In some examples, as shown in FIGS. 1A and 1B, the first direction X can be an extension direction (e.g., a row direction) of the gate lines GL in the display area AA, and the second direction Y can be an extension direction (e.g., a column direction) of the data lines DL in the display area AA. The first direction X and the second direction Y can intersect each other, such as being perpendicular to each other.

[0074] In some examples, one pixel unit of the display area AA can include three sub-pixels, which are a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively. However, the present embodiment is not limited thereto. In some examples, one pixel unit can include four sub-pixels, which are a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel respectively.

[0075] In some examples, the shape of a sub-pixel can be rectangular, diamond, pentagonal or hexagonal. When one pixel unit includes three sub-pixels, the three sub-pixels can be arranged in a horizontal parallel, a vertical parallel or a triangular manner. When one pixel unit includes four sub-pixels, the four sub-pixels can be arranged in a horizontal parallel, a vertical parallel or a square manner. However, the present embodiment is not limited thereto.

[0076] In some examples, one sub-pixel can include a pixel circuit and a light emitting element electrically connected to the pixel circuit (as indicated by L in FIG. 1A, please note that, for the sake of simplicity, only the light emitting element L in one sub-pixel PX is shown in FIG. 1A, which does not represent a limitation on the present disclosure). The pixel circuit can include a plurality of transistors and at least one capacitor. For example, the pixel circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit can include P-type transistors and N-type transistors. However, the present embodiment is not limited thereto.

[0077] In some examples, the plurality of transistors in the pixel circuit can be low temperature poly-silicon thin film transistors and oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate, i.e. LTPS+Oxide (abbreviated as LTPO) display substrate, can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0078] In some examples, the light emitting element can be any one of a light emitting diode (LED), an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro LED (including: mini-LED or micro-LED), etc. For example, the light emitting element can be an OLED, which can emit red light, green light, blue light, or white light, etc. under the driving of the corresponding pixel circuit. The color of the light emitted by the light emitting element can be determined as needed. In some examples, the light emitting element can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element can be electrically connected to the corresponding pixel circuit. However, the present embodiments are not limited thereto.

[0079] In some examples, the display substrate can integrate a touch structure. The display substrate can include an organic light emitting diode display structure, or can be a plasma display structure, or can be an electrophoretic display structure. For example, the display substrate can include an OLED display structure and a touch structure. The touch structure can be disposed on the encapsulation layer of the display structure, forming a touch on thin film encapsulation (Touch on TFE) structure. The display structure and the touch structure are integrated together, which has the advantages of thinness, foldability, etc., and can meet the product requirements of flexible folding, narrow frame, etc.

[0080] In some examples, the touch on thin film encapsulation structure mainly includes a flexible multi-layer on cell (FMLOC) structure and a flexible single-layer on cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection, generally uses two layers of metal to form a driving (Tx) electrode and a sensing (Rx) electrode, and an integrated circuit (IC) realizes touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection, generally uses a single layer of metal to form a touch electrode, and an integrated circuit realizes touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0081] FIG. 4 is a schematic view of a cross section along line aa' of the display region of the display substrate shown in FIG. 1A. In FIG. 4, the structure of one sub-pixel of the display region is taken as an example for illustration. In the present example, the same type of transistors in the pixel circuit is taken as an example for illustration, for example, the transistors in the pixel circuit can all be low-temperature polysilicon thin film transistors or all be oxide thin film transistors. In other examples, the transistors in the pixel circuit can be low-temperature polysilicon thin film transistors and oxide thin film transistors. In addition, the present example takes the display panel integrating a mutual-capacitance touch structure to form an FMLOC structure as an example for illustration.

[0082] In some examples, as shown in FIG. 4, in a direction perpendicular to the display panel, the display region of the display panel can include: a substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 arranged in sequence on the substrate 100. The display structure layer can include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 can include at least: pixel circuits of a plurality of sub-pixels, and each pixel circuit of a sub-pixel can include a plurality of transistors and at least one capacitor. The light-emitting structure layer 30 can include at least: light-emitting elements of a plurality of sub-pixels.

[0083] In some examples, FIG. 4 is shown as an example of one thin film transistor 21 and one capacitor 22 included in each sub-pixel. In some examples, the circuit structure layer 20 of the display area can include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The plurality of display area metal layers of the display structure layer of the present example can include the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer. A first gate insulating layer 201 can be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 can be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 can be disposed between the second gate metal layer and the first source-drain metal layer, a passivation layer 204 and a first planarization layer 205 can be disposed between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer 206 can be disposed between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer 207 can be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 can be inorganic insulating layers, and the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can also be disposed on the side of the semiconductor layer close to the substrate, which can prevent harmful substances in the substrate from invading the inside of the display substrate, and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) can be disposed on the side of the buffer layer close to the substrate, which can be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to avoid the influence of external light on the performance of the thin film transistor. In other examples, the passivation layer can be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planarization layer can be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0084] In some examples, as shown in FIG. 4, the semiconductor layer of the display region can at least include: the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 can include: the first region 2101, the second region 2102, and the channel region 2100 between the first region 2101 and the second region 2102. The first gate metal layer can at least include: the gate 213 of the thin-film transistor 21, and the first plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 on the substrate 100 can cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 100. The second gate metal layer can at least include: the second plate 222 of the capacitor 22. The orthographic projection of the second plate 222 and the first plate 221 of the capacitor 22 on the substrate 100 can at least partially overlap, for example, the two can coincide. The first source-drain metal layer can at least include: the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 can be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display region. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 in the first pixel via can be removed, exposing at least part of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 in the second pixel via can be removed, exposing at least part of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer can at least include: the first transfer electrode 231. The first transfer electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through the third pixel via provided by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer can at least include: the second transfer electrode 232. The second transfer electrode 232 can be electrically connected to the first transfer electrode 231 of the second source-drain metal layer through the fourth pixel via provided by the second planarization layer 206. The first transfer electrode 231 can be electrically connected to the first electrode 301 (for example, anode) of the light-emitting element through the fifth pixel via provided by the third planarization layer 207. The present example can realize the electrical connection between the pixel circuit and the light-emitting element through the first transfer electrode 231 and the second transfer electrode 232.

[0085] In some examples, the gate lines of the display area can be located in the first gate metal layer or the second gate metal layer, for example, the data lines of the display area can be located in the second source-drain metal layer or the third source-drain metal layer, and the high-potential power lines of the display area can be located in at least one of the second source-drain metal layer and the third source-drain metal layer. The embodiments are not limited in this regard. The circuit structure layer of the present example can include three source-drain metal layers, which can avoid arranging more traces in a single source-drain metal layer, thereby facilitating the realization of a narrow frame structure.

[0086] In some examples, as shown in FIG. 4, the light-emitting structure layer 30 can include a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element can include a first electrode 301, an organic light-emitting layer 302, and a second electrode 303 stacked. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on the third planar layer 207 and electrically connected to the second transfer electrode 232 through the fifth pixel via hole of the third planar layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 207, and the pixel definition layer 304 can be provided with a plurality of pixel openings, and each pixel opening can expose at least part of the surface of the corresponding first electrode 301. At least part of the organic light-emitting layer 302 can be disposed in one pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. The side of the pixel definition layer 304 away from the substrate 100 can also be provided with a spacer layer, and the spacer layer can include a plurality of spacers (PS).

[0087] In some examples, the organic light-emitting layer 302 of the light-emitting element can include an emitting layer (EML) and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be utilized to emit light according to the required gray scale.

[0088] In some examples, the light-emitting layers of the light-emitting elements of different colors can be different. For example, the red light-emitting element includes a red light-emitting layer, the green light-emitting element includes a green light-emitting layer, and the blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer located on one side of the light-emitting layer can adopt a common layer, and the electron injection layer and the electron transport layer located on the other side of the light-emitting layer can adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by one process (one evaporation process or one inkjet printing process), and the isolation can be realized by the surface step of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be prepared by evaporation using a fine metal mask (FMM) or an open mask, or by using an inkjet process.

[0089] In some examples, as shown in FIG. 4, in the direction perpendicular to the substrate, the encapsulation structure layer 40 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked. The first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high compactness and can prevent the invasion of water, oxygen, etc. The second encapsulation layer 402 can be made of organic materials. The second encapsulation layer 402 can be arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external water vapor from entering the light-emitting element. The second encapsulation layer 402 can be made of organic materials, for example, can be a high polymer material containing a desiccant or a high polymer material capable of blocking water vapor, etc., or can be a high polymer resin, etc. to perform a planarization process on the surface of the display panel, and can relieve the stress of the first encapsulation layer 401 and the third encapsulation layer 403, and can also include a water-absorbing material such as a desiccant to absorb water, oxygen, etc. invading the inside. However, the present embodiment is not limited thereto. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0090] In some examples, the touch structure layer of the display area can include a plurality of first touch electrodes, a plurality of first connection portions, a plurality of second touch electrodes, and a plurality of second connection portions. The plurality of first touch electrodes can be arranged in the same layer, and adjacent first touch electrodes can be connected by the first connection portion. The plurality of second touch electrodes can be arranged in the same layer, and adjacent second touch electrodes can be connected by the second connection portion.

[0091] In some examples, as shown in FIG. 4, in a direction perpendicular to the substrate, the touch structure layer 50 of the display area can include, in sequence, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch layer insulation layer (TLD) 502, and a second touch conductive layer 512. The touch buffer layer 501 and the touch layer insulation layer 502 can be inorganic insulation layers, for example, SiNx layers. The first touch conductive layer 511 can include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions. The first touch electrodes and the first connecting portions can be an integrated structure connected to each other. The second touch conductive layer 512 can include a plurality of second connecting portions. The second connecting portions can be connected to adjacent second touch electrodes through vias formed in the touch layer insulation layer. However, the present embodiment is not limited in this regard. In other examples, the first touch conductive layer can include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, and the second touch electrodes and the second connecting portions can be an integrated structure connected to each other; the second touch conductive layer can include a plurality of first connecting portions, and the first connecting portions can be connected to adjacent first touch electrodes through vias formed in the touch layer insulation layer. In some examples, the first touch electrodes can be drive (Tx) electrodes, and the second touch electrodes can be sense (Rx) electrodes. Alternatively, the first touch electrodes can be sense (Rx) electrodes, and the second touch electrodes can be drive (Tx) electrodes. The present embodiment is not limited in this regard.

[0092] In some examples, the first touch electrodes and the second touch electrodes can have a diamond shape, for example, a regular diamond shape, or a horizontally long diamond shape, or a vertically long diamond shape. In other examples, the first touch electrodes and the second touch electrodes can have any one or more of a triangular shape, a square shape, a trapezoidal shape, a parallelogram shape, a pentagonal shape, a hexagonal shape, and other polygonal shapes, without limitation in this regard.

[0093] In some examples, the first touch electrodes and the second touch electrodes can be transparent conductive electrodes. In other examples, the first touch electrodes and the second touch electrodes can be metal mesh patterns formed by interlacing a plurality of metal lines, and the metal mesh patterns can include a plurality of mesh patterns, which can be polygons formed by a plurality of metal lines. The first touch electrodes and the second touch electrodes in the form of metal mesh patterns have the advantages of small resistance, small thickness, and fast response speed.

[0094] In some examples, as shown in FIG. 4, in a direction perpendicular to the substrate, the color filter on encapsulation (COE) 60 can include, in sequence, an insulating layer 601, a color film layer, and an overcoat 602, where the color film layer includes a black matrix 610 and color filter units 611 arranged between the black matrix 610, and the color filter units 611 can be, for example, red filter units, green filter units, or blue filter units.

[0095] In some examples, as shown in FIG. 1A, the first bezel area B1 of the display panel can include, in sequence along a direction away from the display area AA, a fan-out wire area B11 and a signal access area B12. In FIG. 1A, only a number of wires in the first bezel area are shown for illustration. The present example is not limited to the number of wires in the first bezel area.

[0096] In some examples, as shown in FIG. 1A, the fan-out wire area B11 can be connected between the display area AA and the signal access area B12. The fan-out wire area B11 can be provided with at least a plurality of data fan-out wires 42. The plurality of data fan-out wires 42 can be electrically connected to the plurality of data lines DL in the display area AA, for example, the plurality of data fan-out wires 42 and the plurality of data lines DL can be one-to-one electrically connected. The plurality of data fan-out wires 42 can extend to the signal access area B12 in a fan-out wire manner. The plurality of data fan-out wires 42 and the plurality of data lines DL can be located in different film layers, and the data fan-out wires 42 can be connected to the data lines DL through vias formed in the insulating layer.

[0097] In some examples, as shown in FIG. 1A, the signal access area B12 can include at least one first signal access area B121. The present example takes one first signal access area as an example for illustration and description. In other examples, the display panel is a large-size panel, and the display panel can include a plurality of first signal access areas, and the plurality of first signal access areas can be arranged in sequence along the first direction X.

[0098] In some examples, as shown in FIG. 1A, the first signal access area B121 can also be referred to as a driving chip (IC) setting area. The first signal access area B121 can be provided with a plurality of contact pads 31, which can be configured to be connected with at least one driving chip. The driving chip can be configured to generate a driving signal required for driving a sub-pixel and provide the driving signal to the data lines DL of the display area AA. For example, the driving signal can be a data signal for driving a sub-pixel. In some examples, the driving chip can be a central processing unit, a digital signal processor, a system chip (SoC), etc. For example, the driving chip can also include hardware circuits and computer executable codes, etc. The hardware circuits can include conventional very large scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete elements; the hardware circuits can also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0099] In some examples, as shown in FIG. 1A, the signal access area B12 can be provided with at least a plurality of data lines 101, which can be electrically connected with, for example, one-to-one corresponding electrically connected with, the plurality of data fan-out lines 42 of the fan-out area B11. For example, the data line 101 and the connected data fan-out line 42 can be an integrated structure connected with each other. That is, the plurality of data lines 101 are electrically connected with, for example, one-to-one corresponding electrically connected with, the plurality of data lines DL through the plurality of data fan-out lines 42. The plurality of data lines 101 can extend into the first signal access area B121 and be electrically connected with the plurality of contact pads 31 in the first signal access area B121. For example, the plurality of data lines 101 and the plurality of contact pads 31 can be one-to-one corresponding electrically connected, or one data line 101 can be electrically connected with at least one contact pad 31. The data line 101 and the data fan-out line 42 can transmit the data signal provided by the driving chip to the data line DL of the display area.

[0100] In some examples, as shown in FIG. 1B, the first frame area B1 of the display substrate can include, in sequence along the direction away from the display area AA, the fan-out area B11, the bending area B13, and the signal access area B12. In FIG. 1B, only a few wires in the first frame area are shown for illustration. The number of wires in the first frame area is not limited in the present example.

[0101] In some examples, as shown in FIG. IB, the bending region B13 can be connected between the fan-out wiring region B11 and the signal access region B12, and can be configured to bend the signal access region B12 to the back of the display region AA. The bending region B13 can be provided with at least a plurality of data bending connection lines 43. One end of the data bending connection line 43 can be connected with the data fan-out line 42 in the fan-out wiring region B11, and the other end can be connected with the data line 101 in the signal access region B12. The plurality of data bending connection lines 43 can be in the same layer, for example, in the first source-drain metal layer or the second source-drain metal layer. The remaining structures of the first bezel region B1 in this example can refer to the descriptions of the foregoing embodiments, and will not be described here again.

[0102] As shown in FIG. 1A and FIG. IB, the signal access region B12 can further include a second signal access region B122, and the second signal access region B122 is provided with a plurality of contact pads 32 for binding with a flexible circuit board. The contact pad described in the disclosure below refers to the contact pad 31 of the first signal access region B121, which is used for binding with at least one driving chip.

[0103] FIG. 2 is a partial enlarged view of the first signal access region of the embodiment of the disclosure. In some examples, as shown in FIG. 2, the plurality of contact pads 31 of the first signal access region B121 can be arranged in multiple rows (for example, four rows). Each row includes a plurality of contact pads 31 arranged in sequence along the first direction X, and the multiple rows of contact pads 31 can be arranged in sequence along the second direction Y. The contact pads 31 of adjacent two rows can be arranged in staggered manner in the first direction X. However, the embodiment is not limited thereto. In other examples, the plurality of contact pads of the first signal access region B121 can be arranged in one row.

[0104] In some examples, the plurality of contact pads 31 of the first signal access area can be divided into at least a plurality of groups (e.g., two groups). FIG. 2 schematically and illustratively shows two groups of contact pads (e.g., a first group of contact pads 31A and a second group of contact pads 31B, the first group of contact pads 31A including a plurality of first contact pads 311, and the second group of contact pads 31B including a plurality of second contact pads 312). The second group of contact pads 31B can be located on a side of the first group of contact pads 31A away from the display area. The first group of contact pads 31A can include three rows of first contact pads 311 arranged along the first direction X. The second group of contact pads 31B can include one row of second contact pads 312 arranged along the first direction X. In some examples, the second group of contact pads 31B is used to input signals, which are converted by the bonded IC and output to the first group of contact pads 31A, and the first group of contact pads 31A transmits signals (e.g., data signals) to the plurality of sub-pixels PX through a plurality of signal lines (e.g., a plurality of data lines DL). The first group of contact pads 31A and the second group of contact pads 31B can be arranged staggered in the first direction X. For example, the contact pads in the first group of contact pads 31A and the second group of contact pads 31B can not be aligned in the second direction Y. There is a gap between adjacent contact pads in the same group, and there is a gap between contact pads of adjacent groups. In some embodiments, a group of contact pads can be one row of contact pads, two rows of contact pads, or three rows of contact pads. The number of rows of contact pads and the number of contact pads per row are not limited in the present disclosure.

[0105] FIG. 3 is an enlarged view of the area S in FIG. 2. In some examples, as shown in FIG. 3, the plurality of data lines 101 can extend in the gap between the plurality of contact pads 31 substantially along the second direction Y. For example, two data lines 101 can be arranged between two adjacent contact pads 31 of a group of contact pads. One data line 101 can be electrically connected to at least one contact pad 31, for example, one data line 101 can be connected to one contact pad 31.

[0106] When the driving chip is bonded to the lower frame of the display substrate, the bonding area of the display substrate is affected by the bonding stress, and is prone to deformation. When the deformation is severe, it can cause cracks or peeling of the film layer of the driving chip, thereby affecting the reliability and stability of the display product.

[0107] Embodiments of the present disclosure provide a display substrate, comprising:

[0108] a substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a bonding area located on a side of the display area;

[0109] a plurality of sub-pixels located on a side of the substrate and in the display area;

[0110] a plurality of data lines located in the display region and extending to the binding area, the plurality of data lines being electrically connected with the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels;

[0111] a plurality of first contact pads located in the binding area and connected with the plurality of data lines;

[0112] a plurality of second contact pads located in the binding area and located on a side of the plurality of first contact pads away from the display region, the plurality of first contact pads and the plurality of second contact pads being configured to be bound with a driving chip;

[0113] a plurality of virtual wires located on a side of the plurality of first contact pads close to the display region and located on at least one side of the plurality of data lines along a first direction.

[0114] In this embodiment, the virtual wires are arranged on the side of the plurality of first contact pads close to the display region, and the virtual wires are located on at least one side of the data lines. The stress of the edge region of the data lines and the stress of the central region of the data lines are uniform through the virtual wires, the heat dissipation of the edge region of the data lines and the heat dissipation of the central region of the data lines are uniform, the deformation of the display substrate in the region of the plurality of contact pads is avoided, the local film layer is prevented from cracking or film layer peeling, and thus the display effect of the display device is improved.

[0115] FIG. 5 is an enlarged schematic view of an S1 region in FIGS. 1A and 1B; FIG. 6 is an enlarged schematic view of an S2 region in FIGS. 1A and 1B; FIG. 7 is an enlarged schematic view of an S3 region in FIGS. 1A and 1B; and FIG. 8 is an enlarged schematic view of an S4 region in FIGS. 1A and 1B.

[0116] As shown in FIGS. 5-8, the plurality of first contact pads 311 are arranged along a first direction, the plurality of second contact pads 312 are arranged along the first direction, and the data lines 101 are connected with the first contact pads 311.

[0117] The plurality of data lines include a first group of data lines A1 and a second group of data lines A2 arranged along the first direction, the plurality of first contact pads 311 include a first group of contact pads E1 and a second group of contact pads E2 arranged along the first direction, the first group of contact pads E1 and the second group of contact pads E2 are arranged along the first direction, the first group of data lines A1 is connected with the first group of contact pads E1, and the second group of data lines A2 is connected with the second group of contact pads E2.

[0118] If the region C1 between the first group of data lines A1 and the gate drive circuit lead-out line 411 in the direction in which the first group of data lines A1 is away from the second group of data lines A2, that is, the edge region of the first group of data lines A1 is not provided with a data line, the region C1 and the wiring distribution density of the region where the first group of data lines A1 is located are different, the stress and heat dissipation are uneven, and the data line is prone to falling off. As shown in FIG. 5, in the embodiment, a plurality of virtual wires 313 can be arranged in the direction in which the first group of data lines A1 is away from the second group of data lines A2, that is, on the side of the first group of data lines A1 away from the second group of data lines A2 along the first direction, that is, in the region C1. In this way, the heat dissipation and stress of the region C1 and the region where the first group of data lines A1 is located can be uniform, the display substrate is prevented from being deformed in the region where the plurality of contact pads are located, and then the local film layer is prevented from being cracked or peeled off, so that the display effect of the display device is improved.

[0119] In some embodiments, the region C1 is further provided with a virtual data line 314, the virtual data line 314 is arranged one by one along the second direction with the plurality of virtual wires 313, and the plurality of virtual data lines 314 are located on the side of the first group of data lines A1 away from the second group of data lines A2 along the first direction. In this way, the heat dissipation and stress of the region C1 and the region where the first group of data lines A1 is located can be further uniform, the display substrate is prevented from being deformed in the region where the plurality of contact pads are located, and then the local film layer is prevented from being cracked or peeled off, so that the display effect of the display device is improved.

[0120] As shown in FIG. 6, in the embodiment, a plurality of virtual wires 313 can be arranged in the direction in which the first group of data lines A1 is close to the second group of data lines A2, that is, on the side of the first group of data lines A1 close to the second group of data lines A2 along the first direction, that is, in the region C2. In this way, the heat dissipation and stress of the region C2 and the region where the first group of data lines A1 is located can be uniform, the display substrate is prevented from being deformed in the region where the plurality of contact pads are located, and then the local film layer is prevented from being cracked or peeled off, so that the display effect of the display device is improved.

[0121] In some embodiments, the region C2 is further provided with a virtual data line 314, the virtual data line 314 is arranged one by one along the second direction with the plurality of virtual wires 313, and the plurality of virtual data lines 314 are located on the side of the first group of data lines A1 close to the second group of data lines A2 along the first direction. In this way, the heat dissipation and stress of the region C2 and the region where the first group of data lines A1 is located can be further uniform, the display substrate is prevented from being deformed in the region where the plurality of contact pads are located, and then the local film layer is prevented from being cracked or peeled off, so that the display effect of the display device is improved.

[0122] As shown in FIG. 7, in the embodiment, a plurality of virtual traces 313 can be arranged in the direction in which the second group of data lines A2 is close to the first group of data lines A1, and the plurality of virtual traces 313 are located on the side of the second group of data lines A2 close to the first group of data lines A1 along the first direction, i.e., in region C3. In this way, the heat dissipation and stress of region C3 and the region where the first group of data lines A1 is located can be uniform, the deformation of the display substrate in the region where the plurality of contact pads is located can be avoided, the local film layer can be prevented from cracking or film layer peeling, and thus the display effect of the display device can be improved.

[0123] In some embodiments, a virtual data line 314 is further arranged in region C3, the virtual data line 314 is arranged one by one in correspondence with the plurality of virtual traces 313 along the second direction, and the plurality of virtual data lines 314 are located on the side of the second group of data lines A2 away from the first group of data lines A1 along the first direction. In this way, the heat dissipation and stress of region C3 and the region where the second group of data lines A2 is located can be further uniform, the deformation of the display substrate in the region where the plurality of contact pads is located can be avoided, and thus the display effect of the display device can be improved.

[0124] As shown in FIG. 8, in the embodiment, a plurality of virtual traces 313 can be arranged in the direction in which the second group of data lines A2 is away from the first group of data lines A1, and the plurality of virtual traces 313 are located on the side of the second group of data lines A2 away from the first group of data lines A1 along the first direction, i.e., in region C4. In this way, the heat dissipation and stress of region C4 and the region where the first group of data lines A1 is located can be uniform, the deformation of the display substrate in the region where the plurality of contact pads is located can be avoided, the local film layer can be prevented from cracking or film layer peeling, and thus the display effect of the display device can be improved.

[0125] In some embodiments, a virtual data line 314 is further arranged in region C4, the virtual data line 314 is arranged one by one in correspondence with the plurality of virtual traces 313 along the second direction, and the plurality of virtual data lines 314 are located on the side of the second group of data lines A2 away from the first group of data lines A1 along the first direction. In this way, the heat dissipation and stress of region C4 and the region where the second group of data lines A2 is located can be further uniform, the deformation of the display substrate in the region where the plurality of contact pads is located can be avoided, and thus the display effect of the display device can be improved.

[0126] In the embodiment, the virtual traces 313 are only used to make the stress and heat dissipation of different regions uniform, and the virtual traces 313 are not used for signal transmission. Therefore, the connection between the virtual traces 313 and the first contact pads 311 is disconnected.

[0127] In the embodiment, the virtual data lines 314 are only used to make the stress and heat dissipation of different regions uniform, and the virtual data lines 314 are not used to transmit signals, and therefore, the connection between the virtual traces 313 and the virtual data lines 314 is disconnected.

[0128] In the embodiment, the virtual traces 313 can be linear, and can also be in other shapes; and the extension direction of the virtual traces 313 can be parallel to the extension direction of the data lines 101, and can also be parallel to other directions.

[0129] For example, the regions S2 and S3, as shown in FIG. 9, the data lines 101 extend from the fan-out trace region B11 to the first signal access region B121, and are connected with the first contact pads 311. The regions S2 and S3 between the first group of data lines A1 and the second group of data lines A2 are not provided with the data lines 101.

[0130] In some embodiments, as shown in FIG. 10, the virtual traces 313 are arranged between the first group of data lines A1 and the second group of data lines A2, the virtual traces 313 are linear, the virtual traces 313 extend to between adjacent first contact pads 311, and the data lines 101 include a portion perpendicular to the first direction, and the virtual traces 313 are parallel to the portion of the data lines. In the embodiment, the virtual traces 313 can be arranged at some positions of the regions S2 and S3, or the virtual traces 313 can be arranged at all positions of the regions S2 and S3. The distribution density of the virtual traces 313 can be substantially the same as the distribution density of the data lines 101, and the virtual traces 313 can be arranged in the same layer and of the same material as the data lines 101, so that the virtual traces 313 can be formed at the same time as the data lines 101 by using a same patterning process, and the virtual traces 313 do not need to be made by a special patterning process, which can simplify the manufacturing process of the display substrate. In the embodiment, the virtual traces 313 are arranged in the regions S2 and S3, and the virtual traces 313 can make the heat dissipation and stress of the regions S2 and S3 and the regions where the data lines 101 are located uniform, avoid the display substrate from deforming in the regions S2 and S3, and further avoid the data lines close to the region S2 in the first group of data lines A1 and the data lines close to the region S3 in the second group of data lines A2 from peeling off, so as to improve the display effect of the display device.

[0131] In some embodiments, as shown in FIG. 11, the dummy traces 313 are arranged between the first group of data lines A1 and the second group of data lines A2, the dummy traces 313 are in a straight line shape, the dummy traces 313 extend between the adjacent first contact pads 311, the dummy traces 313 are parallel to the extension direction of the data lines 101, and the dummy traces 313 are discontinuous to avoid electrical connection with the first contact pads 311. In this embodiment, the dummy traces 313 can be arranged at some positions of the region S2 and the region S3, or the dummy traces 313 can be arranged at all positions of the region S2 and the region S3. The distribution density of the dummy traces 313 can be substantially the same as the distribution density of the data lines 101, the dummy traces 313 can be arranged in the same layer and made of the same material as the data lines 101, so that the dummy traces 313 can be formed at the same time as the data lines 101 by using the same patterning process, and the dummy traces 313 do not need to be made by a special patterning process, which can simplify the manufacturing process of the display substrate. In this embodiment, the dummy traces 313 arranged in the region S2 and the region S3 can uniformly distribute the heat and stress of the region S2, S3 and the region where the data lines 101 are located, so as to avoid deformation of the display substrate in the region S2 and the region S3, and further avoid peeling of the data lines close to the region S2 in the first group of data lines A1 and peeling of the data lines close to the region S3 in the second group of data lines A2, thereby improving the display effect of the display device.

[0132] In some embodiments, as shown in FIG. 12, the dummy traces 313 are arranged between the first group of data lines A1 and the second group of data lines A2, the dummy traces 313 are in a straight line shape, and the first part of the dummy traces 3131 extend between the adjacent first contact pads 311, the first part of the dummy traces 3131 are parallel to the extension direction of the data lines 101, and the first part of the dummy traces 3131 are discontinuous to avoid electrical connection with the first contact pads 311. The display substrate further comprises the second part of the dummy traces 3132 in an inverted V shape, and the dummy traces 3132 in the inverted V shape are located between the region S2 and the region S3. In this embodiment, the distribution density of the dummy traces 313 can be substantially the same as the distribution density of the data lines 101, the dummy traces 313 can be arranged in the same layer and made of the same material as the data lines 101, so that the dummy traces 313 can be formed at the same time as the data lines 101 by using the same patterning process, and the dummy traces 313 do not need to be made by a special patterning process, which can simplify the manufacturing process of the display substrate. In this embodiment, the dummy traces 313 arranged in the region S2 and the region S3 can uniformly distribute the heat and stress of the region S2, S3 and the region where the data lines 101 are located, so as to avoid deformation of the display substrate in the region S2 and the region S3, and further avoid peeling of the data lines close to the region S2 in the first group of data lines A1 and peeling of the data lines close to the region S3 in the second group of data lines A2, thereby improving the display effect of the display device.

[0133] In some embodiments, as shown in FIG. 13, the dummy traces 313 are arranged between the first group of data lines A1 and the second group of data lines A2, and the dummy traces 313 are in a straight line shape; wherein the first part of the dummy traces 3131 extends between the adjacent first contact pads 311, and the first part of the dummy traces 3131 is parallel to the extension direction of the data lines 101, and the first part of the dummy traces 3131 is discontinuous in order to avoid electrical connection between the first part of the dummy traces 3131 and the first contact pads 311. In this embodiment, the display substrate further comprises a third part of the dummy traces 3133 parallel to the first direction, and the third part of the dummy traces 3133 is located between the region S2 and the region S3. The dummy traces 313 can be arranged in the same layer and made of the same material as the data lines 101, so that the dummy traces 313 can be formed at the same time as the data lines 101 by using the same patterning process, without the need for a special patterning process to manufacture the dummy traces 313, which can simplify the manufacturing process of the display substrate. In this embodiment, the dummy traces 313 are arranged in the region S2 and the region S3, and the dummy traces 313 can evenly distribute the heat and stress of the region S2, S3 and the region where the data lines 101 are located, so as to avoid deformation of the display substrate in the region S2 and the region S3, thereby avoiding peeling of the data lines in the first group of data lines A1 close to the region S2 and peeling of the data lines in the second group of data lines A2 close to the region S3, and improving the display effect of the display device.

[0134] In some embodiments, as shown in FIG. 14, the dummy traces 313 are arranged between the first group of data lines A1 and the second group of data lines A2; wherein the first part of the dummy traces 3131 is in a straight line shape, the first part of the dummy traces 3131 extends between the adjacent first contact pads 311, and the first part of the dummy traces 3131 is parallel to the extension direction of the data lines 101, and the first part of the dummy traces 3131 is discontinuous in order to avoid electrical connection between the first part of the dummy traces 3131 and the first contact pads 311. In this embodiment, the display substrate further comprises a fourth part of the dummy traces 3134, and the fourth part of the dummy traces 3134 is in a block shape and arranged in an array between the region S2 and the region S3. The dummy traces 313 can be arranged in the same layer and made of the same material as the data lines 101, so that the dummy traces 313 can be formed at the same time as the data lines 101 by using the same patterning process, without the need for a special patterning process to manufacture the dummy traces 313, which can simplify the manufacturing process of the display substrate. In this embodiment, the dummy traces 313 are arranged in the region S2 and the region S3, and the dummy traces 313 can evenly distribute the heat and stress of the region S2, S3 and the region where the data lines 101 are located, so as to avoid deformation of the display substrate in the region S2 and the region S3, thereby avoiding peeling of the data lines in the first group of data lines A1 close to the region S2 and peeling of the data lines in the second group of data lines A2 close to the region S3, and improving the display effect of the display device.

[0135] In this embodiment, the contact pad 31 can adopt a multi-layer metal structure. As shown in FIG. 15, the display substrate can include a plurality of lead lines 2220 and at least one set of contact pads. The at least one set of contact pads includes a plurality of contact pads 31. The display substrate includes a binding area buffer layer 2241 on the base 2000, and a binding area first gate insulating layer 2242 on the side of the binding area buffer layer 2241 away from the base 2000. The plurality of contact pads 31 are arranged in a single row or multiple rows. There is a gap between the plurality of contact pads 31 in the same row, and there is also a gap between the plurality of contact pads 31 in different rows.

[0136] The display substrate can further include a first insulating layer 2230 and a binding area third insulating layer 2260 disposed on the binding area 2200. The first insulating layer 2230 covers at least part of the edges of the plurality of contact pads 31. The contact pad 31 includes at least one contact pad metal layer, for example, a plurality of contact pad metal layers. In the example shown, the at least one contact pad metal layer of the contact pad 31 can include a first contact pad metal layer 2215 and a second contact pad metal layer 2217, the second contact pad metal layer 2217 being laminated on the side of the first contact pad metal layer 2215 away from the base 2000. The binding area third insulating layer 2260 covers the first insulating layer 2230 and the plurality of contact pads 31. Thus, during the preparation process of the display substrate, the first insulating layer can protect the edges of the contact pads, avoid etching liquid from etching the edges of the exposed contact pads, and thus improve the product yield and reliability of the display substrate.

[0137] As shown in FIG. 15, the display substrate can further include a binding area second gate insulating layer 2243 and a binding area interlayer insulating layer 2244 in the binding area. The binding area interlayer insulating layer 2240 is located in the binding area and between the plurality of contact pads 31 and the first insulating layer 2230 and the base 2000. The binding area second gate insulating layer 2243 is located between the binding area first gate insulating layer 2242 and the binding area interlayer insulating layer 2244 and is laminated with the binding area interlayer insulating layer 2244. The binding area second gate insulating layer 2243 includes a first contact pad via hole 2216, the binding area interlayer insulating layer 2244 includes a second contact pad via hole 2219, and at least one of the data lines 101 is electrically connected to the contact pad 31 through the first contact pad via hole 2216 and the second contact pad via hole 2219.

[0138] In the figure 4, the second touch conductive layer 512 and the second transfer electrode pattern 2270 are in the same layer, the touch interlayer insulating layer 502 and the binding area third insulating layer 2260 are in the same layer, the first transfer electrode 231 and the second contact pad metal layer 2217 are in the same layer, the drain 212 and the first contact pad metal layer 2215 are in the same layer, the gate 213 and the lead 2220 are in the same layer, the interlayer insulating layer 203 and the binding area interlayer insulating layer 2244 are in the same layer, the second gate insulating layer 202 and the binding area second gate insulating layer 2243 are in the same layer.

[0139] For example, as shown in the figure 15, the second contact pad metal layer 2217 is formed on the first contact pad metal layer 2215 and covers the edge of the first contact pad metal layer 2215 to avoid the first contact pad metal layer 2215 being exposed and corroded by etching liquid in subsequent patterning process. The first insulating layer 2230 covers at least part of the edge of the second contact pad metal layer 2217 of the contact pad 31. The height of the first insulating layer 2230 relative to the surface of the substrate 2000, i.e. the vertical distance from the surface of the first insulating layer 2230 to the surface of the substrate 2000, is not greater than the distance from the surface of the second contact pad metal layer 2217 of the contact pad 31 to the surface of the substrate 2000. Defining the height of the first insulating layer 2230, i.e. the thickness of the first insulating layer 2230, can improve the contact failure phenomenon of the binding area and improve the product yield. In addition, the second contact pad metal layer 2217 directly covers the edge of the first contact pad metal layer 2215, which can reduce the thickness of the film layer of the contact pad 31, and further reduce the film layer step, thereby further improving the contact failure phenomenon of the binding area.

[0140] For example, as shown in the figure 15, the display substrate can further include an auxiliary conductive layer. The auxiliary conductive layer is located in the binding area and the display area and is disposed on the binding area third insulating layer 2260. The auxiliary conductive layer includes the second transfer electrode pattern 2270 located in the binding area. The second transfer electrode pattern 2270 is realized to perform the binding process with the external circuit. The third contact pad via hole 2218 is formed in the binding area third insulating layer 2260. The second transfer electrode pattern 2270 is electrically connected with the contact pad through the third contact pad via hole 2218 to transmit the electrical signal. The first insulating layer 2230 is configured to expose the surface of the contact pad 31 away from the substrate 2000. That is, the area of the contact pad 31 in the binding area 2200 except for the contact pad 31 is covered by the first insulating layer 2230, which includes but is not limited to the gap between the contact pads in the same row and the gap between the contact pads in different rows.

[0141] For example, in some examples of the present disclosure, the height of the second transfer electrode pattern 2270 relative to the surface of the substrate 2000 is not greater than the height of the third insulating layer 2260 of the binding area relative to the surface of the substrate 2000, so as to avoid the contact failure phenomenon of the binding area.

[0142] Embodiments of the present disclosure also provide a display device including the display substrate as described above.

[0143] The display device includes, but is not limited to, a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply, and the like. Those skilled in the art can understand that the structure of the display device described above does not constitute a limitation on the display device, and the display device can include more or fewer components described above, or combine certain components, or different component arrangements. In the embodiments of the present disclosure, the display device includes, but is not limited to, a display, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0144] The display device can be a television, a display, a digital photo frame, a mobile phone, a tablet computer, or any product or component with a display function, wherein the display device further includes a flexible circuit board, a printed circuit board, and a back plate.

[0145] Embodiments of the present disclosure also provide a manufacturing method of the display substrate described above, including:

[0146] A substrate is provided, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a binding area located on one side of the display area;

[0147] A plurality of sub-pixels are formed on the substrate, the sub-pixels being located in the display area;

[0148] A plurality of data lines are formed on the substrate, the data lines being located in the display area and extending to the binding area, the plurality of data lines being electrically connected with the plurality of sub-pixels and being configured to provide data signals to the plurality of sub-pixels;

[0149] A plurality of first contact pads are formed on the substrate, the first contact pads being located in the binding area and connected with the plurality of data lines;

[0150] A plurality of second contact pads are formed on the substrate, the second contact pads being located in the binding area and located on a side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound with a driving chip;

[0151] A plurality of virtual traces are formed on the substrate, the virtual traces are located on the side of the plurality of first contact pads close to the display area, and are located on at least one side of the plurality of data lines in a first direction.

[0152] In the embodiment, the virtual traces are formed on the side of the plurality of first contact pads close to the display area, and the virtual traces are located on at least one side of the data lines. The stress of the edge area of the data lines and the stress of the center area of the data lines are uniform through the virtual traces, the heat dissipation of the edge area of the data lines and the heat dissipation of the center area of the data lines are uniform, the deformation of the display substrate in the area of the plurality of contact pads is avoided, the local film layer is prevented from being cracked or peeled off, and the display effect of the display device is improved.

[0153] In the drawings, the thickness of some of the layers and regions can be exaggerated for clarity. Like reference numerals in different drawings denote like elements, and specific descriptive terminology will be used with common understanding of the English language. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the description of the disclosure, numerous specific details are provided for a thorough understanding of embodiments of the disclosure. However, one skilled in the relevant art will recognize that the techniques of the disclosure can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

[0154] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first element, component, region, layer or section discussed above can be called a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0155] Spatially relative terms such as "row," "column," "below," "above," "left," "right," and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that the term "between" when used in relation to two layers means that there can be only those two layers, or there can also be one or more intervening layers.

[0156] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description of the specification, the description of the terms "one embodiment," "another embodiment," and the like means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment of the disclosure. The illustrative appearances of the above-mentioned terms in the description are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Additionally, the disclosure can include a plurality of embodiments or examples that are not necessarily mutually exclusive. Furthermore, the description of a particular feature, structure, material, or characteristic does not imply that the particular feature, structure, material, or characteristic is required in all embodiments or examples.

[0157] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to" or "adjacent to" another element or layer, it can be directly on, connected, coupled or adjacent the other element or layer, or there can be one or more intermediate elements or layers. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly coupled to" or "directly adjacent to" another element or layer, there are no intermediate elements or layers. It will further be understood that "on", "connected", "coupled" or "adjacent" as used herein, can include an element or layer that is formed on, connected, coupled or adjacent to another element or layer as well as one or more intermediate elements or layers. However, "on", "directly on", "connected", "directly connected", "coupled", "directly coupled" or "adjacent" should not be interpreted as requiring a layer to completely cover a below layer.

[0158] Embodiments of the disclosure are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the disclosure.

[0159] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0160] As will be understood by those skilled in the art, although the various steps of the methods in the disclosure are described in a particular order in the drawings, this is not required or implied as the particular order, unless the context clearly indicates otherwise. Additionally or alternatively, multiple steps can be combined into a single step, and / or a single step can be broken up into multiple steps. Moreover, other method steps can be interposed. The interposed steps can represent improvements to the methods as described herein, or can be unrelated to the methods. Furthermore, a given step can not have completed before the next step is initiated.

[0161] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a binding area located at one side of the display area; a plurality of sub-pixels located at one side of the substrate and in the display area; a plurality of data lines located in the display area and extending to the binding area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; a plurality of first contact pads located in the binding area and connected to the plurality of data lines; a plurality of second contact pads located in the binding area and located at one side of the plurality of first contact pads away from the display area, the plurality of first contact pads and the plurality of second contact pads being configured to be bound with a driving chip; a plurality of virtual traces located at one side of the plurality of first contact pads close to the display area and located on at least one side of the plurality of data lines in a first direction.

2. The display substrate of claim 1, wherein, The plurality of data lines comprises a first group of data lines and a second group of data lines arranged in the first direction, the plurality of virtual traces is located on at least one side of the first group of data lines in the first direction, and / or the plurality of virtual traces is located on at least one side of the second group of data lines in the first direction. 3.The display substrate of claim 2, wherein, The plurality of virtual traces is located on both sides of the first group of data lines in the first direction and on both sides of the second group of data lines.

4. The display substrate of claim 2, wherein, The display substrate further comprises virtual data lines located on both sides of the first group of data lines in the first direction and on both sides of the second group of data lines, and arranged one by one with the plurality of virtual traces in a second direction intersecting the first direction. 5.The display substrate of claim 2, wherein, The plurality of first contact pads comprises a first group of contact pads and a second group of contact pads arranged in the first direction, the first group of data lines is connected to the first group of contact pads, and the second group of data lines is connected to the second group of contact pads. 6.The display substrate of claim 1, wherein, The connection between the virtual traces and the first contact pads is disconnected. 7.The display substrate of claim 2, wherein, The extension direction of the virtual traces between the first group of data lines and the second group of data lines is parallel to the extension direction of at least part of the data lines. 8.The display substrate of claim 2, wherein, The virtual traces between the first group of data lines and the second group of data lines are parallel to the first direction. 9.The display substrate of claim 2, wherein, The virtual traces between the first group of data lines and the second group of data lines are arranged in an array in a block shape. 10.The display substrate of claim 1, wherein, The virtual traces extend between a plurality of the first contact pads. 11.The display substrate of claim 1, wherein, The display substrate comprises a first gate metal layer, a first insulating layer, a second gate metal layer, a second insulating layer, a first source-drain metal layer, a third insulating layer, a second source-drain metal layer, and a fourth insulating layer located in sequence on the substrate; The data lines and the virtual traces are both made of the first gate metal layer. 12.The display substrate of claim 1, wherein, The display substrate further comprises: a binding area interlayer insulating layer located in the binding area and between the plurality of first contact pads and the data lines; a binding area first gate insulating layer located in the binding area and located at one side of the binding area interlayer insulating layer close to the substrate; and A second gate insulating layer of the binding area is located in the binding area and between the first gate insulating layer of the binding area and the interlayer insulating layer of the binding area, and is stacked with the interlayer insulating layer of the binding area; The second gate insulating layer of the binding area includes a first contact pad via hole, the interlayer insulating layer of the binding area includes a second contact pad via hole, and at least one of the plurality of data lines is electrically connected to the first contact pad via the first contact pad via hole and the second contact pad via hole. 13.The display substrate of claim 12, wherein, The display substrate further includes a third insulating layer of the binding area, The third insulating layer of the binding area is located in the binding area and is arranged on a side of the first contact pad away from the base to cover the first contact pad, The third insulating layer of the binding area has a third contact pad via hole to expose a surface of the first contact pad. 14.The display substrate of claim 13, wherein, The display substrate further includes an auxiliary conductive layer, The auxiliary conductive layer is located in the binding area and is arranged on a side of the third insulating layer of the binding area away from the base, The auxiliary conductive layer includes a second transfer electrode pattern located in the binding area, The second transfer electrode pattern is electrically connected to the first contact pad through the third contact pad via hole.

15. A display device comprising: The display substrate includes any one of claims 1-14.

16. A manufacturing method of a display substrate, comprising: The display substrate includes: A base is provided, the base includes a display area and a peripheral area surrounding the display area, the peripheral area includes a binding area located on one side of the display area; A plurality of sub-pixels are formed on the base, the sub-pixels are located in the display area; A plurality of data lines are formed on the base, the data lines are located in the display area and extend to the binding area, the plurality of data lines are electrically connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels; A plurality of first contact pads are formed on the base, the first contact pads are located in the binding area and are connected to the plurality of data lines; A plurality of second contact pads are formed on the base, the second contact pads are located in the binding area and are located on a side of the plurality of first contact pads away from the display area, and the plurality of first contact pads and the plurality of second contact pads are configured to be bound with a driving chip; A plurality of virtual traces are formed on the base, the virtual traces are located on a side of the plurality of first contact pads close to the display area and are located on at least one side of the plurality of data lines in a first direction.

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