Display panel and display device

Abstract

A display panel (10) and a display device. The display panel (10) comprises a substrate (11), a gate driving circuit (12), and a plurality of sub-pixel circuits (13). The gate driving circuit (12) of the display panel (10) comprises a plurality of driving units arranged in cascade, active driving units (121) among the plurality of driving units are electrically connected to the sub-pixel circuits (13), and a dummy driving unit (122) among the plurality of driving units is disconnected from the sub-pixel circuit (13), so that the dummy driving unit (122) does not have an output function, and the dummy driving unit (122) can input a shift signal to a corresponding active driving unit (121). Therefore, the partial structure of the dummy driving unit (122) is similar to that of each active driving unit (121). In this way, the etching uniformity of the gate driving circuit (12) can be improved, reducing deviations in line width and thickness of traces formed by etching in different regions of the gate driving circuit (12), and improving the load uniformity of shift signals accessed by a plurality of active driving units (121), thereby improving the stability of the display panel (10).

Description

Display panel and display device

[0001] The present disclosure claims priority to the Chinese patent application No. 202411378553.0, filed on September 29, 2024, and entitled "Display panel and display device", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] The display panel is a device with display function.

[0004] The display panel drives a plurality of sub-pixel circuits to emit light through a gate drive circuit to realize display function. The current gate drive circuit includes a plurality of cascaded driving units. Before the plurality of cascaded driving units, some circuit structures are usually arranged to input shift signals to part of the driving units.

[0005] However, the above-mentioned circuit structure is quite different from the structure of the driving unit, which is easy to cause poor etching uniformity of the gate drive circuit, that is, there is a large deviation in the line width and thickness of the wires formed by etching in different regions of the gate drive circuit, thereby causing poor stability of the display panel. SUMMARY

[0006] Embodiments of the present application provide a display panel and a display device. The technical solutions are as follows:

[0007] According to an aspect of the present application, a display panel is provided, which includes a substrate, a gate drive circuit on the substrate, and a plurality of sub-pixel circuits.

[0008] The gate drive circuit includes a plurality of cascaded driving units, the plurality of driving units including a plurality of effective driving units and at least one virtual driving unit. Each effective driving unit is electrically connected to at least one sub-pixel circuit, and the virtual driving unit is disconnected from the sub-pixel circuit. Each virtual driving unit includes a shift signal output end, and each effective driving unit includes at least one shift signal input end. Each shift signal input end corresponds to and is electrically connected to a shift signal output end.

[0009] The effective driving unit and the virtual driving unit each include a shift register module and an output module. At least part of the structure of the output module of the effective driving unit and the virtual driving unit is different.

[0010] Optionally, the shift register module of the effective driving unit and the shift register module of the virtual driving unit have the same structure, and the output module of the virtual driving unit includes a plurality of transistors, and the plurality of transistors of the output module of the virtual driving unit are all in an off state.

[0011] Optionally, the plurality of transistors of the output module of the virtual driving unit include a first electrode, a second electrode and an active layer, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0012] The active layer of the transistor includes a first part connected to the first electrode and a second part connected to the second electrode, and the first part is disconnected from the second part.

[0013] Optionally, the plurality of transistors of the output module of the virtual driving unit include a first electrode, a second electrode and an active layer, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0014] The active layer of the transistor is connected to the first electrode, and the active layer of the transistor is disconnected from the second electrode.

[0015] Optionally, the plurality of transistors of the output module of the virtual driving unit include a first electrode, a second electrode and an active layer, one of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

[0016] The active layer of a part of the plurality of transistors includes a first part connected to the first electrode and a second part connected to the second electrode, and the first part is disconnected from the second part.

[0017] The active layer of the other part of the plurality of transistors is connected to the first electrode, and the active layer of the other part is disconnected from the second electrode.

[0018] Optionally, the display panel further includes a direct current signal line on the substrate, and the active layer of the plurality of transistors of the output module of the virtual driving unit is electrically connected to the direct current signal line.

[0019] Optionally, the display panel further includes at least one target structure, and the target structure and the active layer are in the same layer structure.

[0020] The target structure satisfies at least one of the following conditions:

[0021] The target structure is located between the first part and the second part of one of the plurality of transistors.

[0022] A normal projection of the target structure on the substrate is located on a side of a first normal projection away from a second normal projection, the first normal projection being a normal projection of an active layer of a transistor of the plurality of transistors on the substrate, and the second normal projection being a normal projection of a first electrode of the transistor on the substrate.

[0023] Optionally, the display panel further comprises an insulating layer located on a side of the active layer away from the substrate, the insulating layer having at least one first opening corresponding to the at least one target structure, a normal projection of the target structure on the substrate and a normal projection of the corresponding first opening on the substrate being overlapped.

[0024] Optionally, the plurality of transistors of the output module of the virtual driving unit further comprise a gate electrode, and in one of the plurality of transistors, a normal projection of the active layer on the substrate and a normal projection of the gate electrode on the substrate are not overlapped.

[0025] Optionally, the effective driving unit and the output module of the virtual driving unit each comprise a plurality of devices, and a circuit layout of the plurality of devices in the effective driving unit is the same as a circuit layout of the plurality of devices in the virtual driving unit.

[0026] The display panel further comprises a direct current signal line and a shift signal line located on the substrate, and the plurality of devices comprise target devices, the target devices of the effective driving unit comprising a first electrode plate and a second electrode plate arranged in a direction away from the substrate, the first electrode plate being connected to the direct current signal line, the second electrode plate being connected to the shift signal line, the target devices of the virtual driving unit and the second electrode plate being a same layer structure, the target devices of the virtual driving unit being connected to the shift signal line, and the target devices of the virtual driving unit being disconnected from the direct current signal line.

[0027] Optionally, the substrate comprises a display area and a non-display area, the plurality of sub-pixel circuits being located on the display area, and the gate electrode driving circuit being located on the non-display area.

[0028] The distance between the virtual driving unit and the display area is equal to the distance between the effective driving unit and the display area.

[0029] Optionally, the display panel further comprises a plurality of clock signal lines and a plurality of first electrodes, the sub-pixel circuits being electrically connected to the first electrodes, the first electrodes corresponding to and being electrically connected to two of the plurality of clock signal lines, the first electrodes having second openings, and a normal projection of the second openings of the first electrodes on the substrate and a normal projection of the corresponding clock signal lines on the substrate being overlapped.

[0030] Optionally, the display panel further comprises a pixel defining layer, the pixel defining layer is located on the substrate, the pixel defining layer comprises a plurality of openings, the plurality of openings correspond to the plurality of first electrodes respectively, and the orthographic projection of the opening on the substrate and the orthographic projection of the corresponding first electrode on the substrate overlap.

[0031] The plurality of openings comprise a first opening and a second opening, the first electrode corresponding to the first opening is electrically connected with the clock signal line, the size of the first opening is smaller than the size of the second opening, and the size of the second aperture of the first electrode corresponding to the first opening is smaller than the size of the second aperture of the first electrode corresponding to the second opening.

[0032] Optionally, in the first direction, the width of the part of the first electrode in contact with the corresponding two clock signal lines is the same.

[0033] In another aspect, a display device is provided, comprising a housing and any of the above display panels.

[0034] The technical solutions provided by the embodiments of the present application have at least the following beneficial effects:

[0035] A display panel is provided. The gate drive circuit of the display panel comprises a plurality of driving units arranged in cascade, the effective driving units in the plurality of driving units are electrically connected with the sub-pixel circuit, the virtual driving units in the plurality of driving units are disconnected with the sub-pixel circuit, the virtual driving units do not have output function, and the virtual driving units can input shift signals for the corresponding effective driving units. Therefore, the virtual driving units provided by the present application are similar in part to the structure of the effective driving units, which can improve the etching uniformity of the gate drive circuit, reduce the deviation of the line width and thickness of the lines formed by etching in different areas of the gate drive circuit, and improve the load uniformity of the shift signals input by the plurality of effective driving units, thereby improving the stability of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] FIG. 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0038] FIG. 2 is a structural schematic diagram of part of the structure of the display panel provided by FIG. 1;

[0039] FIG. 3 is a schematic diagram of a gate driving circuit according to an embodiment of the present application;

[0040] FIG. 4 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present application;

[0041] FIG. 5 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present application;

[0042] FIG. 6 is an enlarged schematic diagram of the partial structure of the display panel according to FIG. 5;

[0043] FIG. 7 is a schematic diagram of a cross-sectional structure of the display panel according to FIG. 6;

[0044] FIG. 8 is a schematic diagram of another cross-sectional structure of the display panel according to FIG. 6;

[0045] FIG. 9 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present application;

[0046] FIG. 10 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present application;

[0047] FIG. 11 is a top view of an active pattern of the display panel according to FIG. 10;

[0048] FIG. 12 is a top view of an active pattern of the display panel according to FIG. 5;

[0049] FIG. 13 is a top view of a first gate pattern of the display panel according to FIG. 10;

[0050] FIG. 14 is a top view of a first gate pattern of the display panel according to FIG. 9;

[0051] FIG. 15 is a top view of a second gate pattern of the display panel according to FIG. 10;

[0052] FIG. 16 is a top view of an insulating layer of the display panel according to FIG. 5;

[0053] FIG. 17 is a top view of a first source-drain pattern of the display panel according to FIG. 5;

[0054] FIG. 18 is a top view of a planarization layer of the display panel according to FIG. 5;

[0055] FIG. 19 is a top view of a second source-drain pattern of the display panel according to FIG. 5;

[0056] FIG. 20 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present application;

[0057] FIG. 21 is a structural schematic diagram of part of a structure of another display panel according to an embodiment of the present application;

[0058] FIG. 22 is a structural schematic diagram of part of a structure of another display panel according to an embodiment of the present application;

[0059] FIG. 23 is a structural schematic diagram of part of a structure of another display panel according to an embodiment of the present application.

[0060] The specific embodiments of the present application have been shown in the above-described drawings, and will be described in more detail hereinafter. The drawings and the written description are not intended to restrict the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be described in more detail hereinafter with reference to the drawings.

[0062] The display panel according to an embodiment of the present application is provided, please refer to FIG. 1 and FIG. 2, FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application, and FIG. 2 is a structural schematic diagram of part of a structure of the display panel provided in FIG. 1. The display panel 10 comprises a substrate 11, a gate drive circuit 12 and a plurality of sub-pixel circuits 13 on the substrate 11.

[0063] The gate drive circuit 12 comprises a plurality of driving units arranged in cascade, the plurality of driving units comprises a plurality of effective driving units 121 and at least one virtual driving unit 122, each effective driving unit 121 is electrically connected with at least one sub-pixel circuit 13, the virtual driving unit 122 is disconnected with the sub-pixel circuit 13, each virtual driving unit 122 comprises one shift signal output end G2, each effective driving unit 121 comprises at least one shift signal input end G1, each shift signal input end G1 corresponds to and is electrically connected with one shift signal output end G2.

[0064] The effective driving unit 121 and the virtual driving unit 122 both comprise a shift register module A1 and an output module A2, at least part of the structures of the output modules A2 of the effective driving unit 121 and the virtual driving unit 122 are different.

[0065] It should be noted that the plurality of sub-pixel circuits 13 can be driving circuits corresponding to a plurality of sub-pixels in the display panel 10. Each of the effective driving units 121 is electrically connected to at least one sub-pixel circuit 13, that is, each of the effective driving units 121 can output a signal to at least one sub-pixel circuit 13, and the virtual driving unit 122 is disconnected from the sub-pixel circuit 13, that is, the virtual driving unit 122 does not have the function of outputting a signal to the sub-pixel circuit 13. The plurality of driving units arranged in cascade can include a first-level driving unit, a second-level driving unit, a third-level driving unit,..., and an nth-level driving unit arranged in sequence, where n is the level of the nth-level driving unit.

[0066] In summary, the display panel provided in the embodiments of the present application includes a plurality of driving units arranged in cascade in the gate driving circuit of the display panel, the effective driving units in the plurality of driving units are electrically connected to the sub-pixel circuit, the virtual driving unit in the plurality of driving units is disconnected from the sub-pixel circuit, the virtual driving unit does not have an output function, and the virtual driving unit can input a shift signal to the corresponding effective driving unit. Therefore, the virtual driving unit and the effective driving unit provided in the present application have similar partial structures, which can improve the etching uniformity of the gate driving circuit, reduce the deviation of the line width and thickness of the lines formed by etching in different regions of the gate driving circuit, and improve the load uniformity of the shift signal input by the plurality of effective driving units, thereby improving the stability of the display panel.

[0067] Please refer to FIG. 1. In the display panel 10 provided in the embodiments of the present application, the substrate 11 can be used to carry the gate driving circuit 12 and the sub-pixel circuit 13. The substrate 11 can include a display area B1 and a non-display area B2. In addition, the shape of the substrate 11 can be a rectangle as shown in FIG. 1, or a rounded rectangle, which is not limited in the embodiments of the present application.

[0068] The gate driving circuit 12 can be located on the non-display area B2 of the substrate 11. The display panel 10 provided in the embodiments of the present application adopts the Gate On Array (GOA) technology, that is, the gate driving circuit 12 is integrated on the array substrate, which can improve the integration of the display panel 10. The gate driving circuit 12 has two functions. One function is an output function, that is, the gate driving circuit 12 can output a gate scanning driving signal to the sub-pixel circuit 13, and the gate scanning driving signal can be used to drive the sub-pixel circuit 13, thereby achieving the effect of driving the sub-pixel to emit light. The other function is a shift register function. The driving circuit 12 includes a plurality of driving units arranged in cascade, and the plurality of effective driving units 121 can transmit a shift signal in a step-by-step manner from the first-level driving unit downward. The cascade relationship of the plurality of driving units can be determined by the circuit structure of the driving unit, which is not limited in the embodiments of the present application.

[0069] The plurality of driving units includes a plurality of effective driving units 121 and at least one virtual driving unit 122. Wherein each effective driving unit 121 is electrically connected with at least one sub-pixel circuit 13, and the virtual driving unit 122 is disconnected with the sub-pixel circuit 13, that is, the effective driving unit 121 has an output function and a shift register function, and the virtual driving unit 122 only has a shift register function. For example, the plurality of sub-pixels of the display panel 10 can be arranged in rows and columns, and each effective driving unit 121 can be electrically connected with the sub-pixel circuit 13 corresponding to the sub-pixels in the same row to transmit the gate scanning driving signal, so as to drive the sub-pixels in the same row to emit light by controlling the switching state of the sub-pixel circuit 13 in the same row. Since the effective driving unit 121 and the virtual driving unit 122 both have a shift register function, when the output of one gate scanning driving signal is completed, the output of the next gate scanning driving signal can be controlled by the clock signal, so as to realize the effect of row-by-row scanning driving, and thus the display panel 10 can be displayed.

[0070] Each effective driving unit 121 includes at least one shift signal input end G1, including two cases: one case is that each effective driving unit 121 can include one shift signal input end G1, since each shift signal input end G1 corresponds to and is electrically connected with one shift signal output end G2, each effective driving unit 121 is only electrically connected with the shift signal output end G2 of one preceding driving unit 12. Therefore, in this case, the maximum preceding level is the difference between the level of the effective driving unit 121 and the level of the electrically connected virtual driving unit 122.

[0071] The other case is that each effective driving unit 121 can include a plurality of shift signal input ends G1, since each shift signal input end G1 corresponds to and is electrically connected with one shift signal output end G2, each effective driving unit 121 can correspond to a plurality of shift signal output ends G2, and the driving units 12 where the plurality of shift signal output ends G2 are located can have different levels, that is, each effective driving unit 121 can be electrically connected with a plurality of preceding driving units 12 to receive shift signals, and therefore in this case, the difference between the level of the effective driving unit 121 and the level of the electrically connected preceding driving unit 12 is multiple, and the maximum preceding level is the maximum value in the multiple differences.

[0072] In addition, in a related technology, the shift signals accessed by part of the plurality of driving units are accessed by the circuit structure, the shift signals accessed by another part of the plurality of driving units come from the preceding driving unit, the structural difference between the driving unit and the circuit structure is large, which is easy to cause the etching uniformity of the gate driving circuit to be poor, and the stability of the formed gate driving circuit is poor. In the display panel provided in the embodiment of the present application, the number of the virtual driving units 122 is the same as the maximum preceding level of the shift signal input end G1 of the effective driving unit 121, the shift signal accessed by each effective driving unit 121 comes from the virtual driving unit 122 or the effective driving unit 121, and the structure of the virtual driving unit 122 is similar to that of the effective driving unit 121. The manufacturing process of the gate driving circuit 12 can include an etching process, and the similar structure of the virtual driving unit 122 and the effective driving unit 121 can ensure that the overall distribution of the pattern and the pattern density are similar, so that the difference in etching rate and etching depth of different regions in the gate driving circuit 12 can be reduced. Therefore, the virtual driving unit 122 provided in the embodiment of the present application can effectively improve the etching uniformity of the gate driving circuit 12, that is, the line width and thickness deviation of the traces in different regions of the gate driving circuit 12 is small, and can improve the uniformity of the load of the shift signal accessed by the plurality of effective driving units 121, thereby improving the stability of the gate driving circuit 12, and further improving the stability of the display effect of the display panel.

[0073] The sub-pixel circuit 13 can be located on the display area B1 of the substrate 11, and a plurality of sub-pixel circuits 13 can correspond to a plurality of sub-pixels in the display panel 10 respectively. The sub-pixel circuit 13 can include a plurality of transistors, and the transistors in the sub-pixel circuit 13 can be driven to be turned on by the gate scanning driving signal, so as to realize the effect of driving the corresponding sub-pixel to emit light.

[0074] In an exemplary embodiment, the effective driving unit and the virtual driving unit both include a shift register module and an output module. Please refer to FIG. 2, the structure of the shift register module A1 of the effective driving unit 121 is the same as that of the virtual driving unit 122, so that the effective driving unit 121 and the virtual driving unit 122 both can realize the shift register function, and can effectively improve the structural similarity of the effective driving unit 121 and the virtual driving unit 122, thereby improving the etching uniformity of the gate driving circuit 12. The output module A2 of the virtual driving unit 122 includes a plurality of transistors, the plurality of transistors of the output module A2 of the virtual driving unit 122 are all in the cut-off state, and at least part of the structure of the output module A2 of the effective driving unit 121 and the virtual driving unit 122 is different, which can ensure that the output function of the virtual driving unit is invalid, so that the virtual driving unit 122 does not have the output function.

[0075] Another related technology also has a virtual driving unit, the virtual driving unit has the same structure as the effective driving unit, and the virtual driving unit is only used to fill the area with larger gaps. The virtual driving unit in the related technology is not electrically connected with other circuit structures and is in a floating state, which is easy to cause the problem of electrostatic breakdown. The virtual driving unit 122 provided by the present application is different from at least part of the structure of the output module A2 of the effective driving unit 121, and the structure of the shift register module A1 is the same, that is, the virtual driving unit 122 of the present application retains the shift register function, but does not have the output function. In addition, the virtual driving unit 122 of the present application is electrically connected with the effective unit 121 to provide a shift signal, which can effectively avoid the part of the structure of the virtual driving unit 122 in the floating state, thereby avoiding the problem of electrostatic breakdown of the part of the structure. For example, the shift register module A1 of the virtual driving unit 122 is not in a floating state, and part of the lines connected with the shift register module A1 in the output module A2 of the virtual driving unit 122 is also not in a floating state.

[0076] FIG. 2 does not show the specific structure of the effective driving unit 121 and the virtual driving unit 122, and the specific structure of the effective driving unit 121 and the virtual driving unit 122 can be determined by the circuit schematic. The circuit schematic of the effective driving unit 121 and the virtual driving unit 122 can be the same to ensure that the circuit layout of the effective driving unit 121 and the virtual driving unit 122 is the same, thereby improving the similarity of the structure of the effective driving unit 121 and the virtual driving unit 122.

[0077] An example of a circuit schematic diagram is shown in FIG. 3, which is a schematic diagram of a gate drive circuit according to an embodiment of the present application. The gate drive circuit 12 includes fifteen transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15) and six capacitor structures (C1, C2, C3, C4, C5, C6), i.e., the gate drive circuit 12 can be a 16T5C structure. The shift register module A1 includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the first capacitor structure C1, and the second capacitor structure C2, i.e., the shift register module A1 corresponds to the 8T2C part. The output module A2 includes the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the third capacitor structure C3, the fourth capacitor structure C4, the fifth capacitor structure C5, and the sixth capacitor structure C6, i.e., the output module A2 corresponds to the 7T4C part. The effective drive unit 121 and the virtual drive unit 122 can both use the circuit schematic diagram shown in FIG. 3. The ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 of the output module A2 of the virtual drive unit 122 are all in the off state, so as to ensure that the virtual drive unit 122 has no output function.

[0078] In the shift register module A1, the gate of the first transistor T1 is electrically connected with the first clock signal end CK1, the first pole is electrically connected with the shift signal input end G1 to access the shift signal carry[N-2], the shift signal carry[N-2] is the shift signal output by the driving unit of the previous two stages, and the second pole is electrically connected with the first node N1. The gate of the second transistor T2 is connected with the second pole of the first transistor T1, the first pole accesses the second clock signal CK2, and the second pole is electrically connected with the second node N2. The gate of the third transistor T3 is electrically connected with the second clock signal end CK2, the first pole is electrically connected with the low-level direct-current signal end VGL, and the second pole is electrically connected with the second node N2. The gate of the fourth transistor T4 is electrically connected with the second node N2, the first pole is electrically connected with the high-level direct-current signal end VGH, and the second pole is electrically connected with the shift signal output end G2. The gate of the fifth transistor T5 is electrically connected with the fourth node T4, the first pole is electrically connected with the third clock signal end CK3, and the second pole is electrically connected with the second capacitor structure C2 and the sixth capacitor structure C6. The gate of the sixth transistor T6 is electrically connected with the second node N2, the first pole is electrically connected with the high-level direct-current signal end VGH, and the second pole is electrically connected with the third node N3. The gate of the seventh transistor T7 is electrically connected with the third clock signal end CK3, the first pole is electrically connected with the third node N3, and the second pole is electrically connected with the first node N1. The gate of the eighth transistor T8 is electrically connected with the low-level direct-current signal end VGL, the first pole is electrically connected with the first node N1, and the second pole is electrically connected with the fourth node N4. The first capacitor structure C1 is electrically connected with the high-level direct-current signal end VGH and the second node N3 respectively. The second capacitor structure C2 is electrically connected with the sixth capacitor structure C6 and the fourth node N4 respectively.

[0079] In the output module A2, the gate of the ninth transistor T9 is electrically connected with the eighth node N8, the first pole is electrically connected with the driving signal output terminal Gout[N], and the second pole is electrically connected with the high level direct current signal terminal VGH. The gate of the tenth transistor T10 is electrically connected with the fifth node N5, the first pole is electrically connected with the third clock signal terminal CK3, and the second pole is electrically connected with the driving signal output terminal Gout[N]. The gate of the eleventh transistor T11 is electrically connected with the sixth node N6, the first pole is electrically connected with the gate of the fourth transistor T4, and the second pole is electrically connected with the eighth node N8. The gate of the twelfth transistor T12 is electrically connected with the sixth node N6, the first pole is electrically connected with the gate of the fifth transistor T5, and the second pole is electrically connected with the fifth node N5. The gate of the thirteenth transistor T13 is electrically connected with the shift signal input terminal G1 to input the shift signal carry[N-10], the first pole is electrically connected with the sixth node N6, and the second pole is electrically connected with the seventh node N7. The gate of the fourteenth transistor T14 is electrically connected with the shift signal input terminal G1 to input the shift signal carry[N-2], the first pole is electrically connected with the gate of the fifth transistor T5, and the second pole is electrically connected with the seventh node N7. The gate of the fifteenth transistor T15 is electrically connected with the voltage control terminal Eout, the first pole is electrically connected with the low level direct current signal terminal VGL, and the second pole is electrically connected with the sixth node N6. The third capacitor structure C3 is electrically connected with the high level direct current signal terminal VGH and the eighth node N8 respectively. The fourth capacitor structure C4 is electrically connected with the fifth node N5 and the driving signal output terminal Gout[N] respectively. The fifth capacitor structure C5 is electrically connected with the fifth node N5 and the sixth node N6 respectively. The sixth capacitor structure C6 is electrically connected with the high level direct current signal terminal VGH and the shift signal output terminal G2 respectively.

[0080] In addition, Fig. 3 shows three kinds of shift signals: Carry[N], Carry[N-2] and Carry[N-10], N is the level of the driving unit, and the shift signal output terminal G2 of the nth level driving unit outputs the shift signal Carry[N], i.e. the shift signal output by the shift register module A1, and the shift signal input terminal G1 of the nth level driving unit inputs the shift signals Carry[N-2] and Carry[N-10], the shift signal Carry[N-2] is output by the nth-2 level driving unit, the source of the first transistor T1 and the gate of the fourteenth transistor T14 are connected to the shift signal Carry[N-2], and the shift signal Carry[N-10] is output by the nth-10 level driving unit, and the gate of the thirteenth transistor T13 is connected to the shift signal Carry[N-10]. Since the maximum preceding level of the three kinds of shift signals is 10 levels, the number of virtual driving units in the gate driving circuit is at least 10.

[0081] The structure of the display panel corresponding to the circuit principle diagram shown in FIG. 3 can refer to FIG. 4, which is a structural schematic diagram of part of the structure of another display panel provided by an embodiment of the present application (for the sake of clearly showing the arrangement of the plurality of driving units, the connection relationship between the active driving units 121 and the virtual driving units 122 is not shown in FIG. 4). The gate driving circuit 12 includes a plurality of driving units, and FIG. 3 only shows part of the driving units. The first-stage driving unit to the tenth-stage driving unit are virtual driving units 122, and the eleventh-stage driving unit to the fifteenth-stage driving unit are active driving units 121. In this way, it can be ensured that the shift signals accessed by the active driving units 121 come from the virtual driving units 122 and the active driving units 121, so as to improve the stability of the shift signals. The display panel can further include a gate scanning driving signal line 151, and the active driving units 121 can be electrically connected to the sub-pixel circuit through the gate scanning driving signal line 151. The gate scanning driving signal line 151 can be used to transmit a gate scanning driving signal, so that the active driving units 121 can control the sub-pixel to emit light. The virtual driving units 122 are not connected to the gate scanning driving signal line 151, so as to ensure that the virtual driving units 122 are disconnected from the sub-pixel circuit. In addition, the shape of the substrate 11 shown in FIG. 4 is a rounded rectangle, but FIG. 4 only shows the rounded corner region of the substrate 11 and part of the structure on the rounded corner region. The ten virtual driving units 122 are arranged on the rounded corner region, so as to improve the space utilization.

[0082] Optionally, referring to FIGS. 1 and 4, the substrate 11 includes a display area B1 and a non-display area B2. The plurality of sub-pixel circuits 13 are located on the display area B1, and the gate driving circuit 12 is located on the non-display area B2. The distance d2 between the virtual driving units 122 and the display area B1 is equal to the distance d1 between the active driving units 121 and the display area B1. In this way, the uniformity of the pattern distribution of the gate driving circuit 12 can be improved, so as to effectively improve the etching uniformity. For the rectangular substrate 11 shown in FIG. 1, the plurality of driving units can be distributed at intervals, and the interval distances can be the same. In this way, the uniformity of the distribution of the plurality of driving units can be improved, so as to further improve the etching uniformity. For the rounded rectangular substrate 11 shown in FIG. 4, the plurality of driving units can be distributed at intervals. Since the plurality of virtual driving units 122 are distributed at intervals on the rounded corner region of the substrate 11, it is not strictly required that the interval distances are the same. For example, the deviation rate of the interval between any two adjacent virtual driving units 122 in the rounded corner region and the interval between any two adjacent active driving units 122 outside the rounded corner region can be in the range of 0-10%.

[0083] In an exemplary embodiment, the active layer of the transistor can be disconnected to make the transistor in an off state. Please refer to FIG. 5 and FIG. 6, FIG. 5 is a structural schematic diagram of a part of structure of another display panel provided by the embodiment of the present application (FIG. 5 corresponds to the circuit schematic diagram shown in FIG. 3, and FIG. 5 can be a top structural schematic diagram of a virtual driving unit), and FIG. 6 is an enlarged schematic diagram of the part of structure of the display panel provided by FIG. 5 (FIG. 6 can be an enlarged schematic diagram of a Q2 region of the display panel provided by FIG. 5), the multiple transistors of the output module of the virtual driving unit include a first pole 161, a second pole 162 and an active layer 163, one of the first pole 161 and the second pole 162 is a source pole, and the other is a drain pole, and the first pole 161 and the second pole 162 can be a same layer structure.

[0084] The structure of the active layer 163 of the transistor includes at least one of the following structures:

[0085] 1) A structure Please refer to FIG. 6 and FIG. 7, FIG. 7 is a sectional structural schematic diagram of the display panel provided by FIG. 6 (FIG. 7 can be a sectional structural schematic diagram of the display panel provided by FIG. 6 at E1-E1), the active layer 163 of the transistor includes a first part 1631 connected with the first pole 161 and a second part 1632 connected with the second pole 162, and the first part 1631 is disconnected with the second part 1632. There is a gap between the first part 1631 and the second part 1632. Exemplarily, corresponding to the circuit schematic diagram shown in FIG. 3, the structure of the fifteenth transistor T15 of the virtual driving unit can be the structure shown in FIG. 7, and since the active layer 163 of the fifteenth transistor T15 is disconnected into the first part 1631 and the second part 1632, the fifteenth transistor T15 cannot form a channel, so that the fifteenth transistor T15 can be made not to work.

[0086] 2) Another structure please refer to FIG. 6 and FIG. 8, FIG. 8 is another cross-sectional structure schematic diagram of the display panel provided by FIG. 6 (FIG. 8 can be a cross-sectional structure schematic diagram of the display panel provided by FIG. 6 at E2-E2), the active layer 163 of the transistor is connected with the first electrode 161, and the active layer 163 of the transistor is disconnected with the second electrode 162. There is a gap on the side of the active layer 163 away from the first electrode 161. For example, corresponding to the circuit schematic diagram shown in FIG. 3, the structure of the thirteenth transistor T13 and the fourteenth transistor T14 of the virtual driving unit can be the structure shown in FIG. 8, the second electrode 162 of the thirteenth transistor T13 and the fourteenth transistor T14 is connected, and because the active layer 163 of the thirteenth transistor T13 and the fourteenth transistor T14 is disconnected into a first part 1631 and a third part 1633, wherein the first part 1631 of the active layer 163 corresponding to the thirteenth transistor T13 is only connected with the first electrode 161 and disconnected with the second electrode 162, and the third part 1633 of the active layer 163 corresponding to the fourteenth transistor T14 is only connected with the first electrode 161 and disconnected with the second electrode 162, then the thirteenth transistor T13 and the fourteenth transistor T14 of the virtual driving unit cannot form a channel, so as to make the thirteenth transistor T13 and the fourteenth transistor T14 not work.

[0087] The above two structures can make the first electrode 161 and the second electrode 162 unable to conduct, so as to make the transistor not work, and the structure of the plurality of transistors of the output module of the virtual driving unit can be any one of the above two structures, so as to make the output function of the virtual driving unit 122 invalid.

[0088] In addition, the first electrode 161 or the second electrode 162 of the transistor of the output module of the virtual driving unit can be removed in the embodiments of the present application, so as to make the transistor not work, and the output function of the virtual driving unit 122 can be invalidated.

[0089] Optionally, referring to FIG. 9, FIG. 9 is a structural schematic diagram of part of structures in another display panel provided by the embodiment of the present application. The display panel further includes a direct current signal line 152 on the substrate 11. The active layers 163 of the plurality of transistors of the output module of the virtual driving unit are electrically connected with the direct current signal line 152. The direct current signal line 152 can supply direct current signals to the disconnected active layers 163, so that the disconnected active layers 163 can be prevented from being in a floating state, and thus the problem of electrostatic breakdown can be avoided. The disconnected active layers 163 of the plurality of transistors can be electrically connected with the direct current signal line 152, that is, the whole is connected with the same direct current signal, so as to facilitate manufacturing, and the wiring arrangement can be facilitated while the circuit is stable, and the wiring space can be saved. For example, the direct current signal line 152 can be used to transmit a high-level direct current signal. In addition, the direct current signal line 152 can be located on the side of the first electrode 161 or the second electrode 162 away from the substrate 11. Then, the disconnected active layers 163 of the plurality of transistors can be connected through the first electrode 161 or the second electrode 162 connected with the active layer 163 to achieve the effect of electrical connection with the direct current signal line 152, so as to be connected with the direct current signal.

[0090] Optionally, referring to FIG. 7, the plurality of transistors of the output module A2 of the virtual driving unit 122 further includes a gate 164. In one of the plurality of transistors, the orthogonal projection of the active layer 163 on the substrate 11 does not overlap with the orthogonal projection of the gate 164 on the substrate 11. In addition, the orthogonal projection of the active layer 163 on the substrate 11 and the orthogonal projection of the gate 164 on the substrate 11 can have a certain spacing, so that the active layer 163 can be disconnected, and the active layer 163 can be electrically connected with the direct current signal line 152. For example, the spacing between the orthogonal projection of the active layer 163 on the substrate 11 and the orthogonal projection of the gate 164 on the substrate 11 can be greater than 0.8 microns.

[0091] Optionally, corresponding to the circuit principle diagram shown in FIG. 3, the output module A2 of the virtual driving unit and the effective driving unit each includes a plurality of devices. The specific structure can be referred to FIG. 5 and FIG. 10. FIG. 10 is a structural schematic diagram of part of structures in another display panel provided by the embodiment of the present application (FIG. 10 can be a top view structural schematic diagram of the effective driving unit). The effective driving unit 121 and the virtual driving unit 122 include active patterns P1, first gate patterns P2, second gate patterns P3, insulating layers P4, first source-drain patterns P5, planar layers P6, and second source-drain patterns P7 located at different layers.

[0092] The active pattern P1 includes active layers of a plurality of transistors. The active layer of the effective driving unit 121 will be described with reference to FIG. 11, which is a top view of the active pattern in the display panel of FIG. 10. The first sub-pattern P101 of the active pattern P1 is the active layer of the first transistor T1. The second sub-pattern P102 of the active pattern P1 is the active layer of the second transistor T2. The third sub-pattern P103 of the active pattern P1 is the active layer of the third transistor T3. The fourth sub-pattern P104 of the active pattern P1 is the active layer shared by the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The fifth sub-pattern P105 of the active pattern P1 is the active layer of the ninth transistor T9. The sixth sub-pattern P106 of the active pattern P1 is the active layer of the tenth transistor T10. The seventh sub-pattern P107 of the active pattern P1 is the active layer of the eleventh transistor T11. The eighth sub-pattern P108 of the active pattern P1 is the active layer of the twelfth transistor T12. The ninth sub-pattern P109 of the active pattern P1 is the active layer shared by the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15.

[0093] In addition, the active layer of the virtual driving unit 122 will be described with reference to FIG. 12, which is a top view of the active pattern in the display panel of FIG. 5. In the shift register module A1 of the effective driving unit 121 and the virtual driving unit 122, the active layers of the first transistor T1 to the eighth transistor T8 have the same structure, so that the structural similarity of the effective driving unit 121 and the virtual driving unit 122 is improved. In the output module A2 of the virtual driving unit 122, the active layers of the ninth transistor T9, the tenth transistor T10, and the fifteenth transistor T15 can be disconnected in the manner shown in FIG. 7, i.e., the active layer 163 of the ninth transistor T9 and the tenth transistor T10 includes a first part 1631 connected to the first electrode 161 and a second part 1632 connected to the second electrode 162, and the first part 1631 is disconnected from the second part 1632. The active layers of the eleventh transistor T11 to the fourteenth transistor T14 can be disconnected in the manner shown in FIG. 8, i.e., the active layers 163 of the eleventh transistor T11 to the fourteenth transistor T14 are connected to the first electrode 161 and disconnected from the second electrode 162.

[0094] The first gate pattern P2 includes the gates of the plurality of transistors and the first plates of the plurality of capacitor structures. The first gate pattern P2 of the effective driving unit 121 will be described with reference to FIG. 13, which is a top view of the first gate pattern in the display panel provided in FIG. 10. The first sub-pattern P201 of the first gate pattern P2 is the gate of the first transistor T1. The second sub-pattern P202 of the first gate pattern P2 is the gate of the second transistor T2. The third sub-pattern P203 of the first gate pattern P2 is the gate of the third transistor T3. The fourth sub-pattern P204 of the first gate pattern P2 is the gate shared by the fourth transistor T4 and the sixth transistor T6 and the first plate of the first capacitor structure C1. The fifth sub-pattern P205 of the first gate pattern P2 is the gate of the eighth transistor T8. The sixth sub-pattern P206 of the first gate pattern P2 is the gate of the fifth transistor T5 and the first plate of the second capacitor structure C2 and the sixth capacitor structure C6. The seventh sub-pattern P207 of the first gate pattern P2 is the gate of the seventh transistor T7. The eighth sub-pattern P208 of the first gate pattern P2 is the gate of the ninth transistor T9 and the first plate of the third capacitor structure C3. The ninth sub-pattern P209 of the first gate pattern P2 is the gate of the tenth transistor T10 and the first plate of the fourth capacitor structure C4 and the fifth capacitor structure C5. The tenth sub-pattern P210 of the first gate pattern P2 is the gate shared by the eleventh transistor T11 and the twelfth transistor T12. The eleventh sub-pattern P211 of the first gate pattern P2 is the gate shared by the thirteenth transistor T13 and the fourteenth transistor T14. The twelfth sub-pattern P212 of the first gate pattern P2 is the gate of the fifteenth transistor T15.

[0095] In addition, the first gate pattern P2 of the virtual driving unit 122 will be described with reference to FIG. 14, which is a top view of the first gate pattern in the display panel provided in FIG. 5. In the shift register module A1 of the effective driving unit 121 and the virtual driving unit 122, the gates of the first transistor T1 to the eighth transistor T8 are the same in structure, and the first capacitor structure C1 and the second capacitor structure C2 are the same in structure. In this way, the structural similarity of the effective driving unit 121 and the virtual driving unit 122 can be improved. In the output module A2 of the virtual driving unit 122, since the active layer of the eleventh transistor T11 and the twelfth transistor T12 only retains the part connected to the first electrode, the gates of the eleventh transistor T11 and the twelfth transistor T12 do not need to be provided, that is, the tenth sub-pattern P210 of the first gate pattern P2 can not be included in the output module A2 of the virtual driving unit 122, thereby saving the etching process. In addition, the sixth sub-pattern P206 of the first gate pattern P2 is the gate of the fifth transistor T5 and the first plate of the second capacitor structure C2, that is, the first plate of the sixth capacitor structure C6 of the virtual driving unit 122 is not provided, so that the sixth capacitor structure C6 of the virtual driving unit 122 can be prevented from being connected to the direct current signal.

[0096] The second gate pattern P3 includes a plurality of second plates of the capacitor structures. The second gate pattern P3 of the effective driving unit 121 and the virtual driving unit 122 will be described with reference to FIG. 15, which is a top view of the second gate pattern in the display panel of FIG. 10. The first sub-pattern P301 of the second gate pattern P3 is the second plate of the first capacitor structure C1. The second sub-pattern P303 of the second gate pattern P3 is the second plate of the second capacitor structure C2 and the sixth capacitor structure C6. The third sub-pattern P303 of the second gate pattern P3 is the second plate of the third capacitor structure C3. The fourth sub-pattern P304 of the second gate pattern P3 is the second plate of the fourth capacitor structure C4. The fifth sub-pattern P305 of the second gate pattern P3 is the second plate of the fifth capacitor structure C5. The second gate pattern P3 of the effective driving unit 121 and the virtual driving unit 122 has the same structure, which can improve the structural similarity of the effective driving unit 121 and the virtual driving unit 122.

[0097] Optionally, the display panel further includes a direct current signal line and a shift signal line on the substrate, and the plurality of devices include a target device, which is the sixth capacitor structure C6, as shown in FIG. 3. The target device of the effective driving unit 121 includes a first plate and a second plate arranged in a direction away from the substrate 11, the first plate is connected to the direct current signal line to access the direct current signal, and the second plate is connected to the shift signal line to output the shift signal, as shown in FIG. 13 and FIG. 15. The target device of the virtual driving unit 122 has a same layer structure as the second plate of the sixth capacitor structure C6, the target device of the virtual driving unit 122 is connected to the shift signal line, and the target device of the virtual driving unit is disconnected from the direct current signal line, so that the target device of the virtual driving unit 122 can avoid accessing the direct current signal, thereby ensuring that the output function of the virtual driving unit 122 is disabled.

[0098] The insulating layer P4 can be an interlayer dielectric layer between the second gate pattern P3 and the first source-drain pattern P5 to play an insulating role. The insulating layer P4 can include a plurality of vias H3, as shown in FIG. 16, which is a top view of the insulating layer in the display panel of FIG. 5. The structures in the active pattern P1, the first gate pattern P2, and the second gate pattern P3 can be electrically connected to the structures in the first source-drain pattern P5 and the second source-drain pattern P7 through the vias H3.

[0099] The first source-drain pattern P5 can include the source and drain of a plurality of transistors. Please refer to FIG. 17, which is a top view of the first source-drain pattern in the display panel of FIG. 5. In the output module A2 of the dummy driving unit 122, the active layer of some transistors is disconnected from the second electrode, so the second electrode corresponding to the active layer of the transistors can not be provided. In addition, as shown in the first sub-pattern P501 of the first source-drain pattern P5 in FIG. 16, in the output module A2 of the dummy driving unit 122, the source or drain of a plurality of transistors can be connected, so that the same direct current signal can be easily accessed, and the manufacturing process can be facilitated.

[0100] The planar layer P6 can serve as an insulating layer between the first source-drain pattern P5 and the second source-drain pattern P7. Please refer to FIG. 18, which is a top view of the planar layer in the display panel of FIG. 5. The planar layer P6 can include a plurality of vias H4, and the structure in the first source-drain pattern P5 can be electrically connected to the structure in the second source-drain pattern P7 through the vias H4. In addition, the planar layer P6 can also improve the flatness of the second source-drain pattern P7.

[0101] The second source-drain pattern P7 can include a plurality of traces. Please refer to FIG. 3 and FIG. 19, which is a top view of the second source-drain pattern in the display panel of FIG. 5. The first trace P701 and the eighth trace P708 are low-level direct current signal lines for transmitting a low-level direct current signal (VGL), the second trace P702 is a first clock signal line for transmitting a first clock signal (CK1), the third trace P703 is a second clock signal line for transmitting a second clock signal (CK2), the fourth trace P704 is a third clock signal line for transmitting a third clock signal (CK3), the fifth trace P705 is a fourth clock signal line for transmitting a fourth clock signal (CK4), the sixth trace P706 and the ninth trace P709 are high-level direct current signal lines for transmitting a high-level direct current signal (VGH), the seventh trace P707 is a power line for transmitting a power signal, the tenth trace P710 is a start signal line for transmitting a start signal, the eleventh trace P711 is a reset signal line for transmitting a first reset signal, the twelfth trace P712 is a reset signal line for transmitting a second reset signal, and the thirteenth trace P713 is a reset signal line for transmitting a third reset signal.

[0102] Optionally, the plurality of devices of the driving unit are transistors and capacitor structures shown in FIG. 3, the circuit layout of the plurality of devices in the effective driving unit 121 is the same as the circuit layout of the plurality of devices in the virtual driving unit 122, and the circuit layout of the plurality of devices can include relative positions and sizes of each layer pattern of the plurality of devices, and the circuit layout of the plurality of devices can further include connection relationships of each layer pattern other than the active pattern P1, the first sub-pattern P501 of the first source-drain pattern P5, and the sixth capacitor structure C6 in the output module A2, so that the structural similarity of the effective driving unit 121 and the virtual driving unit 122 can be further improved, and the etching uniformity of the gate driving circuit 12 can be improved.

[0103] In an exemplary embodiment, the display panel can further include at least one target structure to improve the etching uniformity. Please refer to FIG. 20, which is a structural schematic diagram of part of structures in another display panel provided by an embodiment of the present application. The display panel further includes at least one target structure 17, and the target structure 17 and the active layer 163 are in the same layer structure.

[0104] The target structure 17 satisfies at least one of the following conditions:

[0105] 1) Please refer to FIG. 20 for the case of the setting position of the target structure 17. The orthographic projection of the target structure 17 on the substrate 11 is located between the orthographic projection of the first part 1631 and the orthographic projection of the second part 1632 of one of the plurality of transistors on the substrate 11.

[0106] 2) Please refer to FIG. 21 for another case of the setting position of the target structure 17. FIG. 21 is a structural schematic diagram of part of structures in another display panel provided by an embodiment of the present application. The orthographic projection of the target structure 17 on the substrate 11 is located on the side away from the second orthographic projection from the first orthographic projection, the first orthographic projection is the orthographic projection of the active layer 163 of one of the plurality of transistors on the substrate 11, and the second orthographic projection is the orthographic projection of the first electrode 161 of the one transistor on the substrate 11.

[0107] The above two cases of the setting position of the target structure 17 correspond to the two structures of the active layer 163 shown in FIG. 7 and FIG. 8, respectively. The target structure 17 in the two cases can fill the gap existing in the active layer, avoid the gap affecting the pattern density, and thus improve the etching uniformity.

[0108] For different circuit structures, the setting position of the target structure 17 is different. For the circuit schematic diagram shown in FIG. 3, please refer to FIG. 22, which is a structural schematic diagram of part of the structure of another display panel provided by the embodiment of the present application. The target structure 17 can be arranged on one side of the eighth sub-pattern P108 of the active pattern P1 close to the shift register module A1. This is because the eighth sub-pattern P108 (the active layer of the twelfth transistor T12) only retains a part connected with the first electrode. Therefore, the gap Q1 formed by the active layer of the twelfth transistor T12 has a large size. For example, the distance between the center of the target structure 17 and the adjacent active pattern P1 is greater than 1.5 microns, which is convenient for manufacturing. In addition, the gap exists in the area corresponding to the gap Q1 formed by the active layer of the twelfth transistor T12 in each layer pattern, so that the arrangement of each layer pattern can be affected by the target structure 17, and the target structure 17 can be electrically connected with the direct current signal line through the first source-drain pattern P5.

[0109] Optionally, please refer to FIG. 22, the display panel further comprises an insulating layer P4 located on the side of the active layer 163 away from the substrate 11. The insulating layer P4 has at least one first opening H1 corresponding to at least one target structure 17. The orthographic projection of the target structure 17 on the substrate 11 and the orthographic projection of the corresponding first opening H1 on the substrate 11 overlap. Because the number of openings of the corresponding insulating layer P4 is reduced when the active layer of the transistor is disconnected, the first opening H1 can improve the etching uniformity of the insulating layer P4. In addition, the direct current signal line can be electrically connected with the target structure 17 through the first opening H1, and the target structure 17 is connected with the direct current signal, so that the risk of electrostatic breakdown of the target structure 17 can be reduced.

[0110] In an example embodiment, the display panel further comprises a plurality of clock signal lines and a plurality of first electrodes. Please refer to FIG. 23, which is a structural schematic diagram of part of structures in another display panel provided by the embodiment of the present application, and FIG. 23 can be part of structures on the display area of the substrate 11. The sub-pixel circuit 13 is electrically connected with the first electrode 131, the first electrode 131 corresponds to and is electrically connected with two clock signal lines of the plurality of clock signal lines 154, and the first electrode 131 has a second opening H2, and the orthographic projection of the second opening H2 of the first electrode 131 on the substrate 11 overlaps with the orthographic projection of the corresponding clock signal line 154 on the substrate 11. The plurality of first electrodes 131 are respectively anodes of a plurality of sub-pixels, the sub-pixel circuit 13 can be used to control the voltage of the first electrode 131, and the plurality of clock signal lines 154 can be used to transmit clock signals to the first electrode 131. There is an organic layer between the first electrode 131 and the clock signal line 154 to play an insulating role. During the manufacturing process of the organic layer, there will be gas such as water vapor or oxygen, and the gas will cause the organic layer to bulge. By setting the second opening H2 on the first electrode 131, the second opening H2 can discharge these gases, so as to avoid the influence of the bulging of the organic layer on the transmission of the clock signal by the clock signal line 154. In addition, a filling structure can also be set to fill the second opening H2, so as to increase the flatness of the first electrode 131.

[0111] Optionally, the display panel further comprises a pixel defining layer 18, the pixel defining layer 18 is located on the substrate 11, and the pixel defining layer 18 comprises a plurality of openings 181, the plurality of openings 181 correspond to the plurality of first electrodes 131 respectively, and the orthographic projection of each opening 181 on the substrate 11 overlaps with the orthographic projection of the corresponding first electrode 131 on the substrate 11. The plurality of openings 181 comprise a first opening 181 and a second opening 182, the first electrode 1311 corresponding to the first opening 181 is electrically connected with the clock signal line 154, the size of the first opening 181 is smaller than the size of the second opening 182, and the size of the second opening H2 of the first electrode 1311 corresponding to the first opening 181 is smaller than the size of the second opening H2 of the first electrode 1312 corresponding to the second opening 182. This is because the clock signal line 154 is arranged more densely, so that the area of the first electrode 1311 corresponding to the clock signal line 154 can be reduced to ensure that the clock signal line 154 can be electrically connected with the corresponding first electrode 1311. Moreover, by setting the size of the second opening H2 corresponding to the first opening 181 to be smaller than the size of the second opening H2 corresponding to the second opening 182, the effective area of the first electrode 131 can be ensured not to be too small, so as to avoid affecting the light-emitting area.

[0112] Optionally, in the first direction X, the width d3 of the part of the corresponding first electrode 1311 contacting the corresponding two clock signal lines 154 is the same as the width of the part of the corresponding two clock signal lines 154, and the first direction X is perpendicular to the extension direction of the clock signal line 154. In this way, the load uniformity of the two clock signal lines 154 electrically connected to the first electrode 131 can be improved, and the stability of the transmitted clock signal can be improved.

[0113] Optionally, in the first direction X, the minimum distance d4 between the edge of the clock signal line 154 and the edge of the second opening H2 of the corresponding first electrode 1311 is in the range of 0.5 microns to 1.0 microns. In this way, not only can the effective overlap between the clock signal line 154 and the corresponding first electrode 1311 be ensured, but also the second opening H2 can effectively exhaust gas, avoiding the influence of the gas on the transmission of the clock signal by the clock signal line 154.

[0114] In summary, the display panel provided by the embodiment of the present application is provided. The gate drive circuit of the display panel includes a plurality of cascaded driving units. The effective driving unit in the plurality of driving units is electrically connected to the sub-pixel circuit, and the virtual driving unit in the plurality of driving units is disconnected from the sub-pixel circuit. The virtual driving unit does not have an output function, and the virtual driving unit can input a shift signal to the corresponding effective driving unit. Therefore, the virtual driving unit and the effective driving unit provided by the present application have similar partial structures. In this way, the etching uniformity of the gate drive circuit can be improved, the deviation between the line width and thickness of the lines formed by etching in different areas of the gate drive circuit can be reduced, and the load uniformity of the shift signal input by the plurality of effective driving units can be improved. Therefore, the stability of the display panel can be improved.

[0115] On the other hand, the embodiment of the present application also provides a display device. The display device includes a housing and any one of the display panels provided by the above-mentioned embodiments. The display panel can be located in the housing. The display device can be various devices including a display function, such as a display, a television, a vertical advertising machine, a picture screen device, a mobile phone, various smart wearable devices, and the like.

[0116] Since the display device includes the display panel provided by the above-mentioned embodiments, the display device can also have similar effects, that is, the stability of the display device can be improved.

[0117] The term "at least one of A and B" in the present application is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, at least one of A and B can mean that A exists alone, A and B exist simultaneously, and B exists alone. Similarly, "at least one of A, B and C" means that there can be seven relationships, which can mean that A exists alone, B exists alone, C exists alone, A and B exist simultaneously, A and C exist simultaneously, C and B exist simultaneously, and A, B and C exist simultaneously.

[0118] It should be noted that in the drawings, the dimensions of layers and regions can be exaggerated for clarity. Also, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can also be present. In addition, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or layer, or one or more intervening layers or elements can also be present. In addition, it can also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements, or there can be one or more intervening layers or elements. Similar reference numerals indicate similar elements throughout the specification.

[0119] In the present application, the terms "first", "second", "third" and "fourth" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance. The term "a plurality of" means two or more, unless otherwise explicitly limited.

[0120] The above description is only optional embodiments of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a substrate, a gate drive circuit and a plurality of sub-pixel circuits on the substrate; The gate drive circuit comprises a plurality of driving units arranged in cascade, the plurality of driving units comprise a plurality of effective driving units and at least one virtual driving unit, each effective driving unit is electrically connected with at least one sub-pixel circuit, the virtual driving unit is disconnected with the sub-pixel circuit, each virtual driving unit comprises a shift signal output end, each shift signal input end of each effective driving unit corresponds to and is electrically connected with a shift signal output end; The effective driving unit and the virtual driving unit both comprise a shift register module and an output module, at least part of the structures of the output modules of the effective driving unit and the virtual driving unit are different.

2. The display panel of claim 1, wherein, The structure of the shift register module of the effective driving unit is the same as the structure of the shift register module of the virtual driving unit, the output module of the virtual driving unit comprises a plurality of transistors, and the plurality of transistors of the output module of the virtual driving unit are all in the off state.

3. The display panel of claim 2, wherein, The plurality of transistors of the output module of the virtual driving unit comprise a first electrode, a second electrode and an active layer, one of the first electrode and the second electrode is a source electrode and the other is a drain electrode; The active layer of the transistor comprises a first part connected with the first electrode and a second part connected with the second electrode, and the first part is disconnected with the second part.

4. The display panel of claim 2, wherein, The plurality of transistors of the output module of the virtual driving unit comprise a first electrode, a second electrode and an active layer, one of the first electrode and the second electrode is a source electrode and the other is a drain electrode; The active layer of the transistor is connected with the first electrode, and the active layer of the transistor is disconnected with the second electrode.

5. The display panel of claim 2, wherein, The plurality of transistors of the output module of the virtual driving unit comprise a first electrode, a second electrode and an active layer, one of the first electrode and the second electrode is a source electrode and the other is a drain electrode; The active layer of a part of the plurality of transistors comprises a first part connected with the first electrode and a second part connected with the second electrode, and the first part is disconnected with the second part; The active layer of the other part of the plurality of transistors is connected with the first electrode, and the active layer of the other part of the plurality of transistors is disconnected with the second electrode.

6. The display panel of any of claims 3 to 5, wherein, The display panel further comprises a direct current signal line on the substrate, and the active layer of the plurality of transistors of the output module of the virtual driving unit is electrically connected with the direct current signal line.

7. The display panel of any of claims 3 to 5, wherein, The display panel further comprises at least one target structure, and the target structure and the active layer are in the same layer structure; The target structure satisfies at least one of the following conditions: The target structure is located between the first part and the second part of one transistor of the plurality of transistors; A normal projection of the target structure on the substrate is located on a side of a first normal projection away from a second normal projection, the first normal projection is a normal projection of an active layer of a transistor of the plurality of transistors on the substrate, and the second normal projection is a normal projection of a first electrode of the transistor on the substrate.

8. The display panel of claim 7, wherein, The display panel further includes an insulating layer located on a side of the active layer away from the substrate, the insulating layer has at least one first opening corresponding to the at least one target structure, and a normal projection of the target structure on the substrate overlaps a normal projection of the corresponding first opening on the substrate.

9. The display panel of any of claims 3 to 5, wherein, The plurality of transistors of the output module of the virtual driving unit further include a gate electrode, and in one of the plurality of transistors, a normal projection of the active layer on the substrate does not overlap a normal projection of the gate electrode on the substrate.

10. The display panel of claim 2, wherein, The effective driving unit and the output module of the virtual driving unit each include a plurality of devices, a circuit layout of the plurality of devices in the effective driving unit is the same as a circuit layout of the plurality of devices in the virtual driving unit, the display panel further includes a direct current signal line and a shift signal line on the substrate, and the plurality of devices include target devices; the target devices in the effective driving unit include a first electrode plate and a second electrode plate arranged in a direction away from the substrate, the first electrode plate is connected to the direct current signal line, the second electrode plate is connected to the shift signal line, the target devices in the virtual driving unit and the second electrode plate are a same layer structure, the target devices in the virtual driving unit are connected to the shift signal line, and the target devices in the virtual driving unit are disconnected from the direct current signal line.

11. The display panel of claim 1, wherein, The substrate includes a display area and a non-display area, the plurality of sub-pixel circuits are located on the display area, and the gate electrode driving circuit is located on the non-display area. The distance between the virtual driving unit and the display area is equal to the distance between the effective driving unit and the display area.

12. The display panel of claim 1, wherein, The display panel further includes a plurality of clock signal lines and a plurality of first electrodes, the sub-pixel circuits are electrically connected to the first electrodes, the first electrodes correspond to and are electrically connected to two of the plurality of clock signal lines, the first electrodes have second openings, and a normal projection of the second opening of the first electrode on the substrate overlaps a normal projection of the corresponding clock signal line on the substrate.

13. The display panel of claim 12, wherein, The display panel further includes a pixel definition layer located on the substrate, the pixel definition layer includes a plurality of openings, the plurality of openings respectively correspond to the plurality of first electrodes, and a normal projection of the opening on the substrate respectively overlaps a normal projection of the corresponding first electrode on the substrate. The plurality of openings include first openings and second openings, the first electrode corresponding to the first opening is electrically connected to the clock signal line, the size of the first opening is smaller than the size of the second opening, and the size of the second opening of the first electrode corresponding to the first opening is smaller than the size of the second opening of the first electrode corresponding to the second opening.

14. The display panel of claim 12, wherein, In a first direction, the width of the portion of the first electrode in contact with the corresponding two clock signal lines is the same as the width of the portion of the clock signal lines in the first direction.

15. A display device comprising: The display device comprises a housing and the display panel according to any one of claims 1 to 14.

Images