Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a display region and a peripheral region surrounding the display region, the peripheral region comprises a lead-out line region located on one side of the display region, and the lead-out line region comprises a bending region. A first blocking dam and a second blocking dam surround the display region, and the second blocking dam is located on the side of the first blocking dam away from the display region. At least one isolation trench is located on the side of the second blocking dam away from or close to the display region. A power line is electrically connected to a plurality of sub-pixels in the display region so as to provide a constant voltage signal to the plurality of sub-pixels. At least one power pin electrically connected to the power line and extending in a direction away from the display region is provided in the lead-out line region, the power pin comprises a first part located in the first blocking dam and close to the display region, a second part located between the second blocking dam and the bending region, and an adapter electrode at least partially located between the first part and the second part, and the first part and the second part are in different layers from the adapter electrode and are electrically connected by means of the adapter electrode.

Description

Display substrate and display device

[0001] The present application claims priority to the Chinese patent application No. 202411367439.8, filed on September 27, 2024, and entitled "Display substrate and display device", the content of which is understood to be incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display substrate and a display device. BACKGROUND

[0003] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, a display device with an OLED as a light emitting element and a thin film transistor (TFT) for signal control has become the mainstream product in the current display field.

[0004] However, the lower frame of the display product has a problem of growing dark spot (GDS). SUMMARY

[0005] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a display substrate and a display device to solve the problem of GDS in the lower frame of the display product.

[0007] In one aspect, the display substrate includes a substrate, a plurality of sub-pixels, a first barrier dam, a second barrier dam, at least one isolation groove, a power line, and at least one power pin. The substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a lead-out area on one side of the display area. The lead-out area includes a bending area. The plurality of sub-pixels are located on one side of the substrate and in the display area. The first barrier dam is located on the substrate and in the peripheral area and surrounds the display area. The second barrier dam is located on the substrate and in the peripheral area and surrounds the display area. The second barrier dam is located on a side of the first barrier dam away from the display area. The at least one isolation groove is located on a side of the second barrier dam away from or close to the display area. The power line is electrically connected to the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels. The at least one power pin is located in the lead-out area and extends in a direction away from the display area and is electrically connected to the power line. The at least one power pin includes a first portion located on the first barrier dam close to the display area, a second portion located between the second barrier dam and the bending area, and a transfer electrode located at least partially between the first portion and the second portion. The first portion and the second portion are located in different layers from the transfer electrode, and the first portion and the second portion are electrically connected through the transfer electrode.

[0008] In an example embodiment, in a direction away from the substrate, the display substrate includes a driving structure layer, a transfer layer, a planarization layer, and a display structure layer arranged in sequence. The driving structure layer includes a pixel driving circuit. The display structure layer includes a first electrode, a pixel definition layer, an organic light emitting layer, and a second electrode. The pixel definition layer includes a plurality of pixel openings. The pixel openings expose the first electrode. The organic light emitting layer is arranged in the pixel openings. One end of the organic light emitting layer is electrically connected to the first electrode. The other end of the organic light emitting layer is electrically connected to the second electrode. The anode is electrically connected to the pixel driving circuit through the transfer electrode.

[0009] In an example embodiment, the transfer electrode is arranged in the same layer as the anode. The first portion and the second portion are electrically connected through the transfer electrode. The transfer electrode is electrically connected to the first portion through a first via. The transfer electrode is electrically connected to the second portion through a second via. The first via and the second via penetrate the planarization layer.

[0010] In an example embodiment, the display substrate further comprises a spacer layer above the pixel definition layer, and the transfer electrode is in the same layer as the spacer layer; the first portion and the second portion are electrically connected through the transfer electrode, including that the transfer electrode is electrically connected with the first portion through a first via, and the transfer electrode is electrically connected with the second portion through a second via, and the first via and the second via penetrate the pixel definition layer and the planar layer.

[0011] In an example embodiment, further comprising a touch layer above the display structure layer, and the touch layer comprises a first wiring layer, and the transfer electrode is in the same layer as the first wiring layer.

[0012] In an example embodiment, the driving structure layer comprises a first gate metal layer and a second gate metal layer arranged in sequence away from the substrate; the transfer electrode is in the same layer as any one of the first gate metal layer and the second gate metal layer, or the transfer electrode comprises a stacked structure in the same layer as the first gate metal layer and the second gate metal layer.

[0013] In an example embodiment, the driving structure layer further comprises a third gate metal layer above the second gate metal layer; the transfer electrode is in the same layer as any one of the first gate metal layer, the second gate metal layer and the third gate metal layer, or the transfer electrode comprises a stacked structure in the same layer as at least two of the first gate metal layer, the second gate metal layer and the third gate metal layer.

[0014] In an example embodiment, the material of the pixel definition layer comprises an inorganic material.

[0015] In an example embodiment, the projection of the transfer electrode on the substrate and the projection of the at least one isolation groove on the substrate partially overlap; the at least one isolation groove comprises a first isolation groove and a second isolation groove, and in the plane of the substrate, the first isolation groove is between the first blocking dam and the second blocking dam, and the second isolation groove is between the second blocking dam and the bending area.

[0016] In an example embodiment, the first isolation groove surrounds the display area, or the first isolation groove is located on one side of the display area close to the bending area; the second isolation groove surrounds the display area, or the second isolation groove is located on one side of the display area close to the bending area.

[0017] In an example embodiment, the display substrate further includes an auxiliary transfer electrode, the auxiliary transfer electrode is disposed in the same layer as the first portion and the second portion, and the auxiliary transfer electrode is connected to the first portion and the second portion.

[0018] In an example embodiment, the first portion and the second portion are electrically connected by the transfer electrode, including that at least one of the first portion and the second portion is connected to the transfer electrode by a via, and the transfer electrode is connected to the auxiliary transfer electrode by a via.

[0019] In an example embodiment, the lead-out area further includes an integrated circuit area located on a side of the bending area away from the display area; the power supply line includes a plurality of first power supply lines and a first power supply bus, the plurality of first power supply lines are located in the display area and electrically connected to the plurality of sub-pixels and configured to transmit a first voltage signal to the plurality of sub-pixels; the first power supply bus is located in the lead-out area and between the bending area and the display area, the first power supply bus extends along a first direction and is electrically connected to the plurality of first power supply lines; the at least one power supply pin includes two first power supply pins, the two first power supply pins are located on two sides of the integrated circuit area along the first direction.

[0020] In an example embodiment, the power supply line further includes a second power supply line located in the peripheral area and surrounding the display area, and the at least one power supply pin includes two second power supply pins, the two second power supply pins are located on two sides of the two first power supply pins along the first direction.

[0021] In an example embodiment, the peripheral area further includes a binding area located on a side of the lead-out area away from the display area, the binding area includes a plurality of binding pads; the first power supply pin and the second power supply pin are connected to different binding pads.

[0022] In an example embodiment, the first barrier dam includes a first dam base and a second dam base, the second barrier dam includes a third dam base and a fourth dam base, the first dam base, the third dam base, and the flat layer are disposed in the same layer, and the second dam base, the fourth dam base, and the pixel definition layer are disposed in the same layer.

[0023] In another aspect, the display device includes the display substrate as described above.

[0024] The display substrate provided by the embodiments of the present disclosure, the power supply pin of the lead-out line area includes a first part, a second part and a transition electrode, the transition electrode is electrically connected with the first part and the second part respectively, by arranging the first part, the second part and the transition electrode in different layers, the number of times of wet etching and developing experienced by the first part and the second part is different from the number of times of wet etching and developing experienced by the transition electrode, so that the position and material of the transition electrode and other parameters can be flexibly adjusted, so that the transition electrode will not form a "eave" structure at the edge, thereby not affecting the film formation morphology of the subsequent packaging layer, and GDS defects of the display substrate can be avoided.

[0025] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. Other advantages of the present application can be realized and obtained by means of the solutions described in the specification and the drawings.

[0026] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description with reference to the accompanying drawings.

[0027] SUMMARY

[0028] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, together with the embodiments of the present application, to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0029] Fig. 1 is a structural schematic diagram of a display substrate;

[0030] Fig. 2 is a planar structural schematic diagram of a display area in a display substrate;

[0031] Fig. 3 is an equivalent circuit schematic diagram of a pixel driving circuit;

[0032] Fig. 4 is a structural schematic diagram of a display substrate in an exemplary embodiment;

[0033] Fig. 5 is a sectional view of the display substrate of Fig. 4 along the direction of B-B in an exemplary embodiment;

[0034] Fig. 6 is a structural schematic diagram of an edge of a first power line in an exemplary embodiment;

[0035] Fig. 7 is a sectional view of the display substrate of Fig. 4 along the direction of B-B in another exemplary embodiment;

[0036] Fig. 8 is a sectional view of the display substrate of Fig. 4 along the direction of B-B in another exemplary embodiment;

[0037] Fig. 9 is a sectional view of the display substrate of Fig. 4 along the direction of B-B in another exemplary embodiment;

[0038] FIG. 10 is a cross-sectional view of the display substrate of FIG. 4 along the B-B direction in yet another exemplary embodiment;

[0039] FIG. 11 is a cross-sectional view of the display substrate of FIG. 4 along the B-B direction in yet another exemplary embodiment;

[0040] FIG. 12 is a cross-sectional view of a display substrate of a display area in an exemplary embodiment.

[0041] DETAILED DESCRIPTION

[0042] The present disclosure describes a number of embodiments, but the description is illustrative rather than limiting and many additions, deletions, and modifications can be made to the described embodiments by those skilled in the art without departing from the scope of the described embodiments. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Any feature of any embodiment can be used with any other feature or element from any other embodiment, or can replace any other feature or element in any other embodiment, unless specifically restricted or unless the specific combination is already explicitly disclosed.

[0043] The present disclosure includes and contemplates combinations of features and elements known in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional feature or element to form a unique application of the presently disclosed application. Any feature or element of any embodiment can also be combined with features or elements from other applications to form another unique application of the presently disclosed application. Accordingly, it should be understood that any feature shown and / or discussed in the present disclosure can be used alone or in any combination. The embodiments are therefore not limited to the specific combinations of elements or features disclosed in the specification. In addition, various modifications and changes can be made thereto without departing from the scope of the claims.

[0044] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the specific order of steps described. Other sequences of steps can be possible, depending on the implementation, without departing from the scope of the present disclosure. Accordingly, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. Further, the claims should not be limited to the steps of the method and / or process set forth, as the method and / or process can include changes, modifications, and / or additions to the steps set forth, as will become apparent to those skilled in the art.

[0045] In the drawings, the size, the thickness, or the region of one or a plurality of components is sometimes exaggerated for the sake of clarity. Thus, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the relative sizes of one or a plurality of components shown in the drawings can not reflect the actual ones. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0046] The ordinal numbers, such as "first", "second", and "third", are used for the purpose of avoiding ambiguity, and do not necessarily limit the number or order of the constituent elements. "A plurality of" in the present disclosure means two or more.

[0047] In the present specification, the words "center", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", "outside", and the like used to describe the positional relationship of the components are used for the purpose of facilitating the description of the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed depending on the situation.

[0048] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection via an intermediate component, or communication between the two elements. The meaning of the above terms in the present disclosure can be understood by those skilled in the art according to the situation.

[0049] In the present specification, "electrically connected" includes the case where the components are connected through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can transmit an electrical signal between the components to be connected. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0050] In the present specification, "parallel" means a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0051] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0052] FIG. 1 is a schematic diagram of a structure of a display substrate. As shown in FIG. 1, the display substrate can include a timing controller, a data driver, a scan driver, an emission driver, and a pixel array, the timing controller is connected to the data driver, the scan driver, and the emission driver respectively, the data driver is connected to a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively, and the emission driver is connected to a plurality of emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and an emission element connected to the circuit unit, the circuit unit can include at least a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the data signal line, and the emission signal line respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the emission driver to the emission driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The emission driver can generate emission signals to be provided to the emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the emission driver can sequentially provide the emission signal having an off-level pulse to the emission signal lines E1 to Eo. For example, the emission driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number.

[0053] FIG. 2 is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner. At least one pixel unit P can include a first sub-pixel P1 emitting light rays of a first color, a second sub-pixel P2 emitting light rays of a second color, and a third sub-pixel P3 emitting light rays of a third color. Each sub-pixel can include a circuit unit and a light emitting element. The circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a data signal line, and a light emitting signal line, respectively. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting element. The light emitting element in each sub-pixel is connected to the pixel driving circuit of the sub-pixel in which the light emitting element is located. The light emitting element is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0054] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light rays, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light rays, and the third sub-pixel P3 can be a green sub-pixel (G) emitting green light rays. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal. The three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0055] In an example embodiment, the pixel unit can include four sub-pixels. For example, the four sub-pixels can include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel emitting white (W) light rays. For another example, the four sub-pixels can include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an example embodiment, the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, square, or diamond manner, which is not limited in the present disclosure.

[0056] FIG. 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 3, the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to six signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, initial signal line INIT, and first power supply line VDD), respectively.

[0057] In the example embodiment, the pixel driving circuit can include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively. The second node N2 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively.

[0058] In the example embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, i.e., the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0059] The gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the turn-on level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initial voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.

[0060] The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the turn-on level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode and the second electrode of the third transistor T3.

[0061] The gate electrode of the third transistor T3 is connected to the second node N2, i.e., the gate electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its gate electrode and the first electrode.

[0062] The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, etc., and when the turn-on level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0063] The gate electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light emitting transistors. When an on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting element EL to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0064] The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element EL. When an on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits an initial voltage to the first electrode of the light emitting element EL to initialize the amount of charge accumulated in the first electrode of the light emitting element EL or release the amount of charge accumulated in the first electrode of the light emitting element EL.

[0065] In an exemplary embodiment, the light emitting element EL can be an OLED including a first electrode, an organic light emitting layer, and a second electrode stacked, or can be a QLED including a first electrode, a quantum dot light emitting layer, and a second electrode stacked. In this embodiment, the first electrode can be an anode, and the second electrode can be a cathode, which is not limited in the present disclosure.

[0066] In an exemplary embodiment, the second electrode of the light emitting element EL is connected to the second power supply line VSS, and the signal of the second power supply line VSS is a continuously provided low-level signal. The signal of the first power supply line VDD is a continuously provided high-level signal.

[0067] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0068] In an example embodiment, the first transistor T1 to the seventh transistor T7 can adopt a low temperature poly-silicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low temperature poly-silicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0069] The working process of the pixel driving circuit can include the following stages, taking the example that the seven transistors are all P-type transistors.

[0070] The first stage A1 is called a reset stage. The signal of the second scan signal line S2 is a low level signal, and the signals of the first scan signal line S1 and the emission signal line E are high level signals. The signal of the second scan signal line S2 being a low level signal makes the first transistor T1 and the seventh transistor T7 conduct. The first transistor T1 being conductive makes the initial voltage of the initial signal line INIT provided to the second node N2, and the storage capacitor C is initialized to clear the original data voltage in the storage capacitor. The seventh transistor T7 being conductive makes the initial voltage of the initial signal line INIT provided to the first electrode of the OLED, and the first electrode of the OLED is initialized (reset) to clear the pre-stored voltage in the internal electrode, and the initialization is completed. The signals of the first scan signal line S1 and the emission signal line E being high level signals make the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 disconnected, and the OLED does not emit light in this stage.

[0071] In the second stage A2, referred to as a data writing stage or threshold compensation stage, the signal of the first scan signal line S1 is a low level signal, the signals of the second scan signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs a data voltage. In this stage, the second end of the storage capacitor C is at a low level, so the third transistor T3 is turned on. The signal of the first scan signal line S1 being a low level signal turns on the second transistor T2 and the fourth transistor T4. The turning on of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to pass through the first node N1, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, and be provided to the second node N2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C, so that the voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The signal of the second scan signal line S2 being a high level signal turns off the first transistor T1 and the seventh transistor T7. The signal of the light emitting signal line E being a high level signal turns off the fifth transistor T5 and the sixth transistor T6.

[0072] In the third stage A3, referred to as a light emitting stage, the signal of the light emitting signal line E is a low level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 are high level signals. The signal of the light emitting signal line E being a low level signal turns on the fifth transistor T5 and the sixth transistor T6, and because the voltage Vd-|Vth| is written to the second end of the storage capacitor C in the previous stage, the third transistor T3 can still be kept in a turned-on state in this stage. The power supply voltage output by the first power supply line VDD is provided to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6 to drive the OLED to emit light.

[0073] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode of the third transistor T3. Because the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0074] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0075] A display device includes a driving circuit layer disposed on a substrate, a light emitting element disposed on the driving circuit layer, and an encapsulation layer disposed on the light emitting element, the encapsulation layer for protecting the light emitting element. Research shows that the encapsulation effect of the encapsulation layer has a great influence on the display performance of the display device. If the encapsulation layer fails, such as a gap or a crack occurs in the encapsulation layer, water vapor in the atmosphere will enter the light emitting element along the gap, causing the organic material in the light emitting element to oxidize and fail, forming a failure area that cannot emit light. As the water vapor continuously invades the light emitting element along the gap, the failure area gradually expands, causing the display device to display poorly, which is called growing dark spot (GDS). The GDS occurring at the fixed position of the lower frame of the display device is called GDSX defect.

[0076] FIG. 4 is a schematic diagram of a structure of a display substrate in an example embodiment. As shown in FIG. 4, the display substrate includes a substrate including a display area 100 and a peripheral area surrounding the display area 100. The peripheral area includes a first peripheral area 200 located on one side of the display area 100 along a second direction Y, and a second peripheral area 300 located on the periphery of the display area 100 and away from the side of the first peripheral area 200, the first peripheral area 200 and the second peripheral area 300 being in communication to surround the display area 100. The display area 100 includes at least a plurality of sub-pixels Pxij arranged in a regular manner, for example, the plurality of sub-pixels Pxij can be arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y being perpendicular to each other, for example, the second direction Y can be perpendicular to the first direction X. The plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). In the example embodiment, the display panel can be deformable, for example, curled, bent, folded or rolled up. The display panel includes an upper frame and a lower frame oppositely disposed along the second direction Y, and a left frame and a right frame oppositely disposed along the first direction X, the lower frame being the frame on the side of the first peripheral area 200, and the structure at the lower frame is highlighted in FIG. 4.

[0077] In an example embodiment, the display area 100 can have a quadrilateral shape, a circular shape, an elliptical shape, a polygonal shape of other shapes, or an irregular shape, and the corner shape of the display area 100 can be a rounded corner. In an example embodiment, the display area edge shape at different borders can be different shapes, such as a straight line, a curved line, a broken line, and the like, depending on the display area shape. In an example embodiment, the first peripheral area 200 can include a lead-out line area 210 and a bonding area 230 located on the side of the display area 100 along the second direction Y in sequence, and the lead-out line area 210 includes a bending area 220. The lead-out line area 210 is connected to the display area 100 and can include at least a plurality of data lead-out lines Sx. The signal lines such as the power lines and the data lines Dx of the display area 100 can pass through the lead-out line area 210 in a fan-out manner and be connected to the corresponding signal providing end. As shown in FIG. 4, the lead-out line area 210 includes a first lead-out line area 210A, a bending area 220, a second lead-out line area 210B, a multiplexing circuit area 400, a third lead-out line area 210C, and an integrated circuit area 500 arranged in sequence away from the display area 100, the first lead-out line area 210A is connected to the display area 100, the bending area 220 is connected to the first lead-out line area 210A, the second lead-out line area 210B is connected to the bending area 220, the multiplexing circuit area 400 is connected to the second lead-out line area 210B, the third lead-out line area 210C is connected to the multiplexing circuit area 400, and the integrated circuit area 500 is connected to the third lead-out line area 210C. The bending area 220 can include a composite insulating layer provided with a groove and configured to bend the side substrate of the bending area 220 away from the display area 100 to the back of the display area 100. An integrated circuit (such as a driving IC, not shown in the figure) can be bonded and connected in the integrated circuit area 500. The integrated circuit, the plurality of signal lines (such as the data lead-out lines Sx), can be connected to the integrated circuit after passing through the first lead-out line area 210A and the second lead-out line area 210B, and the integrated circuit can send signals to the sub-pixels Pxij of the display area 10 through the multiplexing circuit provided in the multiplexing circuit area 400. The bonding area 230 can include at least a plurality of bonding pads 231, and the plurality of signal lines can be connected to the corresponding bonding pads 231 after passing through the first lead-out line area 210A, the second lead-out line area 210B, and the third lead-out line area 210C to receive corresponding electrical signals, and the integrated circuit can be connected to the corresponding bonding pads 231. For example, a flexible circuit board (not shown in the figure) can be bonded and connected with the display substrate through the bonding pads 231. After being bent in the bonding area 230, the flexible circuit board can be bent to the back of the display area 100.

[0078] In the example embodiment, the second peripheral region 300 at least includes a plurality of driving circuits, for example, gate driving circuits, a plurality of signal transmission lines of the plurality of driving circuits can pass through the lead-out line region 210 in a fan-out manner and be electrically connected to the pads of the corresponding integrated circuit region 500 to receive corresponding signals and drive the sub-pixels Pxij.

[0079] In the example embodiment, the peripheral region of the substrate further includes a first blocking dam 410 and a second blocking dam 420, the first blocking dam 410 and the second blocking dam 420 surround the display region 100, and the second blocking dam 420 is located on the side of the first blocking dam 410 away from the display region 100. A first isolation groove F1 is arranged on the side of the second blocking dam 420 close to the display region 100, and a second isolation groove F2 is arranged on the side of the second blocking dam 420 away from the display region 100. In FIG. 4, the first isolation groove F1 and the second isolation groove F2 are both taken as examples of surrounding the display region 100, and in other embodiments, the first isolation groove F1 and the second isolation groove F2 can be located only in the lead-out line region 210. In other embodiments, only the first isolation groove F1 or the second isolation groove F2 can be arranged. In the example embodiment, the substrate further includes a power line for transmitting a constant voltage signal to the plurality of sub-pixels Pxij. As shown in FIG. 4, the power line can include a first power line 330 and a first power bus 310, the first power line 330 is located in the display region 100 and is electrically connected to the plurality of sub-pixels Pxij and is configured to transmit a first voltage signal to the plurality of sub-pixels Pxij, the first power bus 310 is located in the lead-out line region 210 and between the bending region 220 and the display region 100, the first power bus 310 extends along the first direction X and is electrically connected to the plurality of first power lines 330, and the first voltage signal can be a high voltage signal, for example, a positive voltage signal. At least one first power pin 320 is further arranged in the lead-out line region 210, the first power pin 320 extends in a direction away from the display region 100, one end of the first power pin 320 is electrically connected to the first power bus 310, and the other end of the first power pin 320 is connected to the corresponding binding pin 231 in the binding region 230 to receive the first power signal.

[0080] As shown in FIG. 4, the power line can further include a second power line 340 located in the peripheral region and surrounding the display region 100, the second power line 340 can be electrically connected with the cathodes of the plurality of sub-pixels Pxij and configured to transmit a second voltage signal to the plurality of sub-pixels Pxij, the second voltage signal can be a low voltage signal, for example, a negative voltage signal. At least one second power pin 350 is further provided in the lead-out region 210, the second power pin 350 extends in a direction away from the display region 100, one end of the second power pin 350 is electrically connected with the second power line 340, and the other end of the second power pin 350 is connected with a corresponding binding pin 231 in the binding region 230 to receive the second power signal.

[0081] As shown in FIG. 4, the first power pin 320 extends to the binding region 230 after passing through the first barrier dam 410 and the second barrier dam 420, at the dashed line region E, the first power pin 320 passes through the first isolation groove F1 and the second isolation groove F2, and the two ends of the first power pin 320 at the dashed line region E are prone to packaging failure in the first direction X. The second power pin 350 is also prone to packaging failure at the corresponding positions where it passes through the first isolation groove F1 and the second isolation groove F2.

[0082] FIG. 5 is a sectional view of the display substrate of FIG. 4 along the direction of B-B in an exemplary embodiment. As shown in FIG. 5, in the direction perpendicular to the display substrate, the display substrate of the display area 100 includes the substrate 10, the driving structure layer 20 disposed on the substrate 10, the display structure layer 30 disposed on the driving structure layer 20, and the encapsulation layer 40 disposed on the display structure layer 30. The driving structure layer 20 of the display area 100 includes a pixel driving circuit, and the display structure layer 30 includes a plurality of light emitting elements in the display area 100, the light emitting elements being connected with the corresponding pixel driving circuits, the light emitting elements being configured to emit light, and the pixel driving circuits being configured to drive the light emitting elements. In the exemplary embodiment, the display unit includes the pixel driving circuit and the corresponding light emitting element, and the pixel driving circuit can include a plurality of thin film transistors (TFT) and a storage capacitor, which are not limited by the present disclosure. The display structure layer 30 includes the first electrode 35, the pixel definition layer 36, the organic light emitting layer 37, and the second electrode 38, the pixel definition layer 36 including a plurality of pixel openings, the pixel openings exposing the first electrode 35, the organic light emitting layer 37 being disposed in the pixel openings, one end of the organic light emitting layer 37 being electrically connected with the first electrode 35, and the other end of the organic light emitting layer 37 being electrically connected with the second electrode 38. In the exemplary embodiment, the first passivation layer 31, the first planarization layer 32, and the transfer layer 33 are sequentially disposed on the driving structure layer 20, the via holes are formed on the first passivation layer 31 and the first planarization layer 32, the via holes on the first passivation layer 31 and the first planarization layer 32 expose the driving transistors in the pixel driving circuit, and the transfer layer 33 is electrically connected with the corresponding driving transistors through the via holes. The second planarization layer 34 is disposed on the transfer layer 33, the via holes are formed on the second planarization layer 34, the via holes on the second planarization layer 34 expose the transfer layer 33, and the first electrode 35 of the light emitting element is electrically connected with the transfer layer 33 through the via holes on the second planarization layer 34, so as to be connected with the corresponding pixel driving circuit. In the exemplary embodiment, the first electrode 35 can be an anode, which is not limited by the present disclosure. The "A and B are disposed in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process when the display panel is prepared.

[0083] In the example embodiment, the display substrate of the lead-out area 210 can include a substrate 10, a driving structure layer 20 disposed on the substrate 10, and a packaging layer 40 disposed on the driving structure layer 20. The first power pin 320 can be disposed in the same layer as the adapter layer 33, and the first barrier dam 410 and the second barrier dam 420 are located on the first power pin 320. The first barrier dam 410 includes a first dam base 411 and a second dam base 412, and the second barrier dam 420 includes a third dam base 421 and a fourth dam base 422. The first dam base 411 and the third dam base 421 can be disposed in the same layer as the second planar layer 34, and the second dam base 412 and the fourth dam base 422 can be disposed in the same layer as the pixel definition layer 36. As shown in FIG. 5, in order to form the first barrier dam 410 and the second barrier dam 420, the first passivation layer 31 and the first planar layer 32 in the area where the first barrier dam 410 and the second barrier dam 420 are located and the surrounding area are removed in the process of forming the first passivation layer 31 and the first planar layer 32. After the second planar layer 34 is formed, the first isolation groove F1 between the first barrier dam 410 and the second barrier dam 420 and the second isolation groove F2 away from the display area 100 side of the second barrier dam 420 will expose the edges of the first power pin 320 and the second power pin 350 in this area, and after the packaging layer 40 is formed later, the display substrate is prone to packaging failure in the edge weak area. For example, there is a weak area (Crack in FIG. 5) on the side of the second barrier dam 420 away from the display area 100,

[0084] In the example embodiment, the packaging layer 40 can adopt a laminated structure of a first packaging layer 41, a second packaging layer 42, and a third packaging layer 43. The first packaging layer 41 adopts an inorganic material, covers the display area 100, and wraps the first barrier dam 410 and the second barrier dam 420 in the lead-out area 210. The second packaging layer 42 adopts an organic material, covers the display area 100, and is located on the side of the first barrier dam 410 close to the display area 100. The third packaging layer 43 adopts an inorganic material, covers the first packaging layer 41 and the second packaging layer 42. The packaging layer 40 can ensure that external moisture cannot enter the light-emitting element. In other embodiments, the packaging layer 40 can also adopt a five-layer laminated structure of inorganic / organic / inorganic / organic / inorganic, and the present disclosure does not limit this.

[0085] Fig. 6 is a structural diagram of the edge of the first power supply line in an exemplary embodiment, showing the edge of the first power supply pin 320 in the first direction X in the area E shown by the dashed line in Fig. 4. As shown in Fig. 6, for the first power supply pin 320 with the Ti / Al / Ti multi-layer composite structure, the edge of the first power supply pin 320 will be eroded by the anode etching solution in the subsequent development of the second planar layer 34, and in the subsequent process of etching the anode. Since the etching solution etches Al at a faster rate than Ti, the eroded edge of the first power supply pin 320 will form a side pit, the Ti layer above the Al layer protruding a distance from the Al layer, forming a "eave" structure. The side pit will be deepened in size in the subsequent development of the pixel definition layer 36, and the material of the pixel definition layer 36 will easily remain in the side pit. In the subsequent process of forming the first encapsulation layer 41 and the third encapsulation layer 43 by chemical vapor deposition (CVD), the "eave" structure will block the vapor deposition particles, so that the side pit cannot be filled with the encapsulation material, forming a hollow 501. Thus, when the first encapsulation layer 41 and the third encapsulation layer 43 crack 502, the moisture from the outside can enter the hollow 501 through the crack 502, causing the moisture to flow through the edge of the first power supply line 310. And since the second planar layer 34 of organic material itself is conductive to moisture, the moisture can spread from the hollow 501 to the second planar layer 34, and spread to the display area 100, causing the display area 100 to be eroded by water and oxygen, resulting in dark spot defects. Figs. 5 and 6 take the first power supply pin 320 as an example for illustration, and the edge of the second power supply pin 350 can also form a "eave" structure, which will not be described here.

[0086] The display substrate provided by the embodiments of the present disclosure includes a substrate, a display area and a peripheral area surrounding the display area, the peripheral area includes a lead-out area on one side of the display area, the lead-out area includes a bending area; a plurality of sub-pixels on one side of the substrate and in the display area; a first barrier dam on the substrate and in the peripheral area and surrounding the display area; a second barrier dam on the substrate and in the peripheral area and surrounding the display area, the second barrier dam is on the side of the first barrier dam away from the display area; at least one isolation groove on the side of the second barrier dam away from or close to the display area; a power line electrically connected to the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels; at least one power pin in the lead-out area and extending away from the display area and electrically connected to the power line; the at least one power pin includes a first part on the first barrier dam close to the display area, a second part between the second barrier dam and the bending area, and a transition electrode at least partially between the first part and the second part, the first part and the second part are in different layers from the transition electrode, and the first part and the second part are electrically connected through the transition electrode.

[0087] The display substrate provided by the embodiments of the present disclosure includes a substrate, a display area and a peripheral area surrounding the display area, the peripheral area includes a lead-out area on one side of the display area, the lead-out area includes a bending area; a plurality of sub-pixels on one side of the substrate and in the display area; a first barrier dam on the substrate and in the peripheral area and surrounding the display area; a second barrier dam on the substrate and in the peripheral area and surrounding the display area, the second barrier dam is on the side of the first barrier dam away from the display area; at least one isolation groove on the side of the second barrier dam away from or close to the display area; a power line electrically connected to the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels; at least one power pin in the lead-out area and extending away from the display area and electrically connected to the power line; the at least one power pin includes a first part on the first barrier dam close to the display area, a second part between the second barrier dam and the bending area, and a transition electrode at least partially between the first part and the second part, the first part and the second part are in different layers from the transition electrode, and the first part and the second part are electrically connected through the transition electrode.

[0088] Figure 7 is a cross-sectional view of the display substrate of Figure 4 along the B-B direction in another exemplary embodiment. The difference between Figure 7 and Figure 5 is that the structure of the power line is different, and the remaining structures can be referred to the description of Figure 5 above, which will not be described here again.

[0089] As shown in FIG. 7, the first power pin 320 of the lead-out area 210 includes a first portion 81 located near the first blocking dam 410 of the display area 100, a second portion 82 located between the second blocking dam 420 and the bending area 220, and a transfer electrode 91 located at least partially between the first portion 81 and the second portion 82, the first portion 81 and the second portion 82 are located in different layers from the transfer electrode 91, and the first portion 81 and the second portion 82 are electrically connected through the transfer electrode 91. The first portion 81 and the second portion 82 are arranged in the same layer as the transfer layer 33, and the transfer electrode 91 is arranged in the same layer as the first electrode 35, which is an anode of the light-emitting element. The first portion 81 is connected to the transfer electrode 91 through a first via K1, and the second portion 82 is connected to the transfer electrode 91 through a second via K2.

[0090] In an example embodiment, the first portion 81 and the second portion 82 are respectively located in the range of the orthogonal projection of the second planar layer 34 on the substrate 10, and the first via K1 and the second via K2 are located in the second planar layer 34. The transfer electrode 91 passes between the first dam base 411 and the second dam base 412, and the transfer electrode 91 passes between the third dam base 421 and the fourth dam base 422.

[0091] In an example embodiment, the thickness of the transfer electrode 91 can be greater than or equal to 90 nanometers (nm) and less than or equal to 110 nm, for example, the thickness of the transfer electrode 91 can be about 100 nm. The thickness of the transfer electrode 91 can be the distance between the surface of the transfer electrode 91 close to the substrate 10 side and the surface of the transfer electrode 91 away from the substrate 10 side in the direction perpendicular to the substrate 10. The thickness of the transfer electrode 91 can be set as needed, and the present disclosure does not limit this.

[0092] In the present embodiment, the first portion 81 and the second portion 82 are covered by the second planar layer 34, and there is no power pin wiring under the first blocking dam 410 and the second blocking dam 420. The end face shape of the power pin will not be affected in the process of forming the second planar layer 34, the first electrode 35 and the pixel definition layer 36. The transfer electrode 91 is arranged in the same layer as the first electrode 35, and the number of times of wet etching and developing in the subsequent process is less, and the "eaves" structure is not formed, which will not affect the film forming morphology of the subsequent packaging layer, and the GDS defect of the display substrate can be avoided.

[0093] FIG. 8 is a cross-sectional view of the display substrate of FIG. 4 along the B-B direction in another example embodiment. The difference between FIG. 8 and FIG. 7 is that the display substrate further includes an isolation column layer 39, and the film layer position of the transfer electrode 91 is different, and the remaining structures can be referred to the foregoing description of FIG. 7, which will not be described here.

[0094] As shown in FIG. 8, the display substrate further comprises a spacer layer 39 on the side of the pixel definition layer 36 away from the substrate 10, and the transfer electrode 91 is arranged in the same layer as the spacer layer 39, and the transfer electrode 91 is on the side of the first barrier dam 410 and the second barrier dam 420 away from the substrate 10.

[0095] In an example embodiment, the material of the spacer layer 39 can be a metal material, and the material of the pixel definition layer 36 can be an inorganic material. The inorganic material of the pixel definition layer 36 helps to avoid crosstalk between different color light emitting elements and improve display effect.

[0096] In an example embodiment, the thickness of the transfer electrode 91 can be greater than or equal to 450 nm and less than or equal to 550 nm, for example, the thickness of the transfer electrode 91 can be about 500 nm. The thickness of the transfer electrode 91 can be set as needed, and the present disclosure does not limit this.

[0097] In an example embodiment, the light emitting element can be formed by using a photolithography OLED (AP technology) method, that is, using a spacer to perform a patterning process by a photolithography process to form light emitting elements of different colors. As shown in FIG. 8, taking a display substrate comprising red, green and blue light emitting elements as an example, after forming the spacer layer, a red organic light emitting layer can be first evaporated in the pixel opening, and a cathode and a first encapsulation layer are deposited to form a red light emitting element; then, the red organic light emitting layer, the cathode and the first encapsulation layer in the pixel opening of the green light emitting element and the blue light emitting element are removed by a photolithography process, a green organic light emitting layer is evaporated, and a cathode and a first encapsulation layer are deposited to form a green light emitting element; then, the green organic light emitting layer, the cathode and the first encapsulation layer in the pixel opening of the blue light emitting element are removed by a photolithography process, a blue organic light emitting layer is evaporated, and a cathode and a first encapsulation layer are deposited to form a blue light emitting element, and finally a second encapsulation layer 42 and a third encapsulation layer 43 are deposited.

[0098] In the present embodiment, the first part 81 and the second part 82 are covered by the second planar layer 34, and there is no wiring of the power supply pin under the first barrier dam 410 and the second barrier dam 420, so that the end face shape of the power supply pin is not affected in the process of forming the second planar layer 34, the first electrode 35 and the pixel definition layer 36. The transfer electrode 91 is on the side of the pixel definition layer 36 away from the substrate 10, and the transfer electrode 91 undergoes fewer times of wet etching and developing in subsequent processes, so that a “eave” structure is not formed, the film forming morphology of the subsequent encapsulation layer is not affected, and GDS defects of the display substrate can be avoided.

[0099] FIG. 9 is a sectional view of the display substrate of FIG. 4 along the direction of B-B in another exemplary embodiment. The difference between FIG. 9 and FIG. 8 is that the display substrate further comprises an auxiliary transfer electrode 83, and the rest of the structure can be referred to the foregoing description of FIG. 8, which will not be repeated here.

[0100] As shown in FIG. 9, the auxiliary transfer electrode 83 is arranged in the same layer as the first part 81 and the second part 82, and is arranged to connect the first part 81 and the second part 82. In the embodiment, the auxiliary transfer electrode 83 is equivalent to adding a connection path between the first part 81 and the second part 82, which helps to improve the connection reliability of the power pin and reduce the voltage drop of the power line. Although the auxiliary transfer electrode 83 is located below the first barrier dam 410 and the second barrier dam 420, since the transfer electrode 91 is electrically connected with the auxiliary transfer electrode 83, the voltage drop of the power pin and the power line can be reduced under the premise of ensuring the packaging effect, and the display effect of the display substrate is improved.

[0101] In the exemplary implementation, the normal projection of the pixel definition layer 36 on the substrate substrate 10 covers the normal projection of the auxiliary transfer electrode 83 on the substrate substrate 10. The material of the pixel definition layer 36 can be an inorganic material. The pixel definition layer 36 of the inorganic material can form a protective layer above the auxiliary transfer electrode 83 to avoid the auxiliary transfer electrode 83 from being eroded in the subsequent process, and cooperate with the transfer electrode 91 to help avoid affecting the film formation morphology of the packaging layer 40 in the subsequent process.

[0102] FIG. 10 is a sectional view of the display substrate of FIG. 4 along the direction of B-B in another exemplary embodiment. The difference between FIG. 10 and FIG. 9 is that the display substrate further comprises a touch layer, and the film layer position of the transfer electrode 91 and the connection mode between the transfer electrode 91 and the first part 81 and the second part 82 are different, and the rest of the content can be referred to the foregoing description of FIG. 9, which will not be repeated here.

[0103] As shown in FIG. 10, the display substrate further comprises a touch layer arranged on the side of the packaging layer 40 away from the substrate substrate 10, forming a structure of touch on thin film encapsulation (Touch on TFE). By integrating the touch layer on the display panel, the display panel does not need to be externally connected with a touch module (TSP), and has the advantages of thinness, foldability, etc., and can meet the product requirements of flexible folding, narrow frame, etc. In the exemplary implementation, the touch layer can comprise a first wiring layer (TMA) 51, a touch layer interlayer insulation layer (TLD) 52, a second wiring layer (TMB) 53, and a touch protection layer (TOC) 54. A plurality of touch electrodes and a plurality of sensing electrodes can be located in the first wiring layer 51 and the second wiring layer 53, and the present disclosure does not limit this.

[0104] In the example embodiment, the transfer electrode 91 can be arranged in the same layer as the first wiring layer 51, the orthogonal projection of the transfer electrode 91 on the substrate 10 can at least partially overlap the second portion 82 and the auxiliary transfer electrode 83, and the orthogonal projection of the transfer electrode 91 on the substrate 10 can not overlap the first portion 81. The transfer electrode 91 can be connected to the second portion 82 through a second via hole K2, and the second via hole K2 can expose the surface of the second portion 82 after penetrating through the encapsulation layer 40, the pixel definition layer 36, and the second planarization layer 34. The transfer electrode 91 can be connected to the auxiliary transfer electrode 83 through a third via hole K3, and the third via hole K3 can expose the surface of the auxiliary transfer electrode 83 after penetrating through the encapsulation layer 40 and the pixel definition layer 36. In the present embodiment, the transfer electrode 91 covers the weak area on the side of the second barrier dam 420 away from the display area 100, which can effectively protect the weak area and avoid encapsulation failure.

[0105] In the example embodiment, the orthogonal projection of the transfer electrode 91 on the substrate 10 can also overlap the first portion 81, and the transfer electrode 91 can be connected to the first portion 81 through a first via hole (not shown in the figure), which is not limited in the present disclosure.

[0106] In the example embodiment, the thickness of the transfer electrode 91 can be greater than or equal to 225 nm and less than or equal to 275 nm, for example, the thickness of the transfer electrode 91 can be about 250 nm. The thickness of the transfer electrode 91 can be set as needed, which is not limited in the present disclosure.

[0107] FIG. 11 is a cross-sectional view of the display substrate of FIG. 4 along the direction B-B in another example embodiment. The difference between FIG. 11 and FIG. 7 is that the position of the transfer electrode 91 is different, and the pixel definition layer 36 can form a protective layer on the first portion 81 and the second portion 82. The remaining contents can be referred to the description of FIG. 9, and will not be repeated here.

[0108] In the example embodiment, the transfer electrode 91 can be located on the side of the first portion 81 and the second portion 82 close to the substrate 10, for example, the transfer electrode 91 can be located on the driving structure layer 20. FIG. 11 is a schematic diagram of an example in which each sub-pixel includes one thin film transistor and one capacitor. In some examples, the driving structure layer 20 of the display area 100 can include a semiconductor layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer disposed on the substrate 10. A first gate insulating layer 11 can be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer 12 can be disposed between the first gate metal layer and the second gate metal layer, and an interlayer insulating layer 13 can be disposed between the second gate metal layer and the first source-drain metal layer. The first source-drain metal layer and the transfer layer 33 are connected through the via disposed on the first passivation layer 31 and the first planarization layer 32. The first gate insulating layer 11, the second gate insulating layer 12, and the interlayer insulating layer 13 can be inorganic insulating layers. However, the present embodiment is not limited thereto. In other examples, a buffer layer can be further disposed on the side of the semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from entering the inside of the display panel, and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal (BSM) layer can be disposed on the side of the buffer layer close to the substrate. The BSM layer can be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit, so as to avoid the influence of external light on the performance of the thin film transistor. In other examples, a second source-drain metal layer can be disposed between the first source-drain metal layer and the transfer layer 33, and the transfer layer 33 is connected through the second source-drain metal layer, the first source-drain metal layer, and the transistor.

[0109] As shown in FIG. 11, the capacitor can include oppositely disposed first and second plates, the first plate can be located on the first gate metal layer, and the second plate can be located on the second gate metal layer. The transfer electrode 91 can be disposed in the same layer as any one of the first gate metal layer and the second gate metal layer, or the transfer electrode 91 can include a stacked structure disposed in the same layer as the first gate metal layer and the second gate metal layer. Generally, the materials of the first gate metal layer and the second gate metal layer are different from the materials of the source-drain metal layer and the transfer layer 33, and are not a Ti / Al / Ti multi-layer composite structure. Therefore, by disposing the transfer electrode 91 in the same layer as at least any one of the first gate metal layer and the second gate metal layer, even if the transfer electrode 91 undergoes subsequent etching and developing processes, an "eave" structure will not be generated at the edge, which will not affect the film formation morphology of the subsequent encapsulation layer, and GDS defects of the display substrate can be avoided.

[0110] FIG. 12 is a cross-sectional view of a display substrate of a display area in an example embodiment. In some examples, as shown in FIG. 12, in a direction perpendicular to the display substrate, the display area of the display substrate can include the substrate 10, and the driving structure layer 20, the light-emitting structure layer 30, the encapsulation structure layer 40, and the touch layer 50 disposed on the substrate in sequence. In FIG. 12, a first transistor 21, a second transistor 22, and a capacitor 23 included in each sub-pixel are taken as an example for illustration. The transistor types of the first transistor 21 and the second transistor 22 can be different. Among them, the first transistor 21 can be a low-temperature polysilicon thin-film transistor, and the second transistor 22 can be an oxide thin-film transistor.

[0111] In some examples, the driving structure layer 20 of the display area can include a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a transfer layer disposed on the substrate 10. A first gate insulating (GI) layer 101 can be disposed between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 102 can be disposed between the first gate metal layer and the second gate metal layer; a first interlayer insulating (ILD) layer 103 and a first buffer layer 104 can be disposed between the second gate metal layer and the second semiconductor layer, and the first buffer layer 104 can be located on a side of the first interlayer insulating layer 103 away from the substrate 10; a third gate insulating layer 105 can be disposed between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 106 can be disposed between the third gate metal layer and the first source-drain metal layer; a passivation (PVX) layer 31 and a first planar (PLN) layer 32 can be disposed between the first source-drain metal layer and the transfer layer 33, and the first planar layer 32 can be located on a side of the passivation layer 31 away from the substrate 10; a second planar layer 34 can be disposed on a side of the transfer layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the first interlayer insulating layer 103, the first buffer layer 104, the third gate insulating layer 105, the transfer layer 33, and the passivation layer 31 can be inorganic insulating layers, and the first planar layer 32 and the second planar layer 34 can be organic insulating layers. However, the present embodiment is not limited thereto. In other examples, a second buffer layer can also be disposed on a side of the first semiconductor layer close to the substrate 10, which can prevent harmful substances in the substrate from invading the inside of the display substrate, and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom light shielding metal layer can also be disposed on a side of the second buffer layer close to the substrate. In other examples, the passivation layer can be omitted between the first source-drain metal layer and the transfer layer, and only the first planar layer can be disposed between the first source-drain metal layer and the transfer layer. In other examples, the first buffer layer can be omitted between the second gate metal layer and the second semiconductor layer, and only the first interlayer insulating layer 103 can be disposed.

[0112] In some examples, as shown in FIG. 12, the first semiconductor layer of the display area can at least include: the first active layer 2100 of the first transistor 21. The first active layer 2100 of the first transistor 21 can include: a first region 2101, a second region 2102, and a channel region 2103 between the first region 2101 and the second region 2102. The first gate metal layer can at least include: the first gate 213 of the first transistor 21, and the first plate 2310 of the capacitor 23. The first gate 213 of the first transistor 21 can cover the channel region 2103 of the first active layer 2100 in the orthographic projection of the substrate 10. The second gate metal layer can at least include: the second plate 2320 of the capacitor 23, and the third gate 2240 of the second transistor 22. The second plate 2320 and the first plate 2310 of the capacitor 23 can at least partially overlap in the orthographic projection of the substrate 10, for example, the two can coincide. The second semiconductor layer can at least include: the second active layer 2200 of the second transistor 22. The third gate metal layer can at least include: the second gate 2230 of the second transistor 22. The second gate 2230 of the second transistor 22 can partially overlap with the second active layer 2200 in the orthographic projection of the substrate 10. The third gate 2240 of the second transistor 22 can partially overlap with the second active layer 2200 in the orthographic projection of the substrate 10. The third gate 2240 can be a bottom gate of the second transistor 22, and the second gate 2230 can be a top gate of the second transistor 22.

[0113] In some examples, as shown in FIG. 12, the first source-drain metal layer can at least include: the first source 211 and the first drain 212 of the first transistor 21, the second source 2210 and the second drain 2220 of the second transistor 22. The second interlayer insulating layer 106 can be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via and a fourth pixel via) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via can be removed to expose at least part of the surface of the first region 2101 of the first active layer 2100; the second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via can be removed to expose at least part of the surface of the second region 2102 of the first active layer 2100. The second interlayer insulating layer 106 and the third gate insulating layer 105 in the third pixel via and the fourth pixel via can be removed to expose at least part of the surface of both ends of the second active layer 2200. The first source 211 of the first transistor 21 can be electrically connected to the first region 2101 of the first active layer 2100 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 2100 through the second pixel via. The second source 2210 of the second transistor 22 can be electrically connected to one end of the second active layer 2200 through the third pixel via, and the second drain 2220 of the second transistor 22 can be electrically connected to the other end of the second active layer 2200 through the fourth pixel via. The transfer layer 33 can be electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through the fifth pixel via provided by the passivation layer 31 and the first planarization layer 32. The present example can realize the electrical connection between the pixel circuit and the light emitting element through the transfer layer 33.

[0114] In some examples, the touch layer 50 of the display area can further include a touch buffer layer (TBL) 150 disposed on the side of the first wiring layer 51 close to the substrate 10. The touch buffer layer 150 and the touch interlayer insulating layer 53 can be inorganic insulating layers, and the protective layer 54 can be an organic insulating layer. The present embodiment is not limited in this regard.

[0115] In some examples, the transfer electrode 91 can be disposed in the same layer as any one of the first gate metal layer, the second gate metal layer and the third gate metal layer, or the transfer electrode 91 can include a stacked structure disposed in the same layer as at least two of the first gate metal layer, the second gate metal layer and the third gate metal layer. The present embodiment is not limited in this regard. In the exemplary embodiments, the structures of the display substrate in FIGS. 7-12 can be arbitrarily combined with each other, and the present disclosure is not limited in this regard.

[0116] The display device can be an OLED display, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present disclosure are not limited thereto.

[0117] Although the embodiments of the present disclosure have been shown and described above, it should be understood by those skilled in the art that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A display substrate, comprising: a substrate substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a lead-out area located at one side of the display area, the lead-out area comprising a bending area; a plurality of sub-pixels located at one side of the substrate substrate and located in the display area; a first barrier dam located on the substrate substrate and located in the peripheral area and surrounding the display area; a second barrier dam located on the substrate substrate and located in the peripheral area and surrounding the display area, the second barrier dam being located at one side of the first barrier dam away from the display area; at least one isolation groove located at one side of the second barrier dam away from or close to the display area; a power supply line electrically connected with the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels; at least one power supply pin located in the lead-out area and extending in a direction away from the display area and electrically connected with the power supply line; the at least one power supply pin comprising a first portion located at the first barrier dam close to the display area, a second portion located between the second barrier dam and the bending area, and a transfer electrode located at least partially between the first portion and the second portion, the first portion and the second portion being located in different layers from the transfer electrode, and the first portion and the second portion being electrically connected through the transfer electrode. 2.The display substrate of claim 1, wherein, In a direction away from the substrate substrate, the display substrate comprises, in sequence, a driving structure layer, a transfer layer, a planarization layer, and a display structure layer; the driving structure layer comprises a pixel driving circuit, the display structure layer comprises a first electrode, a pixel definition layer, an organic light-emitting layer, and a second electrode, the pixel definition layer comprises a plurality of pixel openings, the pixel openings expose the first electrode, the organic light-emitting layer is arranged in the pixel openings, one end of the organic light-emitting layer is electrically connected with the first electrode, and the other end of the organic light-emitting layer is electrically connected with the second electrode; the anode is electrically connected with the pixel driving circuit through the transfer electrode. 3.The display substrate of claim 2, wherein, the transfer electrode is arranged in the same layer as the anode; the first portion and the second portion are electrically connected through the transfer electrode, the transfer electrode is electrically connected with the first portion through a first via, the transfer electrode is electrically connected with the second portion through a second via, and the first via and the second via penetrate the planarization layer; a projection of the transfer electrode on the substrate substrate overlaps a projection of the first barrier dam on the substrate substrate, a projection of the second barrier dam on the substrate substrate, and a projection of the at least one isolation groove on the substrate substrate, and the at least one isolation groove penetrates the planarization layer. 4.The display substrate of claim 2, wherein, the display substrate further comprises an isolation column layer located at one side of the pixel definition layer away from the substrate substrate, and the transfer electrode is arranged in the same layer as the isolation column layer; The first part and the second part are electrically connected through the transfer electrode, including that the transfer electrode is electrically connected with the first part through a first via hole, and the transfer electrode is electrically connected with the second part through a second via hole, and the first via hole and the second via hole penetrate the pixel definition layer and the flat layer; The transfer electrode is overlapped with the at least one isolation groove in the orthographic projection of the substrate in the orthographic projection of the substrate, the orthographic projection of the second barrier dam and the orthographic projection of the substrate. 5.The display substrate of claim 2, wherein, Further comprising a touch layer arranged above the display structure layer, the touch layer comprising a first wiring layer, and the transfer electrode is arranged in the same layer as the first wiring layer. 6.The display substrate of claim 2, wherein, The driving structure layer comprises a first gate metal layer and a second gate metal layer arranged in sequence away from the substrate; the transfer electrode is arranged in the same layer as any one of the first gate metal layer and the second gate metal layer, or the transfer electrode comprises a laminated structure arranged in the same layer as the first gate metal layer and the second gate metal layer. 7.The display substrate of claim 6, wherein, The driving structure layer further comprises a third gate metal layer arranged above the second gate metal layer; the transfer electrode is arranged in the same layer as any one of the first gate metal layer, the second gate metal layer and the third gate metal layer, or the transfer electrode comprises a laminated structure arranged in the same layer as at least two of the first gate metal layer, the second gate metal layer and the third gate metal layer. 8.The display substrate according to any one of claims 2-7, wherein, The material of the pixel definition layer comprises inorganic material. 9.The display substrate of claim 1, wherein, The transfer electrode is partially overlapped with the at least one isolation groove in the orthographic projection of the substrate; the at least one isolation groove comprises a first isolation groove and a second isolation groove, and in the plane of the substrate, the first isolation groove is located between the first barrier dam and the second barrier dam, and the second isolation groove is located between the second barrier dam and the bending area. 10.The display substrate of claim 9, wherein, The first isolation groove surrounds the display area, or the first isolation groove is located on one side of the display area close to the bending area; the second isolation groove surrounds the display area, or the second isolation groove is located on one side of the display area close to the bending area. 11.The display substrate of claim 1, wherein, The power supply pin further comprises an auxiliary transfer electrode, the auxiliary transfer electrode is arranged in the same layer as the first part and the second part, and the auxiliary transfer electrode is connected with each other. 12.The display substrate of claim 11, wherein, The first part and the second part are electrically connected through the transfer electrode, including that at least one of the first part and the second part is connected with the transfer electrode through a via hole, and the transfer electrode is connected with the auxiliary transfer electrode through a via hole. 13.The display substrate of claim 1, wherein, The lead-out line area further comprises an integrated circuit area located on a side of the bending area away from the display area; the power lines comprise a plurality of first power lines and a first power bus, the plurality of first power lines are located in the display area and electrically connected with the plurality of sub-pixels and configured to transmit a first voltage signal to the plurality of sub-pixels; the first power bus is located in the lead-out line area and between the bending area and the display area, the first power bus extends along a first direction and is electrically connected with the plurality of first power lines; The at least one power pin comprises two first power pins, the two first power pins are located on two sides of the integrated circuit area along the first direction. 14.The display substrate of claim 13, wherein, The power lines further comprise a second power line located in the peripheral area and surrounding the display area, the at least one power pin comprises two second power pins, the two second power pins are located on two sides of the two first power pins along the first direction. 15.The display substrate of claim 14, wherein, The peripheral area further comprises a binding area located on a side of the lead-out line area away from the display area, the binding area comprises a plurality of binding pads; the first power pin and the second power pin are connected with different binding pads. 16.The display substrate of claim 2, wherein, The first barrier dam comprises a first dam base and a second dam base, the second barrier dam comprises a third dam base and a fourth dam base, the first dam base, the third dam base and the planar layer are arranged in the same layer, and the second dam base, the fourth dam base and the pixel definition layer are arranged in the same layer.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

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