High-electron-mobility transistor and preparation method therefor, chip, and electronic device

Abstract

Embodiments of the present application provide a high-electron-mobility transistor and a preparation method thereof, a chip, and an electronic device. The high-electron-mobility transistor is disposed on a substrate. The transistor comprises a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer, and a gate metal, wherein the barrier layer is located above the channel layer; the gate is located above the barrier layer; the first passivation layer is located above the barrier layer and is in contact with the gate; the second passivation layer is located above the first passivation layer; the gate metal is located on the gate and is in contact with the gate; and a first opening is formed in the second passivation layer, the first opening is formed in at least one side of the gate metal or surrounds the gate metal, the interior of the first opening is filled with a first insulating medium, and the first insulating medium is in contact with the first passivation layer. By implementing the embodiments of the present application, the reliability of the high-electron-mobility transistor can be improved while good conduction performance of the high-electron-mobility transistor is maintained.

Description

High electron mobility transistor and preparation method thereof, chip and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411370491.9, filed on September 29, 2024, with the State Intellectual Property Office of China, and entitled "High electron mobility transistor and preparation method thereof, chip and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor, in particular to a high electron mobility transistor and preparation method thereof, chip and electronic device. BACKGROUND

[0003] The current high electron mobility transistor (HEMT) of gallium nitride (GaN) mainly uses GAN as the basic material, forms a conductive channel by using the heterojunction structure of GAN, and is made into a voltage modulation type device by combining subsequent passivation and interconnection processes. The passivation layer of the GaN HEMT device can protect the surface of the epitaxial layer and improve the conduction characteristics of the device.

[0004] Moreover, the channel electrons of the GaN HEMT device are generated by spontaneous polarization and piezoelectric polarization. Therefore, the design and growth conditions of the passivation layer will affect the channel electron concentration of the device, thereby affecting the conduction and leakage of the device. Moreover, due to the introduction of the high dielectric constant passivation layer, the overall electron concentration of the device is often increased, resulting in a high electron concentration near the gate, which is easy to cause gate leakage and affect the dynamic conduction performance of the device.

[0005] Therefore, how to provide a HEMT with good performance and high reliability is a technical problem to be solved. SUMMARY

[0006] The present application provides a high electron mobility transistor and preparation method thereof, chip and electronic device, which can improve the reliability of the high electron mobility transistor while maintaining its good conduction performance.

[0007] In a first aspect, the embodiments of the present application provide a high electron mobility transistor, which is characterized in that the transistor is arranged on a substrate, and the transistor comprises a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer and a gate metal; wherein the barrier layer is located above the channel layer; the gate is located above the barrier layer; the first passivation layer is located above the barrier layer and in contact with the gate; the second passivation layer is located on the first passivation layer; and the gate metal is located above the gate and in contact with the gate; wherein a first opening is arranged on the second passivation layer, the first opening is arranged on at least one side of the gate metal or surrounds the gate metal, and the first opening is filled with a first insulating medium, and the first insulating medium is in contact with the first passivation layer.

[0008] In the prior art, in order to reduce the surface trap state of the device, a passivation layer with high dielectric constant is usually introduced. However, the passivation layer with high dielectric constant tends to increase the overall electron concentration of the device, resulting in a high electron concentration near the gate, which is easy to cause gate leakage. Moreover, with the increase of the overall electron concentration of the device, the dynamic on performance of the device is further affected. To this end, the embodiments of the present application provide a high electron mobility transistor, which comprises two passivation layers (i.e., a first passivation layer and a second passivation layer), wherein the high electron mobility transistor is patterned with the second passivation layer, that is, the second passivation layer located near the gate metal (such as on one side of the gate metal or surrounding the gate metal) is etched to form an opening, the second passivation layer in other regions is retained, and an insulating medium is filled in the opening, so that the electron concentration at the opening (i.e., near the gate metal) is significantly lower than the electron concentration in other regions, thereby reducing the gate leakage phenomenon and greatly improving the reliability of the device. Moreover, by patterning only the second passivation layer to reduce the electron concentration near the gate metal, the remaining first passivation layer can still improve the surface trap state of the device, thereby maintaining good dynamic on performance when the transistor is continuously turned on and off (dynamic on).

[0009] In a possible implementation manner, the transistor further comprises a source, a drain and a field plate; wherein the source and the drain are located above the barrier layer and are respectively located on two sides of the first passivation layer; and the field plate is arranged on a side of the second passivation layer away from the substrate or a side of the second passivation layer close to the substrate, and a projection of the field plate on the substrate is located between a projection of the gate metal on the substrate and a projection of the drain on the substrate.

[0010] In the embodiments of the present application, the field plate in the HEMT device can regulate the electric field, so that the electric field distribution curve between the source and the drain is flat, thereby reducing the premature breakdown of the gate near the drain end and improving the performance of the device.

[0011] In a possible implementation, a projection of the first opening on the substrate is located between a projection of the source on the substrate and a projection of the field plate on the substrate.

[0012] In the embodiments of the present application, the first opening can be located between the source and the field plate, i.e., in the region near the gate metal, so as to avoid the decrease of the electron concentration at the opening when the opening is arranged in other regions, and to affect the dynamic conduction performance of the device.

[0013] In a possible implementation, a projection of the first opening on the substrate overlaps with a projection of the field plate on the substrate.

[0014] In the embodiments of the present application, a part of the first opening can be opened to the lower side of the field plate, and the field plate can be arranged in a stepped type, so as to better control the electric field, to make the electric field distribution curve between the source and the drain flat, and to improve the breakdown voltage, so as to improve the performance of the device.

[0015] In a possible implementation, the first insulating medium is in contact with the gate metal.

[0016] In the embodiments of the present application, the first opening is arranged close to the gate metal, and this arrangement can further realize that the channel electron concentration in the region around the gate metal is lower than that of the whole device, so as to reduce the gate leakage phenomenon, to increase the dynamic conduction performance, and to improve the reliability of the device.

[0017] In a possible implementation, the field plate is arranged on the side of the second passivation layer away from the substrate, and the field plate comprises a first part and a second part connected to each other; the first part is arranged on the side of the first opening away from the gate metal, and is in contact with the second passivation layer and the first passivation layer respectively; and the second part is arranged on the first part and is in contact with the second passivation layer.

[0018] In the embodiments of the present application, the first part and the second part connected to each other in the field plate can form a stepped field plate structure, to realize the effect of the stepped field plate, to further improve the breakdown voltage, to avoid the breakdown phenomenon, and to better control the electric field.

[0019] In a possible implementation, along the direction parallel to the substrate, the width of the first part is smaller than the width of the second part.

[0020] In the embodiments of the present application, in order to ensure a good electric field modulation effect and to avoid a significant reduction in the frequency of the device, the width of the first part in the field plate located in the region inside the first opening needs to be smaller than the width of the second part located on the second passivation layer, so as to make the electric field distribution curve flat and to effectively overcome the electric field concentration effect.

[0021] In a possible implementation, the first opening is arranged at one side of the gate metal, and a second opening is further arranged on the second passivation layer, the second opening is arranged at the other side of the gate metal, and the second opening is filled with a second insulating medium, and the second insulating medium is in contact with the first passivation layer.

[0022] In the embodiment of the present application, the gate metal is arranged with openings at both sides, that is, the first opening is arranged at one side, and the second opening is arranged at the other side. That is, the second passivation layer at both sides of the gate metal is etched and filled with an insulating medium, which can further reduce the electron concentration near the gate and reduce the gate leakage phenomenon.

[0023] In a possible implementation, the dielectric constant of the first passivation layer is less than the dielectric constant of the second passivation layer, or the refractive index of the first passivation layer is less than the refractive index of the second passivation layer.

[0024] In the embodiment of the present application, the second passivation layer with high dielectric constant or high refractive index is arranged above the first passivation layer, which can well reduce the influence on the threshold voltage of the gate level, improve the passivation effect, and thus inhibit the current collapse. Moreover, the second passivation layer with high dielectric constant etched away can reduce the gate leakage phenomenon and improve the reliability and dynamic conduction performance of the device.

[0025] In a possible implementation, the first passivation layer includes a plurality of third passivation layers arranged in a stack, and the plurality of third passivation layers are of the same material or different materials.

[0026] In the embodiment of the present application, the first passivation layer can be a stacked structure, for example, the third passivation layer close to the gate in the first passivation layer is a thin layer with high dielectric constant, and the third passivation layer away from the gate is a thick layer with low dielectric constant. This arrangement can further reduce the interface state density and improve the passivation effect, thereby inhibiting the current collapse.

[0027] In a second aspect, the embodiment of the present application provides a preparation method of a high electron mobility transistor, and the method is characterized in that the method comprises the following steps: preparing a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer, and a gate metal on a substrate; the barrier layer is located above the channel layer; the gate is located above the barrier layer; the first passivation layer is located above the barrier layer and in contact with the gate; the second passivation layer is located on the first passivation layer; the gate metal is located above the gate and in contact with the gate; etching a first opening on the surface of the second passivation layer, the first opening is arranged at one side of the gate metal or arranged around the gate metal; and filling a first insulating medium in the first opening, and the first insulating medium is in contact with the first passivation layer.

[0028] In a possible implementation mode, the first opening is arranged at one side of the gate metal, the second passivation layer is further provided with a second opening away from one side of the substrate, and the second opening is arranged at the other side of the gate metal; the method further comprises: etching the surface of the second passivation layer to form the second opening; and filling a second insulating medium in the second opening, and the second insulating medium is in contact with the first passivation layer.

[0029] In a third aspect, the embodiments of the present application provide a chip, characterized in that comprising a circuit and a high electron mobility transistor provided in the first aspect applied to the circuit.

[0030] In a fourth aspect, the embodiments of the present application provide an electronic device, characterized in that comprising a circuit board and a high electron mobility transistor provided in the first aspect, and the circuit board is electrically connected with the high electron mobility transistor.

[0031] It should be understood that the preparation method of the high electron mobility transistor provided in the second aspect of the present application, the chip provided in the third aspect and the electronic device provided in the fourth aspect are consistent with the technical solution of the first aspect of the present application, and the specific contents and beneficial effects can be referred to the high electron mobility transistor provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings needed to be used in the embodiments of the present application or the background art will be described below.

[0033] FIG. 1 is a structural schematic diagram of a HEMT provided by an embodiment of the present application.

[0034] FIGS. 2 and 3 are structural schematic diagrams of a group of HEMT devices provided by an embodiment of the present application.

[0035] FIGS. 4 and 5 are structural schematic diagrams of another group of HEMT devices provided by an embodiment of the present application.

[0036] FIG. 6 is a structural schematic diagram of a HEMT device provided by an embodiment of the present application.

[0037] FIG. 7 is a structural schematic diagram of another HEMT device provided by an embodiment of the present application.

[0038] FIG. 8 is a structural schematic diagram of still another HEMT device provided by an embodiment of the present application.

[0039] FIG. 9 is a structural schematic diagram of still another HEMT device provided by an embodiment of the present application.

[0040] FIG. 10 and FIG. 11 are structural schematic diagrams of another group of HEMT devices provided by the embodiments of the present application.

[0041] FIG. 12 is a flow schematic diagram of a process for preparing a high electron mobility transistor provided by the embodiments of the present application.

[0042] FIG. 13-FIG. 20 are cross-sectional schematic diagrams of a group of processes for preparing a high electron mobility transistor provided by the embodiments of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0044] The terms "first" and "second" and the like in the description and claims of the present application and the accompanying drawings are used to distinguish between similar objects, and are not necessarily used to describe a particular sequential order. Also, the terms "include" and "have" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device that includes a list of steps or units is not limited to the listed steps or units, but can optionally further include other steps or units not listed or can optionally further include other steps or units inherent to such process, method, product or device.

[0045] It should be understood that in the present application, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or", used to describe the association between the associated objects, means that there can be three relationships, for example, "A and / or B" can mean that there are three cases: only A, only B, and A and B at the same time, where A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one of the following" or the like means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0046] For convenience of description, the embodiments of the present application can use spatial relation words such as "under", "below", "lower than", "underneath", "above", "upper" and the like to describe the relationship of one element or feature with other elements or features shown in the drawings. It will be understood that these spatial relation words are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. For example, if the device in the drawings is turned over, the direction of the element described as "below" or "under" or "underneath" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary words "below" and "under" can include both directions of up and down. The device can also have other orientations (rotated 90 degrees or in other directions), and the spatial relation description words used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers.

[0047] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. It will be explicitly understood that the embodiments described herein can be combined with other embodiments in various ways.

[0048] First, in order to facilitate the understanding of the embodiments of the present application, the technical problems to be solved by the embodiments of the present application and the applicable application scenarios are specifically analyzed as follows.

[0049] The current gallium nitride (GaN) high electron mobility transistor (HEMT) mainly uses GaN as a basic material, forms a conductive channel by using a GaN heterojunction structure, and is manufactured into a voltage modulation type device by combining subsequent passivation and interconnection processes. The passivation layer of the GaN HEMT device can protect the surface of the epitaxial layer and improve the turn-on characteristics of the device.

[0050] Referring to FIG. 1, FIG. 1 is a structural schematic diagram of a HEMT provided by an embodiment of the present application. As shown in FIG. 1, the current HEMT generally includes a substrate, a gallium nitride (GaN) layer, an AlGaN layer, a P-type GaN layer, a gate, and a passivation layer, wherein the passivation layer covers the P-type GaN layer and the gate. The passivation layer can include a high dielectric constant material, such as silicon dioxide or silicon nitride. The material and growth conditions of the high dielectric constant passivation layer can increase the electron concentration of the whole device, thereby affecting the turn-on and leakage conditions of the device.

[0051] The passivation layer structure of the current HEMT device also specifically protects the gate region, such as a thicker passivation layer near the gate to increase the two-dimensional electron gas concentration, but due to the introduction of the high dielectric constant passivation layer, the overall electron concentration of the device is often increased, which further leads to a higher electron concentration near the gate, which easily causes gate leakage, and affects the dynamic on-state performance of the HEMT device when the HEMT device is frequently turned on and off.

[0052] Therefore, the embodiment of the present application provides a high electron mobility transistor, which includes two layers of passivation layers (i.e., a first passivation layer and a second passivation layer), wherein an opening is provided on at least one side of the gate metal or around the gate metal, the second passivation layer near the gate metal is etched off, so that the electron concentration at the opening (i.e., near the gate metal) is lower than that in other regions, thereby reducing the gate leakage phenomenon and greatly improving the reliability of the device. Moreover, by only reducing the electron concentration near the gate metal, the first passivation layer can still improve the device surface trap state, thereby maintaining good dynamic on-state performance when the transistor is continuously turned on and off (dynamic on-state).

[0053] Secondly, based on the above-mentioned technical problems, in order to facilitate understanding of the embodiments of the present application, several HEMT devices based on the embodiments of the present application are described below.

[0054] The embodiment of the present application provides a high electron mobility transistor, which can be arranged on a substrate, and includes a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer and a gate metal.

[0055] Please refer to FIG. 2 and FIG. 3, which are structural schematic diagrams of a group of HEMT devices provided by the embodiments of the present application.

[0056] As shown in FIG. 2 and FIG. 3, the HEMT device includes a channel layer 1021, a barrier layer 1022, a gate 103, a first passivation layer 104, a second passivation layer 105 and a gate metal 106. The barrier layer 1022 is located on the channel layer 1021, the gate 103 is located on the barrier layer 1022, the first passivation layer 104 is located on the barrier layer 1022 and contacts the gate 103, the second passivation layer 105 is located on the first passivation layer 104, and the gate metal 106 is located on the gate 103 and contacts the gate 103. In addition, a first opening 107 is arranged on the second passivation layer 105, the first opening is arranged on at least one side of the gate metal or around the gate metal, and the first opening 107 is filled with a first insulating medium, which contacts the first passivation layer.

[0057] That is, as shown in FIG. 2 and FIG. 3, the barrier layer 1022 is stacked on the side of the channel layer 1021 away from the substrate 101, the gate 103 is stacked on the side of the barrier layer 1022 away from the substrate 101, the first passivation layer 104 covers the gate 103 and directly contacts the barrier layer 1022; the second passivation layer 105 covers the first passivation layer 104; the gate metal 106 directly connects the gate 103 through the first passivation layer 104; the second passivation layer 105 further has at least a first opening 107 on the side away from the barrier layer 1022, the first opening 107 is arranged on one side of the gate metal 106 (as shown in FIG. 2) or surrounds the gate metal 106 (as shown in FIG. 3), and the first opening 107 has the first passivation layer 104 at the bottom, and the first opening 107 is filled with a first insulating medium which directly contacts the first passivation layer 104.

[0058] It should be noted that in the embodiments of the present application and the following related embodiments, the HEMT device is taken as an example and is arranged on the substrate 101. The specific arrangement of the HEMT device is not limited in the present application.

[0059] It should be further noted that in the embodiments of the present application and the following related embodiments, the direction parallel to the surface of the substrate 101 and parallel to one side of the HEMT device is taken as the X-axis direction, that is, the left-right direction parallel to the surface of the substrate 101 as shown in FIG. 2 and FIG. 3. The direction parallel to the surface of the substrate 101 and perpendicular to the X-axis direction is taken as the Y-axis direction, that is, the front-back direction parallel to the surface of the substrate 101 as shown in FIG. 2 and FIG. 3. The direction perpendicular to the surface of the substrate 101 as shown in FIG. 2 and FIG. 3, that is, the thickness direction of the HEMT device, is taken as the Z-axis direction, that is, the vertical direction of the surface of the substrate 101 as shown in FIG. 2 and FIG. 3. The X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other.

[0060] As shown in FIG. 2 and FIG. 3, the channel layer 1021 and the barrier layer 1022 stacked in sequence can form a functional layer 102 of the HEMT device, that is, the channel layer 1021 and the barrier layer 1022 are respectively formed by two materials having different energy gaps, and a heterojunction can be formed. Due to the existence of the heterojunction, a two-dimensional electron gas 2DEG is formed between the channel layer 1021 and the barrier layer 1022, and the 2DEG is the conductive channel of the HEMT device. For example, the material forming the channel layer 1021 can include gallium nitride GaN, and the material forming the barrier layer 1022 can include aluminum gallium nitride AlGaN, etc. In addition, the channel layer 1021 and the barrier layer 1022 can also respectively include other different materials, which are not limited in the embodiments of the present application.

[0061] In some embodiments, as shown in FIG. 2 and FIG. 3, the HEMT device can further include a buffer layer 1023, also referred to as a buffer layer, disposed between the substrate 101 and the channel layer 1021. The buffer layer 1023 can relieve stress caused by lattice mismatch of gallium nitride in the channel layer, reduce defect density, and improve film quality. The material forming the buffer layer 1023 can include one or more of the following materials: AlN, GaN, InGaN, etc., which are not specifically limited in the embodiments of the present application.

[0062] It should be noted that the embodiments of the present application do not specifically limit the arrangement and structure of the channel layer 1021, the barrier layer 1022, and the buffer layer 1023.

[0063] As shown in FIG. 2 and FIG. 3, the gate 103, also referred to as a P-type layer, a cap layer, or a hat layer, etc., is disposed on the side of the barrier layer 1022 away from the substrate 101. The HEMT device can rely on the gate 103 to deplete the 2DEG between the channel layer 1021 and the barrier layer 1022, i.e., to pinch off the channel, to control the on or off of the HEMT device. For example, the HEMT device can apply a voltage at the gate metal 106 to control the gate 103 connected thereto, thereby realizing the off of the HEMT device in a non-working state. In addition, the material forming the gate 103 can be a semiconductor conductive material, such as positively charged (P-type) gallium nitride, etc., which is not specifically limited in the embodiments of the present application.

[0064] The HEMT device is provided by a plurality of passivation layers. The first passivation layer 104 is disposed on the barrier layer 1022, for example, can be covered on the gate 103 and directly contact the barrier layer 1022. In addition, the first passivation layer covers around the gate 103, which can protect the surface of the gate 103, suppress surface leakage, and reduce the accumulation of holes on the surface of the gate 103. The second passivation layer 105 is covered on the first passivation layer 104, which can reduce the influence of the first passivation layer itself or its process on the threshold voltage of the gate.

[0065] The gate metal 106 of the HEMT device is arranged on the gate 103 and in contact with the gate 103. That is, as shown in FIGS. 2 and 3, the gate metal 106 is directly connected to the gate 103 through the first passivation layer 104. The second passivation layer 105 away from the functional layer 102 is further provided with at least a first opening 107 arranged on one side of the gate metal 106 or around the gate metal 106, and the first opening 107 exposes the first passivation layer 104 at the bottom. The gate metal 106 can apply a voltage to the gate to turn on or turn off the device. In addition, the material forming the gate metal 106 can be a metal conductive material, such as gold, silver, tungsten, etc., which is not limited in the embodiments of the present application.

[0066] As shown in FIG. 2, the first opening 107 is arranged on one side of the gate metal 106, that is, the second passivation layer 105 near the gate metal 106 is etched to form the first opening 107, and the second passivation layer 105 in other areas is retained, so that the electron concentration at the first opening 107 (i.e., near the gate metal 106) is lower than that in other areas, thereby reducing the leakage of the gate (including the gate metal 106) and greatly improving the reliability of the device.

[0067] As shown in FIG. 3, the first opening 107 can also be arranged around the gate metal 106, that is, the gate metal 106 is arranged inside the first opening 107. At this time, the second passivation layer 105 near the gate metal 106 is completely etched, greatly reducing the electron concentration near the gate metal 106, reducing the leakage of the gate, and greatly improving the reliability of the device. Moreover, after the first opening 107 is arranged, the first passivation layer at the bottom of the first opening 107 can still improve the surface trap state of the device, thereby maintaining good dynamic on performance when the transistor is continuously turned on and off (dynamic on). In order to ensure that the first passivation layer can improve the surface trap state of the device, the first passivation layer can be further etched when etching the second passivation layer 105, until the remaining first passivation layer at the bottom of the opening can be retained for more than 10 nanometers, which is not limited in the embodiments of the present application. In addition, only the second passivation layer 105 can be etched, which is not limited in the embodiments of the present application.

[0068] The first opening 107 can be filled with a first insulating medium to support and insulate the gate metal, further reduce the electron concentration at the first opening 107, and prevent gate leakage. The side of the first insulating medium close to the substrate 101 can be in direct contact with the first passivation layer 104. The first insulating medium can be one or more of silicon oxide, aluminum oxide, silicon nitride, etc., and embodiments of the present application are not limited in this regard. For example, other media to be filled can be determined according to subsequent process or circuit design requirements.

[0069] In some embodiments, the transistor further includes a source, a drain, and a field plate; the source and the drain are located on the barrier layer and on two sides of the first passivation layer, respectively; the field plate is disposed on a side of the second passivation layer away from the substrate or on a side of the second passivation layer close to the substrate, and a projection of the field plate on the substrate is between a projection of the gate metal on the substrate and a projection of the drain on the substrate.

[0070] Please refer to FIG. 4 and FIG. 5, which are structural schematic diagrams of another group of HEMT devices provided by embodiments of the present application.

[0071] As shown in FIG. 4 and FIG. 5, the transistor further includes a source 108, a drain 109, and a field plate 110; the source 108 and the drain 109 are disposed on a side of the barrier layer 1022 away from the substrate 101, and on two sides of the first passivation layer 104, respectively; the field plate 110 is disposed on a side of the second passivation layer 105 away from the substrate 101 (as shown in FIG. 4) or on a side of the second passivation layer 105 close to the substrate 101 (as shown in FIG. 5), and a projection of the field plate 110 on the substrate is between a projection of the gate metal 106 on the substrate 101 and a projection of the drain 109 on the substrate 101.

[0072] Since the source 108 and the drain 109 can be prepared after the first passivation layer 104 is prepared, part of the source 108 and the drain 109 can be stacked above the first passivation layer 104 (not shown), and embodiments of the present application are not limited in this regard.

[0073] It should be noted that in the above-mentioned embodiments related to FIG. 4 and FIG. 5, the surfaces of the source 108 and the drain 109 away from the substrate 101 are covered by the second passivation layer 105, but in other embodiments, the source 108 and the drain 109 can not be covered by the second passivation layer 105 according to corresponding circuit design requirements or process flow, etc., that is, the second passivation layer 105 is only located on the first passivation layer 104 and the barrier layer 1022.

[0074] In addition, the source electrode 108 and the drain electrode 109 can be further provided with the second passivation layer 105 between the first passivation layer 104, that is, the side of the source electrode 108 and the drain electrode 109 close to the first passivation layer 104 is in contact with the second passivation layer 105, and the embodiments of the present application do not make specific limitations in this regard.

[0075] It should be further noted that the relative positions of the source electrode 108 and the drain electrode 109 can be interchanged, and the embodiments of the present application do not make specific limitations in this regard.

[0076] The field plate 110 in the HEMT device can regulate the electric field, so that the electric field distribution curve between the source electrode 108 and the drain electrode 109 is flat, thereby reducing voltage breakdown and improving device performance. Therefore, the field plate 110 needs to be located between the gate metal and the drain electrode 109. In addition, the field plate can also be provided between the gate metal and the source electrode 108, and the embodiments of the present application do not make specific limitations in this regard. According to different process preparation procedures, the field plate 110 can be prepared before the preparation of the second passivation layer, or can be prepared after the preparation of the second passivation layer, and therefore, the field plate 110 is arranged on any one side of the upper and lower sides of the second passivation layer 105.

[0077] In some embodiments, a projection of the first opening on the substrate is located between a projection of the source on the substrate and a projection of the field plate on the substrate.

[0078] The position of the first opening 107 can be arranged between the source electrode 108 and the field plate 110, that is, in the region near the gate electrode 103 and the gate metal 106, so as to avoid being arranged in other regions, which can cause the electron concentration at the opening to be reduced and affect the dynamic conduction performance of the device. In the above FIG. 2 and the above FIG. 4, the first opening 107 is arranged between the gate metal 106 and the field plate 110; in the above FIG. 3 and the above FIG. 5, the first opening 107 is arranged around the gate metal 106; please refer to FIG. 6, which is a structure schematic diagram of a HEMT device provided by an embodiment of the present application. As shown in FIG. 6, the first opening 107 can also be arranged between the source electrode 108 and the gate metal 106, so that the electron concentration at the first opening 107 is lower than that in other regions, thereby reducing the gate leakage phenomenon and greatly improving the reliability of the device.

[0079] In some embodiments, the first insulating medium inside the first opening is in contact with the gate metal.

[0080] As shown in the above FIG. 2, FIG. 4 and FIG. 6, when the first opening 107 is located on any one side of the gate metal 106, the sidewall of the first opening 107 close to the gate metal 106 has the second passivation layer 105, that is, the first opening 107 is not arranged immediately adjacent to the gate metal 106, and the first insulating medium is only in contact with the second passivation layer 105.

[0081] Referring to FIG. 7, FIG. 7 is a structural schematic diagram of another HEMT device provided by the embodiments of the present application. As shown in FIG. 7, when the first opening 107 is located at one side of the gate metal 106, the side wall of the first opening 107 close to one side of the gate metal 106 can also have the gate metal 106, that is, the first opening 107 is arranged close to the gate metal 106, and the first insulating medium is in direct contact with the gate metal 106. This arrangement can further achieve a lower channel electron concentration in the peripheral area of the gate metal 106 than the overall device, thereby reducing the gate leakage phenomenon, increasing the dynamic conduction performance, and improving the reliability of the device.

[0082] In some embodiments, a projection of the first opening on the substrate overlaps with a projection of the field plate on the substrate.

[0083] It can be understood that the above-mentioned related embodiments only illustrate that the first opening 107 opens to the field plate 110, and in the embodiments of the present application, the first opening 107 can also open below the field plate 110, that is, a projection of the first opening 107 on the substrate 101 overlaps with a projection of the field plate 110 on the substrate 101. This opening mode can make a part of the field plate 110 be prepared inside the first opening 107 when the field plate 110 is prepared, at this time, the field plate 110 can be arranged in a stepped type, which can better control the electric field and make the electric field distribution curve between the source and the drain flat, thereby improving the breakdown voltage and improving the device performance.

[0084] In some embodiments, the field plate is arranged on a side of the second passivation layer away from the substrate, and the field plate comprises a first part and a second part connected to each other; wherein the first part is arranged inside the first opening and away from the gate metal, and is in contact with the second passivation layer and the first passivation layer respectively; and the second part is arranged on the first part and is located on a side of the second passivation layer away from the substrate.

[0085] Referring to FIG. 8, FIG. 8 is a structural schematic diagram of another HEMT device provided by the embodiments of the present application. As shown in FIG. 8, the field plate 110 is arranged above the second passivation layer 105, and comprises a first part 1101 and a second part 1102 connected to each other. The first part 1101 of the field plate 110 connected to each other is arranged inside the first opening and away from the gate metal, and is in contact with the second passivation layer 105 and the first passivation layer 104 respectively, and the second part 1102 can achieve the effect of the stepped FP, further improve the breakdown voltage, and better control the electric field.

[0086] As shown in FIG. 8, the first part 1101 and the second part 1102 can form a stepped field plate structure, and in addition, to further increase the effect of the stepped FP or to meet the needs of the process preparation. The first part 1101 and the second part 1102 can be arranged in a stepped shape, or can be arranged in other shapes. For example, as shown in FIG. 8, it can be arranged in a right angle type, or can be arranged in a slope type (not shown), and the specific shape of the field plate is not limited in the embodiments of the present application.

[0087] It should be noted that the first part 1101 and the second part 1102 are prepared together, that is, integrally formed, and do not need to be prepared separately, and the embodiments of the present application do not make specific limitations on this.

[0088] In some embodiments, along the direction parallel to the substrate, the width of the first part is smaller than the width of the second part.

[0089] In order to ensure that a better electric field modulation effect is achieved and to avoid a significant reduction in device frequency, the width of the first part in the field plate located inside the first opening region needs to be smaller than the width of the second part on the second passivation layer, so that the electric field distribution curve is flat and the electric field concentration effect is effectively overcome. For example, the width of the first part can be less than or equal to 75% of the width of the second part. For another example, the width of the first part can be between 25% and 75% of the width of the second part, and the embodiments of the present application do not make specific limitations on this.

[0090] In some embodiments, the first opening is arranged at one side of the gate metal, the second passivation layer is further provided with a second opening away from the substrate, the second opening is arranged at the other side of the gate metal, and the second opening is filled with a second insulating medium, and the second insulating medium is in contact with the first passivation layer.

[0091] The above-mentioned related embodiments only illustrate the case that the second passivation layer 105 is provided with one opening (the first opening 107), and in the embodiments of the present application, the second passivation layer 105 can also be provided with multiple openings near the gate metal 106.

[0092] For example, please refer to FIG. 9, which is a structural schematic diagram of another HEMT device provided by the embodiments of the present application. As shown in FIG. 9, when the first opening 107 is arranged at one side of the gate metal 106, a second opening 111 can also be arranged at the other side of the gate metal 106, the second opening 111 is filled with a second insulating medium, and the side of the second insulating medium close to the substrate 101 can be directly in contact with the first passivation layer 104. When the gate metal 106 is provided with openings on both sides, the electron concentration near the gate can be further reduced, and the gate leakage phenomenon can be reduced.

[0093] It can be understood that the width of the second opening 111 in the X-axis direction can be the same as or different from the width of the first opening 107, and the embodiments of the present application do not make specific limitations thereon.

[0094] It can also be understood that the material of the second insulating medium filled in the second opening 111 can be the same as or different from the material of the first insulating medium filled in the first opening 107, and the embodiments of the present application do not make specific limitations thereon. Moreover, the second insulating medium can be filled together with the first insulating medium, or can be filled separately, and the embodiments of the present application do not make specific limitations thereon.

[0095] In addition, other descriptions of the second opening 111 can also be correspondingly referred to the above-mentioned related descriptions for the first opening 107, and the embodiments of the present application do not make specific descriptions here.

[0096] It should be noted that the embodiments of the present application do not limit the number of openings arranged near the gate metal 106. For example, openings can also be arranged in the Y-axis direction to reduce the electron density near the gate metal 106.

[0097] In summary, the embodiments of the present application provide a high electron mobility transistor, which includes two layers of passivation layers (i.e., a first passivation layer and a second passivation layer), wherein an opening is arranged near the gate metal capable of forming a gate, i.e., on one side of the gate metal or around the gate metal, the second passivation layer near the gate metal is etched away, so that the electron density at the opening (i.e., near the gate metal) is lower than the electron density in other regions, thereby reducing the gate leakage phenomenon and greatly improving the reliability of the device. Moreover, only the electron density near the gate metal is reduced, the first passivation layer can still improve the device surface trap state, thereby maintaining good dynamic on performance when the transistor is continuously turned on and off (dynamic on).

[0098] In some embodiments, the dielectric constant of the first passivation layer is less than the dielectric constant of the second passivation layer, or the refractive index of the first passivation layer is less than the refractive index of the second passivation layer.

[0099] The dielectric constant of the material forming the first passivation layer 104 is generally less than the dielectric constant of the material forming the second passivation layer 105. The refractive index of the material forming the first passivation layer 104 can be less than the refractive index of the material forming the second passivation layer 105. For example, the dielectric constant of the first passivation layer 104 can generally be between 3.8 and 4.3, or can exceed this range interval. For example, the refractive index of the first passivation layer 104 is between 1.46 and 1.5, or can exceed this range interval, and the embodiments of the present application do not make specific limitations thereon.

[0100] Exemplarily, the material forming the first passivation layer 104 and the second passivation layer 105 can be one or more of the following materials: silicon dioxide SiO2, silicon nitride SiN, silicon oxynitride SiON, aluminum nitride AlN, aluminum trioxide Al2O3, and the like.

[0101] When the material forming the first passivation layer 104 is consistent with the material forming the second passivation layer 105, different characteristics can be achieved by adjusting the process growth method.

[0102] In some embodiments, the first passivation layer includes a plurality of third passivation layers arranged in a stack, and the material forming each of the third passivation layers can be the same or different.

[0103] It should be noted that the first passivation layer mentioned in the embodiments of the present application mainly refers to the passivation process before the first layer of metal process (such as FP metal or OM metal), which can be a stack structure. That is, it can include a plurality of third passivation layers arranged in a stack. Taking two layers of third passivation layers as an example, refer to FIGS. 10 and 11, which are structure schematic diagrams of another group of HEMT devices provided by the embodiments of the present application. As shown in FIGS. 10 and 11, the first passivation layer includes a plurality of third passivation layers arranged in a stack, i.e., third passivation layer 1041 and third passivation layer 1042. The thickness of each of the third passivation layers can be the same or different. This arrangement can further reduce the interface state density and improve the passivation effect, thereby suppressing current collapse.

[0104] The material forming each of the third passivation layers can be the same or different. However, the refractive index or dielectric constant of each of the third passivation layers is generally different.

[0105] Exemplarily, in the plurality of third passivation layers, the refractive index or dielectric constant of one of the third passivation layers (such as third passivation layer 1041) directly contacting the gate 103 can be the smallest, and the refractive index or dielectric constant of one of the third passivation layers (such as third passivation layer 1042) farthest from the gate 103 can be the largest. For example, as shown in FIG. 10, the refractive index or dielectric constant of the third passivation layer 1041 is less than or equal to the refractive index or dielectric constant of the third passivation layer 1042, and the refractive index or dielectric constant of the third passivation layer 1042 is further less than the refractive index or dielectric constant of the second passivation layer 105.

[0106] In some embodiments, the third passivation layer 1041 (the layer in direct contact with the gate 103) can also be of high dielectric constant, i.e., the refractive index or dielectric constant of the third passivation layer 1041 is not the smallest among the multi-layered third passivation layer. As shown in FIG. 11, when it is a passivation layer of high dielectric constant, the third passivation layer 1041 is usually arranged as a thin layer, and other passivation layers of low dielectric constant (the third passivation layer 1042) are usually arranged as thick layers. For example, in the direction perpendicular to the substrate 101, the thickness of the third passivation layer 1041 can be less than or equal to 2.5 nm, and the thickness of the third passivation layer 1042 can be greater than or equal to 20 nm.

[0107] It should be noted that when the third passivation layer 1041 is a thin layer of high dielectric constant, the property restrictions mentioned in the above embodiments between the first passivation layer 104 and the second passivation layer 105, especially the size relationship setting for the dielectric constant, mainly refer to the thick passivation layer (i.e., the third passivation layer 1042). For example: the refractive index or dielectric constant of the second passivation layer 105 can only be greater than or equal to the refractive index or dielectric constant of the third passivation layer 1042, and does not need to be greater than or equal to the refractive index or dielectric constant of the third passivation layer 1041.

[0108] Secondly, the embodiments of the present application provide a preparation method of high electron mobility transistors, which can be used to manufacture the high electron mobility transistors mentioned in the above embodiments.

[0109] Please refer to FIGS. 12-20, FIG. 12 is a flowchart of a preparation method of high electron mobility transistors provided by the embodiments of the present application, and FIGS. 13-20 are a set of cross-sectional schematic diagrams of the preparation method of high electron mobility transistors provided by the embodiments of the present application.

[0110] Taking the first passivation layer as a single-layer structure for example, as shown in FIG. 12, the method comprises:

[0111] Step S101: forming a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer and a gate metal on a substrate.

[0112] Specifically, as shown in FIG. 13, the channel layer 1021 and the barrier layer 1022 can be prepared by epitaxial growth technology on the substrate 101, and the barrier layer 1022 is located above the channel layer 1021. The epitaxial growth technology can include one or more of the following growth technologies: Metalorganic Chemical Vapor Deposition (MOCVD), Molecular-Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), and the like, to grow the channel layer 1021 and the barrier layer 1022 on the substrate in sequence.

[0113] In addition, a buffer layer 1023 can also be grown on the substrate 101 before the channel layer 1021 is grown. It can be understood that the epitaxial growth technology used for each epitaxial layer on the substrate 101 can be the same or different, and the embodiments of the present application do not make specific limitations.

[0114] Further, as shown in FIG. 14, the gate 103 and the first passivation layer 104 can be prepared on the surface of the barrier layer 1022. The gate is stacked on the side of the functional layer away from the substrate, and the first passivation layer covers the gate and directly contacts the functional layer. For example, after the barrier layer 1022 is grown, a layer of P-type material can be grown on the functional layer by epitaxial growth technology; after the growth is completed, the device gate area is defined on the surface by photolithography or etching process, that is, the gate 103 is prepared, so that the gate can pinch off the channel through the gate 103 to achieve the off state of the device. The first passivation layer 104 is deposited on the epitaxial device structure (i.e., the surface of the gate 103 and the surface of the barrier layer 1022 exposed after etching).

[0115] It should be noted that due to different preparation processes, the preparation sequence of the source, the drain and the gate metal is different, and the preparation sequence of the gate metal and the first opening is also different. For example, the source and the drain can be formed first, the gate area can be etched to prepare the first opening, and then the gate metal can be formed, and finally the source, the drain and the gate can be led out by interconnection process; or the gate metal can be formed first, the source and the drain can be formed, the gate area can be etched to prepare the first opening, and finally the source, the drain and the gate can be led out by interconnection process.

[0116] As shown in FIG. 15, if the gate metal is formed first, and then the source and the drain are formed, the gate metal 106 can be prepared together when the gate 103 is formed, and the first passivation layer 104 covers the gate metal 106.

[0117] In some embodiments, as shown in FIG. 16, after forming the source 108 and the drain 109, the medium layer of the source-drain region can be completely removed by a photolithography etching method, and then the source metal and the drain metal are deposited and annealed. That is, the source 108 and the drain 109 of the device are formed by a photolithography-etching-annealing process.

[0118] After the source 108 and the drain 109 are prepared, as shown in FIG. 17, based on the structure shown in FIG. 16, the second passivation layer 105 can be further prepared.

[0119] Step S102: etching a first opening on the surface of the second passivation layer.

[0120] Specifically, the first opening is prepared on the surface of the second passivation layer 105, wherein the gate metal 106 is arranged on the gate 103, the first opening is arranged on one side of the gate metal or surrounds the gate metal, and the bottom of the first opening exposes the first passivation layer.

[0121] As shown in FIG. 18, the region to be opened in the second passivation layer 105 is exposed by dry etching or wet etching to form the first opening 107. In the embodiments of the present application, the region to be opened mainly includes the region around the gate 103 or the gate metal 106. For example, the leftmost end of the first opening 107 can reach the right boundary of the source 108, and the rightmost end can reach three quarters of the field plate (not shown). In other embodiments, the opening region of the first opening 107 can also be aligned with the gate 103 (within the manufacturing error).

[0122] Step S103: filling the first insulating medium in the first opening.

[0123] Specifically, as shown in FIG. 19, after the opening is etched, the first insulating medium can be filled in the first opening 107, and the first insulating medium can be in contact with the first passivation layer. In addition, the gate metal 106 can also be prepared before the first insulating medium is filled. Then, the field plate FP and the metal interconnection structure of the device can be prepared by a photolithography-etching-deposition process, and finally the complete high electron mobility transistor is formed.

[0124] It should be noted that, for the preparation method of forming the gate metal first and then forming the source and the drain as shown in FIG. 15, for the above steps, the field plate FP and other structures of the device can be prepared after the first opening 107 is etched; the first insulating medium is filled after the preparation is completed, and finally the gate metal 106 is led out through the metal interconnection structure together with the source 108 and the drain 109, to form the high electron mobility transistor as shown in FIG. 20.

[0125] It can be understood that, due to different preparation processes, the shapes or arrangement modes of the source electrode 108, the drain electrode 109 and the gate metal 106 are different, and the specific preparation process is not limited in the embodiment of the present application.

[0126] The embodiment of the present application further provides a chip, which comprises a circuit and the high electron mobility transistor in the above embodiment.

[0127] The embodiment of the present application further provides an electronic device, which comprises a circuit board and the high electron mobility transistor in the above embodiment.

[0128] It should be understood that the preparation method of the high electron mobility transistor and the electronic device provided by the present application can be consistent with the technical solution of the high electron mobility transistor provided by the present application, and the specific content and beneficial effects can refer to the high electron mobility transistor mentioned in the above embodiments shown in FIGS. 2-11, which will not be repeated here.

[0129] It should be understood that, for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the action sequence described, because according to the present application, some steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0130] In several embodiments provided by the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the above units is only a logical function division. There can be another division manner for actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between the units can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical or other forms.

[0131] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. According to actual needs, part or all of the units can be selected to achieve the purpose of the embodiment of the present application.

[0132] In addition, each of the functional units in each of the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0133] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the foregoing embodiments of the present application are described in detail, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent replacements; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A high electron mobility transistor, characterized by, The transistor is disposed on a substrate, and comprises a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer and a gate metal; wherein The barrier layer is located above the channel layer; The gate is located above the barrier layer; The first passivation layer is located above the barrier layer and in contact with the gate; The second passivation layer is located on the first passivation layer; The gate metal is located above the gate and in contact with the gate; wherein A first opening is disposed on the second passivation layer, the first opening is disposed on at least one side of the gate metal or surrounds the gate metal, and the first opening is filled with a first insulating medium inside, the first insulating medium being in contact with the first passivation layer.

2. The transistor of claim 1, wherein The transistor further comprises a source, a drain and a field plate; wherein The source and the drain are located above the barrier layer and on two sides of the first passivation layer respectively; The field plate is disposed on a side of the second passivation layer away from the substrate or a side of the second passivation layer close to the substrate, and a projection of the field plate on the substrate is located between a projection of the gate metal on the substrate and a projection of the drain on the substrate.

3. The transistor of claim 2, wherein A projection of the first opening on the substrate is located between a projection of the source on the substrate and a projection of the field plate on the substrate.

4. The transistor according to claim 2 or 3, wherein There is an overlapping area between the projection of the first opening on the substrate and the projection of the field plate on the substrate.

5. The transistor according to any one of claims 2 to 4, wherein The first insulating medium is in contact with the gate metal.

6. The transistor according to any one of claims 2 to 5, wherein The field plate is disposed on a side of the second passivation layer away from the substrate, and the field plate comprises a first part and a second part connected to each other; The first part is disposed inside the first opening away from the gate metal and in contact with the second passivation layer and the first passivation layer respectively; The second part is disposed on the first part and in contact with the second passivation layer.

7. The transistor of claim 6, wherein In a direction parallel to the substrate, the width of the first part is smaller than the width of the second part.

8. The transistor according to any one of claims 1 to 7, wherein The first opening is disposed on one side of the gate metal, and a second opening is further disposed on the second passivation layer, the second opening being disposed on the other side of the gate metal, the second opening being filled with a second insulating medium inside, the second insulating medium being in contact with the first passivation layer.

9. The transistor according to any one of claims 1 to 8, wherein The dielectric constant of the first passivation layer is smaller than the dielectric constant of the second passivation layer, or the refractive index of the first passivation layer is smaller than the refractive index of the second passivation layer.

10. The transistor according to any one of claims 1 to 9, wherein The first passivation layer comprises a plurality of third passivation layers stacked, and the materials of the plurality of third passivation layers are the same or different.

11. A method of fabricating a high electron mobility transistor, comprising: The method comprises: forming a channel layer, a barrier layer, a gate, a first passivation layer, a second passivation layer and a gate metal on a substrate; wherein the barrier layer is located above the channel layer; the gate is located above the barrier layer; the first passivation layer is located above the barrier layer and in contact with the gate; the second passivation layer is located on the first passivation layer; and the gate metal is located above the gate and in contact with the gate. etching a first opening on the surface of the second passivation layer, the first opening being arranged on one side of the gate metal or around the gate metal; filling a first insulating medium in the first opening, the first insulating medium being in contact with the first passivation layer.

12. The method of claim 11, wherein, The first opening is arranged on one side of the gate metal, and the second passivation layer is further provided with a second opening away from the side of the substrate, the second opening being arranged on the other side of the gate metal. The method further comprises: etching the second opening on the surface of the second passivation layer; filling a second insulating medium in the second opening, the second insulating medium being in contact with the first passivation layer.

13. A chip, characterized by A high electron mobility transistor as claimed in any one of claims 1-10 applied to a circuit.

14. An electronic device, comprising: A circuit board electrically connected with the high electron mobility transistor as claimed in any one of claims 1-10.

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