Three-dimensional hall device and preparation method therefor, and hall sensor

Abstract

The present application relates to a three-dimensional Hall device and a preparation method therefor, and a Hall sensor. The three-dimensional Hall device comprises: a barrier layer, which is disposed in a substrate; an isolation structure, which is disposed in the substrate and located on the side of the barrier layer that is close to the front side of the substrate; a shallow well layer, which is disposed in a device region, wherein a plurality of first doped layers and a plurality of second doped layers which are arranged at intervals are disposed in the shallow well layer, a first electrode is connected to each first doped layer, and a second electrode is connected to each second doped layer, so as to form a first sensing electrode pair and a first bias electrode pair; and a plurality of deep well layers, which are disposed in the substrate and located on the side of the isolation structure that faces away from the shallow well layer, wherein a plurality of third doped layers and a plurality of fourth doped layers which are arranged at intervals are disposed in each deep well layer, a third electrode is connected to each third doped layer, and a fourth electrode is connected to each fourth doped layer, so as to form a second sensing electrode pair and a second bias electrode pair. The present application can reduce the preparation difficulty and preparation costs of a three-dimensional Hall device.

Description

Three-dimensional Hall devices and their fabrication methods, Hall sensors Cross-references to related applications

[0001] This patent application claims priority to Chinese Patent Application No. 202411347866.X, filed on September 25, 2024, entitled “Three-dimensional Hall device and its preparation method, Hall sensor”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional Hall device and its fabrication method, and a Hall sensor. Background Technology

[0003] Hall sensors are widely used magnetic sensors, consisting of a Hall device and a signal conditioning circuit. When detecting magnetic fields in space, transverse Hall devices (measuring the component of the magnetic field perpendicular to the device surface) and longitudinal Hall devices (measuring the component parallel to the device surface) are limited to specific directions and cannot provide complete three-dimensional magnetic field information. In applications requiring omnidirectional, high-precision magnetic field detection, three-dimensional Hall devices are crucial to the functionality of Hall sensors.

[0004] Three-dimensional Hall devices typically consist of lateral Hall devices and longitudinal Hall devices. The magnetic sensing surface of a lateral Hall device is parallel to the device surface, requiring a shallower active well depth. Conversely, the magnetic sensing surface of a longitudinal Hall device is perpendicular to the device surface, requiring a deeper active well. Therefore, to improve device performance, multiple ion implantations are necessary during the fabrication of three-dimensional Hall devices to form active wells of different depths suitable for lateral and longitudinal Hall devices. However, current fabrication processes for three-dimensional Hall devices are quite complex. Summary of the Invention

[0005] Therefore, it is necessary to provide a three-dimensional Hall device, its fabrication method, and a Hall sensor to address the above-mentioned problems.

[0006] To achieve the above objectives, in a first aspect, this application provides a three-dimensional Hall device, comprising:

[0007] Substrate;

[0008] A barrier layer is disposed within the substrate;

[0009] An isolation structure is disposed within the substrate and located on the side of the barrier layer closest to the front side of the substrate, the isolation structure enclosing to form a device region;

[0010] a plurality of first doped layers and a plurality of second doped layers are arranged in the shallow well layer; each of the first doped layers is connected with a first electrode, and each of the second doped layers is connected with a second electrode, so as to form a first sensing electrode pair and a first bias electrode pair;

[0011] a plurality of deep well layers are arranged in the substrate and located on a side of the isolation structure away from the shallow well layer; each of the deep well layers is provided with a plurality of third doped layers and a plurality of fourth doped layers arranged at intervals, each of the third doped layers is connected with a third electrode, and each of the fourth doped layers is connected with a fourth electrode, so as to form a second sensing electrode pair and a second bias electrode pair.

[0012] In one of the embodiments, the center of the shallow well layer coincides with the center of the device region.

[0013] In one of the embodiments, the orthographic projection of the shallow well layer on the substrate is a first pattern, and the first pattern is a central symmetric pattern.

[0014] In one of the embodiments, the orthographic projection of the first doped layers and the second doped layers on the substrate is a second pattern, and the second pattern is symmetric about the center of the shallow well layer.

[0015] In one of the embodiments, the shallow well layer comprises a first sub-layer and four second sub-layers, two of the second sub-layers are located on two sides of the first sub-layer along a first direction, and the other two of the second sub-layers are located on two sides of the first sub-layer along a second direction.

[0016] In each of the two second sub-layers located on two sides of the first sub-layer along the first direction, one of the first doped layers is arranged; in each of the two second sub-layers located on two sides of the first sub-layer along the second direction, one of the second doped layers is arranged.

[0017] The first direction, the second direction and the thickness direction of the substrate are perpendicular to each other.

[0018] In one of the embodiments, the plurality of deep well layers are symmetrically arranged.

[0019] In one of the embodiments, the plurality of third doped layers and the plurality of fourth doped layers in the same deep well layer are alternately arranged along the extension direction of the deep well layer.

[0020] The orthographic projection of the plurality of third doped layers and the plurality of fourth doped layers on the substrate is a third pattern, and the third pattern is symmetric about the center of the deep well layer.

[0021] In one of the embodiments, the three-dimensional Hall device comprises four deep well layers, two of which are located on both sides of the isolation structure along a first direction, and the other two are located on both sides of the isolation structure along a second direction.

[0022] Each of the deep well layers is provided with three third doped layers and two fourth doped layers arranged alternately.

[0023] In one of the embodiments, the three-dimensional Hall device comprises eight deep well layers, which are arranged at intervals around the center of the shallow well layer or the center of the device region, and are symmetric about the center of the shallow well layer or the center of the device region; or,

[0024] The three-dimensional Hall device comprises eight deep well layers, which are arranged at intervals around the center of the device region, and are symmetric about the center of the device region.

[0025] In one of the embodiments, the material of the barrier layer comprises at least one of silicon oxide, silicon oxynitride or silicon nitride.

[0026] In one of the embodiments, a plurality of the first electrodes constitute the first sensing electrode pair, and a plurality of the second electrodes constitute the first bias electrode pair; or, a plurality of the first electrodes constitute the first bias electrode pair, and a plurality of the second electrodes constitute the first sensing electrode pair.

[0027] In one of the embodiments, a plurality of the third electrodes constitute the second sensing electrode pair, and a plurality of the fourth electrodes constitute the second bias electrode pair; or, a plurality of the third electrodes constitute the second bias electrode pair, and a plurality of the fourth electrodes constitute the second sensing electrode pair.

[0028] In a second aspect, the present application provides a Hall sensor comprising the three-dimensional Hall device of any one of the embodiments of the first aspect.

[0029] In a third aspect, the present application provides a method for preparing a three-dimensional Hall sensor, comprising:

[0030] providing a substrate;

[0031] forming a barrier layer and an isolation structure in the substrate; the isolation structure is located on the side of the barrier layer close to the front surface of the substrate, and encloses a device region;

[0032] forming a shallow well layer in the device region, and forming a plurality of deep well layers in the substrate; the deep well layers are located on the side of the isolation structure away from the shallow well layer;

[0033] a plurality of first doped layers and a plurality of second doped layers are formed in the shallow well layer, and a plurality of third doped layers and a plurality of fourth doped layers are formed in the deep well layer;

[0034] a first electrode, a second electrode, a third electrode and a fourth electrode are respectively formed on the first doped layer, the second doped layer, the third doped layer and the fourth doped layer to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair and a second bias electrode pair.

[0035] In one of the embodiments, the forming of the shallow well layer in the device region and the forming of the plurality of deep well layers in the substrate comprises:

[0036] A photoresist is coated on the front surface of the substrate to define a doped window, and the shallow well layer and the deep well layers are formed by single ion implantation.

[0037] In one of the embodiments, the forming of the plurality of first doped layers and the plurality of second doped layers in the shallow well layer, and the forming of the plurality of third doped layers and the plurality of fourth doped layers in the deep well layer comprises:

[0038] A photoresist is coated on the front surface of the substrate to define a doped window, and the first doped layer, the second doped layer, the third doped layer and the fourth doped layer are formed by single ion implantation.

[0039] The three-dimensional Hall device and the preparation method thereof and the Hall sensor provided by the embodiments of the present application can realize three-dimensional detection of the Hall device, and the barrier layer can play a blocking role in the process of preparing the shallow well layer and the deep well layer. Only one ion implantation is needed to form the shallow well layer and the deep well layer with different implantation depths, thereby reducing the process and the preparation difficulty and cost of the three-dimensional Hall device. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments or the example embodiments, the drawings needed to be used in the following embodiment or example embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0041] FIG. 1 is a structural schematic diagram of a three-dimensional Hall device according to an embodiment of the present application.

[0042] Fig. 2 is a schematic diagram of a partial structure of the three-dimensional Hall device shown in Fig. 1.

[0043] Fig. 3 is a schematic diagram of an A-A cross-sectional structure of the three-dimensional Hall device shown in Fig. 1.

[0044] Fig. 4 is a schematic diagram of a planar shallow well layer of the three-dimensional Hall device shown in Fig. 1.

[0045] Fig. 5 is a schematic diagram of a planar arrangement of a deep well layer and an isolation structure of another three-dimensional Hall device provided by an embodiment of the present application.

[0046] Fig. 6 is a schematic diagram of an arrangement of a third doped layer and a fourth doped layer in a deep well layer of still another three-dimensional Hall device provided by an embodiment of the present application.

[0047] Fig. 7 is a schematic diagram of a flow of a method for manufacturing a three-dimensional Hall device provided by an embodiment of the present application.

[0048] Figs. 8-16 are schematic diagrams of cross-sectional structures of the device during the manufacturing method shown in Fig. 7.

[0049] Explanation of Reference Signs:

[0050] 10, three-dimensional Hall device; 11, substrate; 11a, device region; 12, barrier layer; 13, isolation structure; 14, shallow well layer; 141, first sub-layer; 142, second sub-layer; 151, first doped layer; 152, second doped layer; 16, deep well layer; 171, third doped layer; 172, fourth doped layer; 181, first electrode; 182, third electrode; 183, fourth electrode; 19, dielectric layer; 20, dielectric material layer; 21, contact hole; 30, metal layer. DETAILED DESCRIPTION

[0051] For the purpose of promoting an understanding of the present application, the present application will be described in greater detail below with reference to the drawings. The embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It will be fully appreciated that the present application is applicable to other embodiments as well.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0053] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application, and, similarly, a first aspect, concept or object discussed below could be termed a second aspect, concept or object without departing from the teachings of the present application. For example, a first dopant type can be a second dopant type, and similarly, a second dopant type can be a first dopant type, where the first and second dopant types are different dopant types, e.g., the first dopant type can be P-type and the second dopant type can be N-type, or the first dopant type can be N-type and the second dopant type can be P-type.

[0054] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0055] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0056] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and a surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application.

[0057] In a first aspect, referring to FIG. 1, FIG. 2 and FIG. 3, embodiments of the application provide a three-dimensional Hall device 10. The three-dimensional Hall device 10 includes a substrate 11, a barrier layer 12, an isolation structure 13, a shallow well layer 14 and a plurality of deep well layers 16.

[0058] In particular, the barrier layer 12 is disposed in the substrate 11. The isolation structure 13 is disposed in the substrate 11 and is located on a side of the barrier layer 12 close to a front surface of the substrate 11, and the isolation structure 13 encloses a device region 11a. The shallow well layer 14 is disposed in the device region 11a; the shallow well layer 14 has a plurality of first doped layers 151 and a plurality of second doped layers 152 arranged at intervals therein; each first doped layer 151 is connected with a first electrode 181, and each second doped layer 152 is connected with a second electrode (not shown in the figure) to form a first sensing electrode pair and a first bias electrode pair. The plurality of deep well layers 16 are disposed in the substrate 11 and are located on a side of the isolation structure 13 away from the shallow well layer 14; each deep well layer 16 has a plurality of third doped layers 171 and a plurality of fourth doped layers 172 arranged at intervals therein, each third doped layer 171 is connected with a third electrode 182, and each fourth doped layer 172 is connected with a fourth electrode 183 to form a second sensing electrode pair and a second bias electrode pair.

[0059] It should be noted that if the plurality of first electrodes 181 form the first sensing electrode pair, then the plurality of second electrodes form the first bias electrode pair; if the plurality of first electrodes 181 form the first bias electrode pair, then the plurality of second electrodes form the first sensing electrode pair; if the plurality of third electrodes 182 form the second sensing electrode pair, then the plurality of fourth electrodes 183 form the second bias electrode pair; if the plurality of third electrodes 182 form the second bias electrode pair, then the plurality of fourth electrodes 183 form the second sensing electrode pair.

[0060] Further, the depth of the deep well layer 16 is greater than the depth of the shallow well layer 14. The shallow well layer 14, the first electrode 181 and the second electrode on the shallow well layer 14 constitute a lateral Hall device. In operation, a voltage or a current is applied to the first bias electrode pair, and a magnetic field component perpendicular to the shallow well layer 14 is detected. The potential difference between the first sensing electrode pair is the Hall voltage. The deep well layer 16, the third electrode 182 and the fourth electrode 183 on the deep well layer 16 constitute a longitudinal Hall device. In operation, a voltage or a current is applied to the second bias electrode pair, and the potential difference between the second sensing electrode pair is the Hall voltage.

[0061] It can be understood that the material of the substrate 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art, and the substrate 11 can provide a supporting basis for a structure layer on the substrate 11. The isolation structure 13 can be a deep trench isolation structure or a shallow trench isolation structure. The first doped layer 151, the second doped layer 152, the third doped layer 171 and the fourth doped layer 172 can be heavily doped layers.

[0062] The three-dimensional Hall device 10 provided by the embodiments of the present application sets the blocking layer 12 and the isolation structure 13 in the substrate 11, and makes the isolation structure 13 located on the side of the blocking layer 12 close to the front surface of the substrate 11, sets the shallow well layer 14 in the device region 11a surrounded by the isolation structure 13, and sets the deep well layer 16 on the side of the isolation structure 13 away from the shallow well layer 14. In this way, on the one hand, the Hall device can realize three-dimensional detection; on the other hand, in the process of preparing the shallow well layer 14 and the deep well layer 16, the blocking layer 12 can play a blocking role. Only one ion implantation is needed to form the shallow well layer 14 and the deep well layer 16 with different implantation depths, thereby reducing the process, and reducing the preparation difficulty and preparation cost of the three-dimensional Hall device 10.

[0063] In one of the embodiments, the center of the shallow well layer 14 coincides with the center of the device region 11a. Here, the center of the shallow well layer 14 can be understood as the center of the shape of the orthographic projection of the shallow well layer 14 on the substrate 11. The center of the device region 11a can be understood as the center of the figure surrounded by the orthographic projection of the isolation structure 13 on the substrate 11.

[0064] The above arrangement is conducive to arranging the first doped layer 151 and the second doped layer 152 in the shallow well layer 14, and is conducive to symmetrically arranging the first doped layer 151 and the second doped layer 152.

[0065] Further, the barrier layer 12 can be arranged at the center of the three-dimensional Hall device 10, in particular, the center of the barrier layer 12 is coincident with the center of the three-dimensional Hall device 10 (e.g. the center of the substrate 11), the center of the isolation structure 13 is coincident with the center of the three-dimensional Hall device 10 (e.g. the center of the substrate 11), and the center of the shallow well layer 14 is coincident with the center of the three-dimensional Hall device 10 (e.g. the center of the substrate 11). It should be noted that, due to manufacturing errors, approximate coincidence can also be considered as coincidence.

[0066] In one embodiment, the orthogonal projection of the shallow well layer 14 on the substrate 11 is a first pattern, and the first pattern is a center-symmetrical pattern. Here, the shallow well layer 14 is a center-symmetrical pattern from the top view.

[0067] In this way, the device structure is more symmetrical, the initial misalignment is reduced, and the measurement accuracy of the device is improved.

[0068] Exemplarily, the shape of the shallow well layer 14 from the top view can be a center-symmetrical pattern such as a quadrilateral or an octagon.

[0069] In one embodiment, the orthogonal projection of the first doped layer 151 and the second doped layer 152 on the substrate 11 is a second pattern, and the second pattern is center-symmetrical with respect to the center of the shallow well layer 14. That is, all the doped layers (the first doped layer 151 and the second doped layer 152) in the shallow well layer 14 are center-symmetrical with respect to the center of the shallow well layer 14 from the top view.

[0070] In this way, the device structure is more symmetrical, the initial misalignment is reduced, and the measurement accuracy of the device is improved.

[0071] In one embodiment, as shown in FIG. 4, the shallow well layer 14 includes a first sub-layer 141 and four second sub-layers 142, two second sub-layers 142 are located on both sides of the first sub-layer 141 along a first direction X, and the other two second sub-layers 142 are located on both sides of the first sub-layer 141 along a second direction Y. In each of the two second sub-layers 142 located on both sides of the first sub-layer 141 along the first direction X, a first doped layer 151 is arranged; and in each of the two second sub-layers 142 located on both sides of the first sub-layer 141 along the second direction Y, a second doped layer 152 is arranged. The first direction X, the second direction Y and the thickness direction Z of the substrate 11 are perpendicular to each other. In this way, the shallow well layer 14 is in the shape of a "+" sign. Thus, the device structure is more symmetrical, the initial misalignment is reduced, and the measurement accuracy of the device is improved.

[0072] In one embodiment, the plurality of deep well layers 16 are symmetrically arranged. In this way, the device structure is more symmetrical, the initial misalignment is reduced, and the measurement accuracy of the device is improved.

[0073] Exemplarily, the number of the deep well layers 16 can be 2, 4, or 8, etc.

[0074] In one embodiment, the plurality of third doped layers 171 and the plurality of fourth doped layers 172 in the same deep well layer 16 are arranged alternately along the extension direction of the deep well layer 16. Here, the extension direction of the deep well layer 16 can be the length direction of the deep well layer 16. The orthogonal projection of the plurality of third doped layers 171 and the plurality of fourth doped layers 172 on the substrate 11 is a third pattern, and the third pattern is symmetric about the center of the deep well layer 16. That is, from the top view, all the doped layers (the third doped layers 171 and the fourth doped layers 172) in the same deep well layer 16 are symmetric about the center of the deep well layer 16.

[0075] In this way, it is beneficial to make the device structure more symmetric, reduce the initial misadjustment, and improve the measurement accuracy of the device.

[0076] In one embodiment, as shown in FIGS. 1-3, the three-dimensional Hall device 10 includes four deep well layers 16, two of which are located on both sides of the isolation structure 13 along the first direction X, and the other two of which are located on both sides of the isolation structure 13 along the second direction Y. Each deep well layer 16 is provided with three third doped layers 171 and two fourth doped layers 172 arranged alternately. The first direction X, the second direction Y, and the thickness direction Z of the substrate 11 are perpendicular to each other.

[0077] Further, the four deep well layers 16 are symmetric about the center of the shallow well layer 14 (or the center of the device region 11a). All the doped layers (the third doped layers 171 and the fourth doped layers 172) in the same deep well layer 16 are symmetric about the center of the deep well layer 16.

[0078] In this way, the initial misadjustment can be reduced to the greatest extent, and the measurement accuracy of the device can be improved.

[0079] In one embodiment, as shown in FIG. 5, the three-dimensional Hall device 10 includes eight deep well layers 16, which are arranged at intervals around the center of the shallow well layer 14 (or the center of the device region 11a), and the eight deep well layers 16 are symmetric about the center of the shallow well layer 14 (or the center of the device region 11a). It can be understood that the number of the deep well layers 16 can also be 16, 32, etc., and the number and arrangement of the deep well layers 16 are not particularly limited in the embodiments of the present application.

[0080] In one of the embodiments, referring to FIG. 6, each deep well layer 16 is provided with two third doped layers 171 and two fourth doped layers 172 arranged alternately. The number of deep well layers 16 and the arrangement manner are not particularly limited in the embodiments. It can be understood that the number of third doped layers 171 and fourth doped layers 172 in the deep well layer 16 can also be other numbers, and the number of third doped layers 171 and fourth doped layers 172 is not particularly limited in the embodiments.

[0081] In one of the embodiments, the material of the barrier layer 12 includes at least one of silicon oxide, silicon oxynitride or silicon nitride. In this way, on the one hand, the barrier performance of the barrier layer 12 can be improved, and on the other hand, the preparation cost can be reduced.

[0082] In one of the embodiments, the substrate 11 is a P-type substrate 11, and the doping types of the shallow well layer 14, the deep well layer 16, the first doped layer 151, the second doped layer 152, the third doped layer 171 and the fourth doped layer 172 are all N-type. It can be understood that the above-mentioned doping types can also be reversed.

[0083] In a second aspect, the embodiments provide a Hall sensor including the three-dimensional Hall device 10 in any of the embodiments of the first aspect. Further, the Hall sensor can further include a signal conditioning circuit electrically connected with the three-dimensional Hall device 10.

[0084] In a third aspect, referring to FIG. 7 and combining FIGS. 8-16, the embodiments provide a preparation method of a three-dimensional Hall sensor, which specifically includes the following steps:

[0085] S100: providing a substrate 11. Exemplarily, a P-type substrate 11 can be formed by ion implantation. The structural diagram of the substrate 11 is shown in FIG. 8.

[0086] S200: forming a barrier layer 12 and an isolation structure 13 in the substrate 11. Referring to FIG. 11, the isolation structure 13 is located on the side of the barrier layer 12 close to the front surface of the substrate 11, and encloses a device region 11a.

[0087] S300: forming a shallow well layer 14 in the device region 11a, and forming a plurality of deep well layers 16 in the substrate 11. Referring to FIG. 12, the deep well layer 16 is located on the side of the isolation structure 13 away from the shallow well layer 14. Exemplarily, photoresist can be coated on the front surface of the substrate 11 to define a doped window, and a single high-energy N-type ion implantation is performed to form the shallow well layer 14 above the barrier layer 12 and the deep well layer 16 around the isolation structure 13.

[0088] S400: Forming a plurality of first doped layers 151 and a plurality of second doped layers 152 in the shallow well layer 14, and forming a plurality of third doped layers 171 and a plurality of fourth doped layers 172 in the deep well layer 16. The structure after the first doped layers 151, the second doped layers 152, the third doped layers 171 and the fourth doped layers 172 are formed is shown in FIG. 13. Exemplarily, photoresist can be coated on the front surface of the substrate 11 to define a doped window, and the first doped layers 151, the second doped layers 152, the third doped layers 171 and the fourth doped layers 172 are formed by single high-energy N-type ion implantation.

[0089] S500: Forming a first electrode 181, a second electrode, a third electrode 182 and a fourth electrode 183 on the first doped layers 151, the second doped layers 152, the third doped layers 171 and the fourth doped layers 172 respectively, to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair and a second bias electrode pair.

[0090] The preparation method of the three-dimensional Hall device 10 provided by the embodiments of the present application can realize three-dimensional detection of the Hall device, and the blocking layer 12 can play a blocking role in the process of preparing the shallow well layer 14 and the deep well layer 16, so that the shallow well layer 14 and the deep well layer 16 with different implantation depths can be formed by only one ion implantation, thereby reducing the process, and reducing the preparation difficulty and preparation cost of the three-dimensional Hall device 10.

[0091] In one of the embodiments, S200: forming the blocking layer 12 and the isolation structure 13 in the substrate 11, specifically including the following steps:

[0092] S210: implanting blocking ions in part of the substrate 11. Exemplarily, as shown in FIG. 9, oxygen ions can be implanted.

[0093] S220: performing annealing treatment on the substrate 11 to form the blocking layer 12. The structure after the blocking layer 12 is formed is shown in FIG. 10.

[0094] S230: etching a groove on the substrate 11, and depositing dielectric material in the groove to form the isolation structure 13. The structure after the isolation structure 13 is formed is shown in FIG. 11. Exemplarily, the groove can be formed by dry etching, and the isolation structure 13 can be formed by chemical vapor deposition of silicon dioxide.

[0095] In one of the embodiments, S500: forming the first electrode 181, the second electrode, the third electrode 182 and the fourth electrode 183 on the first doped layer 151, the second doped layer 152, the third doped layer 171 and the fourth doped layer 172 respectively to form the first sensing electrode pair, the first bias electrode pair, the second sensing electrode pair and the second bias electrode pair, specifically including the following steps:

[0096] S510: forming the dielectric material layer 20 on the front surface of the substrate 11. The structure after forming the dielectric material layer 20 is shown in FIG. 14.

[0097] S520: etching the contact hole 21 on the dielectric material layer 20 and forming the dielectric layer 19. The structure after forming the contact hole 21 is shown in FIG. 15.

[0098] S530: forming the metal layer 30 on the dielectric layer 19. The structure after forming the metal layer 30 is shown in FIG. 16.

[0099] S540: patterning the metal layer 30 to form the first electrode 181, the second electrode, the third electrode 182 and the fourth electrode 183. The structure after forming the first electrode 181, the second electrode, the third electrode 182 and the fourth electrode 183 is shown in FIG. 3.

[0100] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0101] The technical features of the above embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features of the above embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present specification.

[0102] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent application scope. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A three-dimensional Hall device, characterized by The three-dimensional Hall device comprises: a substrate; a barrier layer disposed in the substrate; an isolation structure disposed in the substrate and located on a side of the barrier layer close to a front surface of the substrate, the isolation structure enclosing a device region; a shallow well layer disposed in the device region; a plurality of first doped layers and a plurality of second doped layers are disposed in the shallow well layer in a spaced-apart manner; a first electrode is connected to each of the first doped layers, and a second electrode is connected to each of the second doped layers, so as to form a first sensing electrode pair and a first bias electrode pair; a plurality of deep well layers disposed in the substrate and located on a side of the isolation structure away from the shallow well layer; a plurality of third doped layers and a plurality of fourth doped layers are disposed in each of the deep well layers in a spaced-apart manner; a third electrode is connected to each of the third doped layers, and a fourth electrode is connected to each of the fourth doped layers, so as to form a second sensing electrode pair and a second bias electrode pair.

2. The three-dimensional Hall device according to claim 1, characterized in that The center of the shallow well layer coincides with the center of the device region.

3. The three-dimensional Hall device according to claim 1, characterized in that The orthographic projection of the shallow well layer on the substrate is a first pattern, and the first pattern is a central symmetric pattern.

4. The three-dimensional Hall device according to claim 1, characterized in that The orthographic projection of the first doped layers and the second doped layers on the substrate is a second pattern, and the second pattern is symmetric about the center of the shallow well layer.

5. The three-dimensional Hall device according to claim 1, characterized in that The shallow well layer comprises a first sub-layer and four second sub-layers, two of the second sub-layers are located on two sides of the first sub-layer along a first direction, and the other two second sub-layers are located on two sides of the first sub-layer along a second direction. In each of the two second sub-layers located on two sides of the first sub-layer along the first direction, one first doped layer is disposed; in each of the two second sub-layers located on two sides of the first sub-layer along the second direction, one second doped layer is disposed. The first direction, the second direction and the thickness direction of the substrate are perpendicular to each other.

6. The three-dimensional Hall device according to claim 1, characterized in that The plurality of deep well layers are symmetrically arranged.

7. The three-dimensional Hall device according to claim 1, wherein The plurality of third doped layers and the plurality of fourth doped layers in the same deep well layer are arranged alternately along the extension direction of the deep well layer. The orthographic projection of the plurality of third doped layers and the plurality of fourth doped layers on the substrate is a third pattern, and the third pattern is symmetric about the center of the deep well layer.

8. The three-dimensional Hall device according to claim 1, characterized in that The three-dimensional Hall device comprises four deep well layers, two of the deep well layers are located on two sides of the isolation structure along a first direction, and the other two deep well layers are located on two sides of the isolation structure along a second direction. In each of the deep well layers, three third doped layers and two fourth doped layers are arranged alternately; the first direction, the second direction and the thickness direction of the substrate are perpendicular to each other.

9. The three-dimensional Hall device according to claim 1, wherein The three-dimensional Hall device comprises eight deep well layers, the eight deep well layers are arranged at intervals around the center of the shallow well layer or the center of the device region, and the eight deep well layers are symmetric about the center of the shallow well layer or the center of the device region; or The three-dimensional Hall device comprises eight deep well layers, the eight deep well layers are arranged at intervals around the center of the device region, and the eight deep well layers are symmetric about the center of the device region.

10. The three-dimensional Hall device according to claim 1, characterized in that The material of the barrier layer comprises at least one of silicon oxide, silicon oxynitride or silicon nitride.

11. The three-dimensional Hall device according to claim 1, characterized in that The first electrodes form the first sensing electrode pair, and the second electrodes form the first bias electrode pair; or the first electrodes form the first bias electrode pair, and the second electrodes form the first sensing electrode pair.

12. The three-dimensional Hall device according to claim 1, characterized in that The third electrodes form the second sensing electrode pair, and the fourth electrodes form the second bias electrode pair; or the third electrodes form the second bias electrode pair, and the fourth electrodes form the second sensing electrode pair.

13. A Hall sensor, characterized by The Hall device comprises the Hall device as claimed in any one of claims 1-2.

14. A method of manufacturing a Hall device, characterized by, The Hall device comprises: providing a substrate; forming a barrier layer and an isolation structure in the substrate; the isolation structure is located on the side of the barrier layer close to the front surface of the substrate, and encloses a device region; forming a shallow well layer in the device region, and forming a plurality of deep well layers in the substrate; the deep well layers are located on the side of the isolation structure away from the shallow well layer; forming a plurality of first doped layers and a plurality of second doped layers in the shallow well layer, and forming a plurality of third doped layers and a plurality of fourth doped layers in the deep well layer; forming first electrodes, second electrodes, third electrodes and fourth electrodes on the first doped layers, the second doped layers, the third doped layers and the fourth doped layers respectively, to form a first sensing electrode pair, a first bias electrode pair, a second sensing electrode pair and a second bias electrode pair.

15. The method of manufacturing a Hall device according to claim 14, wherein The forming a shallow well layer in the device region, and forming a plurality of deep well layers in the substrate comprises: covering photoresist on the front surface of the substrate to define a doped window, and forming the shallow well layer and the deep well layer by single ion implantation.

16. The method of producing a Hall device according to claim 14, wherein The forming a plurality of first doped layers and a plurality of second doped layers in the shallow well layer, and forming a plurality of third doped layers and a plurality of fourth doped layers in the deep well layer comprises: covering photoresist on the front surface of the substrate to define a doped window, and forming the first doped layers, the second doped layers, the third doped layers and the fourth doped layers by single ion implantation.

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