Chip verification method and apparatus, and chip and electronic device

Abstract

Disclosed in the present application are a chip verification method and apparatus, and a chip and an electronic device, the chip verification method and apparatus being applied to an electronic device, and the electronic device being in communication connection with a chip. The method comprises: when it is determined that a chip enables an i-th round of function verification, loading data to be processed of the i-th round of function verification into a first memory address of the chip, i being a positive integer; reading a protocol value of a first interaction protocol from a second memory address of the chip; and when the protocol value of the first interaction protocol is a first protocol value, reading, from a third memory address of the chip, a function verification result of the chip which is obtained on the basis of said data of the i-th round of function verification, wherein the first protocol value is used for instructing the chip to complete the i-th round of function verification.

Description

Chip verification method and device, chip and electronic device

[0001] Cross-reference to Related Applications

[0002] The present application claims priority to Chinese Patent Application No. 202411344849.0, filed on September 25, 2024, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the technical field of computers, and specifically relates to a chip verification method and device, a chip and an electronic device. BACKGROUND

[0004] In the development and verification phase of a chip, such as a data processing chip, offline data to be processed, such as offline image materials, are usually collected in advance, the chip is caused to process the offline image materials through a certain method, and the verification result is compared with the result of simulation calculation by a personal computer (PC) to confirm the correctness of the functions of the chip.

[0005] At present, the verification process of the chip usually involves manual input of commands to load specified materials to be used, instruct the chip to start working, and trigger the export of a result file from the chip. However, this verification process of manually inputting commands is tedious and time-consuming. SUMMARY

[0006] The purpose of the embodiments of the present application is to provide a chip verification method and device, a chip and an electronic device, which can automatically perform function verification of a chip through an interaction protocol between the electronic device and the chip, simplify the function verification process of the chip, and improve the function verification efficiency of the chip.

[0007] In a first aspect, the embodiments of the present application provide a chip verification method applied to an electronic device, wherein the electronic device is in communication connection with a chip, and the method comprises:

[0008] In a case where it is determined that the chip starts the i-th round of function verification, loading data to be processed in the i-th round of function verification into a first memory address of the chip, i being a positive integer;

[0009] reading a protocol value of a first interaction protocol from a second memory address of the chip;

[0010] In a case where the protocol value of the first interaction protocol is a first protocol value, reading a function verification result of the chip based on the data to be processed in the i-th round of function verification from a third memory address of the chip, the first protocol value being used to indicate that the chip completes the i-th round of function verification.

[0011] In a second aspect, the embodiments of the present application provide a chip verification method, applied to a chip, the chip being in communication connection with an electronic device, and the method comprising:

[0012] obtaining, from a first memory address of the chip, to-be-processed data for i-th round function verification of the chip, the to-be-processed data for the i-th round function verification being loaded into the first memory address of the chip in a case that the electronic device is in communication connection with the chip and it is determined that the chip starts the i-th round function verification, i being a positive integer;

[0013] performing function verification based on the to-be-processed data for the i-th round function verification, to obtain a function verification result;

[0014] storing the function verification result into a third memory address of the chip;

[0015] storing a first protocol value into a second memory address of the chip, the second memory address being used to store a protocol value of a first interaction protocol, and the first protocol value being used to indicate that the chip completes function verification;

[0016] The first protocol value stored in the second memory address is used to instruct the electronic device to read the function verification result from the third memory address.

[0017] In a third aspect, the embodiments of the present application provide a chip verification device, applied to an electronic device, the electronic device being in communication connection with a chip, and the device comprising:

[0018] a loading module, configured to load to-be-processed data for i-th round function verification into a first memory address of the chip in a case that it is determined that the chip starts the i-th round function verification, i being a positive integer;

[0019] a first reading module, configured to read a protocol value of a first interaction protocol from a second memory address of the chip;

[0020] a second reading module, configured to read, in a case that the protocol value of the first interaction protocol is a first protocol value, a function verification result of the chip based on the to-be-processed data for the i-th round function verification from a third memory address of the chip, the first protocol value being used to indicate that the chip completes the i-th round function verification.

[0021] In a fourth aspect, the embodiments of the present application provide a chip verification device, applied to a chip, the chip being in communication connection with an electronic device, and the device comprising:

[0022] The acquisition module is configured to acquire, from a first memory address of the chip, to-be-processed data of an i-th round of function verification of the chip, wherein the to-be-processed data of the i-th round of function verification is loaded into the first memory address of the chip under the condition that the electronic device is in communication connection with the chip and it is determined that the chip starts the i-th round of function verification, i is a positive integer; and the function verification module is configured to perform function verification based on the to-be-processed data of the i-th round of function verification, to obtain a function verification result.

[0023] The function verification module is configured to perform function verification based on the to-be-processed data of the i-th round of function verification, to obtain a function verification result.

[0024] The first storage module is configured to store the function verification result into a third memory address of the chip.

[0025] The second storage module is configured to store a first protocol value into a second memory address of the chip, wherein the second memory address is used to store a protocol value of a first interaction protocol, and the first protocol value is used to indicate that the function verification is completed.

[0026] The first protocol value stored in the second memory address is used to instruct the electronic device to read the function verification result from the third memory address.

[0027] In a fifth aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, the memory stores programs or instructions that can run on the processor, and the programs or instructions are executed by the processor to implement the steps of the chip verification method according to the first aspect.

[0028] In a sixth aspect, an embodiment of the present application provides a chip, including a processor and a communication interface, the communication interface is coupled with the processor, and the processor is configured to run programs or instructions to implement the steps of the chip verification method according to the second aspect.

[0029] In a seventh aspect, an embodiment of the present application provides a readable storage medium, the readable storage medium stores programs or instructions, and the programs or instructions are executed by a processor to implement the steps of the chip verification method according to the first aspect or the steps of the chip verification method according to the second aspect.

[0030] In an eighth aspect, an embodiment of the present application provides a computer program product, the program product is stored in a storage medium, and the program product is executed by at least one processor to implement the steps of the chip verification method according to the first aspect or the steps of the chip verification method according to the second aspect.

[0031] In the embodiments of the present application, the electronic device is in communication connection with the chip, and the electronic device loads the to-be-processed data of the i th round of function verification into the first memory address of the chip in a case where the chip starts the i th round of function verification; the electronic device reads the protocol value of the first interaction protocol from the second memory address of the chip; and the electronic device reads the function verification result of the to-be-processed data of the i th round of function verification of the chip from the third memory address of the chip in a case where the protocol value of the first interaction protocol is the first protocol value. In this way, the interaction protocol between the electronic device and the chip can be stored in the memory address of the chip, and the interaction protocol in the function verification process of the chip can be obtained by the electronic device accessing the memory space of the chip. Thus, the electronic device and the chip can perform the corresponding function verification operation based on the protocol value of the interaction protocol, so that the function verification of the electronic device on the chip can be automatically implemented, and thus the function verification process of the chip can be simplified and the function verification efficiency of the chip can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a flowchart of a chip verification method according to some embodiments of the present application;

[0033] FIG. 2 is a flowchart of a chip verification method according to some embodiments of the present application;

[0034] FIG. 3 is an interaction schematic diagram of a chip verification method according to a specific example in the embodiments of the present application;

[0035] FIG. 4 is a structural schematic diagram of a chip verification apparatus according to some embodiments of the present application;

[0036] FIG. 5 is a structural schematic diagram of a chip verification apparatus according to some embodiments of the present application;

[0037] FIG. 6 is a structural schematic diagram of an electronic device according to some embodiments of the present application;

[0038] FIG. 7 is a hardware structural schematic diagram of an electronic device according to some embodiments of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0040] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the objects before and after are in an "or" relationship.

[0041] The chip verification method provided by the embodiments of the present application will be described in detail below in conjunction with the drawings, specific embodiments and application scenarios.

[0042] It should be noted that the chip verification method of the present embodiment can be applied to a chip verification system, which includes an electronic device and a chip, and the electronic device is used to verify the function of the chip. The chip can be any chip, such as a data processing chip, which can be an image processing chip. Correspondingly, the data to be processed for function verification can be offline materials such as offline image data. Offline materials refer to materials loaded offline to the chip, and offline function verification of the chip is achieved by loading offline materials.

[0043] In the related art, a tool software running on a PC and a firmware running on a chip can be used to send operation commands to drive the function verification process of the chip through a physical protocol such as Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface (SPI) or Secure Digital Input and Output (SDIO) etc. However, sending each operation command through a physical protocol requires specially designed and developed complex communication protocols, which will not be used in actual chip products, which will introduce additional burden to the function verification of the chip and cause waste of development cost.

[0044] In the embodiment, the electronic device and the chip are communicatively connected, and the interaction protocol between the electronic device and the chip is stored in the memory address of the chip. The interaction protocol in the functional verification process of the chip is obtained through the access of the electronic device to the memory space of the chip. The electronic device and the chip can perform corresponding functional verification operations based on the protocol value of the interaction protocol. Compared with sending operation commands through a physical protocol, the electronic device and the chip can interact more efficiently and simply through the interaction protocol in the functional verification process of the chip.

[0045] In the embodiment, the electronic device can be wiredly connected to the chip through a communication mode such as a Command and Data Interface-Serial Peripheral Interface (CDIF-SPI), an Inter-Integrated Circuit (I2C), or the like. Accordingly, the electronic device can directly read and write the memory space of the chip. For example, the electronic device can directly operate the memory space of the chip through the CDIF-SPI. The hardware link between the electronic device and the chip in the following embodiments will be described by taking the CDIF-SPI as an example.

[0046] It should be noted that the memory space of the chip needs to have a certain data space for storing the interaction protocol between the electronic device and the chip. The data space size required by the interaction protocol generally depends on the complexity of the interaction protocol, and a few dozen bytes are generally sufficient.

[0047] In some embodiments, the interaction protocol between the electronic device and the chip stored in the memory space of the chip is shown in Table 1 and Table 2. Table 1 is a control field of the functional verification process, and Table 2 is a data block message field of the functional verification process.

[0048] Table 1 control field table

[0049] Table 2 data block message field

[0050] ic_ready, the data size of the field is 1 byte, which is used for the chip to inform the electronic device that the chip is ready for the functional verification process. The data of the field is stored in the memory space of the chip, such as the 0x1000 address of a Double Data Rate (DDR) memory. When the chip completes the initialization of the basic hardware, system software, and protocol value of the interaction protocol, it means that the chip is ready for the functional verification process.

[0051] process_start, the data size of the field is 1 byte, used for the electronic device to inform the chip whether to start the function verification process, and the data of the field is stored in the 0x1001 address of the DDR memory of the chip.

[0052] process_end, the data size of the field is 1 byte, used for the chip to inform the electronic device that the function verification has been completed, and the data of the field is stored in the 0x1002 address of the DDR memory of the chip.

[0053] next_round_rdy, the data size of the field is 1 byte, used for the electronic device to inform the chip whether to start the next round of function verification, and the data of the field is stored in the 0x1003 address of the DDR memory of the chip.

[0054] load_addr, the data size of the field is 4 bytes, used to indicate the storage address of the data to be processed loaded by the electronic device in the memory space of the chip.

[0055] result_addr, the data size of the field is 4 bytes, used to indicate the storage address of the function verification result of the chip in the memory space of the chip.

[0056] load_size, the data size of the field is 4 bytes, used to indicate the data amount of the loaded data to be processed, in bytes.

[0057] result_size, the data size of the field is 4 bytes, used to indicate the data amount of the function verification result, in bytes.

[0058] It should be noted that the storage address and data size of each field data in the memory space of the chip are only illustrative, and can be set according to actual needs, which are not specifically limited here. In addition, some interactive protocol fields such as ic_ready, load_size, result_size, etc. can also be set according to actual needs, which are not specifically limited here.

[0059] FIG. 1 is one of the flow diagrams of the chip verification method provided by the embodiments of the present application, executed by an electronic device; as shown in FIG. 1, the method comprises the following steps:

[0060] In step 101, in the case where it is determined that the chip starts the i-th round of function verification, the data to be processed of the i-th round of function verification is loaded into the first memory address of the chip, i is a positive integer.

[0061] The data to be processed can be image data, video data or text data, etc.

[0062] In a case that the electronic device is in communication connection with the chip, the electronic device can perform automatic function verification on the chip by configuring an automatic script. The automatic script can include, for example, a number of rounds of function verification on the chip (e.g., 100 rounds) and a data amount of to-be-processed data loaded in each round (e.g., 3 images loaded in each round).

[0063] In some embodiments, in a case that the electronic device automatic script configuration is completed, it can be determined to start the i-th round of function verification on the chip. For example, in a case that the electronic device automatic script configuration is completed, it can be determined to start the first round of function verification on the chip. In a case that i is greater than 1, the fourth interaction protocol value can be configured to start the i-th round of function verification on the chip. For example, the fourth interaction protocol value can be configured in the sixth memory address of the chip to start the i-th round of function verification on the chip, and the fourth interaction protocol value is used to indicate that the i-th round of function verification on the chip is started. The fourth interaction protocol value can be any non-zero value.

[0064] In some embodiments, in a case that it is determined that the chip starts the i-th round of function verification, the to-be-processed data of the i-th round of function verification can be directly loaded into the first memory address of the chip.

[0065] In some embodiments, the second interaction protocol value can be read from the fourth memory address of the chip. In a case that the second interaction protocol value is the second protocol value, the to-be-processed data of the i-th round of function verification can be loaded into the first memory address of the chip. The second interaction protocol value is used to indicate whether the protocol value of the interaction protocol between the electronic device and the chip is initialized, and the second protocol value is used to indicate that the protocol value of the interaction protocol between the electronic device and the chip is initialized. That is, in a case that the electronic device determines that the protocol value of the interaction protocol is initialized, the electronic device loads the to-be-processed data of the i-th round of function verification into the first memory address of the chip.

[0066] The first memory address can be, for example, the data storage address of the load_addr field shown in Table 2. The data storage address can be a 4-byte memory setting, and can include a memory address of 0x1010. The load_addr field can be a pointer field, and can point to a starting address of a memory region planned to store to-be-processed data in a memory space, such as a memory address of 0x1010. That is, the to-be-processed data of the i-th round of function verification can be loaded into addresses of 0x1010, 0x1011, 0x1012 and 0x1013 by using the load_addr pointer field of 0x1010 to point to the starting address.

[0067] Optionally, after the step 101, the method further includes:

[0068] write the second data amount of the to-be-processed data of the i-th round of function verification into an eighth memory address of the chip;

[0069] The second data amount is used to indicate an amount of data obtained by the chip from the first memory address.

[0070] The eighth memory address can be a data storage address of a load_size field as shown in Table 2, and the data storage address can be a 4-byte memory setting and can include a memory address of 0x1018. The memory address of 0x1018 can be a start address, that is, the data storage address of the load_size field can include the addresses of 0x1018, 0x1019, 0x101A, and 0x101B.

[0071] When the to-be-processed data of the i-th round of function verification is loaded, the electronic device can also write the second data amount of the to-be-processed data into the eighth memory address of the chip to inform the chip of the amount of to-be-processed data loaded and guide the chip to obtain the to-be-processed data from the first memory address to complete the function verification, thereby improving the interaction efficiency between the electronic device and the chip.

[0072] In step 102, a protocol value of a first interaction protocol is read from a second memory address of the chip.

[0073] The second memory address can be a data storage address of a process_end field as shown in Table 1, such as the address of 0x1002. The protocol value of the first interaction protocol is used to indicate whether the chip completes the function verification based on the to-be-processed data of the i-th round of function verification. The protocol value of the first interaction protocol can be a first protocol value, which can be any non-zero value. In some embodiments, the first protocol value can be C, indicating that the chip completes the function verification. The protocol value of the first interaction protocol can also be zero, indicating that the chip does not complete the function verification.

[0074] In some embodiments, the protocol value of the first interaction protocol can be read from the second memory address of the chip at the same time as the to-be-processed data of the i-th round of function verification is loaded. In some embodiments, the protocol value of the first interaction protocol can be read from the second memory address of the chip after the to-be-processed data of the i-th round of function verification is loaded.

[0075] The electronic device can read the protocol value of the first interaction protocol from the second memory address of the chip in real time or at intervals. The protocol value of the first interaction protocol can be set by the chip. When the chip determines that the to-be-processed data of the i-th round of function verification completes the function verification, the chip can set the protocol value of the first interaction protocol to the first protocol value, that is, the first protocol value can be stored into the data storage address of the process_end field.

[0076] Step 103, in a case where the protocol value of the first interaction protocol is a first protocol value, reading, from a third memory address of the chip, a function verification result of the chip on the to-be-processed data based on the i-th round of function verification, the first protocol value being used to indicate that the chip completes the i-th round of function verification.

[0077] In some embodiments, the first protocol value can be C, and the protocol value of the first interaction protocol read from the second memory address can be compared with C, and if they are consistent, it indicates that the chip completes the function verification. Correspondingly, the electronic device can read, from the third memory address of the chip, the function verification result of the chip on the to-be-processed data based on the i-th round of function verification.

[0078] The third memory address can be a data storage address of a result_addr field as shown in Table 2, and the data storage address thereof can be a 4-byte memory setting and can include a memory address of 0x1014. The result_addr field can be a pointer field and can point to a starting address of a memory region planned for storing the function verification result in the memory space, such as the memory address of 0x1014. That is, in a case where the to-be-processed data based on the i-th round of function verification is completed, the chip can store the function verification result in the addresses of 0x1014, 0x1015, 0x1016 and 0x1017 through the result_addr pointer field pointing to the starting address of 0x1014.

[0079] Correspondingly, the electronic device can read, from the third memory address of the chip, the function verification result of the chip on the to-be-processed data based on the i-th round of function verification through the result_addr pointer field.

[0080] In some embodiments, the electronic device can read a preset amount of data from the third memory address of the chip to obtain the function verification result. Optionally, the step 103 specifically includes:

[0081] reading a first amount of data from a seventh memory address of the chip;

[0082] reading the first amount of data from the third memory address of the chip to obtain the function verification result.

[0083] The seventh memory address can be a data storage address of a result_size field as shown in Table 2, and the data storage address thereof can be a 4-byte memory setting and can include a memory address of 0x101C. The 0x101C can be a starting address, that is, the data storage address of the result_size field can include the addresses of 0x101C, 0x101D, 0x101E and 0x101F.

[0084] The chip can store the first data amount of the function verification result into the seventh memory address of the chip in the case of completing the function verification, to inform the electronic device of the data amount of the stored function verification result, guide the electronic device to read the function verification result from the third memory address, and improve the interaction efficiency between the electronic device and the chip.

[0085] Correspondingly, the electronic device can read the data of the first data amount from the third memory address of the chip, and obtain the function verification result. In this way, the electronic device can compare the obtained function verification result with the result of the simulation calculation of the electronic device, to verify the function correctness of the chip.

[0086] In the embodiment, the electronic device is in communication connection with the chip, and in the case that the electronic device determines that the chip starts the i-th round of function verification, the electronic device loads the to-be-processed data of the i-th round of function verification into the first memory address of the chip; reads the protocol value of the first interaction protocol from the second memory address of the chip; and in the case that the protocol value of the first interaction protocol is a first protocol value, reads the function verification result of the chip based on the to-be-processed data of the i-th round of function verification from the third memory address of the chip. In this way, the interaction protocol between the electronic device and the chip can be stored in the memory address of the chip, and the interaction protocol in the function verification process of the chip can be obtained through the access of the electronic device to the memory space of the chip. Therefore, the electronic device and the chip can perform the corresponding function verification operation based on the protocol value of the interaction protocol, so that the function verification of the electronic device on the chip can be automatically implemented, and the function verification process of the chip can be simplified, and the function verification efficiency of the chip can be improved.

[0087] Moreover, the function verification of the chip can be supported by a simplified interaction protocol, which can effectively simplify the development cost of offline verification in the chip development and verification stage, and improve the development and verification efficiency.

[0088] Optionally, the step 101 specifically includes:

[0089] reading the protocol value of the second interaction protocol from the fourth memory address of the chip;

[0090] In the case that the protocol value of the second interaction protocol is a second protocol value, the to-be-processed data of the i-th round of function verification is loaded into the first memory address of the chip, and the second protocol value is used to indicate that the protocol value of the interaction protocol between the electronic device and the chip is initialized.

[0091] The fourth memory address can be a data storage address of an ic_ready field as shown in Table 1, such as 0x1000 address. The protocol value of the second interaction protocol is used to indicate whether the protocol value of the interaction protocol between the electronic device and the chip is initialized. The protocol value of the second interaction protocol can be a second protocol value. The second protocol value can be any non-zero value. In some embodiments, the second protocol value can be A, indicating that the protocol value of the interaction protocol between the electronic device and the chip is initialized. The protocol value of the second interaction protocol can also be zero, indicating that the protocol value of the interaction protocol between the electronic device and the chip is not initialized.

[0092] The second protocol value can also indicate that the chip completes basic hardware and system software initialization, that is, the second protocol value can indicate that the chip is ready for the functional verification process.

[0093] In some embodiments, the second protocol value of the chip can be read from the fourth memory address of the chip when the electronic device is powered on and establishes a communication connection with the chip. In some embodiments, the second protocol value of the chip can also be read from the fourth memory address of the chip when the electronic device determines to start the i+1 round of functional verification of the chip.

[0094] The electronic device can read the second protocol value of the chip from the fourth memory address of the chip in real time or at intervals. The second protocol value of the chip can be set by the chip. When the chip completes basic hardware and system software initialization and the initialization of the protocol value of the interaction protocol between the electronic device and the chip, the second protocol value of the chip can be set to the second protocol value, that is, the second protocol value can be stored in the data storage address of the ic_ready field.

[0095] When the chip is powered on, the chip can initialize the basic hardware and system software. When the chip starts the functional verification, the chip can initialize the data part of the interaction protocol, that is, the protocol value of the interaction protocol. For example, the protocol value of the interaction protocol field as shown in Table 1 can be initialized to zero. The 4-byte memory pointed to by the load_addr pointer field as shown in Table 2 can be set to the start address of the memory region planned in the memory space for storing the to-be-processed data. The 4-byte memory pointed to by the result_addr pointer field can be set to the start address of the memory region planned in the memory space for storing the functional verification result.

[0096] Correspondingly, the protocol value of the second interaction protocol read by the electronic device from the fourth memory address can be the second protocol value, and the electronic device loads the to-be-processed data of the i-th round of function verification to the first memory address of the chip only when the read protocol value of the second interaction protocol is the second protocol value. In this way, the electronic device and the chip interact through the protocol value of the second interaction protocol, so as to load the to-be-processed data of the i-th round of function verification to the first memory address of the chip, and improve the interaction efficiency between the electronic device and the chip.

[0097] Optionally, after the step 101, the method further includes:

[0098] In a case where the to-be-processed data of the i-th round of function verification is loaded, a third protocol value is written into a fifth memory address of the chip;

[0099] The fifth memory address is used to store a protocol value of a third interaction protocol, and the third protocol value is used to instruct the chip to start function verification.

[0100] The fifth memory address can be a data storage address of a process_start field as shown in Table 1, such as 0x1001 address, and the protocol value of the third interaction protocol is used to instruct whether the chip starts function verification. The protocol value of the third interaction protocol can be a third protocol value, and the third protocol value can be any non-zero value. In some embodiments, the third protocol value can be B, indicating that the chip starts function verification. The protocol value of the third interaction protocol can also be zero, indicating that the chip does not start function verification.

[0101] The electronic device can write the third protocol value into the fifth memory address of the chip in a case where the to-be-processed data of the i-th round of function verification is loaded. Correspondingly, the chip can obtain the protocol value of the third interaction protocol stored in the fifth memory address in real time or periodically, and can obtain the to-be-processed data from the first memory address and start function verification based on the to-be-processed data in a case where the protocol value of the third interaction protocol is the third protocol value. In this way, the electronic device and the chip interact through the protocol value of the third interaction protocol, so as to start function verification of the chip, and improve the interaction efficiency between the electronic device and the chip.

[0102] Optionally, after the step 103, the method further includes:

[0103] In a case where it is determined that the chip verification is not completed, a fourth protocol value is written into a sixth memory address of the chip;

[0104] The sixth memory address is used to store a protocol value of a fourth interaction protocol, and the fourth protocol value is used to instruct to start the i+1-th round of function verification of the chip.

[0105] The sixth memory address can be a data storage address of the next round rdy field as shown in Table 1, such as 0x1003 address, and the protocol value of the fourth interaction protocol is used to indicate whether to start the i+1 round of functional verification of the chip. The protocol value of the fourth interaction protocol can be the fourth protocol value, and the fourth protocol value can be any non-zero value. In some embodiments, the fourth protocol value can be E, indicating that the i+1 round of functional verification of the chip is started. The protocol value of the fourth interaction protocol can also be zero, indicating that the i+1 round of functional verification of the chip is not started.

[0106] After reading the functional verification result of the chip based on the i round of functional verification of the to-be-processed data from the third memory address of the chip, the electronic device can determine whether the chip verification is completed according to the automated script. In the case where it is determined that the chip verification is not completed, the fourth protocol value can be written into the sixth memory address of the chip. Correspondingly, the chip can obtain the protocol value of the fourth interaction protocol stored in the sixth memory address in real time or periodically. In the case where the chip obtains the protocol value of the fourth interaction protocol as the fourth protocol value, the protocol value of the interaction protocol between the electronic device and the chip in the i+1 round of functional verification of the chip can be initialized to perform the next round of functional test. In this way, the electronic device and the chip interact through the protocol value of the fourth interaction protocol to realize that the chip starts the next round of functional verification, and the interaction efficiency of the electronic device and the chip is improved. The initialization mode of the protocol value of the interaction protocol between the electronic device and the chip in each round of functional verification is similar, which will not be described in detail here.

[0107] It should be noted that the electronic device reads the protocol value of the first interaction protocol from the second memory address of the chip, and in the case where the read protocol value of the first interaction protocol is the first protocol value, the protocol value of the first interaction protocol stored in the second memory address of the chip can be reset to zero. In addition, the electronic device reads the protocol value of the second interaction protocol from the fourth memory address of the chip, and in the case where the read protocol value of the second interaction protocol is the second protocol value, the protocol value of the second interaction protocol stored in the fourth memory address of the chip can also be reset to zero, so as to avoid affecting the subsequent functional verification between the electronic device and the chip and ensure the normal progress of the functional verification process.

[0108] FIG. 2 is a flow diagram of a chip verification method provided by an embodiment of the present application, which is executed by a chip and the chip is in communication connection with an electronic device; as shown in FIG. 2, the method comprises the following steps:

[0109] In step 201, the i-th round of function verification data to be processed of the chip is obtained from a first memory address of the chip, wherein the i-th round of function verification data to be processed is loaded into the first memory address of the chip under the condition that the electronic device is in communication connection with the chip and it is determined that the chip starts the i-th round of function verification, i is a positive integer;

[0110] In step 202, function verification is performed based on the i-th round of function verification data to be processed, and a function verification result is obtained.

[0111] In step 203, the function verification result is stored into a third memory address of the chip.

[0112] In step 204, a first protocol value is stored into a second memory address of the chip, wherein the second memory address is used for storing a protocol value of a first interaction protocol, and the first protocol value is used for indicating that the function verification is completed.

[0113] The first protocol value stored in the second memory address is used for indicating that the electronic device reads the function verification result from the third memory address.

[0114] In step 201, in some embodiments, the chip can query whether the i-th round of function verification data to be processed is stored in the first memory address of the chip in real time or periodically after power-on or after the initialization of the protocol value of the interaction protocol between the electronic device and the chip, and obtain the i-th round of function verification data to be processed of the chip from the first memory address of the chip.

[0115] In some embodiments, the chip can also query the third protocol value of the third interaction protocol stored in the fifth memory address of the chip in real time or periodically, and only obtain the i-th round of function verification data to be processed from the first memory address of the chip when the third protocol value of the third interaction protocol is the third protocol value. The third protocol value of the third interaction protocol is written into the fifth memory address of the chip by the electronic device after the i-th round of function verification data to be processed is loaded.

[0116] In some embodiments, a preset data amount of data to be processed can be obtained from the first memory address of the chip. Optionally, the step 201 specifically includes:

[0117] A second data amount is obtained from an eighth memory address of the chip.

[0118] The second data amount of data is obtained from the first memory address of the chip, and the i-th round of function verification data to be processed of the chip is obtained.

[0119] In this way, the electronic device can write the second data amount of the to-be-processed data into the eighth memory address of the chip to inform the chip of the data amount stored in the first memory address, so as to guide the chip to obtain the to-be-processed data from the first memory address, thereby improving the interaction efficiency between the electronic device and the chip.

[0120] In steps 202 to 204, the chip can process the to-be-processed data by using the chip processing function, such as image processing, to perform function verification, and obtain a function verification result. Then, the function verification result is stored in the third memory address of the chip, and the first protocol value is stored in the second memory address of the chip, so as to inform the electronic device that the chip has completed the function verification through the first protocol value of the first interaction protocol.

[0121] In the case of obtaining the function verification result, the chip can also store a first data amount of the function verification result in the seventh memory address of the chip, so as to guide the electronic device to read the function verification result from the third memory address.

[0122] Correspondingly, the electronic device and the chip can interact through the protocol value of the first interaction protocol to realize the acquisition of the function verification result in the case of completing the function verification.

[0123] In this embodiment, the electronic device and the chip are in communication connection, and in the case that the electronic device determines that the chip starts the i-th round of function verification, the to-be-processed data of the i-th round of function verification is loaded into the first memory address of the chip; the protocol value of the first interaction protocol is read from the second memory address of the chip; in the case that the protocol value of the first interaction protocol is the first protocol value, the function verification result of the to-be-processed data of the chip based on the i-th round of function verification is read from the third memory address of the chip. In this way, the interaction protocol between the electronic device and the chip can be stored in the memory address of the chip, and the interaction protocol in the function verification process of the chip can be acquired by the electronic device accessing the memory space of the chip. Therefore, the electronic device and the chip can perform the corresponding function verification operation based on the protocol value of the interaction protocol, so that the function verification of the electronic device on the chip can be automatically realized, and the function verification process of the chip can be simplified, and the function verification efficiency of the chip can be improved.

[0124] Optionally, before the step 201, the method further includes:

[0125] initializing the protocol value of the interaction protocol between the electronic device and the chip in the i-th round of function verification;

[0126] In the case that the initialization of the protocol value of the interaction protocol between the electronic device and the chip is completed, the second protocol value is stored in the fourth memory address of the chip;

[0127] The fourth memory address is used to store a second interaction protocol value, and the second interaction protocol value is used to indicate that a protocol value of an interaction protocol between the electronic device and the chip is initialized, and the second interaction protocol value stored in the second memory address is used to inform the electronic device to load the to-be-processed data of the i th round of function verification into the first memory address of the chip.

[0128] Optionally, the step 201 comprises:

[0129] In a case where a third interaction protocol value stored in the fifth memory address of the chip is a third protocol value, the to-be-processed data of the i th round of function verification is acquired from the first memory address of the chip.

[0130] The third protocol value is used to indicate that the chip starts to perform function verification, and the third protocol value is written into the fifth memory address of the chip by the electronic device in a case where the loading of the to-be-processed data of the i th round of function verification is completed.

[0131] Optionally, after the step 204, the method further comprises:

[0132] In a case where a fourth interaction protocol value stored in the sixth memory address of the chip is a fourth protocol value, a protocol value of an interaction protocol between the electronic device and the chip in an i+1 th round of function verification of the chip is initialized.

[0133] The fourth protocol value is used to indicate that the i+1 th round of function verification of the chip is started, and the fourth protocol value is written into the sixth memory address by the electronic device in a case where it is determined that the chip verification is not completed.

[0134] The above steps have been described in detail in the chip verification method embodiment executed by the electronic device, and will not be described herein.

[0135] It should be noted that the chip can query the third interaction protocol value stored in the fifth memory address, and in a case where the third interaction protocol value stored in the fifth memory address is the third protocol value, the third interaction protocol value stored in the fifth memory address of the chip can be reset to zero, and the chip can query the fourth interaction protocol value stored in the sixth memory address, and in a case where the fourth interaction protocol value stored in the sixth memory address is the fourth protocol value, the fourth interaction protocol value stored in the sixth memory address of the chip can be reset to zero, so as to avoid affecting the subsequent function verification between the electronic device and the chip and ensure the normal progress of the function verification process.

[0136] The chip verification method of the embodiment is described in detail below with a specific example. FIG. 3 is an interaction diagram of the chip verification method of a specific example in the embodiment, the left flowchart represents the chip function verification flowchart of the electronic device such as a PC, and the right flowchart represents the chip function verification flowchart of the chip. The electronic device and the chip establish a communication connection through CDIF-SPI. The dashed arrow represents the key interaction between the electronic device and the chip through the interaction protocol. As shown in FIG. 3, the method includes the following steps:

[0137] Step 301: power-on initialization of the chip, completion of basic hardware and system software initialization;

[0138] Step 302: initialization of the protocol value of the interaction protocol of the chip, that is, initialization of the data part of all fields shown in Table 1 to zero, setting the 4-byte memory pointed to by the load_addr pointer field shown in Table 2 to the start address of the memory region planned in the memory space for storing the to-be-processed data, and setting the 4-byte memory pointed to by the result_addr pointer field to the start address of the memory region planned in the memory space for storing the function verification result;

[0139] Step 303: the chip sets the protocol value of the is_ready field in the fourth memory address of the chip to A, and performs the polling operation of step 308;

[0140] Step 304: the electronic device reads and checks whether the protocol value of the is_ready field in the fourth memory address of the chip is A. If yes, step 305 is performed. If not, it indicates that the protocol value of the interaction protocol of the chip has not been initialized completely, and the polling check is continued;

[0141] Step 305: after the electronic device reads that is_ready is A, the protocol value of the field is reset to zero, and step 306 is continued to be performed;

[0142] Step 306: the electronic device loads the to-be-processed data into the first memory address pointed to by the protocol field load_addr through batch data communication;

[0143] Step 307: the electronic device sets the protocol value of the protocol field process_start to B in the case where the to-be-processed data is loaded completely, and starts to perform step 313 to poll the protocol value of process_end;

[0144] Step 308: the chip polls the protocol value of process_start. If it is B, it indicates that the electronic device has completed the loading of the to-be-processed data, and the second data amount of the to-be-processed data is written into the eighth memory address indicated by the load_size field;

[0145] Step 309: The chip re-sets the protocol value of the process_start field to zero after polling the protocol value B of the field;

[0146] Step 310: The chip obtains the data to be processed from the first memory address pointed by the load_addr field;

[0147] Step 311: The chip writes the functional verification result to the third memory address pointed by the result_addr pointer field and writes the first data amount of the functional verification result to the seventh memory address indicated by the result_size field after the functional verification based on the data to be processed is completed;

[0148] Step 312: The chip sets the protocol value of the process_end field to C to inform the electronic device that the functional verification has been completed, and then the chip performs step 318 to poll whether the next round of functional verification is needed;

[0149] Step 313: The electronic device polls the protocol value of the process_end field from the second memory address, and if the protocol value is C, it means that the functional verification of the chip has been completed, otherwise, the polling of the protocol value continues;

[0150] Step 314: The electronic device re-sets the protocol value of the process_end field to zero after detecting that the functional verification of the chip has been completed;

[0151] Step 315: The electronic device reads the data amount of data in the seventh memory address indicated by the result_size field from the third memory address pointed by the result_addr pointer field and stores it into a local file for subsequent analysis;

[0152] Step 316: The electronic device checks whether there is data to be processed for functional verification in the local, and if there is, it starts the next round of functional verification and performs step 317, and if there is no data for functional verification, it ends the functional verification process;

[0153] Step 317: The electronic device sets the protocol value of the next_round_rdy field to E if the next round of functional verification is needed, and then jumps to step 304;

[0154] Step 318: The chip polls whether the protocol value of the next_round_rdy field is E, and if it is, it means that the next round of functional verification is to be performed, and step 319 is performed, otherwise, the polling continues;

[0155] Step 319: After the chip polls the protocol value of the next_round_rdy field as E, the protocol value of the field is reset to zero, and then the process jumps to step 302 to start the next round of function verification.

[0156] The chip verification method provided in the embodiments of the present application can be executed by the chip verification device. The chip verification method is executed by the chip verification device in the embodiments of the present application, and the chip verification device provided in the embodiments of the present application is described.

[0157] Referring to FIG. 4, FIG. 4 is a structural schematic diagram of a chip verification device 400 provided in the embodiments of the present application, which is applied to an electronic device in communication with a chip. As shown in FIG. 4, the device includes:

[0158] The loading module 401 is configured to load the to-be-processed data of the i th round of function verification into the first memory address of the chip when it is determined that the chip starts the i th round of function verification, where i is a positive integer.

[0159] The first reading module 402 is configured to read the protocol value of the first interaction protocol from the second memory address of the chip.

[0160] The second reading module 403 is configured to read the function verification result of the to-be-processed data of the i th round of function verification from the third memory address of the chip when the protocol value of the first interaction protocol is a first protocol value, where the first protocol value is used to indicate that the chip completes the i th round of function verification.

[0161] Optionally, the loading module 401 is specifically configured to:

[0162] read the protocol value of the second interaction protocol from the fourth memory address of the chip.

[0163] load the to-be-processed data of the i th round of function verification into the first memory address of the chip when the protocol value of the second interaction protocol is a second protocol value, where the second protocol value is used to indicate that the protocol value of the interaction protocol between the electronic device and the chip is initialized.

[0164] Optionally, the device further includes:

[0165] The first writing module is configured to write a third protocol value into the fifth memory address of the chip when the loading of the to-be-processed data of the i th round of function verification is completed.

[0166] The fifth memory address is used to store the protocol value of the third interaction protocol, and the third protocol value is used to indicate that the chip starts the function verification.

[0167] Optionally, the apparatus further comprises:

[0168] a second writing module, configured to write a fourth protocol value into a sixth memory address of the chip if it is determined that the chip verification is not completed;

[0169] The sixth memory address is used to store a protocol value of a fourth interaction protocol, and the fourth protocol value is used to indicate that the i+1th round of function verification of the chip is started.

[0170] Optionally, the second reading module 403 is specifically configured to:

[0171] read a first data amount from a seventh memory address of the chip;

[0172] read data of the first data amount from a third memory address of the chip to obtain the function verification result.

[0173] Optionally, the apparatus further comprises:

[0174] a third writing module, configured to write a second data amount of the to-be-processed data of the i th round of function verification into an eighth memory address of the chip;

[0175] The second data amount is used to indicate an amount of data obtained by the chip from the first memory address.

[0176] The chip verification apparatus in the embodiments of the present application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and the like. The electronic device can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, and the like. The embodiments of the present application are not limited in this regard.

[0177] The chip verification apparatus in the embodiments of the present application can be an apparatus with an operating system. The operating system can be an Android operating system, an ios operating system, or other possible operating systems, which are not limited in the embodiments of the present application.

[0178] The chip verification apparatus provided in the embodiments of the present application can implement each process implemented by the method embodiment of FIG. 1, and thus details are not repeated here.

[0179] Referring to FIG. 5, FIG. 5 is a structural schematic diagram two of a chip verification apparatus 500 provided in the embodiments of the present application, which is applied to a chip and in communication connection with an electronic device. As shown in FIG. 5, the apparatus includes:

[0180] The obtaining module 501 is configured to obtain, from a first memory address of the chip, to-be-processed data of i-th round function verification of the chip, wherein the to-be-processed data of the i-th round function verification is loaded into the first memory address of the chip under the condition that the electronic device is in communication connection with the chip and it is determined that the chip starts the i-th round function verification, and i is a positive integer;

[0181] The function verification module 502 is configured to perform function verification based on the to-be-processed data of the i-th round function verification, to obtain a function verification result.

[0182] The first storage module 503 is configured to store the function verification result into a third memory address of the chip.

[0183] The second storage module 504 is configured to store a first protocol value into a second memory address of the chip, wherein the second memory address is used to store a protocol value of a first interaction protocol, and the first protocol value is used to indicate that the function verification of the chip is completed.

[0184] The first protocol value stored in the second memory address is used to instruct the electronic device to read the function verification result from the third memory address.

[0185] Optionally, the apparatus further includes:

[0186] The first initialization module is configured to initialize a protocol value of an interaction protocol between the electronic device and the chip in the i-th round function verification.

[0187] The third storage module is configured to store a second protocol value into a fourth memory address of the chip under the condition that the initialization of the protocol value of the interaction protocol between the electronic device and the chip is completed.

[0188] The fourth memory address is used for storing a second interaction protocol value, the second protocol value is used for indicating that a protocol value of an interaction protocol between the electronic device and the chip is initialized, and the second protocol value stored in the second memory address is used for notifying the electronic device to load the to-be-processed data of the i th round of function verification into the first memory address of the chip.

[0189] Optionally, the obtaining module 501 is specifically configured to:

[0190] In a case where a third interaction protocol value stored in a fifth memory address of the chip is a third protocol value, the to-be-processed data of the i th round of function verification is obtained from the first memory address of the chip.

[0191] The third protocol value is used for indicating that the chip starts to perform function verification, and the third protocol value is written into the fifth memory address of the chip by the electronic device in a case where loading of the to-be-processed data of the i th round of function verification is completed.

[0192] Optionally, the apparatus further includes:

[0193] A second initialization module is configured to, in a case where a fourth interaction protocol value stored in a sixth memory address of the chip is a fourth protocol value, initialize a protocol value of an interaction protocol between the electronic device and the chip in an i+1 th round of function verification of the chip.

[0194] The fourth protocol value is used for indicating that the i+1 th round of function verification of the chip is started, and the fourth protocol value is written into the sixth memory address by the electronic device in a case where it is determined that the chip verification is not completed.

[0195] The chip verification apparatus provided by the embodiments of the present application can implement each process implemented by the method embodiment of FIG. 2, and thus details are not repeated here.

[0196] In this embodiment, the electronic device is in communication connection with the chip, and in a case where the electronic device determines that the chip starts the i th round of function verification, the to-be-processed data of the i th round of function verification is loaded into the first memory address of the chip; the protocol value of the first interaction protocol is read from the second memory address of the chip; in a case where the protocol value of the first interaction protocol is a first protocol value, the function verification result of the to-be-processed data of the i th round of function verification of the chip is read from the third memory address of the chip. In this way, the interaction protocol between the electronic device and the chip can be stored in the memory address of the chip, and the interaction protocol in the function verification process of the chip can be obtained through the access of the electronic device to the memory space of the chip. Thus, the electronic device and the chip can perform corresponding function verification operations based on the protocol value of the interaction protocol, so that the function verification of the electronic device on the chip can be automatically implemented, and thus the function verification process of the chip can be simplified and the function verification efficiency of the chip can be improved.

[0197] Optionally, as shown in FIG. 6, the embodiment of the present application further provides an electronic device 600, which comprises a processor 601 and a memory 602, and the memory 602 stores programs or instructions executable on the processor 601, which implement each step of the above-mentioned chip verification method embodiment on the electronic device side when executed by the processor 601 and achieve the same technical effects. To avoid repetition, details are not described herein.

[0198] Optionally, the embodiment of the present application further provides a chip, which comprises a processor and a communication interface, the communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement each process of the above-mentioned chip verification method embodiment on the chip side and achieve the same technical effects. To avoid repetition, details are not described herein.

[0199] It should be noted that the electronic device in the embodiment of the present application includes the above-mentioned mobile electronic device and non-mobile electronic device.

[0200] FIG. 7 is a schematic diagram of the hardware structure of an electronic device for implementing the embodiment of the present application.

[0201] The electronic device 700 includes but is not limited to the following components: a radio frequency unit 701, a network module 702, an audio output unit 703, an input unit 704, a sensor 705, a display unit 706, a user input unit 707, an interface unit 708, a memory 709, and a processor 710, etc.

[0202] Those skilled in the art can understand that the electronic device 700 can further include a power supply (such as a battery) for supplying power to each component, and the power supply can be logically connected to the processor 710 through a power management system, so that the power management system can realize the functions of managing charging, discharging, and power consumption management. The electronic device structure shown in FIG. 7 does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than those shown, or combine certain components, or different component arrangements, which are not described here.

[0203] The processor 710 is configured to:

[0204] In a case where it is determined that the chip starts the i th round of function verification, load the to-be-processed data of the i th round of function verification into a first memory address of the chip, i being a positive integer;

[0205] Read a protocol value of the first interaction protocol from a second memory address of the chip;

[0206] In a case where the protocol value of the first interaction protocol is a first protocol value, read a function verification result of the to-be-processed data of the chip based on the i th round of function verification from a third memory address of the chip, the first protocol value being used to indicate that the chip completes the i th round of function verification.

[0207] In this embodiment, the electronic device is in communication connection with the chip, and in a case where the electronic device determines that the chip starts the i th round of function verification, the to-be-processed data of the i th round of function verification is loaded into a first memory address of the chip; a protocol value of the first interaction protocol is read from a second memory address of the chip; and in a case where the protocol value of the first interaction protocol is a first protocol value, a function verification result of the to-be-processed data of the chip based on the i th round of function verification is read from a third memory address of the chip. In this way, the interaction protocol between the electronic device and the chip can be stored in the memory address of the chip, and the interaction protocol in the function verification process of the chip can be obtained through the access of the electronic device to the memory space of the chip. Therefore, the electronic device and the chip can perform corresponding function verification operations based on the protocol value of the interaction protocol, so that the function verification of the electronic device on the chip can be automatically realized, and the function verification process of the chip can be simplified, and the function verification efficiency of the chip can be improved.

[0208] Optionally, the processor 710 is further configured to:

[0209] Read a protocol value of the second interaction protocol from a fourth memory address of the chip;

[0210] In a case where the protocol value of the second interaction protocol is a second protocol value, the to-be-processed data of the i th round of function verification is loaded into a first memory address of the chip, the second protocol value being used to indicate that a protocol value of an interaction protocol between the electronic device and the chip is initialized.

[0211] Optionally, the processor 710 is configured to:

[0212] In a case where the loading of the to-be-processed data of the i th round of function verification is completed, a third protocol value is written into a fifth memory address of the chip.

[0213] The fifth memory address is used to store a protocol value of a third interaction protocol, and the third protocol value is used to indicate that the chip starts the function verification.

[0214] Optionally, the processor 710 is further configured to:

[0215] In a case where it is determined that the chip verification is not completed, a fourth protocol value is written into a sixth memory address of the chip.

[0216] The sixth memory address is used to store a protocol value of a fourth interaction protocol, and the fourth protocol value is used to indicate that i + 1 th round of function verification of the chip is started.

[0217] Optionally, the processor 710 is further configured to:

[0218] A first data amount is read from a seventh memory address of the chip.

[0219] Data of the first data amount is read from a third memory address of the chip, and the function verification result is obtained.

[0220] Optionally, the processor 710 is further configured to:

[0221] A second data amount of the to-be-processed data of the i th round of function verification is written into an eighth memory address of the chip.

[0222] The second data amount is used to indicate a data amount obtained by the chip from the first memory address.

[0223] It should be understood that in the embodiments of the present application, the input unit 704 can include a graphics processor (GPU) 7041 and a microphone 7042. The graphics processor 7041 processes image data of a still picture or a video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 706 can include a display panel 7061, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 707 includes at least one of a touch panel 7071 and other input devices 7072. The touch panel 7071 is also referred to as a touch screen. The touch panel 7071 can include two parts of a touch detection device and a touch controller. The other input devices 7072 can include, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, and the like), a trackball, a mouse, a joystick, and the like, which will not be described here.

[0224] The memory 709 can be used to store software programs and various data. The memory 709 can mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, and the like), and the like. In addition, the memory 709 can include a volatile memory or a non-volatile memory, or the memory 709 can include both volatile and non-volatile memories. The non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synch link dynamic random access memory (SLDRAM), and a direct memory bus random access memory (Direct Rambus RAM, DRRAM). The memory 709 in the embodiments of the present application includes but is not limited to these and any other suitable types of memory.

[0225] The processor 710 can include one or more processing units; in some embodiments, the processor 710 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and an application program, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 710.

[0226] Optionally, a processor in a chip according to an embodiment of the present application is used to:

[0227] obtain, from a first memory address of the chip, to-be-processed data of an i th round of function verification of the chip, the to-be-processed data of the i th round of function verification being loaded into the first memory address of the chip in a case that the electronic device is in communication connection with the chip and it is determined that the chip starts the i th round of function verification, i being a positive integer;

[0228] perform function verification based on the to-be-processed data of the i th round of function verification, to obtain a function verification result;

[0229] store the function verification result into a third memory address of the chip;

[0230] store a first protocol value into a second memory address of the chip, the second memory address being used to store a protocol value of a first interaction protocol, the first protocol value being used to indicate that the function verification is completed;

[0231] The first protocol value stored in the second memory address is used to instruct the electronic device to read the function verification result from the third memory address.

[0232] Optionally, the processor is further used to:

[0233] initialize a protocol value of an interaction protocol between the electronic device and the chip in the i th round of function verification;

[0234] store a second protocol value into a fourth memory address of the chip in a case that the initialization of the protocol value of the interaction protocol between the electronic device and the chip is completed;

[0235] The fourth memory address is used to store a protocol value of a second interaction protocol, the second protocol value being used to indicate that the initialization of the protocol value of the interaction protocol between the electronic device and the chip is completed, and the second protocol value stored in the second memory address is used to instruct the electronic device to load the to-be-processed data of the i th round of function verification into the first memory address of the chip.

[0236] Optionally, the processor is further used to:

[0237] in a case where a protocol value of a third interaction protocol stored in a fifth memory address of the chip is a third protocol value, obtaining the to-be-processed data of the i th round of function verification from the first memory address of the chip;

[0238] The third protocol value is used to instruct the chip to start the function verification, and the third protocol value is written into the fifth memory address of the chip by the electronic device in a case where the to-be-processed data of the i th round of function verification is loaded.

[0239] Optionally, the processor is further configured to:

[0240] in a case where a protocol value of a fourth interaction protocol stored in a sixth memory address of the chip is a fourth protocol value, initializing the protocol value of the interaction protocol between the electronic device and the chip in the i+1 th round of function verification of the chip;

[0241] The fourth protocol value is used to instruct to start the i+1 th round of function verification of the chip, and the fourth protocol value is written into the sixth memory address by the electronic device in a case where it is determined that the chip verification is not completed.

[0242] The embodiment of the application further provides a readable storage medium, and the readable storage medium stores a program or instructions. The program or instructions are executed by a processor to implement each process of the chip verification method embodiment, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0243] The processor is a processor in the electronic device in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0244] The embodiment of the application further provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is configured to run a program or instructions to implement each process of the chip verification method embodiment, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0245] It should be understood that the chip mentioned in the embodiment of the application can also be referred to as a system-level chip, a system chip, a chip system, or a system-on-chip, etc.

[0246] The embodiment of the application provides a computer program product. The program product is stored in a storage medium. The program product is executed by at least one processor to implement each process of the chip verification method embodiment, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0247] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. Furthermore, it is to be understood that the method and apparatus of the present application can be carried out by more than one process, method, article, or apparatus either simultaneously, concurrently, or with intervening action that are carried out at the same time, either in a simultaneous fashion or in a fashion that is interleaved in time. For example, the described methods can be performed in a different order from that described, and / or various steps can be combined or omitted, and / or additional steps can be added, without departing from the scope of the described methods. Also, features described with respect to certain examples can be combined in other examples.

[0248] From the above description of the embodiments, it is apparent that the above-mentioned method can be realized by means of software plus necessary universal hardware platforms, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of computer software products in essence or in the form of the part that contributes to the prior art, which are stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and include a plurality of instructions for making an electronic device (which can be a mobile phone, computer, server, or network device, etc.) execute the method of each embodiment of the present application.

[0249] The embodiments of the present application are described above in combination with the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative rather than limiting, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A chip verification method applied to an electronic device, the electronic device being in communication connection with a chip, the method comprising: loading, in a case where it is determined that the chip starts an i-th round of function verification, i being a positive integer, to-be-processed data of the i-th round of function verification into a first memory address of the chip; reading a protocol value of a first interaction protocol from a second memory address of the chip; in a case where the protocol value of the first interaction protocol is a first protocol value, reading a function verification result of the chip based on the to-be-processed data of the i-th round of function verification from a third memory address of the chip, the first protocol value being used to indicate that the chip completes the i-th round of function verification.

2. The method of claim 1, wherein, The loading, to the first memory address of the chip, of the to-be-processed data of the i-th round of function verification comprises: reading a protocol value of a second interaction protocol from a fourth memory address of the chip; in a case where the protocol value of the second interaction protocol is a second protocol value, loading the to-be-processed data of the i-th round of function verification into the first memory address of the chip, the second protocol value being used to indicate that a protocol value of an interaction protocol between the electronic device and the chip is initialized.

3. The method of claim 1, wherein, After the loading, into the first memory address of the chip, of the to-be-processed data of the i-th round of function verification, the method further comprises: in a case where the loading of the to-be-processed data of the i-th round of function verification is completed, writing a third protocol value into a fifth memory address of the chip; wherein the fifth memory address is used to store a protocol value of a third interaction protocol, and the third protocol value is used to indicate that the chip starts function verification.

4. The method of claim 1, wherein, After the reading, from the third memory address of the chip, of the function verification result of the chip based on the to-be-processed data of the i-th round of function verification, the method further comprises: in a case where it is determined that the chip verification is not completed, writing a fourth protocol value into a sixth memory address of the chip; wherein the sixth memory address is used to store a protocol value of a fourth interaction protocol, and the fourth protocol value is used to indicate that an i+1-th round of function verification of the chip is started.

5. The method of claim 1, wherein, The reading, from the third memory address of the chip, of the function verification result of the chip based on the to-be-processed data of the i-th round of function verification comprises: reading a first data amount from a seventh memory address of the chip; reading data of the first data amount from the third memory address of the chip to obtain the function verification result.

6. The method of claim 1, wherein, After the loading, into the first memory address of the chip, of the to-be-processed data of the i-th round of function verification, the method further comprises: writing a second data amount of the to-be-processed data of the i-th round of function verification into an eighth memory address of the chip; wherein the second data amount is used to indicate an amount of data acquired by the chip from the first memory address.

7. A chip verification method applied to a chip, the chip being in communication connection with an electronic device, the method comprising: obtaining, from a first memory address of the chip, to-be-processed data of an i-th round of function verification of the chip, the to-be-processed data of the i-th round of function verification being loaded into the first memory address of the chip in a case where the electronic device is in communication connection with the chip and it is determined that the chip starts the i-th round of function verification, i being a positive integer; performing function verification based on the to-be-processed data of the i-th round of function verification, to obtain a function verification result; storing the function verification result into a third memory address of the chip; storing a first protocol value into a second memory address of the chip, the second memory address being used to store a protocol value of a first interaction protocol, the first protocol value being used to indicate that the function verification of the chip is completed; wherein the first protocol value stored in the second memory address is used to instruct the electronic device to read the function verification result from the third memory address.

8. The method of claim 7, wherein, Before the obtaining, from the first memory address of the chip, the to-be-processed data of the i-th round of function verification of the chip, the method further comprises: initializing a protocol value of an interaction protocol between the electronic device and the chip in the i-th round of function verification; in a case where the initialization of the protocol value of the interaction protocol between the electronic device and the chip is completed, storing a second protocol value into a fourth memory address of the chip; wherein the fourth memory address is used to store a protocol value of a second interaction protocol, the second protocol value being used to indicate that the initialization of the protocol value of the interaction protocol between the electronic device and the chip is completed, and the second protocol value stored in the second memory address is used to instruct the electronic device to load the to-be-processed data of the i-th round of function verification into the first memory address of the chip.

9. The method of claim 7, wherein, The obtaining, from the first memory address of the chip, the to-be-processed data of the i-th round of function verification of the chip comprises: in a case where a protocol value of a third interaction protocol stored in a fifth memory address of the chip is a third protocol value, obtaining the to-be-processed data of the i-th round of function verification from the first memory address of the chip; wherein the third protocol value is used to instruct the chip to start the function verification, and the third protocol value is written into the fifth memory address of the chip by the electronic device in a case where the loading of the to-be-processed data of the i-th round of function verification is completed.

10. The method of claim 7, wherein, After the writing of the first protocol value into the second memory address of the chip, the method further comprises: in a case where a protocol value of a fourth interaction protocol stored in a sixth memory address of the chip is a fourth protocol value, initializing the protocol value of the interaction protocol between the electronic device and the chip in an i+1-th round of function verification of the chip; wherein the fourth protocol value is used to instruct to start the i+1-th round of function verification of the chip, and the fourth protocol value is written into the sixth memory address by the electronic device in a case where it is determined that the function verification is not completed.

11. A chip verification apparatus, applied to an electronic device, the electronic device being in communication connection with a chip, the apparatus comprising: The loading module is configured to load the to-be-processed data of the i-th round of function verification into the first memory address of the chip when it is determined that the chip starts the i-th round of function verification, where i is a positive integer. The first reading module is configured to read a protocol value of a first interaction protocol from a second memory address of the chip. The second reading module is configured to read a function verification result of the to-be-processed data of the i-th round of function verification of the chip from a third memory address of the chip when the protocol value of the first interaction protocol is a first protocol value, where the first protocol value is used to indicate that the chip completes the i-th round of function verification.

12. The apparatus of claim 11, wherein, The second reading module is specifically configured to: read a first data amount from a seventh memory address of the chip; and read data of the first data amount from the third memory address of the chip to obtain the function verification result. 13.A chip verification apparatus applied to a chip, wherein the chip is in communication connection with an electronic device, and the apparatus comprises: an acquisition module configured to acquire to-be-processed data of an i-th round of function verification of the chip from a first memory address of the chip, wherein the to-be-processed data of the i-th round of function verification is loaded into the first memory address of the chip when it is determined that the chip starts the i-th round of function verification and the electronic device is in communication connection with the chip, where i is a positive integer; a function verification module configured to perform function verification based on the to-be-processed data of the i-th round of function verification to obtain a function verification result; a first storage module configured to store the function verification result into a third memory address of the chip; a second storage module configured to store a first protocol value into a second memory address of the chip, wherein the second memory address is used to store a protocol value of a first interaction protocol, and the first protocol value is used to indicate that the chip completes function verification; wherein the first protocol value stored in the second memory address is used to instruct the electronic device to read the function verification result from the third memory address. 14.An electronic device comprising a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the chip verification method according to any one of claims 1-6. 15.A chip comprising a processor and a memory, wherein the memory stores programs or instructions executable on the processor, and the programs or instructions are executed by the processor to implement the steps of the chip verification method according to any one of claims 7-10. 16.A readable storage medium, wherein the readable storage medium stores programs or instructions, and the programs or instructions are executed by a processor to implement the steps of the chip verification method according to any one of claims 1-6, or to implement the steps of the chip verification method according to any one of claims 7-10.

17. A computer program product, the program product being stored in a storage medium, the program product being executed by at least one processor to implement the steps of the chip verification method of any one of claims 1-6, or to implement the steps of the chip verification method of any one of claims 7-10.

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