Display screen refresh method and display driving apparatus

Abstract

A display screen refresh method and a display driving apparatus, which can improve the display effect of a display screen. The refresh method comprises: a display driving apparatus sequentially outputting a high-frequency clock signal and a timing signal to a display screen (S402), wherein the timing signal comprises a transition from a first level to a second level, and is used for driving the refresh of the display screen.

Description

Refresh method of display screen and display driving device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411395358.9, filed on September 30, 2024, and entitled "Refresh method of display screen and display driving device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, and in particular to a refresh method of display screen and a display driving device. BACKGROUND

[0004] Display technology, as an important component of information industry, has played a very important role in the development of information technology. The display driving device can drive the display of the display screen. For example, the display driving device outputs a timing signal through the gate driver on array (GOA) to drive the refresh of the display screen.

[0005] The level flip in the timing signal has a long time delay, which cannot meet the time requirement corresponding to the refresh rate of the display screen. Such a design is likely to cause abnormal display effect at the boundary of the display picture. SUMMARY

[0006] The present application provides a refresh method of display screen and a display driving device, which can improve the display effect.

[0007] In a first aspect, the present application provides a refresh method of display screen. The method is applied to a display driving device, for example, can be executed by the display driving device. The display driving device can be a display driving chip, or a component in the display driving chip, or a display driving integrated circuit. The method comprises: sequentially outputting a high-frequency clock signal and a timing signal to the display screen, the timing signal comprising a flip from a first level to a second level, and the timing signal being used to drive the refresh of the display screen.

[0008] Considering that the timing signal driving the refresh of the display screen in the prior art solution has a long time delay of level flip, which cannot meet the time requirement corresponding to the refresh rate of the display screen, the present application outputs the high-frequency clock signal before outputting the timing signal, which can shorten the time length of the level flip corresponding to the timing signal, so as to meet the high refresh rate requirement of the display screen, thereby improving the display effect.

[0009] In a possible design, the high-frequency clock signal comprises a pulse signal. For example, the pulse signal comprises a square wave, and / or the pulse signal comprises a sine wave. The pulse signal can accelerate the level transition of the timing signal.

[0010] In a possible design, the timing signal comprises a waveform that satisfies: transition from the first level to the second level, and maintaining the second level. For example, the first level is a low level, and the second level is a high level; or, the first level is a high level, and the second level is a low level. In addition, it can be understood that the higher the frequency of the high-frequency clock signal is, the shorter the transition time of the timing signal from the first level to the second level is.

[0011] In a possible design, the timing signal comprises a video synchronization signal VFE. For example, the display driving apparatus comprises a GOA, and the high-frequency clock signal and the timing signal are output by the GOA, and the timing signal can be understood as the VFE.

[0012] In a possible design, the display driving apparatus sequentially outputs the high-frequency clock signal and the timing signal to the display screen, comprising: sequentially outputting the high-frequency clock signal and the timing signal to a first display area on the display screen, so that the refresh rate of the first display area is greater than that of a second display area; and wherein the first display area and the second display area are adjacent on the display screen. Such a design can be applied to a scenario in which a local area of the same display screen has a high refresh rate requirement, and sequentially transmitting the high-frequency clock signal and the timing signal to drive display refresh can meet the refresh time requirement corresponding to the high refresh rate.

[0013] In a possible design, before sequentially outputting the high-frequency clock signal and the timing signal to the first display area on the display screen, the display driving apparatus further comprises: obtaining first information, the first information indicating that the refresh rate of the first display area is greater than that of the second display area. The display driving apparatus can be triggered to sequentially transmit the high-frequency clock signal and the timing signal to a specified area of the display screen by information indication, and can be applied to various display scenarios.

[0014] In a possible design, the display driving apparatus further comprises: generating the high-frequency clock signal by a clock module.

[0015] In a second aspect, the display driving apparatus can be a display driving chip or a component in the display driving chip. The display driving apparatus comprises a processing module and an output module. The processing module is configured to generate a high-frequency clock signal and a timing signal. The output module is configured to sequentially output the high-frequency clock signal and the timing signal to a display screen, the timing signal comprising a transition from a first level to a second level, and the timing signal being used to drive refresh of the display screen.

[0016] In a possible design, the high-frequency clock signal comprises a pulse signal.

[0017] In a possible design, a waveform of the timing signal satisfies: flipping from the first level to the second level and keeping the second level.

[0018] In a possible design, the higher the frequency of the high-frequency clock signal is, the shorter the flipping duration of the timing signal from the first level to the second level is.

[0019] In a possible design, the timing signal comprises a video synchronization signal VFE.

[0020] In a possible design, the output module is specifically configured to: sequentially output the high-frequency clock signal and the timing signal to a first display area on a display screen, so that a refresh rate of the first display area is greater than that of a second display area; and the first display area and the second display area are adjacent in position on the display screen.

[0021] In a possible design, the apparatus further includes an obtaining module configured to obtain first information, where the first information indicates that the refresh rate of the first display area is greater than that of the second display area.

[0022] In a possible design, the processing module is further configured to generate the high-frequency clock signal by using a clock module. In a third aspect, the present application provides an electronic device, including: a processor and a memory; the memory is configured to store one or more computer programs, and the one or more computer programs include computer execution instructions; when the computing device runs, the processor executes the one or more computer programs stored in the memory, so that the computing device executes the method in the first aspect and any design in the first aspect.

[0023] In a third aspect, the present application provides a communication device, including: a processor and a communication interface, the communication interface is configured to receive signals from other devices outside the communication device and transmit the signals to the processor or send signals from the processor to other devices outside the communication device, and the processor implements the method in the first aspect and any design in the first aspect by executing code instructions through a logic circuit.

[0024] In a fourth aspect, an embodiment of the present application provides a chip system, including: a processor and an interface. Wherein, the processor is configured to call and run instructions from the interface, and when the processor executes the instructions, the method in the first aspect and any design in the first aspect is implemented.

[0025] In a fifth aspect, an embodiment of the present application provides a computer readable storage medium for storing computer programs or instructions, when the computer programs or instructions are run by a processor, the method of the first aspect and any one of the designs of the first aspect is implemented.

[0026] In a sixth aspect, an embodiment of the present application provides a computer program product containing instructions, when it is run on a computer, the method of the first aspect and any one of the designs of the first aspect is implemented.

[0027] The beneficial effects of any of the technical solutions of the second aspect to the sixth aspect can be referred to the beneficial effects of the corresponding technical solutions in the first aspect, and the repeated parts will not be listed here. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a structural schematic diagram of an electronic device;

[0029] FIG. 2A is a structural schematic diagram of a display driver chip DDIC;

[0030] FIG. 2B is a schematic diagram of the generation and output process of a timing signal;

[0031] FIG. 3 is a waveform schematic diagram of a timing signal;

[0032] FIG. 4 is a flow schematic diagram of a refresh method of a display screen provided by an embodiment of the present application;

[0033] FIG. 5A is a waveform schematic diagram of a high-frequency clock signal combined with a timing signal;

[0034] FIG. 5B is a waveform schematic diagram of a high-frequency clock signal combined with a timing signal;

[0035] FIG. 6A is a waveform schematic diagram of a high-frequency clock signal combined with a timing signal;

[0036] FIG. 6B is a waveform schematic diagram of a high-frequency clock signal combined with a timing signal;

[0037] FIG. 7A is a waveform schematic diagram of a high-frequency clock signal combined with a timing signal;

[0038] FIG. 7B is a waveform schematic diagram of a high-frequency clock signal combined with a timing signal;

[0039] FIG. 8 is a distribution schematic diagram of a display screen provided by an embodiment of the present application;

[0040] FIG. 9 is a flow schematic diagram of a refresh method of a display screen provided by an embodiment of the present application;

[0041] FIG. 10 is a distribution schematic diagram of another display screen provided by an embodiment of the present application;

[0042] FIG. 11 is a structural schematic diagram of a display driving apparatus according to an embodiment of the present application;

[0043] FIG. 12 is a structural schematic diagram of a chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings.

[0045] At least one (item) referred to in the present application indicates one (item) or more (items). More (items) refers to two (items) or more than two (items). "And / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the front and rear associated objects. In addition, it should be understood that although the terms first, second, etc. may be used to describe various objects in the present application, these objects should not be limited by these terms. These terms are only used to distinguish each object from each other.

[0046] The terms "include" and "have" and any variations thereof mentioned in the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include other steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device. It should be noted that the words "exemplary" or "for example" in the present application are used to represent an example, illustration or description. Any method or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other methods or design schemes. On the contrary, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific way.

[0047] FIG. 1 shows an electronic device according to an embodiment of the present application. The electronic device 100 includes a display driving apparatus 101 and a display screen 102.

[0048] The display driving apparatus 101 can be any chip or integrated circuit with display driving capability, and is used to drive and control the display of the display screen 102. In the embodiments of the present application, the display driving apparatus 101 can be arranged independently of the display screen 102, or the display driving apparatus 101 can be arranged in the display screen 102.

[0049] The display driving apparatus 101 involved in the present application can be a display driver IC (DDIC) or other driving chip or driving integrated circuit. The display screen 102 can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light emitting diode (AMOLED), a flex light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-oLed, a quantum dot light emitting diodes (QLED), etc. In some embodiments, the electronic device 100 can include one or N display screens, where N is a positive integer greater than 1.

[0050] It can be understood that the display driving apparatus can also be alternatively described as a display driving module, a display driving unit, a display driving circuit, a driving apparatus, a driving module, a driving unit, or other names; and the display screen can also be alternatively described as a display panel, a display module, a display unit, a display apparatus, or other names, which are not limited in the embodiments of the present application.

[0051] The display driving apparatus is taken as a DDIC as an example for description below. The DDIC outputs driving signals and data to the display screen in the form of electrical signals to control the brightness and color of the screen, so that image information such as letters and pictures can be displayed on the screen. As shown in FIG. 2A, the DDIC includes a source driver (Source IC), a gate driver (Gate IC), a timing controller (TCON), and a power management IC (PMIC). The display power management IC is responsible for the power management of the entire display system to ensure efficient use and energy saving of the device. The TCON is responsible for managing the refresh rate, frame rate, and scanning sequence of the display screen, and controls the operation of the source driver and the gate driver to ensure the correctness and efficiency of the screen display. The source driver (Source IC) controls the brightness, gray scale, color, etc. of a single pixel point on the display screen through voltage. The gate driver (Gate IC) is responsible for the switching of each column of transistors, and only when the transistor is turned on, the source driver can control the brightness, gray scale, color, etc. of a single pixel point through voltage. The gate driver involved in the embodiments of the present application is implemented by GOA technology.

[0052] In a possible implementation, the display driving apparatus 101 can further comprise a memory for storing instructions and data. For example, the memory can pre-store program instructions and display-related control parameters such as brightness, color, gray scale, refresh rate, display effect requirement, etc. Then, when the display driving apparatus 101 drives the display screen 102 to dynamically display the image information to be displayed, the TCON can run the program instructions according to the control parameters in the memory to correctly control the operation of the source driver and the gate driver.

[0053] In a possible implementation, the electronic device comprises a processor, and the display driving apparatus 101 can receive display-related control parameters from the processor and store the parameters in the memory. The processor can be any chip or integrated circuit with computing capability. For example, the processor can be an application processor (AP), a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), other programmable logic devices, transistor logic devices, or any combination thereof. The general-purpose processor can be a microprocessor, for example, a micro controller unit (MCU), or can also be other conventional processors. The processor can comprise one or more processing units, and different processing units can be independent devices or integrated in one or more processors.

[0054] It can be understood that the processor can also be referred to as a processing module, a processing circuit, or other names; and the memory can also be referred to as a storage module, a storage unit, or other names, which are not limited in the embodiments of the present application.

[0055] The electronic device 100 described above can be a portable electronic device comprising functions such as a personal digital assistant and / or a music player, for example, a mobile phone, a tablet computer, a wearable device (for example, a smart watch) with wireless communication function, etc. Exemplary embodiments of the portable electronic device include, but are not limited to, mobile phones, tablet computers, smart watches, and the like. or other operating systems. The portable electronic device described above can also be other portable electronic devices, such as a laptop having a touch-sensitive surface (e.g., a trackpad) and / or the like. It should also be understood that, in some other embodiments of the present application, the electronic device described above can also not be a portable electronic device, but a desktop computer having a touch-sensitive surface (e.g., a trackpad), and the embodiments of the present application are not limited in this regard.

[0056] Currently, the DDIC can output a timing signal to drive the refresh of the display screen in addition to controlling the switching of the transistor through the GOA. For example, the timing signal is used to power the display screen to drive the refresh of the display screen. As shown in FIG. 2B, the generation and output process of the timing signal is as follows: the TCON converts the control parameter into an analog signal (such as a low-voltage signal), and the low-voltage signal is converted into a high-voltage signal through a level shifter (LVS), and then the high-voltage signal is output through the GOA. The high-voltage signal can be understood as a timing signal used to drive the refresh of the display screen.

[0057] As shown in (a) of FIG. 3, the waveform of the timing signal can satisfy: after flipping from low level to high level, maintaining high level; or as shown in (b) of FIG. 3, the waveform of the timing signal can satisfy: after flipping from high level to low level, maintaining low level. Wherein, the time length between t1 and t2 in FIG. 3 indicates the level flip time length of the timing signal. If the level flip time length of the timing signal exceeds the effective frame time of the display screen, it does not meet the time requirement corresponding to the refresh rate of the display screen, and is easy to cause abnormal display effect of the display screen boundary.

[0058] Based on this, the embodiments of the present application provide a display screen refresh method, which can shorten the level flip time of the timing signal, meet the time requirement corresponding to the refresh rate of the display screen, and thus improve the display effect.

[0059] FIG. 4 is an implementation flow of the method provided by the embodiments of the present application, mainly including the following steps.

[0060] S401, the display driving device generates a high-frequency clock signal and a timing signal.

[0061] Taking the display driving device as an example, the TCON and the LVS are deployed in the DDIC. The TCON can insert the high-frequency clock signal before converting the control parameter into the low-voltage signal, and then obtain the high-frequency clock signal and the timing signal after the voltage conversion of the LVS, and the high-frequency clock signal is in front and the timing signal is in back in time.

[0062] The waveform of the timing signal can satisfy a flip from a first level to a second level and a keeping of the second level. As the timing signal described above, the first level is a low level and the second level is a high level, or the first level is a high level and the second level is a low level. In the embodiment of the application, the actual voltage corresponding to the level ranges from -16v to +16v. In a possible design, the TCON can determine the actual voltage value corresponding to the second level according to the control parameter. For example, the TCON reads the target voltage of +12v of the display effect requirement of the display screen from the memory, and the actual voltage value corresponding to the second level is +12v. The actual voltage value corresponding to the first level can be preset, for example, 0v, -16v or other initial voltage value, which is not limited in the embodiment of the application.

[0063] The high-frequency clock signal can be used to accelerate the flip of the timing signal from the first level to the second level, or can be understood as that the high-frequency clock signal is added before the timing signal to accumulate the electric charge to shorten the flip time length of the timing signal. In addition, it can be understood that the higher the frequency of the high-frequency clock signal is, the shorter the flip time length of the timing signal from the first level to the second level is. In a possible implementation, the TCON can generate the high-frequency clock signal by using a clock module.

[0064] In a possible implementation, the high-frequency clock signal can include a pulse signal. Optionally, the TCON can determine the frequency, pulse quantity and other parameters of the pulse signal according to the display-related control parameter, or determine the frequency, pulse quantity and other parameters of the pulse signal according to the power consumption cost related to the frequency of the pulse signal. For example, the TCON sets the parameters of the pulse signal according to the refresh rate required by the display screen, so that the flip time length is less than the effective frame time of the display screen.

[0065] Exemplarily, the waveforms of the pulse signals included in the high-frequency clock signal can all be rectangular waves, or square waves. FIG. 5A schematically shows that the display driving apparatus generates the square wave pulse signal and the timing signal in sequence, and the timing signal shows a flip from a low level to a high level and a keeping of the high level. FIG. 5B schematically shows that the display driving apparatus generates the square wave pulse signal and the timing signal in sequence, and the timing signal shows a flip from a high level to a low level and a keeping of the low level.

[0066] Exemplarily, the waveforms of the pulse signals included in the high-frequency clock signal can all be sine waves. FIG. 6A schematically shows that the display driving apparatus generates the sine wave pulse signal and the timing signal in sequence, and the timing signal shows a flip from a low level to a high level and a keeping of the high level. FIG. 6B schematically shows that the display driving apparatus generates the sine wave pulse signal and the timing signal in sequence, and the timing signal shows a flip from a high level to a low level and a keeping of the low level.

[0067] Exemplarily, the waveform of the pulse signal included in the high-frequency clock signal can be both a sine wave and a square wave. Alternatively, the number and position of the sine wave in the high-frequency clock signal can be pre-configured in the memory of the display driving apparatus, or can be specified by the processor of the electronic device, and the embodiments of the present application do not limit this. FIG. 7A schematically shows that the display driving apparatus generates the pulse signal and the timing signal in sequence, and the timing signal is flipped from low to high and high. FIG. 7B schematically shows that the display driving apparatus generates the pulse signal and the timing signal in sequence, and the timing signal is flipped from high to low and low. The waveform of the pulse signal in FIG. 7A and FIG. 7B includes a sine wave and a square wave.

[0068] S402, the display driving apparatus sequentially outputs the high-frequency clock signal and the timing signal to the display screen.

[0069] Corresponding to the DDIC exemplified in S401, the DDIC can sequentially output the high-frequency clock signal and the timing signal to the display screen through the GOA. It can be understood that the timing signal is used to drive the refresh of the display screen. For example, the timing signal is used to provide power supply for the display screen to drive the refresh of the display screen.

[0070] Alternatively, the timing signal mentioned above in the embodiments of the present application can also be described as a video front-end (VFE) signal, and the timing signal output by the GOA can also be described as a GOA VFE signal, and the embodiments of the present application do not limit this.

[0071] The above method of outputting the high-frequency clock signal (pulse signal) before outputting the timing signal (VFE signal) can shorten the establishment process of the timing signal, thereby meeting the high refresh rate requirement of the display screen and improving the display effect. The application scenarios of the method are as follows: the electronic device only includes one display screen, and the display screen requires a high refresh rate, for example, 120Hz; or the electronic device includes multiple display screens, and the multiple display screens include display screens requiring a high refresh rate and display screens requiring a low refresh rate, and the display driving apparatus can specifically sequentially output the high-frequency clock signal and the timing signal to the display screen requiring a high refresh rate. As shown in FIG. 8, the electronic device includes three electronic screens, the refresh rate of the electronic screen 1 among the three electronic screens is a high refresh rate, and the refresh rates of the other two electronic screens (electronic screen 2 and electronic screen 3) are low refresh rates. Alternatively, the high refresh rate described in the embodiments of the present application is greater than or equal to 60Hz, for example, the high refresh rate can be 90Hz, 120Hz or 240Hz. The low refresh rate is less than 60Hz, for example, the low refresh rate can be 30Hz.

[0072] In addition, it can be understood that, corresponding to multiple display screens with high refresh rate requirements but different refresh rate values, the display driving apparatus outputs high-frequency clock signals with different frequencies, pulse numbers, and other parameters to different display screens.

[0073] FIG. 9 is another implementation flow of the method provided by the embodiments of the present application, mainly including the following steps.

[0074] S901, the display driving apparatus acquires first information indicating that a refresh rate of a first display region on the display screen is greater than a refresh rate of a second display region.

[0075] For example, the display driving apparatus acquires the first information from a processor in the electronic device. The first display region and the second display region are adjacent in position on the display screen. For example, FIG. 10 shows that a display screen is divided into three display regions from top to bottom, which are respectively denoted as region 1, region 2, and region 3. The refresh rate of the region 2 is greater than the refresh rates of the region 1 and the region 3. For example, the refresh rate of the region 2 is 120 Hz, and the refresh rates of the region 1 and the region 3 are 60 Hz. The region 2 can be understood as an example of the first display region, and the region 1 and the region 3 can be understood as two examples of the second display region.

[0076] Optionally, the first display region can be preconfigured to be a display region with a refresh rate higher than that of an adjacent display region, and the configuration can be stored in a memory of the display driving apparatus. Thus, the display driving apparatus can not perform S901, and directly read the memory to determine the first display region. It can be understood that S901 is an optional step, which is shown in dashed lines in FIG. 9.

[0077] S902, the display driving apparatus generates a high-frequency clock signal and a timing signal.

[0078] This step can be implemented by referring to the description in S401, and the embodiments of the present application do not make further description.

[0079] S903, the display driving apparatus sequentially outputs the high-frequency clock signal and the timing signal to the first display region of the display screen.

[0080] This step can be implemented by referring to the description in S402, and the embodiments of the present application do not make further description. This step can achieve that the refresh rate of the first display region is greater than the refresh rate of the second display region.

[0081] In the above method, the high-frequency clock signal is output before the timing signal is output, which can shorten the establishment process of the timing signal, so as to meet the high refresh rate requirement of part of the display screen and improve the display effect.

[0082] In addition, it can be understood that, corresponding to the multiple display areas with high refresh rate requirements but different refresh rate values, the display driving device outputs high-frequency clock signals with different frequencies, pulse numbers, and other parameters to different display areas.

[0083] Based on the same idea, referring to FIG. 11, the embodiment of the present application further provides a signal display driving device 1100. The signal processing device 1100 includes a processing module 1101 and an output module 1102. The processing module 1101 and the output module 1102 can be implemented in the form of a processor calling software; for example, the device includes a processor, the processor is connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or to implement the functions of the units of the device, wherein the processor is, for example, a general-purpose processor such as a central processing unit (CPU) or a microprocessor, and the memory is an internal memory of the device or an external memory of the device. Alternatively, the processing module 1101 and the output module 1102 can be implemented in the form of a hardware circuit, and the functions of part or all of the units can be implemented by designing the hardware circuit. The hardware circuit can be understood as one or more processors; for example, in one implementation, the hardware circuit is an application-specific integrated circuit (ASIC), and the functions of part or all of the units are implemented by designing the logical relationship of elements in the circuit; for example, in another implementation, the hardware circuit is a programmable logic device (PLD), and a field programmable gate array (FPGA) is taken as an example, which can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by a configuration file, so as to implement the functions of part or all of the units. All units of the above device can be implemented in the form of a processor calling software, or all units can be implemented in the form of a hardware circuit, or part of the units can be implemented in the form of a processor calling software, and the remaining part can be implemented in the form of a hardware circuit.

[0084] The processing module 1101 is configured to generate a high-frequency clock signal and a timing signal; and the output module 1102 is configured to sequentially output the high-frequency clock signal and the timing signal to a display screen, the timing signal includes a flip from a first level to a second level, and the timing signal is used to drive the refresh of the display screen.

[0085] Based on the same technical concept, the embodiment of the present application further provides a chip, as shown in FIG. 12, which comprises at least one processor 1201 and a communication interface 1203. In an optional design, a memory 1202 can also be included. In the chip 1200, the processor 1201 can perform data transmission through the communication interface 1203 when communicating with other devices. The processor 1201 in FIG. 12 can invoke computer execution instructions stored in the memory 1202, so that the chip 1200 can execute any of the above method embodiments.

[0086] In a possible implementation, the processor 1201 can be coupled with the memory 1202 through the interface 1203. The specific connection medium between the processor 1201 and the memory 1202 in the embodiment of the present application is not limited. For example, it can be a bus 1204.

[0087] In another possible implementation, the chip can also directly include the memory 1202, which stores computer programs or computer instructions. For example, the memory 1202 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically EPROM (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink DRAM (SLDRAM) and direct memory bus random access memory (DR RAM).

[0088] In a possible implementation, the embodiment of the present application provides a computer readable storage medium, which stores program codes, and when the program codes are executed on the computer, the computer executes the method embodiment.

[0089] In a possible implementation, the embodiment of the present application provides a computer program product, which, when executed on a computer, enables the computer to execute the method embodiment.

[0090] It should be understood that all related contents of each step involved in the above method embodiment can be cited to the function description of the corresponding function module, and will not be repeated here.

[0091] The method steps in the embodiments of the present application can be realized by means of hardware, or by means of the processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically programmable read-only memory, a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a base station or a terminal. Of course, the processor and the storage medium can also exist as discrete components in the base station or the terminal.

[0092] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are performed. The computer can be a general purpose computer, a special purpose computer, a computer network, a network device, a user equipment or other programmable apparatus. The computer programs or instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer programs or instructions can be transferred from one website site, computer, server or data center to another website site, computer, server or data center through wired or wireless manner. The computer readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center and the like integrated with one or more available media. The available media can be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; an optical medium, such as a digital video disc; a semiconductor medium, such as a solid state disk. The computer readable storage medium can be a volatile or non-volatile storage medium, or can include both volatile and non-volatile storage media.

[0093] In various embodiments of the present application, the terms and / or descriptions of different embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship.

[0094] It can be understood that various numerical numbers involved in the embodiments of the present application are only used for differentiation for convenience of description, and are not used to limit the scope of the embodiments of the present application. The size of the serial number of the above processes does not mean the execution order, and the execution order of the processes should be determined according to their functions and inherent logic.

Claims

1. A method of refreshing a display screen, characterized by, Applied to a display driving device, comprising: Outputting a high-frequency clock signal and a timing signal to a display screen in sequence, the timing signal including a flip from a first level to a second level, the timing signal being used to drive refresh of the display screen.

2. The method of claim 1, wherein, The high-frequency clock signal includes a pulse signal.

3. The method of claim 1 or 2, wherein, The waveform of the timing signal satisfies: Flip from the first level to the second level and keep the second level.

4. The method according to any one of claims 1 to 3, characterized in that, The higher the frequency of the high-frequency clock signal, the shorter the flip duration of the timing signal from the first level to the second level.

5. The method according to any one of claims 1 to 4, characterized in that, The timing signal includes a video synchronization signal VFE.

6. The method according to any one of claims 1 to 5, wherein, The outputting of the high-frequency clock signal and the timing signal to the display screen in sequence comprises: Outputting the high-frequency clock signal and the timing signal to a first display area on the display screen in sequence, so that the refresh rate of the first display area is greater than that of a second display area; wherein the first display area and the second display area are adjacent in position on the display screen.

7. The method of claim 6, wherein, Before outputting the high-frequency clock signal and the timing signal to the first display area on the display screen in sequence, further comprising: Obtaining first information indicating that the refresh rate of the first display area is greater than that of the second display area.

8. The method according to any one of claims 1 to 7, wherein Further comprising: Generating the high-frequency clock signal by a clock module.

9. A display driving device, characterized by comprising: Comprising: A processing module for generating a high-frequency clock signal and a timing signal; An output module for outputting the high-frequency clock signal and the timing signal to a display screen in sequence, the timing signal including a flip from a first level to a second level, the timing signal being used to drive refresh of the display screen.

10. The apparatus of claim 9, wherein, The high-frequency clock signal includes a pulse signal.

11. The apparatus of claim 9 or 10, wherein, The waveform of the timing signal satisfies: Flip from the first level to the second level and keep the second level.

12. The device of any one of claims 9-11, wherein, The higher the frequency of the high-frequency clock signal, the shorter the flip duration of the timing signal from the first level to the second level.

13. The apparatus of any one of claims 9-12, wherein, The timing signal includes a video synchronization signal VFE.

14. The apparatus of any one of claims 9-13, wherein, The output module is specifically configured to: Output the high-frequency clock signal and the timing signal to a first display area on the display screen in sequence, so that the refresh rate of the first display area is greater than that of a second display area; wherein the first display area and the second display area are adjacent in position on the display screen.

15. The apparatus of claim 14, wherein, Further comprising: An obtaining module for obtaining first information indicating that the refresh rate of the first display area is greater than that of the second display area.

16. The apparatus of any one of claims 9-15, wherein, The processing module is further configured to generate the high-frequency clock signal by a clock module.

17. An electronic device, comprising: Comprising: A processor and a memory; The memory is configured to store one or more computer programs, the one or more computer programs including computer execution instructions, when the computing device is running, the processor executes the one or more computer programs stored in the memory, so that the computing device executes the method as claimed in any one of claims 1-8.

18. A communication device, comprising: Comprising: a processor and a communication interface for receiving signals from other devices outside the communication device and transmitting to the processor or sending signals from the processor to other devices outside the communication device, the processor implementing the method of any one of claims 1-8 by executing code instructions through a logic circuit.

19. A computer-readable storage medium, characterized in that, The storage medium has stored therein a computer program or instructions, which, when executed by a processor, cause the method of any one of claims 1-8 to be performed.

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