Synchronous serial communication system, synchronous serial communication module, synchronous serial communication method and computer readable storage medium

Abstract

The invention provides a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method and a computer readable storage medium. The synchronous serial communication system includes: a host configured to provide a clock signal; and a plurality of cascaded slave machines, each slave machine comprises a first serial interface and a second serial interface, the first slave machine is coupled to the host machine through the first serial interface, for adjacent slave machines, the second serial interface of the upstream slave machine is coupled with the first serial interface of the downstream slave machine, and the second serial interface of the downstream slave machine is coupled with the first serial interface of the downstream slave machine. Each slave synchronously receives a clock signal from the host through the first serial interface and the second serial interface. According to the synchronous serial communication system, the SPI only communicates between the host and the first slave and between the two adjacent slaves, the number of the slaves is not limited by the number of chip selection signals provided by the SPI host, the communication speed is not limited by the farthest distance slave, the communication speed is not limited by the number of the slaves, the communication speed can be increased, and the communication efficiency is improved. The communication efficiency is improved.

Description

Technical Field

[0001] This invention relates generally to the field of communication technology, and in particular to a synchronous serial communication system, a synchronous serial communication module, a synchronous serial communication method, and a computer-readable storage medium. Background Technology

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus. SPI employs a master-slave architecture, consisting of one master and multiple slaves. Each slave has an SPI interface, and the master's SPI interface polls each slave's SPI interface, thus enabling communication between the master and slaves. This communication method has two drawbacks: first, if each SPI slave is selected using a chip select signal, the number of slaves is limited by the number of chip select signals the SPI master can provide; second, if each slave is cascaded through a single SPI interface, the communication speed is limited by the number of slaves—the more slaves, the slower the communication speed, and communication latency accumulates. Therefore, a new synchronous serial communication system and method are urgently needed to overcome these drawbacks.

[0003] The content of the background section is merely the technology known to the inventor and does not necessarily represent the prior art in this field. Summary of the Invention

[0004] To address one or more of the problems existing in the prior art, the present invention provides a synchronous serial communication system, comprising: a host configured to provide a clock signal; and a plurality of cascaded slave devices, wherein each slave device includes a first serial interface and a second serial interface, a first slave device being coupled to the host device through the first serial interface, and for adjacent slave devices, the second serial interface of an upstream slave device being coupled to the first serial interface of a downstream slave device, wherein each slave device synchronously receives the clock signal from the host device through the first serial interface and the second serial interface.

[0005] Optionally, the host includes a host clock interface, a host data output interface, and a host data input interface. The first serial interface includes a first slave clock interface, a first slave data input interface, and a first slave data output interface. The second serial interface includes a second slave clock interface, a second slave data output interface, and a second slave data input interface. The first slave clock interface, the first slave data input interface, and the first slave data output interface of the first slave are respectively connected to the host clock interface, the host data output interface, and the host data input interface of the host. For adjacent slaves, the second slave clock interface, the second slave data output interface, and the second slave data input interface of the second serial interface of the upstream slave are respectively coupled to the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first serial interface of the downstream slave.

[0006] Optionally, the first slave clock interface and the second slave clock interface of each slave are coupled to the host clock interface of the host to receive the clock signal synchronously.

[0007] Optionally, the host includes a host control chip, each slave includes a slave control chip, and the slave control chip of each slave is coupled to the host control chip and coupled to its respective first serial interface and second serial interface.

[0008] Optionally, the plurality of slave devices includes at least two slave devices.

[0009] Optionally, the received information of the downstream slave device is forwarded to the downstream slave device through its upstream slave device.

[0010] Optionally, the received information of the slave device includes its operating mode information and the operating mode information of its downstream slave devices.

[0011] Optionally, the received information of the slave device may also include its IO output data and the IO output data of its downstream slave devices.

[0012] Optionally, the information sent by the downstream slave device is forwarded to the host device via its upstream slave devices.

[0013] Optionally, the information transmitted by the slave device includes its own parameter information and the own parameter information of its downstream slave devices; and / or its operating status information and the operating status information of its downstream slave devices.

[0014] Optionally, the information transmitted by the slave device may also include its IO input data and the IO input data of its downstream slave devices.

[0015] Optionally, the transmission information of the slave device further includes termination information, which is received through the second data input interface of the last slave device, sent to its first data output interface through the slave control chip of the last slave device, and forwarded to the master device through its upstream slave devices.

[0016] Optionally, the host is configured to receive the self-parameter information and the termination information, and determine the number of slave devices based on the self-parameter information and the termination information.

[0017] The present invention also provides a synchronous serial communication module, comprising: a first serial interface adapted to connect to a host or an upstream serial communication module; a second serial interface adapted to connect to a downstream serial communication module, wherein a first slave clock interface of the first serial interface and a second slave clock interface of the second serial interface are also adapted to connect to a host to synchronously receive a clock signal provided by the host.

[0018] The present invention also provides a synchronous serial communication method, which is executed by the synchronous serial communication system described above.

[0019] The present invention also provides a computer-readable storage medium including computer-executable instructions stored thereon, wherein the executable instructions, when executed by a processor, implement the synchronous serial communication method as described above.

[0020] The synchronous serial communication system of this invention has a clock controlled by the master. Each slave device includes two SPI interfaces, both operating in slave mode and capable of synchronously receiving clock signals. For adjacent slave devices, one SPI interface can communicate with the preceding slave device, and the other SPI interface can communicate with the following slave device. SPI communication only occurs between the master and the first slave device, and between two adjacent slave devices. Therefore, the number of slave devices is not limited by the number of chip select signals that the SPI master can provide, and the communication speed is not limited by the furthest slave device or the number of slave devices, thus improving communication speed and efficiency. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0022] Figure 1 A schematic diagram of the existing PLC and expansion module SPI communication topology is shown.

[0023] Figure 2 A schematic diagram of the topology of a synchronous serial communication system according to some embodiments of the present invention is shown.

[0024] Figure 3 A schematic diagram comparing the communication rates of the present invention with those of existing SPI systems is shown.

[0025] Figure 4 A schematic diagram of a synchronous serial communication system according to some preferred embodiments of the present invention is shown.

[0026] Figure 5 A schematic diagram illustrating the transmission process of a slave device receiving and / or sending information according to some embodiments of the present invention is shown.

[0027] Figure 6 A schematic diagram illustrating the transmission process of a slave device receiving and / or sending information according to other embodiments of the present invention is shown.

[0028] Figure 7 A schematic diagram of a synchronous serial communication system according to some other preferred embodiments of the present invention is shown.

[0029] Figure 8 A schematic diagram illustrating the transmission process of receiving and / or sending information according to some embodiments of the present invention is shown.

[0030] Figure 9 A schematic diagram illustrating the transmission process of receiving and / or sending information according to further embodiments of the present invention is shown.

[0031] Figure 10 A schematic diagram of a host-to-slave data transmission process according to some embodiments of the present invention is shown.

[0032] Figure 11 A schematic diagram of a slave-to-master data reception process according to some embodiments of the present invention is shown.

[0033] Figure 12 A schematic diagram of the communication delay between MOSI and MISO is shown.

[0034] Figure 13 A schematic diagram of a synchronous serial communication module according to some embodiments of the present invention is shown. Detailed Implementation

[0035] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0036] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0039] The following provides many different embodiments or examples for implementing various structures of the invention. To simplify the invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0040] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0041] For Programmable Logic Controllers (PLCs), their I / O channels can be expanded by installing expansion modules. In most cases, SPI is a good solution for the communication bus between the PLC and its expansion modules. Figure 1 A schematic diagram of an existing PLC and expansion module SPI communication topology is shown. Figure 1 As shown, the PLC is the master, and Sx (x = 1, 2, 3…n) are expansion modules (i.e., slaves). Each expansion module uses a slave SPI interface to communicate with the PLC. The communication method is that the PLC's SPI master polls the SPI interface of each expansion module, polling the clock, MOSI (master-output, slave-in) signal lines, and MISO (master-in, slave-output) signal lines. If each SPI slave is selected using a chip select signal, the number of slaves will be limited by the number of chip select signals that the SPI master can provide. If each slave is cascaded through a single SPI interface, the communication speed will be limited by the number of slaves; the more slaves there are, the slower the communication speed, and the communication delay will accumulate. Therefore, the SPI communication speed should be set slow enough to allow the master to communicate with the slave at the furthest distance.

[0042] Traditionally, the speed of expansion modules Sx (x = 1, 2, 3…n) is fixed and low enough that the PLC can successfully communicate with the last expansion module Sn. In this case, there are two main constraints:

[0043] 1) SPI performance cannot be fully realized. Even though the maximum speed of the SPI bus can reach 40MHz, the actual speed of the PLC is less than 4MHz, around 1MHz or 2MHz due to communication latency. Each expansion module has a specific latency, and the more expansion modules installed, the more the communication latency accumulates. Therefore, the communication speed is limited by the number of expansion module nodes. The traditional solution is to set the communication speed as low as possible until the PLC can tolerate the maximum latency when communicating with its last expansion module, Sn.

[0044] 2) Performance cannot be fully realized when expansion requires high communication speeds. In some cases, some expansion modules require very high communication speeds. For example, for motion modules, precise control of position or speed may require a communication rate of 6MHz or higher. If the PLC always uses the same low speed for communication, motion performance will be affected.

[0045] To address the aforementioned shortcomings, this invention proposes a novel synchronous serial communication system. This is described in detail below.

[0046] Figure 2 A schematic diagram of the topology of a synchronous serial communication system 10 according to some embodiments of the present invention is shown. Figure 2 As shown, the synchronous serial communication system 10 includes a master M (e.g., a PLC) and multiple cascaded slave devices S1 to Sn, where n is a positive integer. The master M is configured to provide a clock signal. Each slave device includes a first serial interface SPI1 and a second serial interface SPI2. The first slave device S1 is coupled to the master M through the first serial interface SPI1. For adjacent slave devices S, the second serial interface SPI2 of the upstream slave device is coupled to the first serial interface SPI1 of the downstream slave device. For example, the second serial interface SPI2 of slave device S1 is coupled to the first serial interface SPI1 of slave device S2. Each slave device synchronously receives the clock signal from the master M through the first serial interface SPI1 and the second serial interface SPI2. In the synchronous serial communication system of the present invention, the clock is controlled by the master device, and each slave device includes two SPI interfaces, both of which operate in slave mode and can synchronously receive the clock signal. For adjacent slave devices, one SPI interface can communicate with the preceding slave device, and the other SPI interface can communicate with the following slave device. SPI only communicates between the master and the first slave, and between two adjacent slaves. Therefore, the number of slaves is not limited by the number of chip select signals that the SPI master can provide, the communication speed is not limited by the furthest slave, and it is not limited by the number of slaves, which can improve communication speed and efficiency.

[0047] Figure 3 A schematic diagram comparing the communication rates of this invention with existing SPI protocols is shown. For example... Figure 3 As shown, in some existing embodiments, the communication speed f1 (e.g., 1-2 MHz) is limited by the number of slave devices n, while the communication speed f2 of the present invention is not limited by the number of slave devices n, and can reach up to 20 MHz, which is about 10 times faster than 2 MHz. For motion modules, high-speed communication can be achieved, which helps to achieve precise control of position or speed, thereby improving motion performance.

[0048] Figure 4 A schematic diagram of a synchronous serial communication system 20 according to some preferred embodiments of the present invention is shown. For example... Figure 4 As shown, the synchronous serial communication system 20 includes a master unit M and multiple slave units, with the multiple slave units including at least two slave units ( Figure 4 Two slave devices (S1 and S2) are illustrated exemplarily. The master device M includes a master control chip C1, and each slave device includes a slave control chip C2. The slave control chip C2 of each slave device is coupled to the master control chip C1 (e.g., coupled to the master clock interface CLK of the master control chip C1), and also coupled to its respective first serial interface SPI1 and second serial interface SPI2. The master device M also includes a master clock interface CLK, a master data output interface SDO, and a master data input interface SDI. The first serial interface SPI1 includes a first slave clock interface CLK1, a first slave data input interface IN1, and a first slave data output interface OUT1. The second serial interface SPI2 includes a second slave clock interface CLK2, a second slave data output interface OUT2, and a second slave data input interface IN2. The first slave clock interface CLK1, the first slave data input interface IN1, and the first slave data output interface OUT1 of the first slave device S1 are respectively connected to the master clock interface CLK, the master data output interface SDO (or MOSI), and the master data input interface SDI (or MISO) of the master device M. Furthermore, for adjacent slave devices, the second slave clock interface CLK2, second slave data output interface OUT2, and second slave data input interface IN2 of the second serial interface SPI2 of the upstream slave device (e.g., slave S1) are respectively coupled to the first slave clock interface CLK1, first slave data input interface IN1, and first slave data output interface OUT1 of the first serial interface SPI1 of the downstream slave device (e.g., slave S2). The first slave clock interface CLK1 and second slave clock interface CLK2 of each slave device are coupled to the master clock interface CLK of the master device M to synchronously receive clock signals. It should be noted that... Figure 4 Two slave devices are illustrated as an example, but the present invention is not limited thereto. Examples of three, four, five, or more slave devices are similar, and all of these are within the scope of protection of the present invention.

[0049] The following example, using two or three slave devices, illustrates the process of receiving and / or sending information. It should be understood that the process is similar for examples involving more than one slave device.

[0050] In some embodiments, the received information of a downstream slave device is forwarded to that downstream slave device via its upstream slave device. Figure 5 A schematic diagram illustrating the transmission process of a slave device receiving and / or sending information according to some embodiments of the present invention is shown. Figure 5 As shown, a synchronous serial communication system includes, for example, two slave devices, slave S1 and slave S2, wherein the received information of slave S2 is forwarded to slave S2 via slave S1. Figure 6 A schematic diagram illustrating the transmission process of a slave device receiving and / or sending information according to other embodiments of the present invention is shown. Figure 6 As shown, a synchronous serial communication system includes, for example, three slave devices, namely slave S1, slave S2 and slave S3. The information received by slave S3 is forwarded to slave S2 via slave S1, and then forwarded to slave S3 by slave S2.

[0051] In some embodiments, the received information of the slave device includes its operating mode information and the operating mode information of its downstream slave devices. Specifically, for example, such as... Figure 5 As shown, the host M sends the operating mode information of slaves S1 to S2 to slave S1. Slave S1 receives the operating mode information of slaves S1 to S2 and forwards the operating mode information of slave S2 to slave S2. For example, as... Figure 6 As shown, the host M sends the operating mode information of slaves S1 to S3 to slave S1. Slave S1 receives the operating mode information of slaves S1 to S3 and forwards the operating mode information of slaves S2 to S3 to slave S2. Slave S2 receives the operating mode information of slaves S2 to S3 and forwards the operating mode information of slave S3 to slave S3.

[0052] In some embodiments, the slave device is, for example, a data acquisition module, and its operating mode is, for example, current mode or voltage mode. In other embodiments, the slave device is, for example, an input / output module, and its operating mode is, for example, positive logic mode or negative logic mode. It should be understood that the specific modules and operating modes of the slave device described herein are merely illustrative examples, and the present invention is not limited thereto.

[0053] In some embodiments, the received information from the slave device also includes its own I / O output data and the I / O output data of its downstream slave devices. Specifically, for example, such as... Figure 5 As shown, the master M sends the I / O output data from slaves S1 to S2 to slave S1. Slave S1 receives the I / O output data from slaves S1 to S2 and forwards the I / O output data from slave S2 to slave S2. For example, as... Figure 6As shown, the master M sends the I / O output data of slaves S1 to S3 to slave S1. Slave S1 receives the I / O output data of slaves S1 to S3 and forwards the I / O output data of slaves S2 to S3 to slave S2. Slave S2 receives the I / O output data of slaves S2 to S3 and forwards the I / O output data of slave S3 to slave S3.

[0054] In some embodiments, information transmitted by a downstream slave device is forwarded to the master device via its upstream slave devices. For example, such as Figure 5 As shown, the information sent by slave S2 is forwarded to master M via slave S1. For example, as... Figure 6 As shown, the information sent by slave S3 is forwarded to slave S1 via slave S2, and then forwarded to master M by slave S1.

[0055] In some embodiments, the information transmitted by the slave device includes its own parameter information and the own parameter information of its downstream slave devices. For example, such as Figure 5 As shown, slave device S2 sends its own parameter information to slave device S1. Slave device S1 receives the parameter information from slave device S2 and then sends the parameter information of slave devices S1 to S2 to master device M. Master device M is configured to receive the parameter information of slave devices S1 to S2. For example, as... Figure 6 As shown, slave device S3 sends its own parameter information to slave device S2. Slave device S2 receives the parameter information from slave device S3 and then sends the parameter information of slave devices S2 to S3 to slave device S1. Slave device S1 receives the parameter information of slave devices S2 to S3 and then sends the parameter information of slave devices S1 to S3 to master device M. Master device M is configured to receive the parameter information of slave devices S1 to S3. The parameter information includes, but is not limited to, static information such as the serial number of the slave device.

[0056] In some embodiments, the information transmitted by the slave device includes its own operating status information and the operating status information of its downstream slave devices. For example, such as... Figure 5 As shown, slave device S2 sends its operating status information to slave device S1. Slave device S1 receives the operating status information from slave device S2 and then sends the operating status information of slave devices S1 to S2 to master device M. Master device M is configured to receive the operating status information of slave devices S1 to S2. For example, as... Figure 6 As shown, slave device S3 sends its operating status information to slave device S2. Slave device S2 receives the operating status information from slave device S3 and then sends the operating status information of slave devices S2 to S3 to slave device S1. Slave device S1 receives the operating status information from slave devices S2 to S3 and then sends the operating status information of slave devices S1 to S3 to master device M. Master device M is configured to receive the operating status information from slave devices S1 to S3. The operating status information includes, but is not limited to, dynamic information such as the operating status of the slave devices.

[0057] In some embodiments, the slave device's transmitted information also includes its own I / O input data and the I / O input data of its downstream slave devices. For example, such as... Figure 5 As shown, slave device S2 sends its I / O input data to slave device S1. Slave device S1 receives the I / O input data from slave device S2 and then sends the I / O input data from slave devices S1 to S2 to master device M. Master device M is configured to receive the I / O input data from slave devices S1 to S2. For example, as... Figure 6 As shown, slave device S3 sends its I / O input data to slave device S2. Slave device S2 receives the I / O input data from slave device S3 and then sends all the I / O input data from slave devices S2 to S3 to slave device S1. Slave device S1 receives the I / O input data from slave devices S2 to S3 and then sends all the I / O input data from slave devices S1 to S3 to master device M. Master device M is configured to receive the I / O input data from slave devices S1 to S3.

[0058] In some embodiments, the information transmitted by the slave device may further include one or more of the following: its own parameter information and the own parameter information of its downstream slave devices, its operating status information and the operating status information of its downstream slave devices, or its I / O input data and the I / O input data of its downstream slave devices. Correspondingly, the host may receive one or more of the following: the slave device's own parameter information and the own parameter information of its downstream slave devices, the slave device's operating status information and the operating status information of its downstream slave devices, or the slave device's I / O input data and the I / O input data of its downstream slave devices.

[0059] In some embodiments, the transmission information of the slave device also includes termination information. The termination information is received through the second data input interface of the last slave device, sent to its first data output interface through the slave control chip of the last slave device, and forwarded to the master device through its upstream slave devices. Figure 7 A schematic diagram of a synchronous serial communication system 30 according to some other preferred embodiments of the present invention is shown. For example... Figure 7 As shown, the synchronous serial communication system 30 also includes a first pull-up resistor R1 and a second pull-up resistor R2. The second slave data output interface OUT2 of the last slave device Sn is connected to the voltage source VCC through the first pull-up resistor R1, and the second slave data input interface IN2 of the slave device Sn is connected to the voltage source VCC through the second pull-up resistor R2. The slave device Sn receives the end information FF through the second slave data input interface IN2, and sends it to its first data output interface OUT1 through the slave control chip of the slave device Sn, and forwards it to the master device M through the upstream slave devices Sn-1 to S1. The master device M can receive the end information FF. Alternatively, the first pull-up resistor R1 and the second pull-up resistor R2 can also be grounded. The slave device Sn receives the end information FF through the second slave data input interface IN2 (in Figure 7In this embodiment, the end information FF (i.e., the high-level signal of the second slave data input interface IN2) can be used by the slave control chip of slave Sn to determine that it is the last slave.

[0060] In some embodiments, the host M receives the slave's own parameter information (e.g., serial number) and end information FF, and can determine the number of slaves based on the own parameter information and end information.

[0061] Figure 8 A schematic diagram illustrating the transmission process of receiving and / or sending information according to some embodiments of the present invention is shown. For example... Figures 6 to 8 As shown, at time T1: Master M sends the value "1" to slave S1. Slave S1 sends its own parameter information S1info to Master M. Slave S2 sends its own parameter information S2info to slave S1. Slave S3 sends its own parameter information S3info to slave S2.

[0062] At time T2: Slave S1 sends its own parameter information S2info from slave S2 to master M. Slave S1 sends the value "2" determined based on the value "1" to slave S2. Slave S2 sends its own parameter information S3info from slave S3 to slave S1. Slave S3 sends the end information FF to slave S2.

[0063] At time T3: Slave S1 sends its own parameter information S3info from slave S3 to master M. Slave S2 sends end information FF to slave S1. Slave S2 sends the value "3" determined based on the value "2" to slave S3. Slave S3 sends end information FF to slave S2.

[0064] At time T4: Slave S1 sends the end message FF to master M. Slave S2 sends the end message FF to slave S1. Slave S3 sends the end message FF to slave S2.

[0065] The host M receives the self-parameter information S1info to S3info and the end information FF from the slaves S1 to S3. It can determine that the number of self-parameter information received is 3, and thus the number of slaves can be determined to be 3.

[0066] Figure 9 A schematic diagram illustrating the transmission process of receiving and / or sending information according to further embodiments of the present invention is shown. For example... Figure 6 , Figure 7 and Figure 9As shown, at time T5: Master M sends the value "3" (number of slaves or number of data) to slave S1. Slave S1 sends its own IO input data S1in to Master M. Slave S2 sends its own IO input data S2in to slave S1. Slave S3 sends its own IO input data S3in to slave S2.

[0067] At time T6: Master M sends slave S3's IO output data S3out to slave S1. Slave S1 sends slave S2's IO input data S2in to master M. Slave S1 sends the value "2" to slave S2. Slave S2 sends slave S3's IO input data S3in to slave S1.

[0068] At time T7: Master M sends slave S2's IO output data S2out to slave S1. Slave S1 sends slave S3's IO input data S3in to master M. Slave S1 sends slave S3's IO output data S3out to slave S2. Slave S2 sends the value "1" to slave S3.

[0069] At time T8: Master M sends slave S1's IO output data S1out to slave S1. Slave S1 sends slave S2's IO output data S2out to slave S2. Slave S2 sends slave S3's IO output data S3out to slave S3.

[0070] Figure 10 A schematic diagram illustrating a data transmission process from host M to slave S according to some embodiments of the present invention is shown. Figure 10 As shown, on the falling edge (1) of the clock, the master M updates the data on the MOSI (master output, slave input) signal line, and then the clock and MOSI are transmitted together to the slave S. The slave S reads the data on the MOSI on the rising edge (2) of the clock.

[0071] Figure 11 A schematic diagram illustrating the data reception process from slave device S to master device M according to some embodiments of the present invention is shown. Figure 11 As shown, firstly, on the falling edge (1) of the clock, the slave S updates the data on the MISO (master-in, slave-out) signal line, and then the MISO is transmitted from the slave S to the master M. Finally, the master M reads the data on the MISO on the rising edge (2) of the clock.

[0072] Figure 12 A schematic diagram illustrating the communication delays between MOSI and MISO is shown. (As shown...) Figure 12As shown, when data transmission begins, the master M sends a clock and a MOSI to the slave S. Because of the transmission distance and buffer between master M and slave S, the clock arrives at slave S with a delay of t1. The MOSI will have a delay of t2. Typically, the clock and MOSI have the same transmission distance and buffer, so t1 is essentially equal to t2. Even with a long transmission distance from master M to slave S, the clock and MOSI will maintain the same phase relationship, ensuring that the data transmission process always executes successfully.

[0073] However, during the receiving process, when the master M transmits its clock to the slave S, there is a delay of t1 in the clock signal and another delay of t3. This is because the slave S's MISO signal is transmitted from the slave S to the master M. Therefore, the total delay t1 + t3 occurs between the master S's clock signal and its MISO signal. If the total delay t1 + t3 is greater than T / 2 (where T is the clock cycle), this will lead to a communication error. If the master M is connected to n slaves, the total delay will be n*(t1 + t3), and the total delay will accumulate as the number of slaves S increases. This is why traditional solutions keep the clock frequency (communication rate) as low as possible; they aim to avoid n*(t1 + t3) ≥ T / 2 when the master communicates with the last slave. In other words, in traditional solutions, n*(t1 + t3) < T / 2 is required for normal communication.

[0074] The solution of this invention differs significantly from traditional solutions. In this solution, for adjacent slave devices, since each slave device has two SPI interfaces to connect to its neighboring slave devices, even if n slave devices are installed, the MISO communication delay reference clock for each slave device is always t1+t3. This is because the clock delay is only t1 once, and the MISO delay also occurs only once, t1+t3. In other words, each slave device has the same communication delay, t1+t3, and therefore they have the same communication speed. The communication speed is not limited by the number of slave devices or the communication distance. The number of slave devices is not limited by the number of chip select signals that the SPI master can provide, greatly improving the communication speed between the master and slave devices, which can reach up to 20MHz. For motion modules, it can meet the requirements of 6MHz or higher communication rates, significantly optimizing the motion performance of existing low-speed communication and enabling precise control of the position or speed of the motion module. The control chips for both the master and slave devices only require MCUs that support two SPI interfaces, making high-speed communication easy to implement.

[0075] The present invention also provides a synchronous serial communication module. Figure 13 A schematic diagram of a synchronous serial communication module 40 according to some embodiments of the present invention is shown. Figure 13As shown, the synchronous serial communication module 40 includes a first serial interface SPI1 and a second serial interface SPI2. The first serial interface SPI1 is adapted to connect to the host M or its upstream serial communication module. The second serial interface SPI2 is adapted to connect to its downstream serial communication module. Furthermore, the first slave clock interface CLK1 of the first serial interface SPI1 and the second slave clock interface CLK2 of the second serial interface SPI2 are also adapted to connect to the host M to synchronously receive the clock signal provided by the host M.

[0076] In some embodiments, such as Figure 13 As shown, the first serial interface SPI1 further includes a first slave data input interface IN1 and a first slave data output interface OUT1. The second serial interface SPI2 further includes a second slave data output interface OUT2 and a second slave data input interface IN2. For adjacent synchronous serial communication modules, the first slave data input interface IN1 is adapted to connect to its upstream second slave data output interface OUT2, and the first slave data output interface OUT1 is adapted to connect to its upstream second slave data input interface IN2. The synchronous serial communication module 40 also includes a control chip C, adapted to connect to the host control chip C1 of the host M and its first serial interface SPI1 and second serial interface SPI2.

[0077] The synchronous serial communication module of the present invention is coupled to the host or an adjacent synchronous serial communication module upstream of it through a first serial interface, and coupled to an adjacent synchronous serial communication module downstream of it through a second serial interface. This allows the SPI to communicate only between the synchronous serial communication module and the host, and between the synchronous serial communication module and its adjacent downstream synchronous serial communication module, or between the synchronous serial communication module and its adjacent upstream synchronous serial communication module, and between the synchronous serial communication module and its adjacent downstream synchronous serial communication module. This can improve communication speed and communication efficiency.

[0078] The present invention also provides a synchronous serial communication method, wherein the communication method is executed by the synchronous serial communication system 10 / 20 / 30 as described above, which can improve the communication speed and improve the communication efficiency.

[0079] The technical solution of this invention can be applied to motion modules, industrial robots, etc., which can improve communication speed and efficiency, and help to achieve real-time and accurate control of motion parameters such as position or speed, thereby improving work performance.

[0080] In some embodiments, the host / host control chip / slave / slave control chip / synchronous serial communication module / processor may include a central processing unit (CPU), other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic controllers (PLCs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and other components or circuits.

[0081] The present invention also provides a computer-readable storage medium including computer-executable instructions stored thereon, wherein the executable instructions, when executed by a processor, implement the synchronous serial communication method as described above.

[0082] This invention can take the form of a computer program product implemented on one or more storage media containing program code. Computer storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to: PRAM, SRAM, DRAM, other types of RAM, ROM, EEPROM, flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0083] It should be noted that although the synchronous serial communication system and several modules of the synchronous serial communication module have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of the present invention, the features and functions of two or more modules described above can be implemented in one module. Conversely, the features and functions of one module described above can be further divided and embodied by multiple modules.

[0084] It should be noted that the present invention may include only Figure 1-13Any one or more features of any one or more embodiments. In other words, not all of the features shown need to be implemented simultaneously in the synchronous serial communication system of the present invention.

[0085] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A synchronous serial communication system, comprising: The host is configured to provide a clock signal; and Multiple cascaded slave devices, each slave device including a first serial interface and a second serial interface, wherein the first slave device is coupled to the master device through the first serial interface, and for adjacent slave devices, the second serial interface of the upstream slave device is coupled to the first serial interface of the downstream slave device. Each slave device receives the clock signal synchronously from the master device through the first serial interface and the second serial interface.

2. The synchronous serial communication system according to claim 1, wherein the host includes a host clock interface, a host data output interface, and a host data input interface; the first serial interface includes a first slave clock interface, a first slave data input interface, and a first slave data output interface; the second serial interface includes a second slave clock interface, a second slave data output interface, and a second slave data input interface; the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first slave are respectively connected to the host clock interface, the host data output interface, and the host data input interface of the host; and for adjacent slaves, the second slave clock interface, the second slave data output interface, and the second slave data input interface of the second serial interface of the upstream slave are respectively coupled to the first slave clock interface, the first slave data input interface, and the first slave data output interface of the first serial interface of the downstream slave.

3. The synchronous serial communication system according to claim 2, wherein the first slave clock interface and the second slave clock interface of each slave are coupled to the host clock interface of the host to receive the clock signal synchronously.

4. The synchronous serial communication system according to claim 3, wherein the host includes a host control chip, each slave includes a slave control chip, and the slave control chip of each slave is coupled to the host control chip and coupled to its respective first serial interface and second serial interface.

5. The synchronous serial communication system according to claim 4, wherein the plurality of slaves includes at least two slaves.

6. The synchronous serial communication system according to claim 5, wherein the received information of the downstream slave is forwarded to the downstream slave via its upstream slave in a step-by-step manner.

7. The synchronous serial communication system according to claim 6, wherein the received information of the slave device includes its operating mode information and the operating mode information of its downstream slave devices.

8. The synchronous serial communication system according to claim 6 or 7, wherein the received information of the slave device further includes its IO output data and the IO output data of its downstream slave devices.

9. The synchronous serial communication system according to claim 5, wherein the transmission information of the downstream slave is forwarded to the master through its upstream slave in a step-by-step manner.

10. The synchronous serial communication system according to claim 9, wherein the transmission information of the slave device includes its own parameter information and the own parameter information of its downstream slave devices; and / or its operating status information and the operating status information of its downstream slave devices.

11. The synchronous serial communication system according to claim 10, wherein the transmission information of the slave device further includes its IO input data and the IO input data of its downstream slave devices.

12. The synchronous serial communication system according to claim 11, wherein the transmission information of the slave device further includes termination information, the termination information being received through the second data input interface of the last slave device, and transmitted through the slave control chip of the last slave device to its first data output interface, and then forwarded to the master device level by level through its upstream slave devices.

13. The synchronous serial communication system according to claim 12, wherein the host is configured to receive the self-parameter information and the termination information, and determine the number of slave devices based on the self-parameter information and the termination information.

14. A synchronous serial communication module, comprising: The first serial interface is suitable for connecting to a host or its upstream serial communication module; The second serial interface is suitable for connecting to its downstream serial communication module. Furthermore, the first slave clock interface of the first serial interface and the second slave clock interface of the second serial interface are also adapted to connect to a host to synchronously receive the clock signal provided by the host.

15. A synchronous serial communication method, performed by a synchronous serial communication system as described in any one of claims 1-13.

16. A computer-readable storage medium comprising computer-executable instructions stored thereon, the executable instructions, when executed by a processor, implementing the synchronous serial communication method of claim 15.

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