Display device and method for manufacturing same

Abstract

An organic EL display device (1) comprises: a circuit configuration layer (20) including a circuit element and wiring; a planarization film (50) provided on the circuit configuration layer; and a plurality of organic EL elements (62) provided on the planarization film. Each organic EL element includes: a first electrode (63) individually provided on the planarization film; an organic EL layer (66) provided on the first electrode; and a second electrode (68) provided so as to overlap the first electrode with the organic EL layer interposed therebetween. A low-melting-point metal layer (61) having a melting point lower than the melting point of the planarization film is provided between the planarization film and the EL layer in a region corresponding to the first electrode.

Description

Display device and method for manufacturing the same

[0001] The present disclosure relates to a display device and a method for manufacturing the same.

[0002] In recent years, as a display device, an organic electroluminescence (EL) display device using an organic EL element has been put into practical use. As an organic EL display device, a configuration in which a plurality of organic EL elements are provided via a planarization film on a circuit configuration layer including circuit elements such as thin film transistors and capacitors and wiring is known (see, for example, Patent Document 1). The organic EL element has a structure in which a first electrode, an organic EL layer, and a second electrode are laminated in this order on the surface of the planarization film.

[0003] Japanese Patent Application Laid-Open No. 2024-018461

[0004] In the organic EL display device having the above-described configuration, the first electrode included in the organic EL element is provided on the surface of the planarization film. In manufacturing such an organic EL display device, when forming the first electrode, in order to improve the adhesion of the first electrode to the surface of the planarization film, a surface treatment of performing ashing on the surface of the planarization film under low-power conditions may be performed.

[0005] However, when performing a surface treatment by ashing on the surface of the planarization film, if foreign matter is present on the surface of the planarization film, the surface of the planarization film remains without being vaporized and decomposed at the location of the foreign matter, so that relatively high protrusions are formed on the surface of the planarization film. When the first electrode is formed on such a surface of the planarization film, the shape of the protrusion is reflected in the first electrode. And the organic EL layer formed on the first electrode may not completely cover the portion reflecting the shape of the protrusion, or may become extremely thin even if it is completely covered, resulting in a risk of leakage between the first electrode and the second electrode. This leads to a defect called a black dot in the corresponding unit pixel (sub-pixel).

[0006] An object of the present disclosure is to reduce the risk of leakage between the first electrode and the second electrode of the light-emitting element.

[0007] This disclosure relates to a display device. The display device of this disclosure comprises a circuit configuration layer including circuit elements and wiring, a planarization film provided on the circuit configuration layer, and a plurality of light-emitting elements provided on the planarization film. Each of the plurality of light-emitting elements has a first electrode individually provided on the planarization film, an EL layer provided on the first electrode, and a second electrode provided so as to overlap the first electrode via the EL layer. A low-melting-point metal layer having a melting point lower than the melting point of the planarization film is provided between the planarization film and the EL layer in the region corresponding to the first electrode.

[0008] This disclosure relates to a method for manufacturing a display device. The method for manufacturing a display device according to this disclosure includes a circuit configuration layer formation step of forming the circuit configuration layer on a substrate; a planarization film formation step of forming the planarization film on the circuit configuration layer; a surface treatment step of performing ashing on the surface of the planarization film; a low melting point layer formation step of forming the low melting point metal layer on the ashing surface of the planarization film; a first electrode formation step of forming the first electrode on the low melting point metal layer; an EL layer formation step of forming the EL layer on the first electrode; and a second electrode formation step of forming the second electrode so as to overlap the first electrode via the EL layer. In the low-melting-point layer formation step, a low-melting-point metal film having a melting point lower than the melting point of the planarization film is formed, and the substrate on which the low-melting-point metal film is formed is heated at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film, and then the low-melting-point metal film is patterned to form the low-melting-point metal layer, or the substrate on which the low-melting-point metal layer is formed is heated at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film.

[0009] Furthermore, the method for manufacturing the display device of the present disclosure includes a circuit configuration layer formation step of forming the circuit configuration layer on a substrate; a planarization film formation step of forming the planarization film on the circuit configuration layer; a surface treatment step of performing ashing on the surface of the planarization film; a first electrode formation step of forming the first electrode on the ashing surface of the planarization film; a low melting point layer formation step of forming the low melting point metal layer on the first electrode; an EL layer formation step of forming an EL layer so as to overlap the first electrode via the low melting point metal layer; and a second electrode formation step of forming the second electrode so as to overlap the first electrode via the low melting point metal layer and the EL layer. In the low-melting-point layer formation step, a low-melting-point metal film having a melting point lower than the melting point of the planarization film is formed, and the substrate on which the low-melting-point metal film is formed is heated at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film, and then the low-melting-point metal film is patterned to form the low-melting-point metal layer, or the substrate on which the low-melting-point metal layer is formed is heated at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film.

[0010] According to the technology of this disclosure, the risk of leakage occurring between the first electrode and the second electrode of the light-emitting element can be reduced.

[0011] Figure 1 is a plan view illustrating the schematic configuration of an organic EL display device according to an embodiment. Figure 2 is a cross-sectional view of the organic EL display device along line II-II in Figure 1. Figure 3 is a plan view illustrating pixels and various wirings that constitute the display area of ​​the organic EL display device. Figure 4 is a cross-sectional view of the organic EL display device along line IV-IV in Figure 3. Figure 5 is an enlarged cross-sectional view of the main part of the organic EL display device enclosed by V in Figure 4. Figure 6A is a plan view illustrating the configuration of one pixel and its surroundings. Figure 6B is a plan view illustrating other configurations of one pixel and its surroundings. Figure 7 is a graph showing the relationship between the thickness of the low-melting-point metal layer and the black spot occurrence rate. Figure 8A is a cross-sectional view illustrating the main part of the manufacturing process of the organic EL display device according to an embodiment. Figure 8B is a cross-sectional view illustrating the main part of the manufacturing process of the organic EL display device according to an embodiment. Figure 8C is a cross-sectional view illustrating the main part of the manufacturing process of the organic EL display device according to an embodiment. Figure 8D is a cross-sectional view illustrating the main part of the manufacturing process of the organic EL display device according to an embodiment. Figure 8E is a cross-sectional view illustrating the main part of the manufacturing process of the organic EL display device according to an embodiment. Figure 8F is a cross-sectional view illustrating the main parts in the manufacturing process of an organic EL display device according to an embodiment. Figure 9 is a cross-sectional view corresponding to Figure 5 of an organic EL display device according to a first modification. Figure 10A is a cross-sectional view illustrating the main parts in the manufacturing process of an organic EL display device according to a first modification. Figure 10B is a cross-sectional view illustrating the main parts in the manufacturing process of an organic EL display device according to a first modification. Figure 11 is a cross-sectional view corresponding to Figure 5 of an organic EL display device according to a second modification. Figure 12A is a cross-sectional view illustrating the main parts in the manufacturing process of an organic EL display device according to a second modification. Figure 12B is a cross-sectional view illustrating the main parts in the manufacturing process of an organic EL display device according to a second modification. Figure 12C is a cross-sectional view illustrating the main parts in the manufacturing process of an organic EL display device according to a second modification.

[0012] Hereinafter, exemplary embodiments will be described in detail with reference to the drawings. In the following embodiments, an organic EL display device will be used as an example of the display device according to the Disclosure. The drawings are intended to conceptually illustrate the technology of the Disclosure. Therefore, in order to facilitate understanding of the technology of the Disclosure, dimensions, ratios, or numbers may be exaggerated or simplified in the drawings.

[0013] In the following embodiments, "first direction" means the horizontal direction of the screen in a predetermined orientation of the display device. "Second direction" means the direction orthogonal to the first direction and means the vertical direction of the screen in a predetermined orientation of the display device. A row of subpixels means an arrangement of subpixels forming a column in the first direction. A column of subpixels means an arrangement of subpixels forming a column in the second direction.

[0014] Furthermore, in the following embodiments, the statement that another film, layer, element, or other component is provided or formed on top of a certain film, layer, element, or other component does not mean only that the other component exists directly above the other component, but also includes cases where other films, layers, elements, or other components are interposed between the two components.

[0015] Furthermore, in the following embodiments, any description of a component being connected to another component means an electrically connected connection unless otherwise specified. Such description means not only a direct connection but also an indirect connection via other components, without departing from the spirit of the art of this disclosure. Such description also includes cases where one component is integrated with another component, that is, where a part of one component constitutes another component.

[0016] Furthermore, in the following embodiments, a statement that one component is a lower layer of another component means that the component is deposited in a process earlier than the other component, or is formed from a film deposited in an earlier process. A statement that one component is an upper layer of another component means that the component is deposited in a process later than the other component, or is formed from a film deposited in a later process.

[0017] 《Embodiment》 The organic EL display device 1 of this embodiment is used as a display for mobile devices such as smartphones and tablet terminals. The organic EL display device 1 may also be used as a display for various other devices such as personal panel computers (PCs) and television equipment.

[0018] -Configuration of the Organic EL Display Device- The Organic EL display device 1 is a display device that uses an organic EL element 62, also called an OLED (Organic Light Emitting Diode). The Organic EL display device 1 employs an active matrix drive method and is configured to display full color. As shown in Figure 1, the Organic EL display device 1 has a display area DA and a bezel area FA.

[0019] The display area DA is the area where the image is displayed and constitutes the screen. The display area DA is provided in a rectangular shape, for example. The display area DA may be a substantially rectangular shape such as a shape in which at least one side is arc-shaped, a shape in which at least one corner is arc-shaped, or a shape in which at least one side has a notch, or it may be any other arbitrary shape.

[0020] The frame area FA is the area that constitutes the non-display portion other than the screen. The frame area FA is provided around the display area DA, for example, in the shape of a rectangular frame. The frame area FA may be a frame shape other than a rectangle. The frame area FA includes a terminal portion TP and a bend portion BP. The terminal portion TP and the bend portion BP are provided in the portion that constitutes the same side of the frame area FA.

[0021] The terminal section TP is the part for connecting to an external circuit. The terminal section TP is provided at the end of the frame area FA. Specifically, the terminal section TP is located near the outer edge of the part that constitutes one side of the frame area FA and extends along that side. Multiple terminals (not shown) are provided on the terminal section TP in a predetermined pattern. A wiring board CB, such as an FPC (Flexible Printed Circuit), is connected to the terminal section TP.

[0022] The bent portion BP is provided between the terminal portion TP and the display area DA in the frame area FA, extending in the first direction Dx. The bent portion BP is the part that is bent around an axis extending in the first direction Dx. The bent portion BP extends horizontally across the entire frame area FA in the first direction Dx. In the bent portion BP, the inorganic insulating film contained in the circuit component layer 20 is removed, resulting in higher flexibility than other parts.

[0023] The bezel area FA of the organic EL display device 1 is bent at the bending portion BP to form a U-shape, for example, by about 180° (shown by the dashed line in Figure 2). As a result, the terminal portion TP and the wiring board CB are located on the back side of the organic EL display device 1. Display control circuits, such as source drivers, are mounted on the wiring board CB as IC (Integrated Circuit) chips or connected via other circuit boards.

[0024] A drive circuit Dc is provided in the frame region FA. The drive circuit Dc is positioned in the portion of the frame region FA that constitutes the side adjacent to the side where the terminal portion TP is provided (each side on the left and right in Figure 1). The drive circuit Dc is formed monolithically as part of the circuit configuration layer 20. The drive circuit Dc includes a gate driver and an emission driver.

[0025] The frame area FA is further provided with numerous wirings of various types, such as power lines 30 and lead lines 36. The power lines 30 are wirings for applying current to the organic EL element 62 by the pixel circuit Pc. The power lines 30 include a first power trunk line 32 (shown with upward-sloping diagonal hatching in Figure 1 for convenience) and a second power trunk line 34 (shown with upward-sloping diagonal hatching in Figure 1 for convenience).

[0026] The first power trunk line 32 is provided so as to extend in a first direction Dx between the display area DA and the bent portion BP. On both sides of the first power trunk line 32 in the first direction Dx, portions are provided that extend to the terminal portion TP via the bent portion BP. A high-level power supply voltage (ELVDD) is supplied to the first power trunk line 32 at the terminal portion TP via the wiring board CB.

[0027] The second power line 34 is provided in a roughly C-shape so as to surround the first power line 32 and the display area DA. Both ends of the second power line 34 extend to the terminal section TP via the bent section BP so as to run parallel to the first power line 32. A low-level power supply voltage (ELVSS) is supplied to the second power line 34 at the terminal section TP via the wiring board CB.

[0028] Multiple lead wires 36 are provided between the display area DA and the terminal section TP. The lead wires 36 are drawn out from the display area DA through the bending section BP to the terminal section TP. The lead wires 36 are connected to the source line 28 on the display area DA side. The lead wires 36 are part of the source line 28. The end of each lead wire 36 located at the terminal section TP and the respective ends of the first power trunk line 32 and the second power trunk line 34 each form a terminal at the terminal section TP.

[0029] <Display Area> As shown in Figure 3, the display area DA is composed of multiple pixels PX. The multiple pixels PX are arranged in a matrix. Each pixel PX is composed of three subpixels SP. The three subpixels SP are a red subpixel SPr that emits red light, a green subpixel SPg that emits green light, and a blue subpixel SPb that emits blue light. These red subpixels SPr, green subpixels SPg, and blue subpixels SPb are arranged, for example, in a stripe pattern.

[0030] The display area DA is provided with a plurality of organic EL elements 62 and a plurality of pixel circuits Pc. The organic EL element 62 is an example of a light-emitting element. The plurality of organic EL elements 62 are provided corresponding to a plurality of sub-pixels SP. Each organic EL element 62 constitutes a sub-pixel SP. The pixel circuit Pc is a circuit for each sub-pixel and controls the light emission of the organic EL elements 62 that make up the corresponding sub-pixel SP.

[0031] The display area DA is further provided with various wirings related to the operation of the pixel circuit Pc. The wiring provided in the display area DA includes a plurality of gate lines 22, a plurality of light emission control lines 24, a plurality of power supply branch lines 26, and a plurality of source lines 28. The gate lines 22, light emission control lines 24, power supply branch lines 26, and source lines 28 are each connected to the pixel circuit Pc.

[0032] Each of the multiple gate lines 22 is a wiring that transmits a gate signal to the pixel circuit Pc. The multiple gate lines 22 are spaced apart from each other in the second direction Dy and extend parallel to each other in the first direction Dx. A gate line 22 is provided for each row of sub-pixel SP. Each gate line 22 is led out to the frame area FA and connected to the gate driver of the drive circuit Dc.

[0033] Each of the multiple light emission control lines 24 is a wire that transmits an emission signal to the pixel circuit Pc. The multiple light emission control lines 24 are spaced apart from each other in the second direction Dy and extend parallel to each other in the first direction Dx. A light emission control line 24 is provided for each row of sub-pixel SP. Each light emission control line 24 is led out to the frame area FA and connected to the emission driver of the drive circuit Dc.

[0034] Each of the multiple power supply branch lines 26 is part of the power supply line 30 and is wiring that supplies a predetermined high-level power supply voltage (ELVDD) to the pixel circuit Pc. The multiple power supply branch lines 26 are arranged spaced apart from each other in the first direction Dx and extend parallel to each other in the second direction Dy. A power supply branch line 26 is provided for each row of sub-pixels SP. Each power supply branch line 26 is led out to the frame area FA on the terminal section TP side and connected to the first power supply trunk line 32.

[0035] Each of the multiple source lines 28 is a wiring that transmits a source signal to the pixel circuit Pc. The multiple source lines 28 are arranged spaced apart from each other in the first direction Dx and extend parallel to each other in the second direction Dy. A source line 28 is provided for each row of sub-pixels SP. Each source line 28 is led out as a lead line 36 to the terminal section TP and connected to the source driver via the wiring board CB.

[0036] The pixel circuit Pc operates based on signals and voltages supplied by gate line 22, light emission control line 24, power supply branch line 26, and source line 28, and supplies drive current to the corresponding organic EL element 62. The pixel circuit Pc is composed of a plurality of thin film transistors (hereinafter referred to as TFTs) 40 and a capacitor 42.

[0037] <Laminated structure of organic EL display device> As shown in Figure 2, the organic EL display device 1 comprises a substrate layer 10, a circuit configuration layer 20, a planarization film 50, a light-emitting element layer 60, and a sealing film 70. The substrate layer 10 and the circuit configuration layer 20 constitute a circuit board called a backplane.

[0038] <Substrate Layer> The substrate layer 10 is the base layer of the organic EL display device 1. The substrate layer 10 is an example of a substrate. The substrate layer 10 is flexible. The substrate layer 10 is formed from an organic resin material such as polyimide resin, polyamide resin, or epoxy resin. A protective film 12 is attached to the back surface of the substrate layer 10.

[0039] <Circuit Configuration Layer> As shown in Figure 4, the circuit configuration layer 20 is provided on the substrate layer 10. The circuit configuration layer 20 includes a drive circuit Dc, various wirings (not shown in Figure 4) as described above, and a plurality of TFTs 40 and capacitors 42 that form a pixel circuit Pc. The TFTs 40 and capacitors 42 are examples of circuit elements.

[0040] A base coat film (not shown) is provided on the surface of the substrate layer 10. The base coat film is formed from an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The TFT 40 and capacitor 42 are provided on the base coat film. A base coat film is not required on the surface of the substrate layer 10.

[0041] Multiple TFTs 40 are provided for each pixel circuit Pc. The TFTs 40 are configured, for example, as a top-gate type. As semiconductors, oxide semiconductors such as In-Ga-Zn-O semiconductors or low-temperature polycrystalline silicon (LTPS) are used for the TFTs 40. Although not shown in the figure, the TFTs 40 have a gate electrode, a first terminal electrode, and a second terminal electrode.

[0042] The capacitor 42 is provided with at least one for each pixel circuit Pc. Although not shown, the capacitor 42 has a first capacitive electrode and a second capacitive electrode. The first capacitive electrode and the second capacitive electrode overlap each other via an insulating film contained in the circuit configuration layer 20. The first capacitive electrode and the second capacitive electrode may each be constituted by a part of another electrode or wiring.

[0043] 〈Planarization film〉 The planarization film 50 is provided on the circuit configuration layer 20 so as to cover the drive circuit Dc, various wirings, the plurality of TFTs 40, and the plurality of capacitors 42. The planarization film 50 is provided over the entire display area DA and extends to the frame area FA. The upper surface of the circuit configuration layer 20 is planarized by the planarization film 50. The thickness of the planarization film 50 is, for example, about 1 μm to 4 μm. The planarization film 50 may be constituted by a single-layer film or a laminated film.

[0044] Contact holes Hc are formed in the planarization film 50. The contact holes Hc are provided for each subpixel Sp (that is, for each organic EL element 62). The contact hole Hc is a through hole for connecting the first electrode 63 to a predetermined TFT 40 in the corresponding pixel circuit Pc, and penetrates a first terminal electrode or a second terminal electrode forming the predetermined TFT 40, or a wiring connected to either of them.

[0045] A plurality of recesses 52 are formed in a portion of the surface of the planarization film 50 corresponding to the first electrode 63. The recess 52 is a portion recessed toward the circuit configuration layer 20 side of the surface of the planarization film 50, and is provided separately for each first electrode 63. As shown in FIG. 6A, the recess 52 in this example is formed in a shape in which the corner portion of a rectangular shape in plan view is curved. The shape of the recess 52 may be a rectangular shape with corners or an oval shape, or may take any other shape, but it is preferably a shape having a circumferential surface that is curved in plan view.

[0046] Each recess 52 is formed so as not to include the formation site of the contact hole Hc in a plan view. The contact hole Hc in this example is located on the side of the subpixel SP. As shown in FIG. 6B, the contact hole Hc may be located closer to the inside of the subpixel SP. In this case, the recess 52 has a peripheral shape that is recessed inward so as to avoid the formation site of the contact hole Hc in a plan view. The depth of the recess 52 is, for example, 50 nm or more and 2000 nm or less.

[0047] As shown in FIG. 5, an uneven shape is formed on the surface of the planarization film 50, including the inner surface of the recess 52. This uneven shape is formed by performing ashing on the surface of the planarization film 50 under low-power conditions in order to improve the adhesion of the upper layer film to the surface of the planarization film 50. The planarization film 50 is made of, for example, an organic resin material such as a polyimide resin or an acrylic resin, or a polysiloxane-based SOG (Spin On Glass) material.

[0048] 〈Light-emitting element layer〉 The light-emitting element layer 60 is provided on the planarization film 50. The light-emitting element layer 60 includes a plurality of low-melting-point metal layers 61, a plurality of organic EL elements 62, and a bank 65. The organic EL element 62 is an example of a light-emitting element. Each organic EL element 62 is connected to a separate pixel circuit Pc. The light emission of each organic EL element 62 is controlled by the operation of the corresponding pixel circuit Pc.

[0049] The low-melting-point metal layer 61 is a metal layer made of a low-melting-point metal. The low-melting-point metal is a metal material having a melting point lower than that of the planarization film 50. The low-melting-point metal layer 61 is provided for each subpixel SP. The low-melting-point metal layer 61 is located between the planarization film 50 and the organic EL layer 66 in the region corresponding to the first electrode 63 forming the organic EL element 62. The low-melting-point metal layer 61 in this example is formed under the first electrode 63 and is located between the planarization film 50 and the first electrode 63.

[0050] The low-melting-point metal layer 61 is provided in a region on the surface of the planarized film 50 that includes the recesses 52 and the contact holes Hc. That is, the low-melting-point metal layer 61 is formed to extend from the bottom surface of the recesses 52 to its inner circumferential surface and the outer circumferential surface of the recesses 52, and also to extend into the contact holes Hc. The melting point of the low-melting-point metal layer 61 is lower than 350°C. Preferably, the melting point of the low-melting-point metal layer 61 is lower than 300°C, and more preferably lower than 250°C.

[0051] Furthermore, the melting point of the low-melting-point metal layer 61 is above the operating temperature of the organic EL element 62. If the melting point of the low-melting-point metal layer 61 is lower than the operating temperature of the organic EL element 62, defects may occur in the low-melting-point metal layer 61 during the operation of the organic EL display device 1, which may cause product defects. The organic EL element 62 generates heat to about 60°C during the operation of the organic EL display device 1. For this reason, it is preferable that the melting point of the low-melting-point metal layer 61 be 60°C or higher.

[0052] The low-melting-point metal layer 61 is made of a metallic material containing at least one metal selected from lead (Pb; melting point 328°C), cadmium (Cd; melting point 321°C), bismuth (Bi; melting point 271°C), tin (Sn; melting point 232°C), and indium (In; melting point 157°C). This metallic material may be a metallic compound or an alloy. For example, the low-melting-point metal layer 61 is formed of tin (Sn) and has a melting point lower than 250°C.

[0053] The thickness of the low-melting-point metal layer 61 is 10 nm or more and 1000 nm or less, and preferably 180 nm or more. As shown in Figure 7, if the thickness of the low-melting-point metal layer 61 is 180 nm or more, the occurrence rate of black spots can be reduced to a level that is acceptable or not problematic for the product. The thickness of the low-melting-point metal layer 61 is, for example, about 200 nm. The low-melting-point metal layer 61 may be considered as being included in the organic EL element 62. More specifically, the low-melting-point metal layer 61 may be recognized as a layer that constitutes a part of the first electrode 63.

[0054] Each of the multiple organic EL elements 62 is configured as a top-emission type. The light emitted from each organic EL element 62 is extracted to the sealing film 70 side. As shown in Figures 4 and 5, each organic EL element 62 has a first electrode 63, an organic EL layer 66, and a second electrode 68. The organic EL layer 66 is an example of an electroluminescent layer. Each organic EL element 62 has a light-emitting layer that is individually separated as part of the organic EL layer 66.

[0055] Multiple organic EL elements 62 are composed of multiple types of organic EL elements 62 that emit light in colors different from each other. The multiple types of organic EL elements 62 include a red light-emitting element 62r, a green light-emitting element 62g, and a blue light-emitting element 62b. The red light-emitting element 62r includes a light-emitting layer that emits red light. The green light-emitting element 62g includes a light-emitting layer that emits green light. The blue light-emitting element 62b includes a light-emitting layer that emits blue light.

[0056] Each of the multiple first electrodes 63 is individually provided on the planarized film 50, covering the low-melting-point metal layer 61. The first electrodes 63 are arranged in a predetermined sequence to correspond to a plurality of subpixels SP. Each first electrode 63, together with the low-melting-point metal layer 61, is connected to the connecting line 54 via a contact hole Hc. The first electrodes 63 have the property of reflecting light and function as an anode. It is preferable to use a conductive material with a large work function for the first electrodes 63.

[0057] The material of the first electrode 63 may be a metal such as silver (Ag) or nickel (Ni), or it may be a metal compound or alloy. The material of the first electrode 63 may also be a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first electrode 63 may be composed of a single layer film or a multilayer film.

[0058] The bank 65 is provided on the planarized film 50 to partition a plurality of first electrodes 63. The bank 65 is formed in a grid pattern as a whole and is provided on the planarized film 50 to extend between adjacent first electrodes 63 and around the display area DA. The bank 65 is also called an edge cover and covers the peripheral portion of each first electrode 63.

[0059] The bank 65 is provided so as to cover the inner circumferential surface of the recess 52. In a plan view, the bank 65 overlaps the inner circumferential surface of the recess 52 via the low melting point metal layer 61 and the first electrode 63, the opening of the bank 65 corresponds to the bottom surface of the recess 52, and the periphery of the opening of the bank 65 is located inside the periphery of the recess 52. The bank 65 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

[0060] The organic EL layer 66 is provided in a region enclosed by the bank 65. The organic EL layer 66 is provided so as to overlap each of the first electrodes 63 within the opening of the bank 65. The organic EL layer 66 has a hole injection layer, a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer, which are provided in order on the first electrodes 63. These functional layers are made of well-known compounds suitable for their respective functions. Some functional layers may be provided in common as a continuous series across multiple subpixels SP.

[0061] For example, the hole injection layer and hole transport layer are provided in common as a continuous unit for multiple sub-pixels SP so as to cover the bank 65 and overlap the first electrode 63 inside each opening of the bank 65. The light-emitting layer is provided individually for each sub-pixel SP so as to overlap the first electrode 63 via the hole injection layer and hole transport layer. The electron transport layer and electron injection layer are provided in common as a continuous unit for multiple sub-pixels SP so as to cover the light-emitting layer.

[0062] The second electrode 68 is provided as a continuous unit across multiple subpixels SP. The second electrode 68 is positioned on the organic EL layer 66, covering the bank 65, and is provided so as to overlap each first electrode 63 via the organic EL layer 66. The second electrode 68 has light-transmitting properties and functions as a cathode. It is preferable to use a conductive material with a small work function for the second electrode 68.

[0063] The material of the second electrode 68 may be a metal such as magnesium (Mg) or aluminum (Al), or it may be an alloy or metal compound such as magnesium-silver alloy (MgAg). The material of the second electrode 68 may also be a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second electrode 68 may be composed of a single layer film or a multilayer film.

[0064] <Sealing Film> The sealing film 70 is provided on the light-emitting element layer 60. The sealing film 70 covers and seals the plurality of organic EL elements 62, protecting each organic EL element 62 (especially the organic EL layer 66) from moisture, oxygen, and the like. The sealing film 70 is provided over the entire display area DA and extends to the frame area FA. The sealing film 70 has a first inorganic layer 72, an organic layer 74, and a second inorganic layer 76.

[0065] The first inorganic layer 72 is provided so as to cover the second electrode 68. The organic layer 74 is provided on the first inorganic layer 72. The second inorganic layer 76 is provided so as to cover the organic layer 74. The first inorganic layer 72 and the second inorganic layer 76 overlap each other in the frame region FA. The organic layer 74 is enclosed by the first inorganic layer 72 and the second inorganic layer 76.

[0066] The first inorganic layer 72 and the second inorganic layer 76 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The organic layer 74 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, or polyamide resin.

[0067] -Method for manufacturing an organic EL display device- The method for manufacturing the organic EL display device 1 includes a substrate layer formation step, a circuit configuration layer formation step, a planarization film formation step, a surface treatment step, a low melting point layer formation step, a first electrode formation step, a bank formation step, an organic EL layer formation step, a second electrode formation step, and a sealing film formation step. The organic EL layer formation step corresponds to the electroluminescence layer formation step.

[0068] <Substrate Layer Formation Process> To manufacture the organic EL display device 1, the substrate layer formation process is performed first. In the substrate layer formation process, a glass substrate such as an alkali-free glass substrate is prepared. Then, the surface of the glass substrate is cleaned in advance by methods such as IPA (Iso-Propyl Alcohol) ultrasonic cleaning or pure water cleaning to remove foreign matter such as organic matter. An organic resin material is applied to the surface of this glass substrate 100 and baked. In this way, a substrate layer 10 is formed on the surface of the glass substrate 100, as shown in the upper left diagram of Figure 8A.

[0069] <Circuit Layer Formation Process> Next, the circuit layer formation process is performed. In the circuit layer formation process, as shown in the lower left diagram of Figure 8B, a circuit layer 20 is formed on the substrate layer 10. Specifically, a base coat film is formed on the surface of the substrate layer 10 by sequentially depositing a silicon oxide film and a silicon nitride film, for example, by plasma CVD (Chemical Vapor Deposition). Then, on the substrate on which the base coat film has been formed, various wirings, TFTs 40 and capacitors 42 are fabricated using known film deposition methods such as plasma CVD and sputtering, and known patterning techniques such as photolithography.

[0070] <Planarization Film Formation Process> Next, the planarization film formation process is performed. In the planarization film formation process, a planarization film 50 is formed on the circuit component layer 20. Specifically, as shown in the upper right diagram of Figure 8A, a photosensitive resin such as polyimide resin is applied to the substrate on which the circuit component layer 20 is formed by a known coating method such as spin coating or slit coating, to form a photosensitive resin coating film 101. In this example, a positive-type photosensitive resin is used as the photosensitive resin.

[0071] Furthermore, the photosensitive resin coating film 101 is subjected to pre-baking, exposure, development, and post-baking. During the exposure process, a multi-tone mask 200, such as a halftone mask or a graytone mask, is used. That is, light L is irradiated onto the photosensitive resin coating film 101 through the multi-tone mask 200, causing the photosensitive resin to react with the light L. The multi-tone mask 200 is configured to allow light L to pass through unnecessary parts of the photosensitive resin coating film 101, partially block light L to the recess 52 formation area, and completely block light L to other areas.

[0072] Furthermore, in the development process, the photosensitive resin coating film 101 exposed using the multi-gradation mask 200 as described above is developed with a developer such as an alkaline solution. Then, in the post-bake process, the substrate having the developed photosensitive resin coating film 101 is heated in an oven. The heating temperature in this example is 300°C. By using the multi-gradation mask 200 in this way, the planarization film 50 is partially thinned and patterned, as shown in the lower right figure of Figure 8A, to form a planarization film 50 having contact holes Hc and recesses 52.

[0073] <Surface Treatment Process> Next, a surface treatment process is performed. In the surface treatment process, the surface of the planarization film 50 is subjected to ashing. The ashing is performed using an oxygen-based plasma under relatively low power conditions. This roughens the surface of the planarization film 50, creating an uneven surface and activating it. This improves the adhesion of the upper film to the surface of the planarization film 50.

[0074] When transporting the substrate on which the planarized film 50 has been formed to the apparatus for the next process, when loading it into the apparatus, or during storage of the substrate, foreign matter X may adhere to the surface of the planarized film 50, as shown in the upper diagram of Figure 8B. In the surface treatment process, if foreign matter X adheres to the surface of the planarized film 50, the surface of the planarized film 50 remains without vaporization and decomposition at the location of the foreign matter X. As a result, relatively high protrusions 54 are formed on the surface of the planarized film 50, as shown in the lower diagram of Figure 8B. After that, the substrate is cleaned. In the substrate cleaning, even if the foreign matter X is removed, the protrusions 54 remain on the surface of the planarized film 50.

[0075] When the first electrode 63 is formed on the surface of the planarized film 50, the shape of the protrusions 54 is reflected in the first electrode 63. The organic EL layer 66 formed on the first electrode 63 may not be able to completely cover the portion that reflects the shape of the protrusions 54, or even if it does cover it completely, it may become extremely thin, potentially causing leakage between the first electrode 63 and the second electrode 68. This can lead to the corresponding subpixel SP becoming a defect called a black spot. In this embodiment, a low-melting-point layer formation process is performed as a countermeasure against such subpixel SP defects caused by contamination.

[0076] <Low Melting Point Layer Process> Next, a low melting point layer formation process is performed. In the low melting point layer formation process, a low melting point metal layer 61 is formed on the surface of the planarized film 50 that has been ashed. Specifically, as shown in the upper diagram of Figure 8C, a low melting point metal film 102 made of a low melting point metal such as a tin film (Sn film) is deposited on a substrate having an ashed planarized film 50 by vacuum deposition. The surface of this low melting point metal film 102 is made uneven, reflecting the surface shape of the planarized film 50.

[0077] Next, the substrate on which the low-melting-point metal film 102 is formed is heated. The heating temperature at this time is higher than the melting point of the low-melting-point metal layer 61 and lower than the melting point of the planarization film 50. The heating temperature of the substrate is lower than or equal to the heating temperature used for post-bake during the formation of the planarization film 50. Applying a higher temperature to the substrate would create voids and defects in the low-melting-point metal film 102. For example, the substrate is placed on a hot plate and heated at 280°C for 2 minutes.

[0078] In this way, by heating the substrate, the low-melting-point metal film 102 is subjected to a temperature above its melting point, causing the low-melting-point metal film 102 to melt. As a result, the surface of the low-melting-point metal film 102 is flattened, as shown in the lower part of Figure 8C. When the low-melting-point metal film 102 melts, it becomes fluid, but the low-melting-point metal film 102 provided in the recess 52 does not flow out from the recess 52 to the area outside of it. Therefore, the surface of the low-melting-point metal film 102 can be smoothed while preventing the low-melting-point metal film 102 from disappearing from the area corresponding to the first electrode 63 or becoming extremely thin.

[0079] Subsequently, the low-melting-point metal film 102 is patterned by photolithography to form a low-melting-point metal layer 61, as shown in the upper diagram of Figure 8D. More specifically, a resist is formed on the substrate having the planarized low-melting-point metal film 102 by a known photoprocess, overlapping the area where the low-melting-point metal layer 61 is formed. Furthermore, the low-melting-point metal film 102 is patterned by etching, such as wet etching, using the resist as a mask. For example, if the low-melting-point metal film 102 is made of a tin film (Sn film), ferric chloride etching solution is used as the etching solution for patterning the low-melting-point metal film 102.

[0080] <First Electrode Formation Process> Next, the first electrode formation process is performed. In the first electrode formation process, as shown in the lower diagram of Figure 8D, the first electrode 63 is formed on the low-melting-point metal layer 61. Specifically, on the substrate on which the low-melting-point metal layer 61 is formed, an indium tin oxide film (ITO film), a silver alloy film (Ag alloy film), and an indium tin oxide film (ITO film) are sequentially deposited, for example, by sputtering. For example, the thickness of the upper indium tin oxide film is set to 5 nm to 50 nm, the thickness of the silver alloy film is set to 100 nm to 500 nm, and the thickness of the lower indium tin oxide film is set to 5 nm to 50 nm. In this way, a conductive film is formed on the second planarization film 56.

[0081] Next, the conductive film is patterned by photolithography to form the first electrode 63. More specifically, a resist is formed on the substrate on which the conductive film is formed, using a known photoprocess, so as to overlap the area where the first electrode 63 is formed. Furthermore, the conductive film is patterned by etching, such as wet etching, using the resist as a mask. For example, if the conductive film consists of an indium tin oxide film (ITO film), a silver alloy film (Ag alloy film), and an indium tin oxide film (ITO film), a PAN-based etching solution, which is a mixture of phosphoric acid, nitric acid, and acetic acid, is used as the etching solution for patterning the conductive film.

[0082] <Bank Formation Process> Next, the bank formation process is performed. In the bank formation process, as shown in the upper diagram of Figure 8E, banks 65 are formed between adjacent first electrodes 63 on the surface of the planarized film 50. Specifically, a photosensitive resin is applied to the substrate on which the first electrodes 63 are formed by a known coating method such as spin coating. Furthermore, the coated film of the photosensitive resin is pre-baked, exposed, developed, and post-baked to pattern the coated film. In this way, banks 65 are formed on the planarized film 50.

[0083] <Organic EL Layer Formation Process> Next, the organic EL layer formation process is performed. In the organic EL layer formation process, as shown in the lower diagram of Figure 8E, an organic EL layer 66 is formed on the first electrode 63. In this embodiment, a hole injection layer, a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer are formed in order on the substrate on which the bank 65 is formed. Of these five layers, the hole injection layer, hole transport layer, electron transport layer, and electron injection layer are formed to cover the bank 65 as layers common to all subpixels SP.

[0084] Specifically, an organic material, which is a solution containing a compound suitable for the layer function to be formed (hole injection function or transport function), is applied to the substrate on which the bank 65 is formed by a known coating method. Subsequently, the coated film of the organic material is baked to evaporate the solvent. By repeating this process, a hole injection layer and a hole transport layer are formed so as to spread over the entire portion forming the display area DA on the substrate.

[0085] Furthermore, an organic material, which is a solution containing a compound suitable for light emission, is applied to the substrate on which the hole injection layer and hole transport layer are formed, for example by an inkjet method. At this time, the organic material to be applied is applied to each first electrode 63 within the opening of the bank 65 according to the light emission color of the organic EL element 62. Subsequently, the applied film of the organic material is baked to evaporate the solvent. In this way, individual light-emitting layers are formed in the region corresponding to each first electrode 63. These light-emitting layers may also be formed by a lift-off process.

[0086] Then, an organic material, which is a solution containing a compound suitable for the layer function to be formed (electron injection function or transport function), is applied to the substrate on which the light-emitting layer is formed, using a known coating method. Subsequently, the coated film of the organic material is baked to evaporate the solvent. By repeating this process, an electron transport layer and an electron injection layer are formed so as to cover each light-emitting layer and spread over the entire portion forming the display area DA on the substrate.

[0087] <Second Electrode Formation Process> Next, the second electrode formation process is performed. In the second electrode formation process, as shown in the upper diagram of Figure 8F, the second electrode 68 is formed so as to overlap each first electrode 63 via the organic EL layer 66. Specifically, a conductive film such as an indium tin oxide film (ITO film), an indium zinc oxide film (IZO film), or a magnesium silver alloy film (MgAg film) is deposited on the substrate on which the organic EL layer 66 is formed, for example by vacuum deposition. As a result, the second electrode 68 is formed so as to extend over the entire portion of the display area DA and the frame area FA on the substrate.

[0088] <Sealing Film Formation Process> Next, the sealing film formation process is performed. In the sealing film formation process, as shown in the lower diagram of Figure 8F, a sealing film 70 is formed so as to cover the entire second electrode 68. Specifically, a first inorganic layer 72 is formed on the substrate on which the second electrode 68 is formed by plasma CVD. Subsequently, an organic resin material is applied to the substrate on which the first inorganic layer 72 is formed, and the applied film of the organic resin material is cured to form an organic layer 74. Then, a second inorganic layer 76 is formed on the substrate on which the organic layer 74 is formed by plasma CVD.

[0089] <Other processes> After that, the glass substrate 100 is peeled off the substrate layer 10 by irradiating the back surface of the substrate layer 10 with laser light from the glass substrate 100 side. Next, a protective film 12 is attached to the back surface of the substrate layer 10. A polarizing plate and cover panel are also attached to the surface of the sealing film 70. Furthermore, a wiring board CB is connected to the terminal section TP provided in the frame area FA, and a display control circuit such as a source driver is mounted.

[0090] In this manner, the organic EL display device 1 can be manufactured.

[0091] -Features of the Embodiment- In the organic EL display device 1 of this embodiment, a low-melting-point metal layer 61 is provided between the planarization film 50 and the organic EL layer 66 in the region corresponding to the first electrode 63. The melting point of the low-melting-point metal layer 61 is lower than the melting point of the planarization film 50. In the manufacturing of the organic EL display device 1, the adhesion of the upper layer to the surface of the planarization film 50 can be improved by performing a surface treatment by ashing on the surface of the planarization film 50.

[0092] Furthermore, before forming the organic EL layer 66 on the substrate on which the low-melting-point metal layer 61 is formed, a heat treatment is performed by heating it at a temperature higher than the melting point of the low-melting-point metal layer 61 and lower than the melting point of the planarization film 50. This melts the low-melting-point metal layer 61, and the surface of the low-melting-point metal layer 61 can be leveled to create a flat surface. In this way, even if protrusions 54 caused by the adhesion of foreign matter X are formed on the surface of the planarization film 50 due to the ashing of the surface treatment, the height difference caused by these protrusions 54 is absorbed by the low-melting-point metal layer 61. As a result, the organic EL layer 66 can be formed to a suitable thickness even in the areas corresponding to these protrusions 54. Consequently, the risk of leakage between the first electrode 63 and the second electrode 68 can be reduced.

[0093] In the organic EL display device 1 of this embodiment, a recess 52 is formed in the portion of the surface of the planarized film 50 corresponding to the first electrode 63. The low-melting-point metal layer 61 is provided in the region including the recess 52. In the manufacturing of the organic EL display device 1, when the substrate on which the low-melting-point metal layer 61 is formed is subjected to a heating process as described above, the molten low-melting-point metal layer 61 gains fluidity. Therefore, if the flow of the low-melting-point metal layer 61 is not restricted, the metal material forming the low-melting-point metal layer 61 spreads out, and the low-melting-point metal layer 61 becomes thinner. If this happens, and a protrusion 54 caused by foreign matter X is formed on the surface of the planarized film 50 by the surface treatment by ashing, the low-melting-point metal layer 61 may not be able to sufficiently absorb the height difference caused by the protrusion 54.

[0094] In contrast, when the low-melting-point metal layer 61 is provided within the recess 52, the flow of the molten low-melting-point metal layer 61 is restricted within the recess 52. This prevents the low-melting-point metal layer 61 from becoming thinner and ensures its thickness. As a result, if a protrusion 54 caused by the adhesion of foreign matter X is formed on the surface of the flattened film 50 due to the surface treatment by ashing, the height difference caused by the protrusion 54 can be suitably absorbed by the low-melting-point metal layer 61.

[0095] In this embodiment of the organic EL display device 1, the recesses 52 are provided separately for each first electrode 63. If the recesses 52 are provided in common to correspond to multiple first electrodes 63, the area in which the recesses 52 are formed is relatively large, and even if the flow of the molten low-melting-point metal layer 61 is restricted within the recesses 52, the variation in the thickness of the low-melting-point metal layer 61 tends to be large. In contrast, if the recesses 52 are provided separately for each first electrode 63, the variation in the thickness of the low-melting-point metal layer 61 can be reduced. This is advantageous for the low-melting-point metal layer 61 to suitably absorb the height difference caused by the protrusions 54 on the surface of the planarized film 50.

[0096] In this embodiment of the organic EL display device 1, the bank 65 is provided so as to cover the inner circumferential surface of the recess 52. The organic EL layer 66 is provided in the region enclosed by the bank 65. If the organic EL layer 66 is provided so as to cover the inner circumferential surface of the recess 52 and extends to the outside of the recess 52 in a laminated state on the first electrode 63, the organic EL layer 66 will become thinner due to the step formed by the inner circumferential surface of the recess 52, causing light emission failure on the outside of the recess 52, thus reducing the reliability of the organic EL element 62. In contrast, if the organic EL layer 66 is provided in the region enclosed by the bank 65 that covers the inner circumferential surface of the recess 52, the light-emitting region of the organic EL element 62 can be defined as the region enclosed by the bank 65. This improves the reliability of the organic EL element 62.

[0097] In this embodiment of the organic EL display device 1, the recess 52 is formed such that, in a plan view, it does not include the contact hole Hc formation area on its interior. In the manufacturing of the organic EL display device 1, when the low-melting-point metal layer 61 is melted by heating the substrate on which the low-melting-point metal layer 61 is formed as described above, it is possible to suppress the thinning of the low-melting-point metal layer 61 due to the metal material forming the low-melting-point metal layer 61 flowing into the contact hole Hc. This is advantageous for the low-melting-point metal layer 61 to suitably absorb the height difference caused by the protrusions 54 on the surface of the planarized film 50.

[0098] In this embodiment of the organic EL display device 1, the thickness of the low-melting-point metal layer 61 is 180 nm or more. As a result, even if protrusions 54 caused by the adhesion of foreign matter X are formed on the surface of the planarized film 50 due to surface treatment by ashing, the height difference caused by these protrusions 54 can be suitably absorbed by the low-melting-point metal layer 61. As a result, the occurrence rate of black spots can be reduced to a level that is acceptable or poses no problem for the product.

[0099] In the manufacturing method of the organic EL display device 1 of this embodiment, the surface of the planarization film 50 is subjected to a surface treatment by ashing. This improves the adhesion of the upper layer film to the surface of the planarization film 50. Then, before forming the first electrode 63 on the substrate on which the low-melting-point metal layer 61 is formed, a heat treatment is performed in which the substrate is heated at a temperature higher than the melting point of the low-melting-point metal layer 61 and lower than the melting point of the planarization film 50. In this heat treatment, the low-melting-point metal layer 61 melts, and the surface of the low-melting-point metal layer 61 can be leveled to make it a flat surface. As a result, even if protrusions 54 caused by the adhesion of foreign matter X are formed on the surface of the planarization film 50 due to the ashing surface treatment, the height difference caused by the protrusions 54 is absorbed by the low-melting-point metal layer 61. This allows the organic EL layer 66 to be formed to a suitable thickness even in the area corresponding to the protrusions 54. As a result, the risk of leakage between the first electrode 63 and the second electrode 68 can be reduced.

[0100] 《First Modified Example》 As shown in Figure 9, the configuration of the low-melting-point metal layer 61 in this first modified example of the organic EL display device 1 differs from that of the above embodiment.

[0101] In this example, the low-melting-point metal layer 61 is provided in areas excluding the contact holes Hc. Specifically, the low-melting-point metal layer 61 is provided only within each recess 52 on the surface of the planarized film 50. The recesses 52 are formed in the same way as in the above embodiment, so as not to include the contact hole Hc formation area on the inside when viewed from above. The low-melting-point metal layer 61 is formed to cover the entire bottom surface of the recess 52. The low-melting-point metal layer 61 is not provided on the outside of the recesses 52 on the surface of the planarized film 50.

[0102] To manufacture the organic EL display device 1 of this example, a planarization film 50 is formed in the same manner as in the above embodiment, and after ashing the surface of the planarization film 50, a low-melting-point metal layer 61 is formed on the surface of the planarization film 50 in a predetermined pattern. Specifically, as shown in the upper part of Figure 10A, on a substrate having the ashing planarization film 50, a low-melting-point metal layer 61 made of indium (In) is formed in each recess 52 by vacuum deposition using a deposition mask 210 called an FMM (Fine Metal Mask) which has apertures 211 that can be patterned on a sub-pixel basis.

[0103] Next, the substrate on which the low-melting-point metal layer 61 is formed is heated. For example, the substrate is placed on a hot plate and heated at 280°C for 2 minutes. By heating the substrate in this way, the low-melting-point metal layer 61 is subjected to a temperature above its melting point, causing it to melt. As a result, the surface of the low-melting-point metal layer 61 is flattened, as shown in the lower part of Figure 10A. At this time, even if the low-melting-point metal layer 61 melts, it does not flow out from the recess 52 to the area outside of it.

[0104] In the subsequent first electrode formation step, the first electrode 63 is formed on the low-melting-point metal layer 61 after heating the substrate, as shown in the upper diagram of Figure 10B, in the same manner as in the above embodiment. Furthermore, in the bank formation step, the bank 65 is formed on the substrate on which the first electrode 63 is formed, as shown in the lower diagram of Figure 10B, in the same manner as in the above embodiment. Then, the organic EL layer formation step and the second electrode formation step are performed in the same manner as in the above embodiment, and the organic EL layer 66 and the second electrode 68 are formed on the substrate on which the bank 65 is formed, respectively.

[0105] Thereafter, the organic EL display device 1 can be manufactured by performing the sealing film formation step and other steps in the same manner as in the above embodiment.

[0106] -Features of the First Modified Example- In this first modified example of the organic EL display device 1, the low-melting-point metal layer 61 is provided in the region excluding the contact hole Hc. As a result, the contact resistance between the first electrode 63 and the TFT 40 can be reduced because the low-melting-point metal layer 61 is not interposed in the conductive path between the first electrode 63 and the TFT 40. Other effects similar to those of the above embodiment can be obtained.

[0107] 《Second Modification》 As shown in Figure 11, in this second modification of the organic EL display device 1, the configuration of the planarization film 50 and the low melting point metal layer 61 differs from that of the above embodiment.

[0108] In this example, the planarization film 50 does not have the recess 52 formed as in the above embodiment. In this example, the low-melting-point metal layer 61 is formed on the upper layer of the first electrode 63 and is located between the first electrode 63 and the organic EL layer 66. The low-melting-point metal layer 61 is provided within the opening of the bank 65 and is provided so as to cover the surface of the first electrode 63 that is exposed within the opening. The low-melting-point metal layer 61 may extend outside the opening of the bank 65 as long as it is separated for each sub-pixel SP. The low-melting-point metal layer 61 is considered to be included in the first electrode 63. In this case, the low-melting-point metal layer 61 constitutes the surface layer of the first electrode 63.

[0109] To manufacture the organic EL display device 1 in this example, the following steps are performed in order after the planarization film formation step: surface treatment step, first electrode formation step, bank formation step, and low melting point layer formation step.

[0110] In the planarization film formation process, after forming the circuit component layer 20 in the same manner as in the above embodiment, a photosensitive resin coating film is formed on the substrate on which the circuit component layer 20 is formed, and pre-baking, exposure, development, and post-baking are performed on the coating film to form a planarization film 50 having contact holes Hc. During subsequent transport and storage of the substrate, foreign matter X may adhere to the surface of the planarization film 50, as shown in the upper part of Figure 12A.

[0111] In the surface treatment process, similar to the embodiment described above, the surface of the planarization film 50 is ashing to roughen the surface of the planarization film 50, creating an uneven surface and activating it, thereby improving the adhesion of the upper layer film to the surface of the planarization film 50. If foreign matter X adheres to the surface of the planarization film 50 during the surface treatment process, relatively high protrusions 54 are formed on the surface of the planarization film 50, as shown in the lower diagram of Figure 12A. These protrusions 54 remain even after substrate cleaning.

[0112] In the first electrode step, as in the above embodiment, the first electrode 63 is formed on the surface of the planarized film 50 that has been ashed, as shown in the upper part of Figure 12B. Furthermore, in the bank formation step, as shown in the lower part of Figure 12B, a bank 65 is formed on the substrate on which the first electrode 63 is formed, as in the above embodiment. Then, in the low melting point layer formation step, as in the first modified example above, a low melting point metal layer 61 is formed in the opening of the bank 65 by vacuum deposition using a multi-gradation mask 200, as shown in the upper part of Figure 12C. The shape of the protrusion 54 of the first electrode 63 is reflected on the surface of this low melting point metal layer 61.

[0113] Next, the substrate on which the low-melting-point metal layer 61 is formed is heated. For example, the substrate is placed on a hot plate and heated at 280°C for 2 minutes. By heating the substrate in this way, the low-melting-point metal layer 61 is subjected to a temperature above its melting point, causing it to melt. As a result, the surface of the low-melting-point metal layer 61 is flattened, as shown in the lower diagram of Figure 12C. At this time, even if the low-melting-point metal layer 61 melts, it does not flow out of the opening of the bank 65 into the area outside of it.

[0114] In addition, in the low-melting-point layer formation process, the low-melting-point metal layer 61 may be formed in the opening of the bank 65 in the same manner as in the above embodiment. That is, a low-melting-point metal film 102 having a melting point lower than the melting point of the planarization film 50 may be formed on the substrate on which the bank 65 is formed, and the substrate on which the low-melting-point metal film 102 is formed may be heated at a temperature higher than the melting point of the low-melting-point metal layer 61 and lower than the melting point of the planarization film 50, and then the low-melting-point metal film 102 may be patterned to form the low-melting-point metal layer 61.

[0115] Thereafter, the organic EL display device 1 can be manufactured by performing the organic EL layer formation step, the second electrode formation step, the sealing film formation step, and other steps in the same manner as in the above embodiment.

[0116] -Features of the Second Modified Example- In the manufacturing method of the organic EL display device 1 of this second modified example, a substrate on which a first electrode 63 including a low-melting-point metal layer 61 as a surface layer is formed is subjected to a heat treatment at a temperature higher than the melting point of the low-melting-point metal layer 61 and lower than the melting point of the planarization film 50 before forming the organic EL layer 66. In this heat treatment, the low-melting-point metal layer 61 melts, and the surface of the low-melting-point metal layer 61 can be leveled to make a flat surface. As a result, even if protrusions 54 caused by the adhesion of foreign matter X are formed on the surface of the planarization film 50 due to the ashing of the surface treatment, the height difference caused by the protrusions 54 is absorbed by the low-melting-point metal layer 61. This makes it possible to form the organic EL layer 66 with a suitable thickness even in the areas corresponding to the protrusions 54. As a result, the risk of leakage between the first electrode 63 and the second electrode 68 can be reduced.

[0117] 《Other Embodiments》 In the above embodiment, the recess 52 is provided separately for each first electrode 63, but this is not limited to this. The recess 52 may be provided in common for multiple first electrodes 63, as long as the low-melting-point metal layer 61 is separated for each sub-pixel SP. For example, the recess 52 may be provided separately for each pixel PX and extend to correspond to the three sub-pixel SPs that make up one pixel PX. Alternatively, one recess 52 may be provided over the entire display area DA. Furthermore, the recess 52 may not be formed at all.

[0118] In the above embodiment, each pixel PX is assumed to be composed of three sub-pixels SP, but this is not limited to this. The sub-pixels SP constituting each pixel PX may be four or more colors. Also, the sub-pixels SP constituting each pixel PX are assumed to be arranged in a stripe pattern, but this is not limited to this. The arrangement of the multiple sub-pixels SP may be other arrangements, such as a pentile arrangement.

[0119] Furthermore, each pixel PX may not be divided into multiple subpixels SP, but rather composed of a single organic EL element 61. Such an organic EL element 61 performs monochrome display, such as grayscale.

[0120] In the above embodiment, the light-emitting layer is provided individually for each subpixel SP, but this is not limited to this. The light-emitting layer may be provided in common as a continuous unit for multiple subpixels SP. In this case, the organic EL display device 1 may provide a color filter or the like to express the color tone at each subpixel SP.

[0121] In the above embodiment, each TFT 40 is assumed to be a top-gate type, but this is not limited to this configuration. Each TFT 40 may also be configured as a bottom-gate type.

[0122] In the above embodiment, the first electrode 63 functions as the anode and the second electrode 68 functions as the cathode, but the embodiment is not limited to this. The organic EL display device 1 may be configured such that the first electrode 63 functions as the cathode and the second electrode 68 functions as the anode. In this case, the organic EL layer 66 has an inverted stacked structure.

[0123] In the above embodiment, the organic EL layer 66 is assumed to have a five-layer structure consisting of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, but it is not limited to this. The organic EL layer 66 may also have a three-layer structure consisting of a hole injection layer / transport layer, a light-emitting layer, and an electron transport layer / injection layer, and any other arbitrary stacked structure can be adopted.

[0124] In the above embodiment, the substrate of the organic EL display device 1 is a substrate layer 10 made of a thin resin film, but it is not limited to this. As the substrate, it is possible to use a substrate made of any material, such as a plastic substrate made of polyethylene terephthalate (PET) or a glass substrate.

[0125] In the above embodiments, an organic EL display device 1 was given as an example of the display device according to the present disclosure, but the invention is not limited thereto. The technology of the present disclosure is applicable to a display device having a plurality of light-emitting elements. An example of such a display device is a quantum dot display device. A quantum dot display device is a display device that uses a quantum dot light-emitting element, also called a QLED (Quantum-dot Light Emitting Diode), which has a quantum dot-containing layer, as the light-emitting element.

[0126] As described above, preferred embodiments have been explained as examples of the technology of this disclosure. However, the technology of this disclosure is not limited thereto and can be applied to embodiments that are modified, replaced, added to, or omitted as appropriate. It will be understood by those skilled in the art that various further modifications are possible to the above embodiments without departing from the spirit of the technology of this disclosure, and that such modifications also fall within the scope of the technology of this disclosure.

[0127] Furthermore, the notations "First," "Second," etc., mentioned above are merely used to distinguish the phrases to which these notations are attached, and do not limit the number or order of such phrases. Also, the notation "~" in numerical ranges means a range that includes the numbers before and after it. That is, if X and Y are used as substitutes for numbers, then "X~Y" indicates a range of "greater than or equal to X and less than or equal to Y."

[0128] As described above, this disclosure is useful for display devices and methods for manufacturing the same.

[0129] 1 Organic EL display device (display device) 20 Circuit configuration layer 22 Gate line (wiring) 24 Light emission control line (wiring) 26 Power branch line (wiring) 28 Source line (wiring) 30 Power line (wiring) 32 First power main line (wiring) 34 Second power main line (wiring) 36 Lead line (wiring) 40 TFT (circuit element) 42 Capacitor (circuit element) 50 Planarization film 52 Recess 61 Low melting point metal layer 62 Organic EL element (light-emitting element) 63 First electrode 66 Organic EL layer (electroluminescence layer) 68 Second electrode 102 Low melting point metal film Hc Contact hole

Claims

1. A display device comprising: a circuit configuration layer including circuit elements and wiring; a planarization film provided on the circuit configuration layer; and a plurality of light-emitting elements provided on the planarization film, wherein each of the plurality of light-emitting elements has a first electrode individually provided on the planarization film, an electroluminescent layer provided on the first electrode, and a second electrode provided so as to overlap the first electrode via the electroluminescent layer, and a low-melting-point metal layer having a melting point lower than the melting point of the planarization film is provided between the planarization film and the electroluminescent layer in the region corresponding to the first electrode.

2. A display device according to claim 1, wherein a recess is formed in the portion of the surface of the planarized film corresponding to the first electrode, and the low-melting-point metal layer is provided in a region including the recess.

3. A display device according to claim 2, wherein the recess is provided separately for each of the first electrodes.

4. A display device according to claim 3, further comprising a bank provided on the planarized film so as to extend between adjacent first electrodes, wherein the bank is provided so as to cover the inner circumferential surface of the recess, and the electroluminescent layer is provided in the region surrounded by the bank.

5. A display device according to any one of claims 2 to 4, wherein the planarized film has a contact hole formed therein for connecting the first electrode to the circuit element, and the recess is formed such that, in a plan view, the portion where the contact hole is formed is not included on the inside.

6. A display device according to any one of claims 1 to 5, wherein the thickness of the low-melting-point metal layer is 180 nm or more and 1000 nm or less.

7. A display device according to any one of claims 1 to 6, wherein the low-melting-point metal layer is provided between the planarized film and the first electrode.

8. A display device according to claim 7, wherein the planarized film has contact holes formed therein for connecting the first electrode to the circuit element, and the low-melting-point metal layer is provided in a region excluding the contact holes.

9. A display device according to any one of claims 1 to 6, wherein the low-melting-point metal layer is included in the first electrode and constitutes the surface layer of the first electrode.

10. A display device according to any one of claims 1 to 9, wherein the low-melting-point metal layer is made of a metallic material containing at least one metal selected from lead, cadmium, bismuth, tin, and indium.

11. A display device according to any one of claims 1 to 10, wherein the light-emitting element is an organic electroluminescent element or a quantum dot light-emitting element.

12. A method for manufacturing the display device described in claim 1, comprising: a circuit configuration layer formation step of forming the circuit configuration layer on a substrate; a planarization film formation step of forming the planarization film on the circuit configuration layer; a surface treatment step of ashing the surface of the planarization film; a low melting point layer formation step of forming the low melting point metal layer on the ashing surface of the planarization film; a first electrode formation step of forming the first electrode on the low melting point metal layer; an electroluminescence layer formation step of forming an electroluminescence layer on the first electrode; and a second electrode formation step of forming the second electrode so as to overlap the first electrode via the electroluminescence layer, wherein in the low melting point layer formation step, a low melting point metal film having a melting point lower than the melting point of the planarization film is formed, and the substrate on which the low melting point metal film is formed is heated at a temperature higher than the melting point of the low melting point metal layer and lower than the melting point of the planarization film, and then the low melting point metal film is patterned to form the low melting point metal layer, or A method for manufacturing a display device, comprising heating a substrate on which the low-melting-point metal layer is formed at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film.

13. A method for manufacturing the display device described in claim 1, comprising: a circuit configuration layer formation step of forming the circuit configuration layer on a substrate; a planarization film formation step of forming the planarization film on the circuit configuration layer; a surface treatment step of performing ashing on the surface of the planarization film; a first electrode formation step of forming the first electrode on the ashing surface of the planarization film; a low melting point layer formation step of forming the low melting point metal layer on the first electrode; an electroluminescence layer formation step of forming an electroluminescence layer so as to overlap the first electrode via the low melting point metal layer; and a second electrode formation step of forming the second electrode so as to overlap the first electrode via the low melting point metal layer and the electroluminescence layer, wherein in the low melting point layer formation step, A method for manufacturing a display device, comprising: forming a low-melting-point metal film having a melting point lower than the melting point of the planarization film; heating the substrate on which the low-melting-point metal film is formed at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film, and then patterning the low-melting-point metal film to form the low-melting-point metal layer; or heating the substrate on which the low-melting-point metal layer is formed at a temperature higher than the melting point of the low-melting-point metal layer and lower than the melting point of the planarization film.

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