Heteroepitaxial wafer and method for manufacturing same

Abstract

The present invention pertains to: a heteroepitaxial wafer comprising a 3C-SiC epitaxial layer on a single crystal silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer; and a method for manufacturing the same. As a result, provided are: a heteroepitaxial wafer having a gate-insulating film in which the problem of basal plane dislocation does not occur, and which has high reliability at level equivalent to that of silicon; and a method for manufacturing the same.

Description

Heteroepitaxial Wafer and Method for Producing the Same

[0001] The present invention relates to a heteroepitaxial wafer and a method for producing the same.

[0002] In fields such as the electrification of automobiles and FA (Factory Automation), the need for power devices has been increasing in a very wide range. Also, energy losses in power semiconductors have become non-negligible, and research on structures with good energy efficiency has been conducted and significant results have been achieved. This energy loss is caused by the conversion of electrical energy into heat, and while many measures have been taken for this waste heat, there are also constraints. For example, in the case of in-vehicle IGBTs, as HV and EVs become more highly functional, the number of mounted electronic devices has increased, and the cooling system has become larger for cooling, to the extent that it also affects the design of automobiles.

[0003] Therefore, the use of materials other than silicon has been studied. Among them, SiC has a high breakdown strength because it has a wide bandgap of 2.2 to 3.3 eV, and also has a large thermal conductivity, so it is expected as a semiconductor material for various semiconductor devices such as power devices and high-frequency devices.

[0004] Patent Document 1 discloses a method for manufacturing a semiconductor wafer in which a 3C-SiC layer is formed on a silicon substrate and a silicon layer is formed on the 3C-SiC layer.

[0005] U.S. Patent No. 9,576,793

[0006] Shiozaki, Fumio, "Semiconductor Silicon Engineering", p170, Maruzen Co., Ltd. (1993)

[0007] Unlike silicon, which is grown by melting, SiC is grown using methods such as sublimation and gas growth. However, it has more crystal defects than silicon and its productivity is inferior. Furthermore, when used in actual devices, substrates with epitaxial growth on top of the bulk crystal are used. In this case, especially when forward current flows in power devices, the basal plane dislocations of the bulk crystal expand as stacking faults, leading to a problem of current degradation. In addition to the high number of crystal defects, the composition of silicon and carbon makes it difficult to form highly reliable gate insulating films like those made of silicon in devices such as IGBTs.

[0008] The present invention has been made to solve the above problems and aims to provide a heteroepitaxial wafer having a gate insulating film that does not cause basal plane dislocation problems and has the same level of reliability as silicon, and a method for manufacturing the same.

[0009] The present invention has been made to achieve the above objective and provides a heteroepitaxial wafer having a 3C-SiC epitaxial layer on a single-crystal silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer.

[0010] Such heteroepitaxial wafers, by having a 3C-SiC epitaxial layer on a silicon substrate, enable large-diameter substrates and eliminate the problem of basal plane dislocation expansion due to forward current. Furthermore, because 3C-SiC has a wide bandgap, in IGBT applications, it can have a voltage-holding layer with equivalent voltage resistance characteristics even when thinner than silicon. Moreover, since silicon on the 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film is equivalent to that of silicon.

[0011] The present invention has also been made to achieve the above objectives and provides a method for manufacturing a heteroepitaxial wafer, comprising the steps of: removing a native oxide film on the surface of a single-crystal silicon substrate by hydrogen baking; epitaxially growing a 3C-SiC epitaxial layer on the surface of the single-crystal silicon substrate using a gas containing carbon and silicon as a source gas; forming a silicon layer on the 3C-SiC epitaxial layer; and thermally oxidizing the silicon layer.

[0012] This heteroepitaxial wafer manufacturing method allows for the creation of large-diameter substrates by epitaxially growing a 3C-SiC epitaxial layer on a silicon substrate, and prevents the problem of bulk crystal basal plane dislocations expanding as stacking faults due to forward current flow. Furthermore, because 3C-SiC has a wide bandgap, for IGBT applications, it is possible to form a voltage-bearing layer with equivalent voltage resistance characteristics to silicon even when thinner. In addition, since silicon grown on the 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film can be manufactured to be equivalent to that of silicon.

[0013] In this case, the silicon layer can be single-crystal silicon, polysilicon, or amorphous silicon.

[0014] These silicon materials can be used to oxidize the aforementioned silicon layer into an amorphous silicon oxide film.

[0015] In this case, the thickness of the silicon layer can be set to 0.45 times the thickness of the silicon oxide film formed by thermal oxidation.

[0016] This makes it possible to form a silicon oxide film of the desired thickness.

[0017] As described above, the heteroepitaxial wafer of the present invention, by having a 3C-SiC epitaxial layer on a silicon substrate, results in a large-diameter substrate, and the problem of basal plane dislocation expansion due to forward current is eliminated. Furthermore, because 3C-SiC has a wide bandgap, in the case of IGBT applications, it can have a voltage-holding layer with equivalent voltage resistance characteristics even if it is thinner than silicon. Moreover, since silicon on the 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film is also equivalent to that of silicon.

[0018] Furthermore, according to the heteroepitaxial wafer manufacturing method of the present invention, a large-diameter substrate can be realized by epitaxially growing a 3C-SiC epitaxial layer on a silicon substrate, and a wafer can be manufactured without the problem of basal plane dislocations of the bulk crystal expanding as stacking faults due to forward current. In addition, since 3C-SiC has a wide bandgap, in the case of IGBT applications, a voltage-resistant layer with equivalent voltage resistance characteristics can be formed even if it is thinner than silicon. Moreover, since silicon grown on 3C-SiC is used as an oxide film in the gate area where reliability is required, a gate insulating film with the same reliability as silicon can be manufactured.

[0019] A schematic cross-sectional view of an example of a heteroepitaxial wafer according to the present invention is shown. An example of a wafer growth sequence by the heteroepitaxial wafer manufacturing method according to the present invention is shown.

[0020] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0021] As described above, there was a need for heteroepitaxial wafers and manufacturing methods thereof that do not experience basal plane dislocation problems and have gate insulating films with reliability equivalent to those of silicon.

[0022] The inventors of this invention have diligently studied the above-mentioned problems and have come up with the idea that by combining SiC, which has basic characteristics suitable for power devices (high insulation properties due to a wide bandgap and high thermal conductivity), with conventionally used silicon, it is possible to manufacture efficient substrates for power semiconductors, especially for IGBTs.

[0023] As a result of further investigation, the inventors have found that a heteroepitaxial wafer having a 3C-SiC epitaxial layer on a single-crystal silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer results in a large-diameter substrate due to the presence of the 3C-SiC epitaxial layer on the silicon substrate, and eliminates the problem of basal plane dislocation expansion due to forward current. Furthermore, because 3C-SiC has a wide bandgap, in the case of IGBT applications, it is possible to have a voltage-holding layer with equivalent voltage resistance characteristics even if it is thinner than silicon. Moreover, since silicon on the 3C-SiC is used as an oxide film in the gate area where reliability is required, the reliability of the gate insulating film is also equivalent to that of silicon. With these findings, the inventors have completed the present invention.

[0024] The inventors have also conducted extensive research on the above problem and have now developed a method for manufacturing a heteroepitaxial wafer that includes the steps of: removing the native oxide film on the surface of a single-crystal silicon substrate by hydrogen baking; epitaxially growing a 3C-SiC epitaxial layer on the surface of the single-crystal silicon substrate using a gas containing carbon and silicon as a source gas; forming a silicon layer on the 3C-SiC epitaxial layer; and thermally oxidizing the silicon layer. By using scalar growth, large-diameter substrates can be realized, and products can be manufactured that do not suffer from the problem of bulk crystal basal plane dislocations expanding as stacking faults due to forward current. Furthermore, because 3C-SiC has a wide bandgap, in the case of IGBT applications, a voltage-resistant layer with equivalent voltage resistance characteristics can be formed even if it is thinner than silicon. Moreover, since silicon grown on 3C-SiC is used as an oxide film in the gate area where reliability is required, it has been found that a gate insulating film with the same reliability as silicon can be manufactured, thus completing the present invention.

[0025] [Hetero-epitaxial wafer] Embodiments of the present invention will be described below with reference to the drawings. Figure 1 shows a schematic cross-sectional view of an example of a hetero-epitaxial wafer according to the present invention. The hetero-epitaxial wafer 1 shown in Figure 1 has a 3C-SiC epitaxial layer 3 on a single-crystal silicon substrate 2 and a silicon oxide film 5 on the 3C-SiC epitaxial layer 3.

[0026] A single-crystal silicon substrate 2 can be a substrate with a diameter of 300 mm or more. This makes it possible to manufacture devices with larger diameters than when using single-crystal bulk SiC manufactured by sublimation or other methods. Other characteristics are not particularly limited, but for example, the plane orientation of the main surface may be (111), the conductivity type may be p-type or n-type, and the resistivity may be low resistivity of 0.1 Ω·cm or less or high resistivity of 1000 Ω·cm or more. The single-crystal silicon substrate can be manufactured using the same single-crystal manufacturing equipment and procedures as conventional methods.

[0027] By having a 3C-SiC epitaxial layer 3 on a single-crystal silicon substrate 2, the electrical conductivity degradation that occurs when bulk crystals are used, as described above, is avoided.

[0028] In IBGT applications, the 3C-SiC epitaxial layer 3 serves as the dielectric strength retention layer. While the dielectric breakdown field strength of silicon is 0.3 MV / cm, the dielectric breakdown field strength of 3C-SiC is 3 MV / cm, which is 10 times greater for 3C-SiC than for silicon. In other words, equivalent performance can be obtained with a dielectric strength retention layer that is 1 / 10th the thickness of that of conventional silicon IGBTs. It is not necessary to form the dielectric strength retention layer with only 3C-SiC; a combination of SiC and silicon may also be used.

[0029] As described later, the silicon oxide film 5 becomes a gate insulating film with the same reliability as silicon.

[0030] [Method for Manufacturing Hetero-Epitaxial Wafers] Next, the method for manufacturing hetero-epitaxial wafers according to the present invention will be described with reference to Figure 2. Figure 2 shows an example of a wafer growth sequence by the hetero-epitaxial wafer manufacturing method according to the present invention. Note that the matters described above regarding hetero-epitaxial wafers may be omitted.

[0031] (Step to remove native oxide film by hydrogen baking: S1) First, a single crystal silicon substrate 2 is placed in a reduced pressure (RP-)CVD apparatus, and the native oxide film on the surface is removed by hydrogen baking (H ２ It is removed by annealing. If an amorphous oxide film remains, SiC nucleation on the single-crystal silicon substrate 2 will not be possible. At this time, H ２ The annealing process is not particularly limited, but it is preferable to use a temperature of 1000°C to 1200°C. Within this temperature range, it is not necessary to allow for a long processing time to prevent the residue of the native oxide film, and the occurrence of slip can be effectively reduced. ２ There are no particular restrictions on the annealing pressure or time, as long as it is sufficient to remove the native oxide film.

[0032] (Step for epitaxial growth of 3C-SiC epitaxial layer: S2) Next, the single-crystal silicon substrate 2 is preferably set to a temperature of 300°C to 1100°C, and a gas containing carbon and silicon, such as monomethylsilane or trimethylsilane, is introduced as a source gas to perform SiC nucleation. Compared to Si, C atoms are smaller and more easily vaporized, so trimethylsilane is easier to adjust the growth conditions with when considering raw material efficiency.

[0033] SiC nucleation can be performed, for example, on the surface of a single-crystal silicon substrate 2 at a pressure of 100 Torr (13332 Pa) or less and a temperature of 300°C or higher. However, since epitaxial growth of SiC is promoted at temperatures of 800°C or higher, it is more preferable to set the SiC nucleation temperature to 800°C or higher so that SiC nucleation and the formation of the 3C-SiC epitaxial layer 3 can be performed under the same conditions. Furthermore, if the temperature is 1100°C or lower, polycrystallization and the adhesion of by-products to the inner wall of the CVD apparatus can be effectively suppressed. This is presumed to be because at high temperatures, molecules adsorbed on the substrate surface desorb before epitaxial growth, causing a gas-phase reaction.

[0034] Furthermore, the growth pressure for epitaxial growth of the 3C-SiC epitaxial layer 3 is preferably 100 Torr (13332 Pa) or less. If the growth pressure is 100 Torr or less, polycrystallization of the 3C-SiC can be effectively prevented. If the pressure is 10 Torr or less, and more preferably 1 Torr or less, vacancies will be formed directly beneath the 3C-SiC epitaxial layer 3, and the effect of relaxing the stress on the entire epitaxial layer can be obtained.

[0035] Since the film thickness at this time depends on the pressure and temperature, the film deposition time can be appropriately set based on the pressure and temperature conditions set to achieve the desired thickness of the 3C-SiC epitaxial layer 3.

[0036] (Step to form the silicon layer: S3) A silicon layer 4 is grown on the 3C-SiC epitaxial layer 3, which has been grown to a predetermined thickness as described above, using a CVD apparatus.

[0037] The silicon layer 4 does not need to be single-crystal silicon; it can also be polysilicon or amorphous silicon. This is because the silicon layer 4 is oxidized to form an amorphous silicon oxide film.

[0038] (Process of thermal oxidation of the silicon layer: S4) The silicon layer 4 is thermally oxidized to form a silicon oxide film 5. The thermal oxidation conditions are not particularly limited and can be adjusted and optimized according to the equipment and process.

[0039] In order to completely oxidize the silicon layer 4 into the silicon oxide film 5, the thickness of the silicon layer 4 is calculated backward from the desired thickness of the silicon oxide film 5. Although it is preferable to determine the thickness by prior tests, the thickness of the silicon layer 4 can be set to 45% of the desired thickness of the silicon oxide film 5. This is because it is known that when silicon is oxidized to form a silicon oxide film, due to volume expansion, the ratio of the thickness of the silicon oxide film to the original silicon is 1:0.45 (Non-Patent Document 1).

[0040] By forming the silicon layer 4 into the silicon oxide film 5, the quality of the gate oxide film in the semiconductor device can be improved. That is, in the conventional SiC device, the gate insulating film was formed using SiC, and there were reliability problems. However, in the present invention, silicon is grown on the 3C-SiC epitaxial layer 3, and this silicon is used to form the gate insulating film, so it is possible to ensure the same gate reliability as the conventional silicon IGBT. Also, the thickness of the silicon layer at this time only needs to be thicker than the required gate structure and can be set arbitrarily.

[0041] Hereinafter, the present invention will be specifically described with reference to examples, but this does not limit the present invention.

[0042] A 3C-SiC epitaxial layer was formed on a single crystal silicon substrate with a diameter of 300 mm, and further a single crystal Si epitaxial layer was formed on its surface. By oxidizing this silicon epitaxial layer, a substrate with a silicon oxide film having a thickness of 100 nm formed on its surface was fabricated.

[0043] Specifically, first, as the single crystal silicon substrate 2, a single crystal silicon substrate with a diameter of 300 mm, a surface plane orientation of (111), boron-doped, and a high resistivity was prepared. The single crystal silicon substrate was placed on the susceptor in the reaction furnace of the reduced pressure CVD apparatus, and annealing was performed at 1080 °C for 1 minute to remove the natural oxide film on the substrate surface. ２ Annealing was performed to remove the natural oxide film on the substrate surface.

[0044] Subsequently, trimethylsilane gas was introduced with a growth temperature of 900 °C and a growth pressure of 5 Torr (666.6 Pa), and nucleation of SiC and growth of the 3C-SiC epitaxial layer 3 were performed. Growth was carried out for 15 minutes to achieve a film thickness of 45 nm. Thereafter, when the XRD spectrum was confirmed in the In Plane configuration, a peak of 3C-SiC(220) parallel to Si(220) was confirmed, and it was confirmed that the single-crystalline 3C-SiC epitaxial layer 3 had grown.

[0045] Subsequently, trichlorosilane gas was introduced onto the 3C-SiC epitaxial layer 3 with a growth temperature of 1100 °C and normal pressure to form a 45-nm single-crystalline silicon layer 4. The substrate was introduced into a pyrogenic oxidation furnace, and the silicon layer 4 was completely oxidized under the conditions of 1000 °C for 30 minutes to form a silicon oxide film 5, obtaining a desired heteroepitaxial wafer.

[0046] For the obtained heteroepitaxial wafer, a breakdown voltage evaluation of the oxide film was performed. Phosphorus-doped polysilicon was grown to 300 nm as an electrode. Thereafter, 300 electrodes with a size of 1 mm were formed on the wafer by photolithography and dry etching (CF ４ / O ２ mixed gas). An electrical stress of 0.01 A / cm ２ was applied to these elements at room temperature for 10 seconds to check for initial defective elements, and this ratio was 0%, indicating good quality.

[0047] Next, 10 of these elements were randomly selected, and the current was monitored while applying a voltage in steps of 0.25 V. When the current value reached 0.01 A, it was defined as dielectric breakdown, and the breakdown voltage was measured. As a result, the breakdown voltages of these elements were all greater than 70 V, indicating good characteristics.

[0048] As described above, according to the embodiment of the present invention, a heteroepitaxial wafer having breakdown voltage characteristics equivalent to those of silicon and reliability of the gate insulating film can be manufactured on a large-diameter substrate without current degradation when used for IGBT applications.

[0049] ​​It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention.

Claims

1. A heteroepitaxial wafer characterized by having a 3C-SiC epitaxial layer on a single-crystal silicon substrate and a silicon oxide film on the 3C-SiC epitaxial layer.

2. A method for manufacturing a heteroepitaxial wafer, comprising the steps of: removing a native oxide film on the surface of a single-crystal silicon substrate by hydrogen baking; epitaxially growing a 3C-SiC epitaxial layer on the surface of the single-crystal silicon substrate using a gas containing carbon and silicon as a source gas; forming a silicon layer on the 3C-SiC epitaxial layer; and thermally oxidizing the silicon layer.

3. The method for manufacturing a heteroepitaxial wafer according to claim 2, characterized in that the silicon layer is single-crystal silicon, polysilicon, or amorphous silicon.

4. The method for manufacturing a heteroepitaxial wafer according to claim 2 or 3, characterized in that the thickness of the silicon layer is 0.45 times the thickness of the silicon oxide film formed by thermal oxidation.

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