Testing system, source measure unit therefor, and associated method of testing a device under test

Abstract

The testing system can have a controller, and a plurality of channels which may have source measure units, each channel individually connectable to one or more electrical connection of a device under test (DUT). A source measure unit can have voltage sources connected to the controller; a pulse generator having an input port connected to the voltage sources, a control port connected to the controller, and an output port; an analog-to-digital converter (ADC); and a current-to-voltage (I / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT. The testing system or the source measure unit can further have current limitation units connected in series between the source measure units and / or a fixed voltage reference and the DUT, each current limitation unit having a first transistor and a second transistor configured in a common source or common drain configuration and each having a corresponding gate, the gates having an electrical potential controllable to an intermediary value by the controller.

Description

TESTING SYSTEM, SOURCE MEASURE UNIT THEREFOR, AND ASSOCIATED METHOD OF TESTING A DEVICE UNDER TESTBACKGROUND

[0001] Some electronic devices, such as diodes, memristors, NMOS transistors and some types of “chips”, have one or more electrical connections (e.g. pins or connectors) and require testing. Testing systems can be used to perform testing of such electronic devices, in which case the electronic device can be referred to as a device under test (DUT). Many testing systems have one or more channels which apply a voltage difference in series across the DUT. Some testing systems include one or more units of the source measure type (commonly referred to as source measure unit - SMU). A source measure unit is an instrument that combines a sourcing function and a measurement function on the same connection. Indeed, to perform current measurements while applying a voltage on a Device Under Test (DUT), a source measure unit can generate a voltage signal on a given input-output (I / O) port, while simultaneously measuring the current sourced or sunk by the same input-output (I / O) port. While existing testing systems were satisfactory to a certain degree, there always remains room for improvement, such as reducing cost, footprint, increasing precision, reliability, measurement speed, etc.SUMMARY

[0002] In accordance with a first aspect, in some embodiments, there can be provided a source measure unit which can be integrated to a testing system. The source measure unit can have a pulse generator connectable to a connexion of the DUT via a current-to-voltage converter, the current-to-voltage converter having an output connectable to a connexion of a controller via an analog-to-digital converter.

[0003] Indeed, it can be preferred in some cases for a source measure unit (SMU) to perform pulsed measurements, in which cases the SMU can be referred to as pulse measurement unit (PMU). In some cases, PMUs can be embodied as arbitrary pulse measurement units (APMUs). Pulsed measurements can be beneficial in applications where controlling power dissipation, avoiding thermal effects, and capturing dynamic responses are concerns. For instance, prolonged exposure to voltages can lead to the heating of the Device Under Test(DUT), potentially damaging the device or yielding inaccurate results. Fast pulsed current measurements can provide accurate data while minimizing thermal stress on components. This can be relevant, in particular, for DllTs having transistors such as MOSFETs, BJTs, and IGBTs, where prolonged polarization can undesirably shift component characteristics due to heating. Pulsed measurements can also be relevant for a wide range of other applications, including DllTs such as LEDs, low-power IC components, MEMS, nanoelectronic devices having nanowires and / or carbon nanotubes, and materials like ferroelectrics or piezoelectrics.

[0004] Alternately, or in addition to mitigating heat-induced errors, pulsed measurements can facilitate transient analysis. Transient analysis involves examining the time-varying behavior of devices over short periods. This type of analysis can be beneficial for various types of DllTs, including memory devices such as memristors, transient overvoltage protection (TVS) devices, capacitors and inductors with charging and discharging capabilities, switch-mode power supplies (SMPS), and DC-DC converters.

[0005] In accordance with one aspect, one approach to perform source measurements involves using a voltage source connected directly to a current-to-voltage (l-V) converter. When speed of testing is a concern, one potential inconvenience of the latter approach is that high-speed voltage sources can require multiple parallel interface signals connected to a processing unit, which may increase the costs or otherwise decrease feasibility of integrating numerous SMlls into a single piece of equipment while maintaining a compact design (small footprint). One way to address this challenge is to combine one or more lower-frequency voltage sources (which can be represented by fixed voltage references or variable DAC outputs) with a pulse generator, and connecting the pulse generator to the current-to-voltage converter.

[0006] In accordance with one aspect, there is provided a source measure unit drivable by a controller to perform testing of a device under test (DUT), the source measure unit comprising: voltage sources connectable to the controller; a pulse generator having an input port connected to the voltage sources, a control port connectable to the controller, and an output port; an analog-to-digital converter (ADC); and a current-to-voltage (1 / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT.

[0007] In accordance with one other aspect, there can be provided a current limitation unit which can be integrated to or connected to a testing system. The current limitation unit can have two transistors disposed in a common source configuration in series between the device under test and a voltage source such as a source measure unit. By contrast with a mode of operation where the current limitation unit can be used as a switch, in which case the voltage at the gates can be set to zero, to open the switch, or set to a relatively high voltage, to allow unimpeded current circulation across the switch, the current limitation unit can be used in a current limiting mode of operation, where the voltage at the gates can be set to an intermediary value which limits current circulation to values considered “safe” for the DUT. In some embodiments, a same current limitation unit can be controlled in a manner to toggle between the switch mode of operation, and the current limitation mode of operation.

[0008] Indeed, when performing measurements on DUT, there may be a risk of imparting a current across the DUT above values which may be considered acceptable for the DUT. Moreover, where different source measurements are performed independently on a same DUT, such as via different channels, an excessive voltage or current may stem from the combined actions performed by two or more of the channels. One way to address such issues is to use a current-limiting feature that either shuts down or limits the output signal when excess current is detected. However, such features involve monitoring current against a threshold and reacting to detecting that the current has exceeded the threshold by taking action. Such processes can introduce delays of several milliseconds before the current is limited. In some cases, such as applications involving sensitive nanodevices like analog memory and transistors, even a few milliseconds of excessive current may cause permanent damage and may be undesirable.

[0009] It was found that a hardware-based approach can limit the current passing through the DUT without significant delay (e.g., a delay in the order of magnitude of the nanoseconds). The unit can use a tunable hardware design involving two MOSFET transistors (either common-source or common-drain) connected in series, with their gates attached to a voltage source. This configuration allows the current limitation at the "sinking end" of the DUT, the point where the current exits the DUT towards a lower potential, such as ground. By adjusting the voltage applied to the transistor gates, it is possible to control the current limit precisely.

[0010] In accordance with another aspect, there is provided a method of testing a device under test DUT comprising : varying the electrical potential of a point Vi while maintaining the electrical potential of a point V2constant and below the electrical potential of the point V1, thereby applying a difference of potential V12 in series from point Vi to point V2across the DUT, a first transistor and a second transistor, the first transistor and the second transistor being configured in a common source or common drain configuration and each having a respective gate; and simultaneously to said varying the electrical potential, maintaining a difference of potential VG2 between a control potential VGand point V2at an intermediary value including applying the control potential VGto the gates, including the first transistor and the second transistor limiting current circulation across the DUT to below a current limit independently of Vi2while allowing current circulation below the current limit across the DUT.

[0011] More generally, in accordance with another aspect, there is provided a testing system comprising: a controller, and a plurality of channels which may have corresponding source measure units or reference voltages, each channel individually connectable to one or more electrical connection of a device under test (DUT). A source measure unit can have voltage sources connected to the controller; a pulse generator having an input port connected to the voltage sources, a control port connected to the controller, and an output port; an analog-to- digital converter (ADC); and a current-to-voltage (l / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT. The testing system or the source measure unit can further have current limitation units connected in series between the source measure units and / or a fixed voltage source and the DUT, each current limitation unit having a first transistor and a second transistor configured in a common source or common drain configuration and each having a corresponding gate, the gates having an electrical potential controllable to an intermediary value by the controller.

[0012] Many further features and combinations thereof concerning the present improvements will appear to those skilled in the art following a reading of the instant disclosure.DESCRIPTION OF THE FIGURES

[0013] In the figures,

[0014] Fig. 1 is a block diagram of an example of a testing system;

[0015] Fig. 2 is a block diagram of another example of a testing system;

[0016] Figs 3A to 3D are schematics presenting possible variants of pulse generators;

[0017] Figs 4A to 4D are schematics presenting possible variants of current sensing circuits;

[0018] Fig. 5 is a block diagram of another example of a testing system;

[0019] Fig. 6 is a graph showing the relationship between resistance across the current limitation circuit as a function of variations in voltage between the gates and the output;

[0020] Figs 7A to 7C present different example applications of a testing system such as shown in Fig. 5;

[0021] Fig. 7D is a graph showing the relationships between voltage and current in an example process of testing a diode;

[0022] Fig. 7E is a graph showing three different possible relationships between current and voltage across a diode, based on application of different gate voltage;

[0023] Figs 8A to 8B present example variants of transistors configured in common source or common drain configurations;

[0024] Fig 9 presents an example application of a testing system used to test an ASIC;

[0025] Fig. 10 presents a high-level block diagram of the components of an example system;

[0026] Fig. 11 presents a mid-level block diagram illustrating modules of an example measurement platform;

[0027] Fig. 12A presents a high-level architecture of a pulse measurement unit (APMLI);

[0028] Fig. 12B presents a general measurement system, which uses two or more APMlls;

[0029] Fig. 13 is a graph presenting positive and negative pulses of ±5 V generated with the APMlls, probed with an oscilloscope, and concatenated for illustration purposes;

[0030] Fig. 14 is a graph presenting APMLI timing definitions for pulse and arbitrary voltage generation capabilities;

[0031] Fig. 15a and 15b are graphs presenting examples of sinusoid and sweep voltage waveforms, respectively, with amplitude 1 to 5 V, generated with voltage waveform generation functionality of the APMlls;

[0032] Fig. 16 is a graph presenting an average accuracy for the output voltage of eight APMUs, where the respective means and variance are represented by dots and bars;

[0033] Fig. 17 is a graph presenting APMU current measurement accuracy;

[0034] Fig. 18 is a graph presenting APMU current measurement error for varying reading pulse width;

[0035] Fig. 19 is a graph presenting noise results; and

[0036] Fig. 20 is a schematic view of a computer.DETAILED DESCRIPTION

[0037] Fig. 1 shows an example of a testing system 10 which can be used to perform electrical testing on a device under test (DUT) 12. The testing system 10 has a testing module 14 which can have one or more channels 16a, 16b. The different channels 16a, 16b can have corresponding voltage sources (e.g., as part of source-measure units). The testing system 10 can optionally further have a current limitation module 18. The current limitation module 18 can have one or more current limitation unit, such as different current limitation units 20a, 20b, connected in series between the different channels 16a, 16b and the DUT 12. The testing system 10 can have a controller 22 which can control the operation of the testing module 14 and / or the current limitation module 18. The controller 22, the testing module 14, and the current limitation module18 can be sold separately, by different providers, in the form of different parts adapted to be connected to one another, or sold in combination or as any sub-combination, with different parts connected to one another in a more permanent manner. In this specification, the expression “connectable” is intended to include “connected”. The DUT 12 can be of various types, as exposed above and below for illustrative purposes. The controller 22 can be, or include, a computer for instance, in which case it can include a processing unit and a memory operable to store instructions and data. The controller 22 can have different architectures. These architectures can be sequential, such as a central processing unit (CPU) or a microcontroller, or parallel, such as a field-programmable gate array (FPGA) or a graphics processing unit (GPU). The speed of the communication between the processing unit and components of the testing module 14 will vary depending on the chosen architecture for the processing unit and the communication protocol used between the two.

[0038] Fig. 2 presents another example of a testing system 110 having a controller 122 and a testing module 114. In this example, the testing module 114 has n channels, and each channel has a source measure unit (SMU) 116a, 116b, 116n. The channels can be configured similarly (e.g., identically) to one another. In this example, each source measure unit 116a, 116b, 116n has two or more voltage sources, a pulse generator, a current-to-voltage (l / V) converter, and an analog-to-digital converter (ADC). Each channel can be connected to one or more electrical connexions of the DUT 112. Different channels may be connected to different electrical connexions of the DUT 112, or, in some cases, some different channels may have one or more connexion on a same electrical connexion of the DUT 112. In some alternate embodiments, the testing module 114 may have a single channel.

[0039] In this example, more specifically, in the source measure unit 116a, the pulse generator has an input port connected to the voltage sources, a control port connected to the controller 122, and an output port connected to an input port of the l / V converter. The voltage sources are connected to the controller 122 and can receive data from the controller 122. The voltage sources can be fixed voltage references, or digital-to-analog converters (DAC) for instance. The l / V converter has an output port connected to the ADC, and a third port connectable to one or more electrical connexions of the DUT 112. The third port can be used as an input / output (I / O) port of the SMU 116a. The ADC is further connected to the controller 122 and can feed data to the controller 122.

[0040] The direct connection (coupling) between the pulse generator and the current-to- voltage converter can be instrumental in allowing the SMU 116 to perform high-speed measurements. Indeed, such as will be exemplified in greater detail below, this can involve pulsing the I / O port of the SMU 116a. By contrast, connecting the pulse generator directly to the I / O port may limit the ability to perform pulsed measurements at higher speeds. Indeed, the pulse generator can produce high-speed pulses by alternating between the outputs of two or more voltage sources, in an arrangement resulting in a variable voltage source based on two or more voltage sources which can be fixed voltage sources. This can be achieved using only one or a few digital control signals connected to the pulse generator, depending on the number of voltage sources at its input.

[0041] Figs. 3A to 3D present different examples of topological variations which can be used for a pulse generator (e.g., pulse generators of Fig. 2 or of Figs. 4A to 4D) in different embodiments. One option is using an analog switch 30, 32 with two or more inputs (as shown Figs. 3A and 3B), or multiple analog switches with a common output (shown at Fig. 3D). Another option involves transistors 34a, 34b, such as MOSFETs or bipolar transistors (as depicted in Fig. 3C).

[0042] In some embodiments, a topology such as shown Fig. 3A or 3B may be selected because it may allow higher-frequency pulse generation with better signal integrity compared to a MOSFET-based design. Additionally, it uses only two inputs, which may be sufficient and preferable in some embodiments.

[0043] Referring to examples presented in Figs 4A to 4D, a current-to-voltage converter (e.g., current-to-voltage converter of Fig. 2) can be used to apply the output voltage from the pulse generator to the I / O port of the SMU (e.g., SMU 116a) while converting the current passing through a sensing resistor 40 (Rsense) into a voltage. This voltage can then be read by an analog-to-digital converter (ADC - e.g., ADC of Fig. 2). In some embodiments, these latter components can be collectively referred to as a current sensing circuit. Depending on the embodiment, different topologies may be retained for the current sensing circuit, examples of which will now be presented. The Figs 4A and 4B feature an instrumentation amplifier 42, while the Figs 4C and 4D use a transimpedance amplifier 44. Both topologies are shown witha single-ended ADC configuration (Fig. 4A and 4C) and with a differential ADC configuration (Fig. 4B and 4D) to illustrate some possible variants.

[0044] In some embodiments, the topology shown in Fig. 4D, featuring a transimpedance amplifier 44 (TIA), may be selected because some TIAs 44 may offer better frequency response than some instrumentation amplifiers 42. The output of the pulse generator can be connected directly to the non-inverting input of the TIA 44. In some embodiments, connecting the pulse generator output to the non-inverting input of the TIA 44, as opposed to connecting the pulse generator's output directly to the I / O port of an SMU (e.g., SMU 116a), can lead to a greater measurement speed.

[0045] It will be noted that the source measure units presented above in relation to Figs. 2 to 4D may be integrated to channels 16a, 16b of Fig. 1 , such as part of the testing module 14. For instance, source measure units can be used as variable voltage sources of the testing module 14. Alternately, the testing system 10 of Fig. 1 may be used with different types of source measure units, such as non-pulsed source measure units, or altogether with a different type of testing module 14 which does not use source measure units.

[0046] In the specific example presented in Fig. 2, a serial communication is used for the DATA between the controller 122 and the SMlls 116a, 116b, and a parallel communication for the CONTROL SIGNAL, as shown.

[0047] Such an architecture may facilitate the integration of many measurement channels in a small footprint by using a serial-to-parallel communication flow and a buffer for data storage. The communication flow can include three components. First, a serial computing unit can transmit all the information serially to the second component. The second component can be a serial-to-parallel computing unit, which could be an FPGA or application-specific integrated circuit (ASIC), responsible for converting the serial data into parallel format and storing it in a buffer. This buffer can hold all voltage and measurement commands along with their timestamps. Once the buffer is fully populated with the serial data provided by the serial computing unit, it may be emptied based on specific timestamps, ensuring complete synchronization across all measurement channels.

[0048] It will be noted however that this is optional, and testing systems can be embodied with configurations other than serial to parallel in alternate embodiments.

[0049] Fig. 5 presents another example of a testing system 210. The testing system 210 can be controlled by a controller 222 to apply a voltage difference between V1 and V2, to perform testing of electrical nature on the device under test. V1 and V2 are voltage sources, and can be of various forms, such as a DAC output, a fixed voltage reference, an output of a source measure unit, etc. A current limitation unit 250 is connected in series between the DUT 212 and V2.

[0050] The current limitation unit 250 can be a tunable hardware design involving two MOSFET transistors 252a, 252b (either common-source or common-drain) connected in series, with their gates attached to one another and to a control voltage source 254. This configuration allows the current limitation at the "sinking end" of the DUT. By "sinking end," we mean the point where the current exits the DUT 212 towards a lower potential, such as ground. By adjusting the voltage applied to the transistor gates, it is possible to control the current limit precisely. One convenient example topology, shown in Fig. 5, consists of two NMOS transistors connected in series with a common source. NMOS transistors may be preferred over PMOS due to their lower cost and higher availability, for instance. It will be noted however that PMOS may remain preferred in some embodiments, and other transistors than NMOS, PMOS, or MOSFET may be used in alternate embodiments.

[0051] In Fig. 5, five main components are depicted: the DUT 212, the current limitation circuit 250, and three voltage sources (V1 , V2, and VG254). These voltage sources can take various forms, such as a voltage generator, DAC, or reference voltage, to apply either an AC or DC signal to the DUT 212. In the embodiment shown, V1 is at a higher value of electrical potential amplitude than V2 and acts as a voltage generator that sends a signal to one terminal of the DUT 212, while V2 applies a voltage to another terminal, creating a voltage drop across the DUT 212 and acting as the sinking source that receives the current leaving the DUT 212.

[0052] Interestingly, in this configuration, the current limitation unit 250 can be controlled by the controller 222 in different ways. In one mode of operation, which will be referred to herein as the current limitation mode, the controller 222 can apply a precise voltage to the transistorgate (VG) to set a specific current limit that the circuit will allow. In another mode of operation, which will be referred to herein as the switch mode, the controller 222 can alternately control the voltage at the transistor gate (VG) in a manner to operate the current limiting unit as an open switch or a closed switch. In the current limiting mode, the voltage V2 may be constant while the voltage V1 is varied, for instance.

[0053] More specifically, when the controller 222 sets the voltage at the transistor gates to be as close as possible to V2, essentially opening the switch and preventing current independently of the difference of potential between V1 and V2. Alternately, when the controller 222 sets the voltage at the transistor gates to the maximum possible value, it minimizes the transistor's resistance allowing current circulation without limit. This enables current to flow with minimal interference, achieving a resistance as close as possible to the transistor's lowest drain-source "on-state" resistance (RDSoN

[0054] In some embodiments, a voltage that falls between these two states — neither fully ON nor fully OFF, may be used. This can lead to controlling the system within a continuous range of current limitations, as opposed to a discrete on / off setting. The following discussion will aim to clarify what is meant by using a voltage that falls between these two states, and which allows to operate the current limitation unit in current limitation mode instead of in the open or closed switch modes.

[0055] The following explanations are intended to shed more light on these different modes of operation.

[0056] RDScan be characterized as the resistance between the drain and the source of a MOSFET when a given voltage VGSis applied between the gate and the source of the transistor. As the gate voltage nears the maximum value specified for a transistor, RDSreaches a value RDSON) corresponding to operating the transistor in a closed switch, ON, mode. RDS(ON) may be within 115%, 105% or even 101 % of a minimum resistance value exhibited by the transistor. RDSON) isaparameter of transistors and different transistors may have different values of this parameter.

[0057] Similarly, as exemplified in Fig. 6, in a testing system such as testing system 210, RI0, can be used instead of RDS, and RI0can be defined as the resistance between the input and output of the current limitation circuit 250 when a gate-to-output (VG0- which corresponds to the difference of potential between VGand V2 in Fig. 5) is applied. When VG0reaches a value which will be referred to as VG0(0W) on the transistor gates, RI0reaches RIO(ON) ’ which may be within 115%, 105% or even 101 % of a minimum resistance value achievable with the current limitation circuit for a given set of transistors. Applying this difference of potential, or a higher difference of potential, via the control of the potential VGat the gates corresponds to operating the current limitation circuit 250 in a closed switch mode of operation.

[0058] Conversely, when the goal is to open the switch and prevent any current flow through the Device Under Test (DUT), the gate voltage can be set to be operationally the same as the voltage of the source (VG0~ 0 = VG0(0FF), which corresponds to operating the current limitation unit in an open switch mode of operation leading to high value of resistance R|O(off).

[0059] Applying a potential VGwhich leads to an intermediary value of VGo falling between these two states — neither fully ON nor fully OFF, allows to impart a current limitation which can allow free circulation of current levels below the current limitation value, while capping current circulation at the current limitation value. The current limitation value may be controlled to a specific value within a continuous range of current limitations.

[0060] In many embodiments, this intermediary value of VG0may be set to be within the range of 0.005 VGO(ON)0.7 ^GO(ON) > although in some embodiments, the intermediary value of VG0may rather be within the range of between 0.001 and 0.5 ofand in some other embodiments, the intermediary value of VG0may rather be within the range of between 0.01 and 0.4 of yG0(0N).

[0061] Referring to Fig. 5, since the current-limiting circuit 250 is directly in line with the DUT 212, its resistance can respond instantly to limit the current to the specified value. This can lead to a more reactive and faster protection mechanism compared to alternatives like software feedback loops. This rapid response can help protect sensitive devices during measurements and tests.

[0062] In some embodiments, V1 and V2 of Fig. 5 can be embodied as variable or fixed voltage sources in an embodiment such as shown in Fig. 1 , and current limitation unit 250 can be embodied as one or more current limitation units 20a, 20b, to name another example.

[0063] Several types of DllTs, such as diodes, memristors, and NMOS transistors, could benefit from a testing system integrating such a current limitation unit 250, such as schematized in Figs. 7A to 7C.

[0064] For example, consider a diode characterization. In a diode testing process, the voltage can be swept across the diode while measuring the current. During the initial characterization, it is difficult to predict the voltage level at which the current might rise to a damaging value. However, with the current-limiting circuit, the maximum allowable current can be specified, ensuring the diode is not damaged while still allowing accurate measurements.

[0065] Fig. 7D shows an example embodiment of characterization of a diode using two source measure units (SMlls). The bottom figure illustrates the voltage waveform generated by SMLI1 (e.g., SMU 116a) while SMLI2 (e.g., SMU 116b) is kept at 0V. SMLI1 is generating a train of pulses with increasing voltages to obtain points of measurements of the current passing through the diode for different voltage values. By pulsing with a 50% duty cycle, it is possible to reduce the heat dissipated by the diode by a factor of two compared to a DC voltage sweep (shown with a dotted line). The shorter the pulse, the smaller the heat dissipation and the less the heat will affect the characteristics of the diode, hence why fast measurements with a pulsed SMU can be of increasing value. Example current measurement points are illustrated in the upper graph and present a scenario where the current through the diode is not limited.

[0066] This will be further exemplified with reference to Fig. 8 which schematically represents testing operations based on the configuration of Fig. 5, where the DUT 212 is specifically a diode, such as in Fig. 7A. Referring to Fig. 8, the current limitation circuit can operate in three different regimes due to the transistors’ internal behavior: 1) the ON, or closed switch mode, 2) the OFF, or open switch mode, and 3) an intermediary current limiting mode. Fig. 8 presents three relationships between IDUT and VDUT, including, respectively, 1) a relationship when VGO> O'? ;o(cw)> corresponding to the ON mode, 2) a relationship when VG0< 0.005 VGO(ON) . corresponding to the OFF mode, and 3) a relationship when 0.005 VGO(ON)VG0< 0.7 VGO(ON), corresponding to the current limiting mode. Specifications for the diode may specify a maximum current, above which the diode may become damaged. In the relationship 1), the current IDUT may be allowed to exceed this maximum current specification if VDUT exceeds a given value, whereas in the relationship 2), current may be essentially prevented from circulating through the diode in a manner which is not compatible with the testing to be performed. In the relationship 3) current may be allowed to circulate to a certain extent as VDUT increases, while being capped at a given value which may be set to be at, below, or well below the max specified current value. When the current through the DUT 212 is below the current limit, the circuit operates in the linear region, allowing current to flow freely through the device. As the voltage from V1 increases, the current through the DUT 212 also increases, nearing the current limit of the protection circuit. At this point, the transistors transition from the linear region to the saturation region, limiting the current flowing through the DUT 212. As V1 continues to rise, the current remains constant due to the saturation characteristics of the transistors, defined by the equation:

[0067] VI0> (VGS- yT)

[0068] Where VIOis the voltage difference between the input and output voltage of the currentlimiting circuit (V, - 70), VGSis the voltage difference between the gate voltage VGand the source voltage Vsand VTis the threshold voltage of the MOSFETs used.

[0069] The current-limiting circuit, with a precisely applied gate voltage, can thus function as a tunable series resistance added to the DUT 212, sharing the voltage drop across it. Initially, when the current through the DUT 212 is low, the entire voltage drop occurs across the DUT 212. As the current increases, the equivalent resistance of the limitation circuit increases, sharing the voltage drop between the DUT 212 and the current limitation unit 250. Configuring the current limit is achieved by tuning the voltage at the transistor gate, as defined by:

[0071] Where IDis the current through the DUT 212, L is the transistor channel length, p the carrier mobility, C is the gate capacitance per unit area, W is the transistor width, VTis thethreshold voltage and Vois the voltage of the sinking source (V2). This voltage can be calibrated on the chosen transistor for the circuit to provide more accurate current limitations.

[0072] In the current limiting mode, the gate voltage may be controlled to a fixed value set lower than the voltage typically applied to the gate of the transistors in the closed switch (ON) mode. More specifically, the gate voltage may be set to 0 < VG0< 2 VT. In other embodiments, it may be preferred to set the gate voltage of the current limiting mode to between 0 and 3 VT, or to between 0.05 and 1.5 VT.

[0073] Referring to Fig. 5, the current limitation unit 250 has a first transistor 252a, and a second transistor 252b connected in series between the DUT 212 and the second voltage source V2. The first transistor 252a and the second transistor 252b are in a common source configuration. A first example of a common source configuration is schematized in Fig. 5, whereas other examples are presented in Fig. 8A, Fig. 8B, and Fig. 8C, in which case the equation governing the current limit may change in a manner which can be accounted for by the control scheme applied by the controller 222. Returning to Fig. 5, and with reference to a first mode of operation of the current limitation unit 250, the controller 222 can further control the voltage at the gates of the first transistor 252a and second transistor 252b in a manner to limit the current which is allowed to pass through the DUT 212. It is also noted that while in Fig. 5 the current limitation unit 250 is presented as forming part of the testing system 210, it may alternately be provided as a distinct unit from the testing system 210 in alternate embodiments.

[0074] A current limitation unit 250 such as described above in relation with Figs. 5 to 8C can alternately be used in association with a testing system 10 such as the one shown in Fig. 1 , a testing system 110 such as the one shown in Fig. 2, or with a different type of testing system such as a testing system having with different types of source measure units, such as nonpulsed source measure units, or with a testing system which does not use source measure units to perform testing.

[0075] Referring to Fig. 1 , in one example embodiment, the testing system 10 can have one or more channels 16a, 16b, each having variable voltage source (such as a source measure unit or another variable voltage source) connected to a device under test 12 via, in series, acurrent limitation unit 20a, 20b. The testing system 10 can also have one or more fixed voltage source connected to the device under test 12 via, in series, a current limitation unit. In some embodiments, the current limitation units 20a, 20b may be as schematized in Fig. 5 or as schematized in Figs. 8A to 8C, for instance. Some example modes of operation of such a testing system 10 which make use of the current limitation functionality of the current limitation units 250 will now be provided.

[0076] In a first example, a first variable voltage source connects, in series, a first current limitation unit 20a, the DUT 12, another current limitation unit 20c, and the fixed voltage source. Testing of the DUT 12 can be performed in a manner which involves varying the electrical potential of the first variable voltage source while maintaining the electrical potential of the fixed voltage source at a constant value, below or equal to the electrical potential of the first variable voltage source. This may have the effect of varying VDUT over time in a way which may cause variations in IDUT over time. The variations of IDUT over time may represent a risk of exceeding the maximum specified current for the DUT 12. During the testing process, the first current limitation unit 20a may be operated in a closed switch mode, such as by applying an electrical potential at the transistor gates which cause VGO <ON), allowing free circulation of current across the DUT. On the other hand, the other current limitation unit 20c may be operated in a current limiting mode, such as by applying an electrical potential causing an intermediary voltage VGO between 0.005 and 0.7 GO <ON) which, in turn, causes the other current limitation unit 20c to apply a current limitation across the DUT 12 which allows safe levels of current to circulate thereacross during testing. The process may terminate at that stage, or, if another one of the voltages sources, which we will label second voltage source, is also connected to the fixed voltage source across the DUT, the first current limitation unit 20a may be toggled to open switch mode, the second current limitation unit may be toggled to closed switch mode, and testing may proceed via variation in electrical potential of the second voltage source while maintaining the fixed voltage source at a constant value, below the electrical potential of the second voltage source.

[0077] In another example, two of the channels may be connected in series across the DUT 212. Let us take an example where a first channel 16a, which will be referred to as channel 1 , is connected in series with a second channel 16b, which will be referred to aschannel 2, across the DUT 212, and where both channels 1 and 2 have variable voltage sources connected in series to the DUT 212 via a corresponding current limitation unit 20a, 20b. In one mode of operation, the first current limitation unit 20a may be toggled to a closed switch mode, the second current limitation unit 20b may be operated in current limitation mode, and the second variable voltage source may be operated in fixed voltage mode, at an electrical potential which remains below the variable electrical potential of the first voltage source as a first testing procedure is performed via the control of the electrical potential of the first voltage source. Then, a second testing procedure may be performed. In the second testing procedure, the second current limitation unit 20b may be toggled to a closed switch mode, the first current limitation unit 20a may be operated in current limitation mode, and the first variable voltage source may be operated in fixed voltage mode, at an electrical potential which remains below the variable electrical potential of the second voltage source. The second testing procedure can then be performed via the control of the electrical potential of the second voltage source.

[0078] In addition to examples presented above, various other forms of device under test (DUT) 12 may be tested using testing systems such as described above. Fig. 9 illustrates an example application involving an Application Specific Integrated Circuit (ASIC) with specific needs that require multiple analog signals. These signals can be provided by various Source measure Units (SMUs), which supply the necessary voltage while measuring the generated current at high speeds. The required signals may include power or specific waveform patterns, such as DC and pulsed signals. Example pulse source measure units presented above may be capable of both DC and pulsed measurements, offers significant flexibility for different circuits. Given that some ASICs have numerous connections, using a compact testing system with minimal control signal requirements becomes a significant driver when choosing a testing system.

[0079] We will now proceed to provide a more detailed description of an example embodiment of a testing system with reference to Figs 10 and 11 . In this example embodiment, the testing system has an FPGA-controlled high-speed, parallel current voltage measuring platform optimized for the characterization of in-memory computing architecture and memristive neuromorphic circuits. The system incorporates 32 fully asynchronous analog channels, which enables the generation of custom waveforms in the range ±5 V with timing resolutions of 6.25ns. It also includes 32 high-speed digital channels, which facilitate the interfacing of devices with up to 64 pins with both analog and digital signals, within a compact, portable size. Test results demonstrate the ability of the system to generate high-speed voltage pulses as short as 25 ns, with voltage accuracy of up to 0.05%. Moreover, the system can achieve accurate current measurements of 0.5% with reading cycles of as little as 325 ns. The FPGA can gather up to 17.92 Gbps of current measurements, while the system’s measuring channels allow for up to 1.53 GFLOPS on 16x16 crossbar arrays of resistors. These characteristics arise from its current sensing circuit design, which allows for both accurate and high-speed measurements. The capabilities of the proposed system in terms of parallelism, speed and precision make it suitable for a multitude of applications such as machine learning, sensor matrices and quantum dot interfacing.

[0080] The field of information and communication technologies is currently undergoing a profound transformation, characterized by the emergence of innovative computing solutions that go beyond conventional approaches based on the von Neumann CMOS architecture. Unlike traditional CPU-based innovations, which focus primarily on algorithmic advancements, this transformation involves a synergy between hardware and software innovations, necessitating co-design methodologies between the two. This novel methodology places application-specific hardware at the forefront of research on the development of new circuits and systems. To develop and iterate on these hardware designs, a profound understanding of their behavior and underlying physical mechanism is required. For emerging types of memory for which accurate models do not yet exist, an understanding of the material parameters of the fabricated devices requires in-depth electrical characterizations, where hardware-in-the-loop simulations are preferred over standard simulations using complex models. Since integrated circuits and nanodevices are often integrated with CMOS technologies, there is a growing demand for new hardware-specific characterization instruments that are capable of handling both analog and digital signals.

[0081] One of the most promising approaches to overcoming the memory wall arising from von Neumann’s architecture is the in-memory computing (IMC) paradigm, which is particularly suited to artificial intelligence applications in the form of neuromorphic circuits and memristive artificial neural networks. These IMC architectures leverage the analog behavior of emergingresistive memory devices (also called memristors), which can be implemented in multiple ways and in different topologies, such as passive and one-transistor-one-resistor (1T1 R) crossbar arrays. In the absence of integrated CMOS-based control electronics, driving a memristive crossbar requires external custom instrumentation electronics that can perform parallel voltage-current measurements simultaneously, with both digital and analog signals. These instrumentation systems are used to provide and measure electrical signals to and from the crossbar arrays, with the help of fast programming pulses. As crossbar arrays tend to have a high number of inputs and outputs, one strategy to address this is to multiplex a small number of these pulsed signals to the connections of the devices, using devices that integrate switching matrices. Such systems may lack the capability to generate expansive parallel voltage vectors and require the interconnection of multiple instruments in parallel to read parallel vectors of currents. To achieve full parallelism without losing accuracy and speed, new system architectures may need to be considered. Such a system would represent progress towards highly parallel innovative circuits, such as sensor matrices and quantum dot interfacing, while opening novel avenues for the exploration of neuromorphic circuits.

[0082] The following description presents a design for a characterization system that can achieve highly parallel and fast l-V measurements without compromising speed or accuracy. The design is based on a highly flexible FPGA-controlled printed circuit board (PCB), which can generate a mix of 32 digital and 32 analog signals for interfacing with crossbar arrays and various other mixed-signal integrated circuits. This system was designed to have fully parallel capabilities as well as independent channels. The channels were designed to achieve competitive accuracy and speeds when compared to commercial equipment, but with a higher number of measurement channels at a lower cost.

[0083] Fig. 10 presents a high-level block diagram of the five main components of an example system: the device under test (DUT) interface (shown in yellow), four variable power supplies (blue), eight groups of four arbitrary pulse measurement units (APMlls) (orange), four banks of eight general purpose input / output (GPIOs) (blue) and the Zynq™ system-on-module (SOM) computing unit (red).

[0084] The system presented in Fig. 10 is centered around a high fanout device under test (DUT) interface, which allows for the connection of an 84-pin LCC chip carrier or a custommezzanine PCB. Through these interfaces, connections can be established between a selected chip and the main components of the system, including the measurement channels and the other subsystems. The measurement channels include 32 fully asynchronous and parallel arbitrary pulse measurement units (APMlls), organized into eight groups of four, as illustrated in Fig. 110. Each APMLI can be accessed independently, enabling each channel to generate arbitrary voltage pulses without depending on the timing of any other channel. To provide more flexibility in terms of the types of devices that can be interfaced with the system, other subsystems have been added to the design, including 32 general purpose inputs / outputs (GPIOs) and four variable voltage sources, which are accessible through the DUT interface. Furthermore, a bidirectional current compliance circuit has been integrated in series with each APMLI channel. Finally, an external sensor interface and a link for connecting multiple measurement platforms together are included in the system. In this embodiment, the APMlls and subsystems are controlled by a Python user interface.

[0085] In this embodiment, the testing system includes three components, as shown in Fig. 11 : the electronics system that generates and measures different signals; the user interface, which allows commands to be sent to the measurement platform; and the computing unit, which is responsible for interfacing between the two. The computing unit chosen for this system was based on a Zynq™ 7000 system on chip (SoC), featuring a dual-core ARM Cortex- A9 processing system (PS) mated with 28 nm ArtixTM 7 based programmable logic (PL) on the same chip, thereby offering a unique combination of processing power and programmability. This chip was integrated on a custom system-on-module (SOM). A fully integrated SoC allows the system to accelerate specific tasks with the PL without losing flexibility in terms of software, as the PS CPU runs an on-board Linux kernel.

[0086] Fig. 11 presents a mid-level block diagram illustrating the three main modules of the measurement platform: the user interface (on the left), the computing unit (in the middle), composed of a processing system (PS) and a programmable logic (PL), and the PCB system (on the right). The figure shows the different interactions between the system components as well as the communication speeds between them. There are three possible feedback loops within the system where data processing can be done and a signal response can be initiated: (1) the standard PC PCB, (2) PS PCB and (3) PL PCB.

[0087] The PS is responsible for processing the flow of instructions coming from the user’s PC, whereas the PL is responsible for controlling the PCB electronics at a high speed, in parallel. The electronic system has measurement channels, the APMlls, which use voltage and timing commands in order to generate and measure the desired signals. The computing unit receives these voltage and timing instructions from the user interface PC and then transfers them directly through an advanced extensible interface (AXI) to the control blocks in the PL, the digital-to-analog DAC Manager and the Pulse Manager. These are responsible for managing the voltage levels and timings of each output signal waveform coming out of the APMUs. When a test is executed by the user interface, the DAC Manager sends the requested commands to each DAC IC in parallel with a custom Quad-SPI protocol, which is used to control the output voltages of each channel. This protocol allows the measurement platform to change the output voltage of eight APMUs every 600 ns. While the DAC Manager controls the output voltages, the Pulse Manager controls the duration of the segments used to generate the pulses and arbitrary waveforms with the right timings, by toggling the APMU’s pulse generator. The requested measurements are transferred in parallel from each APMU’s analog- to-digital converter (ADC) to the PL via 32 serial low-voltage differential signaling (LVDS) pairs operating at up to 560 MHz. This operation speed allows for the capture of one current measurement every 25 ns, resulting in a simultaneous 17.92 Gbps data transfer from the APMUs to the PL. While the test is being executed, these data are transferred progressively to the Zynq™ CPU at a rate of up to 3.2 Gbps, making them accessible in real time for further signal processing operations. To reduce the quantity of data that needs to be transferred to the PS, these measurements can be averaged down directly in the PL or stored in a first-in first-out (FIFO) stack, waiting to be transferred. As the number of logic gates are limited in the programmable logic, the FIFO storing capacity is limited to 8,192 samples per channel. To generate fast voltage pulses and make current measurements at a high frequency, the SOM acts as the controller of all the APMUs’ measurement channels.

[0088] One significant function of the proposed system is its ability to generate 32 arbitrary pulsed voltage signals simultaneously, in parallel, while measuring the output or input current of each channel. To do this, a novel APMU circuit was designed, as shown in Fig. 12.

[0089] Fig. 12A presents a high-level architecture of a source measure unit embodied more specifically as a pulse measurement unit (APMLI), featuring a pulse generator with an analog switch, a current sensing circuit with transimpedance amplifier (TIA), current compliance block, and analog / digital converters. Fig. 12B presents a general measurement system, which uses two or more APMlls to generate two biasing voltages (V1 and V2) to measure a current that passes through the device under test.

[0090] In this embodiment, each APMLI is made up of two main parts, the pulse generator (PG) and the current sensor (CS). The high number of channels that were implemented meant that careful optimization of space and power was necessary at the hardware design stage. As pulse measurements are the predominant method for programming emerging memory devices, the implementation of a high-speed PG was favored over a high-speed digital to analog converter (DAC), as it is more effective in terms of power and cost. The precision and flexibility of a multi-channel DAC is thus combined with the high-frequency capability of a PG. The DAC utilized in the design has eight 16-bit outputs that can be reprogrammed every 600 ns, with a slew rate of 1.8 V / ps. Providing two DAC outputs to each APMLI (e.g., V1 and V2) allows the pulse generator to use them as precise voltage references for the bottom and top voltages of the pulses it generates. With the help of a high-frequency analog switch, it creates the voltage pulse by alternating between those two inputs. After undergoing filtering and scaling to achieve the proper output voltage of ±5 V, the final voltage resolution of the APMLI is as low as 152.6 pV. In terms of timing resolution, since the PG control is coming directly from the PL, it has a timing resolution of as low as 6.25 ns per segment. The rising and falling times of the PG limit the minimum pulse width to 20 ns for 1 V pulses. Notably, the proposed offers the direct integration of the pulse generator with a high-speed CS circuit, thereby unlocking the possibility of generating rapid voltage pulses while taking measurements simultaneously. This eliminates the necessity of multiplexing the voltage generator and current sensing circuit when changing from writing to reading operations.

[0091] By combining the sensing circuit with the pulse generator, as shown in Fig. 12a and 12b, the CS of each APMLI can benefit from the speed of the PG in sensing the positive or negative current drawn or sourced by its output with high-speed pulse measurements. This is due to the CS architecture, which is composed of a high-speed transimpedance amplifier(TIA), a fully differential operational amplifier, and an ADC. The coupling between the voltage generation and current sensing is achieved by connecting the output of the pulse generator to the positive input (IN+) of a high-speed 210 MHz TIA. By replicating the pulse generator signal (IN+) to the output of the APMLI (IN-), the TIA must source or sink a current from its output. This current has to travel across a gain resistor, thus generating a voltage that is proportional to the APMLI output current following Ohm’s law. This value is extracted by measuring the voltage difference across the gain resistor with a fully differential ADC, with the help of a differential amplifier. The 14-bit fully differential ADC selected in this case is configured to sample the voltage at a speed of 40 MHz, resulting in a measurement sample every 25 ns. Keeping a differential signal from the TIA all the way to the ADC helps to reduce the impact of noise on the measurements, as the common voltage noise is cancelled out when the two differential signals are subtracted together. To ensure a good reading resolution for current measurements of different orders of magnitude (1 mA to a few nA), a variable gain TIA topology was adopted. This design required the use of multiple gain.TABLE I - APMU CURRENT RANGES WITH RESPECTIVE RESISTANCE GAIN ANDMAXIMUM CURRENT RESOLUTION

[0092] Emerging devices commonly benefit from current limitation, as excessive current flowing through them could lead to damage or degradation. For instance, resistive memories generally require control over the maximum current flowing through them during the forming and writing steps. There may be a challenge in devising a current limitation unit which is compatible with direct integration with the measurement channels, meaning that switches are needed to multiplex the circuit output sequentially to the connections of the devices under test.As the system proposed here was designed to run in parallel, a novel approach was used in which high-speed NMOS transistors were connected in series with each APMU channel, allowing for bidirectional current limitations of up to 14 mA with a minimum resolution of 3.5 pA. This scheme has a fast reaction time of below 30 ps before protection takes effect, namely 16 ns.

[0093] Overall, the system can provide fully parallel, high-speed voltage signals with simultaneous precise current measurements. To assess its performance, several metrics were benchmarked.

[0094] First, the minimum pulse width that can be generated by the system’s APMU defines its suitability for performing high-speed writing operations with pulse measurements. To benchmark this performance, a high-speed 1 GSPS oscilloscope was used to probe the signal output of an APMU as it generated pulses of different shapes. The output of the tested APMU was loaded with a 1 MQ resistor and a 15 pF parasitic capacitance. By generating multiple pulses with varying voltages and duration and concatenating them together to fit in the same image, the waveforms presented in Fig. 13 were obtained.

[0095] The different time metrics used for this evaluation are shown in Fig. 14 and summarized in Table II.TABLE II - MINIMUM ACHIEVABLE TIMING FOR PULSES ANDWAVEFORM GENERATION

[0096] The minimum achievable pulse widths are limited by the APMll’s minimum rising (T_Rise) and falling times (T_Fall), resulting in a minimum pulse width (T_Pulse) of 20 ns for a voltage amplitude of 1 V. As the voltage amplitude of the pulse increases, T_Rise increases, leading to a minimum pulse width of 300 ns for the 5 V pulse. This is due to the use of the TIA to provide a fast-rising edge voltage, which becomes more difficult as the voltage rises. Nevertheless, the achievable pulse speed for this instrument may be suitably fast, with recommended pulse lengths of 170 ns and 60 ns, respectively. To evaluate the signal integrity of the pulses, it is important to evaluate the voltage overshoot and undershoot at the rising and falling edges of the pulse: if the overshoot is too high, this parasitic effect can lead to inconsistent behaviors or even damage to the device under test as the voltage goes above or below the expected value. As can be seen from Fig. 13, the overshoot and undershoot are less than 8% of the generated pulse, which may be suitable. Fig. 13 also demonstrates the ability of the system to generate ±1 V pulses down to 20 ns.

[0097] As the pulse generators are controlled by the FPGA, which operates at 160 MHz, the minimum timing resolution of the pulses is 6.25 ns. To generate two successive pulses of different voltages, the DACs must be programmed to change the pulse generator references, thus leading to a delay T_DAC of 600 ns for each successive change plus a slew rate of 1.8 V / ps. By changing the DAC output, it is possible to generate any arbitrary waveform with a minimum timing resolution of 600 ns, plus the slew rate. To test the arbitrary waveform generation capabilities of the APMlls, five sinusoidal and sweep voltage waveforms were measured, using the same methodology as for the pulse generation test. Fig. 15 shows that the measured voltage waveforms are well in agreement with the required shapes. These waveforms were generated with voltage segments of 2.5 ps, but these could have been reduced to a minimum of 627 ns per segment, as allowed by the slew rate for voltage steps of 5 mV. When the pulse generation and arbitrary signal generation speeds had been assessed, the voltage precision of these functionalities was evaluated.

[0098] The accuracy of the output voltage is determined by the amplitude of the error between the requested output voltage and the measure output voltage at the APMll. To extract this metric, a mezzanine PCB was designed with eight ADC input channels of 16 bits, resulting in an input resolution of 152.6 pV. By sweeping each APMll output from 0 to 5 V and connectingit to the mezzanine ADCs through the DUT interface, the output voltage was measured and averaged across all eight APMlls. The error between the expected voltage at the output of the APMlls and the measured voltage by the ADCs is shown in Fig. 16.

[0099] The offset for the APMU voltage output error is shown to be less than 500 pV for the range 0-2 V, and is below ±0.05 % over the whole voltage range of 0-5 V. This metric is mostly important when it comes to making current measurements with the system, as an error in the output voltage would translate directly to an error in the measured current.

[0100] As the system was designed to make current measurements, it can aim to achieve a high level of accuracy in order to give relevant and analyzable data. For this reason, the reading accuracy of each APMU channels was quantified. As electronic components have a certain variability, which is inherent to the manufacturing process, each APMU channel was calibrated with a custom calibration PCB. A total of 16 resistors ranging from 100 Q to 10 MQ, with an accuracy of 0.1 %, were measured using 16 different APMU channels. Each resistance was measured with a voltage pulse ranging from 0.1-0.5 V, with an average of 400 samples. An appropriate current range was selected for each data point based on the resistance value under measurement.

[0101] The error in the resistance measurement and the current range used for each resistor are shown in Fig. 17. More specifically, Fig. 17 presents APMU current measurement accuracy for resistances between 100 Q and 10 MQ. These measurements were made with two APMUs with reading pulse voltages of 0.1 V and 0.5 V. All five current ranges were used for different resistance values, as indicated in the figure.

[0102] The channels achieve a minimum overall accuracy of ±0.5 % between the range 200 Q to 5 MQ. Closer to the limit in terms of lower and higher output impedances, the system loses accuracy, as the parasitic line resistance of the PCB and its current leakage affect the measurements. The highest resistance measured with the system was 100 MQ, which resulted in a 1.82% reading error using a 5 V reading pulse. With a lower voltage reading pulse of 0.5 V, resistances of up to 51.2 MQ could be read with an error of 5%. Since the goal of this test was only to assess the maximum achievable accuracy with the system, a longerpulse duration of 10 ps with data averaging was used, as the system was designed to achieve accurate measurements at higher speeds.

[0103] The reading speed of a system is limited by the time it takes for the current measurement to settle to its final value. To verify that the system could achieve accurate current measurements at high speeds, the minimum settling time of the APMLI was characterized. To do this, the measurement error was assessed with multiple reading pulses of varying duration. As the measurement settling time is different for each current range, this test was repeated for each current range, with resistances of 500 Q, 5 kQ, 50 kQ, 500 kQ and 5 MQ. Each reading pulse was sampled during the last 25% duration of the pulse with a 25 ns current samples rate.

[0104] In Fig. 18, all five current ranges were tested to find the minimum pulse needed to achieve the desired accuracy. The results in Fig. 18 show that it is possible to achieve reading cycle timings of as low as 325 ns for the 1 mA current range, when aiming for an accuracy of ±1 %. Slower reading speeds limit the capabilities of an instrument in terms of possible applications, as it is not possible to capture fast switching events, and also prevent intensive data gathering such as cycle-to-cycle endurance, as billions of reading cycles would require multiple days of tests. This speed is possible because the settling time for the 1 mA range is 294 ns, and we can sample the current every 25 ns. As we change the current range to read lower currents, we increase the gain resistance of the TIA, which reduces its gain bandwidth and leads to an increase in the measurement settling time. The minimum reading pulse and settling time for each current range are presented in Table II, where the settling time is defined as the time it takes for the measurement to settle to within ±1% of its final value.

[0105] The more sensitive ranges of the instrument are shown to reach suitably fast; for example, the 1 pA range requires a minimum reading pulse of 25 ps. As measurements based on only one or a few samples can lead to variability in the values, it is generally recommended to take readings based on averaged data points. Evaluating the variability in the measurements by generating the noise figures provides valuable information on how many averaged samples are necessary to reduce this variability.

[0106] Noise is always present in any electronic system and may arise from internal components or external sources such as nearby electrical cables, motors or RF equipment. This noise can impact measurements by adding unpredictable offsets between data samples. As the impact of noise can be greatly reduced by taking an average of multiple samples, applications requiring individual sampling are more affected. It is important to quantify the baseline noise of the system to determine its achievable precision. Hence, 8,000 nonaveraged measurements of 0.1% tolerance resistors ranging from 1 kQ to 10 MQ were made for each current range. These measurements were obtained using 200 ps reading pulses of 0.5 V.TABGESTABLE IV - RESULTS OF MEASUREMENT VARIABILITY TEST FOR FIVE CURRENTRANGES WITH STANDARD DEVIATION AND VARIANCE

[0107] The resulting histogram for the 1 mA current range is presented in Fig. 19. In this graph, the noise results are plotted for the current measurement error based on 8,000 nonaveraged samples for the 1 mA current range, measured on a 1 kQ resistor. The other current ranges were also tested, and the results are presented in Table IV. The measurement variability for the 1 mA range is characterized by a variance of 0.05%, which translates to a noise of 0.45 mV at the input of the ADC. The lower current ranges show higher variability, ranging from 0.16% for the 100 pA range to 2.05% for the 100 nA range, which corresponds to a minimum variability of 2.05 nA. This increase in noise amplitude can be explained by the fact that thermal noise is proportional to both the gain resistance of the TIA and its temperature, following Eq. (1). Thus, the smaller the current range (higher gain), the higher the relative noise will be, as the TIA gain increases by a factor of 10 for each range.

[0108] This system enables the testing of devices in different configurations. Some examples of which will now be presented.

[0109] Memory devices: As the system can read resistance values from 200 Q to 5 MQ with high precision (< 0.5% error), it is suitable for use with different memory technologies such as RRAM and phase-change memory (PCM), which typically range between 1 kQ and 1 MQ, as well as magnetoresistive random-access memory (MRAM), which typically does not exceed a few tens of MQ. For higher resistive memories such as ferroelectric random-access memory (FeRAM), which can reach up to 1 GQ, some improvements would need to be considered, such as adding preamplifiers to the mezzanine daughterboard to amplify the measured current.

[0110] Integrated technologies: With its 32 APMlls, the system can interface integrated devices such as crossbar arrays, with or without transistors, with a maximum size of up to 16x16 with completely independent channels. Its ability to perform asynchronous operations unlocks more exotic applications such as neuromorphic circuits with the generation of uncorrelated spike pulses. The flexibility of the APMLI and its arbitrary signal generation capability mean that it is possible to generate any shape of signal on any of the 32 channels, which could help in exploring different kinds of memory encoding mechanisms.

[0111] Furthermore, the architecture of the system was designed to be as efficient as possible in transferring information between a sequential computing unit (CPU) and a fully parallel circuit (crossbar). This hybrid approach using a CPU / FPGA could be reused as a building block for other circuits and systems that require distributed computing, such as loT.

[0112] In summary, we have shown the system can offer the capabilities of generating short writing and reading pulses of as little as 20 ns and 325 ns, respectively, while reaching current measurement accuracies of < 0.5% for all 32 channels. This FPGA-based system is a remarkable tool for interfacing CMOS ASIC chips with digital signals, while the analog portion of the instrument offers the capability to handle applications requiring mixed signals (analog and digital). Moreover, the flexible mezzanine DUT interface of the system could be used in a multitude of applications through the implementation of custom circuits on a mezzanine PCB to fit their specific needs.

[0113] Referring to Fig. 20, it will be understood that the expression “computer” 400 as used herein is not to be interpreted in a limiting manner. It is rather used in a broad sense to generally refer to the combination of some form of one or more processing units 412 and some form of memory system 414 accessible by the processing unit(s). The memory system can be of the non-transitory type. The use of the expression “computer” in its singular form as used herein includes within its scope the combination of a two or more computers working collaboratively to perform a given function. Moreover, the expression “computer” as used herein includes within its scope the use of partial capabilities of a given processing unit.

[0114] A processing unit can be embodied in the form of a general-purpose micro-processor or microcontroller, a digital signal processing (DSP) processor, an integrated circuit, a field programmable gate array (FPGA), a reconfigurable processor, and a programmable read-only memory (PROM), to name a few examples.

[0115] The memory system can include a suitable combination of any suitable type of computer-readable memory located either internally, externally, and accessible by the processor in a wired or wireless manner, either directly or over a network such as the Internet. A computer-readable memory can be embodied in the form of random-access memory (RAM), read-only memory (ROM), compact disc read-only memory (CDROM), electro-opticalmemory, magneto-optical memory, erasable programmable read-only memory (EPROM), and electrically-erasable programmable read-only memory (EEPROM), Ferroelectric RAM (FRAM)to name a few examples.

[0116] A computer can have one or more input / output (I / O) interface to allow communication with a human user and / or with another computer via an associated input, output, or input / output device such as a keyboard, a mouse, a touchscreen, an antenna, a port, etc. Each I / O interface can enable the computer to communicate and / or exchange data with other components, to access and connect to network resources, to serve applications, and / or perform other computing applications by connecting to a network (or multiple networks) capable of carrying data including the Internet, Ethernet, plain old telephone service (POTS) line, public switch telephone network (PSTN), integrated services digital network (ISDN), digital subscriber line (DSL), coaxial cable, fiber optics, satellite, mobile, wireless (e.g. Wi-Fi, Bluetooth, WiMAX), SS7 signaling network, fixed line, local area network, wide area network, to name a few examples.

[0117] It will be understood that a computer can perform functions or processes via hardware or a combination of both hardware and software. For example, hardware can include logic gates included as part of a silicon chip of a processor. Software (e.g. application, process) can be in the form of data such as computer-readable instructions stored in a non-transitory computer-readable memory accessible by one or more processing units. With respect to a computer or a processing unit, the expression “configured to” relates to the presence of hardware or a combination of hardware and software which is operable to perform the associated functions. Different elements of a computer, such as processor and / or memory, can be local, or in part or in whole remote and / or distributed and / or virtual.

[0118] As can be understood, the examples described above and illustrated are intended to be exemplary only. The scope is indicated by the appended claims.

Claims

WHAT IS CLAIMED IS:

1. A source measure unit drivable by a controller to perform testing of a device under test (DUT), the source measure unit comprising: voltage sources connectable to the controller; a pulse generator having an input port connected to the voltage sources, a control port connectable to the controller, and an output port; an analog-to-digital converter (ADC); and a current-to-voltage (l / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT.

2. The source measure unit of claim 1 wherein the pulse generator has an analog switch with two or more inputs connected to the voltage sources and the control port.

3. The source measure unit of claim 1 or 2 wherein the voltage sources are fixed voltage references.

4. The source measure unit of claim 1 or 2 wherein the voltage sources are digital-to- analog converters (DACs).

5. The source measure unit of any one of claims 1 to 4 wherein the l / V converter has a transimpedance amplifier with a non-inverting port associated to the input port of the l / V converter, an inverting port associated to the third port of the l / V converter, and the third port, and a resistor connected in a retroaction loop in parallel to the transimpedance amplifier between the third port and the first output port of the l / V converter.

6. The source measure unit of any one of claims 1 to 5 wherein the ADC is a single ended ADC.

7. The source measure unit of any one of claims 1 to 5 wherein the ADC is a differential ADC.

8. The source measure unit of any one of claims 1 to 7 further comprising a current limitation unit having a first transistor and a second transistor connected in series to the third port and connectable to the DUT, the first transistor and the second transistor configured in a common source or common drain configuration and each having a corresponding gate.

9. The method of claim 8 wherein the first transistor and the second transistor are MOSFETs.

10. The method of claim 8 wherein the first transistor and the second transistor are NMOSs.11 . A method of testing a device under test DUT comprising: varying the electrical potential of a point Vi while maintaining the electrical potential of a point V2 constant and below the electrical potential of the point V1 , thereby applying a difference of potential V12 in series from point Vi to point V2 across the DUT, a first transistor and a second transistor, the first transistor and the second transistor being configured in a common source or common drain configuration and each having a respective gate; and simultaneously to said varying the electrical potential, maintaining a difference of potential VG2 between a control potential VG and point V2 at an intermediary value including applying the control potential VG to the gates, including the first transistor and the second transistor limiting current circulation across the DUT to below a current limit independently of 12 while allowing current circulation below the current limit across the DUT.

12. The method of claim 11 wherein a difference of potential 12 from point Vi to point V2is in series across a third transistor, a fourth transistor, the DUT, the first transistor and the second transistor, the third transistor and the fourth transistor being configured in the common source or common drain configuration and each having a respective gate, further comprising:during said maintaining the difference of potential VG2 at the intermediary value, maintaining a difference of potential VIH between point Vi and the gates of the third transistor and the fourth transistor at an ON value including the third transistor and the fourth transistor freely allowing current circulation across the DUT.

13. The method of claim 11 or 12 further comprising maintaining the difference of potential VG2 at the ON value including the first transistor and the second transistor freely allowing current circulation across the DUT and changing the difference of potential VG2 to the intermediary value prior to said varying the electrical potential.

14. The method of claim 13 further comprising during said maintaining the difference of potential VG2 at the ON value, varying the electrical potential of a point V2 while maintaining the electrical potential of a point Vi constant and below the electrical potential of the point V2.

15. The method of any one of claims 11 to 14 further comprising maintaining the difference of potential VG2 at an OFF value including the first transistor and the second transistor preventing current circulation across the DUT and changing the difference of potential VG2 to the intermediary value prior to said varying the electrical potential.

16. The method of any one of claims 11 to 15 wherein the intermediary value of VG2 is between 0.001 and 0.7 of 7G2ON) > wherein VG2<ON) is the value of VG2 for which, when progressively increasing VG2, a resistance of the first transistor and the second transistor first reach a value of within 115% of a minimum resistance value.

17. The method of claim 16 wherein VG2<ON) is the value of VG2 for which, when progressively increasing VG2, a resistance of the first transistor and the second transistor first reach a value of within 105% of a minimum resistance value.

18. The method of claim 16 or 17 wherein the intermediary value of VG2 is between 0.005 and 0.5 of yG2(ON).

19. The method of any one of claims 16 to 18 wherein the intermediary value of VG2 is between 0.01 and 0.4 of VG2(ON) -20. The method of any one of claims 11 to 19 wherein the intermediary value of VG2 is between 0 and 3 VT, where VTis a threshold voltage of the first transistor and of the second transistor.21 . The method of claim 20 wherein the intermediary value of VG2 is between 0 and 2VT.

22. The method of claim 20 wherein the intermediary value of VG2is between 0.05 and 1.5VT.

23. The method of any one of claims 11 to 22 wherein the intermediary value of VG2is between a value of near zero corresponding to operating the first transistor and the second transistor in open switch mode, and a high or maximum value corresponding to operating the first transistor and the second transistor in a closed switch mode, the intermediary value of potential VG2corresponding to operating the first transistor and the second transistor in a current limitation mode.

24. The method of any one of claims 11 to 23 wherein the DUT has a maximum current specification, further applying the difference of potential VG2in a manner for the current limit to be at or below the maximum current specification of the DUT.

25. A testing system comprising: a controller, and a plurality of source measure units, each source measure unit individually connectable to one or more electrical connection of a device under test (DUT).

26. The testing system of claim 25, wherein each source measure unit has voltage sources connected to the controller;a pulse generator having an input port connected to the voltage sources, a control port connected to the controller, and an output port; an analog-to-digital converter (ADC); and a current- to-voltage (1 / V) converter having a first output port connected to the ADC, an input port connected to the output port of the pulse generator, and a third port connectable to the DUT.

27. The testing system of claim 25 or 26 further comprising current limitation units connected in series between the source measure unit and the DUT, each current limitation unit having a first transistor and a second transistor configured in a common source or common drain configuration and each having a corresponding gate, the gates having an electrical potential controllable by the controller.

28. The testing system of claim 27 wherein the electrical potential of the gates is controllable by the controller in a manner to set an intermediary difference of potential with the corresponding source measure unit, the intermediary difference of potential causing a current limitation across the DUT and being between an ON difference of potential allowing free current limitation across the DUT and an OFF difference of potential preventing current circulation across the DUT.

29. The testing system of claim 28 wherein the electrical potential of the gates is further controllable by the controller to the ON difference of potential.

30. The testing system of claim 28 or 29 wherein the electrical potential of the gates is further controllable by the controller to the OFF difference of potential.31 . The testing system of any one of claims 25 to 30 wherein the controller has an FPGA.

32. The testing system of any one of claims 25 to 30 wherein the controller has a microcontroller.

33. The testing system of any one of claims 25 to 30 wherein the controller has a serial to parallel computing unit connecting the plurality of source measure units to a serial computing unit.

34. The testing system of any one of claims 26 to 30 wherein a serial communication protocol is used by the controller to control the voltage sources and to receive data from the ADCs.

35. The testing system of any one of claims 26 to 30 wherein a parallel communication protocol is used to control the pulse generator.

36. The testing system of any one of claims 25 to 35 further comprising a first transistor and a second transistor connected in series between a fixed voltage source and the DUT, the first transistor and the second transistor configured in a common source or common drain configuration and each having a corresponding gate, the gates having an electrical potential controllable by the controller.

37. The testing system of any one of claims 27 to 30 and 36 wherein the controller has a processor and memory storing instructions which, when executed by the processor cause the controller to: vary the electrical potential Vi of a first source measure unit while maintaining the electrical potential V2 of a second source measure unit or fixed voltage source constant and below the electrical potential of the point V1, thereby applying a difference of potential V12 in series from point Vi to point V2 across the DUT, the first transistor and the second transistor; and simultaneously to said varying the electrical potential, maintaining a difference of potential VG2 between the gates and point V2at an intermediary value, thereby controlling the first transistor and the second transistor in a manner to limit current circulation across the DUT to below a current limit independently of V12 while allowing current circulation below the current limit across the DUT.

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