Imaging device

Abstract

The present invention provides an imaging device that allows easy drive control. The imaging device includes circuit blocks arranged in two rows and two columns, pixel blocks arranged in two rows and two columns on the circuit blocks, and a control circuit. Pixels are arranged in a matrix in each of the pixel blocks. Each of the circuit blocks arranged in two rows and two columns has a plurality of drive circuits. Each of the plurality of drive circuits has a function of controlling driving of mutually different pixels. The circuit blocks arranged in two rows and two columns are laid out line-symmetrically about boundaries between the blocks. The control circuit has a function of simultaneously driving drive circuits having the same address among the drive circuits included in the circuit blocks arranged in two rows and two columns. The control circuit has a function of causing a part of the pixels included in each of the first to fourth pixel blocks to acquire imaging data.

Description

Imaging device

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an object, a driving method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the invention disclosed in this specification or the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, storage devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, their driving methods, or their manufacturing methods.

[0003] In an imaging device, due to the high integration of pixels, the scale of the driving circuit having a function of driving the pixels has become large. In Patent Document 1, an imaging device is disclosed in which a driving circuit and pixels are stacked to increase the scale of the driving circuit while suppressing an increase in the occupied area.

[0004] JP 2021-16639⑤ A

[0005] Takashi Koiwa, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Solar Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0006] When the driving circuit for driving the pixels becomes large-scale, the control of the driving circuit becomes complicated. In addition, a large-scale driving circuit has a large burden on the layout design.

[0007] One aspect of the present invention is to provide an imaging device that can easily perform drive control. Another aspect of the present invention is to provide an imaging device that can easily perform layout design. Another aspect of the present invention is to provide an imaging device with low power consumption. Another aspect of the present invention is to provide an imaging device with a low price. Another aspect of the present invention is to provide a highly functional imaging device. Another aspect of the present invention is to provide a small-sized imaging device. Another aspect of the present invention is to provide a high-resolution imaging device. Another aspect of the present invention is to provide an imaging device that drives at high speed. Another aspect of the present invention is to provide a highly reliable imaging device. Another aspect of the present invention is to provide a novel imaging device or the like. Another aspect of the present invention is to provide a driving method for the above imaging device.

[0008] Note that the above problems do not prevent the existence of other problems. Other problems other than the above problems will become obvious from the description in this specification, drawings, or claims, etc., and it is possible to extract other problems other than the above problems from the description in this specification, drawings, or claims, etc. Note that one aspect of the present invention does not need to solve all of these problems (the above problems and other problems).

[0009] One aspect of the present invention comprises a first circuit block, a second circuit block, a third circuit block, a fourth circuit block, a first pixel block, a second pixel block, a third pixel block, and a fourth pixel block, wherein each of the first to fourth circuit blocks has a plurality of drive circuits, and each of the first to fourth pixel blocks has pixels arranged in a matrix, each having a photodetector and a transistor, the first pixel block is located on the first circuit block, the second pixel block is located on the second circuit block, and the third pixel block is located on the third circuit The imaging device is configured such that the fourth pixel block is located on a block, the fourth pixel block is located on a fourth circuit block, each of the multiple drive circuits has the function of controlling the driving of different pixels, the layout of the second circuit block is line-symmetric with respect to the layout of the first circuit block with respect to the first axis as the axis of symmetry, the layout of the third circuit block is line-symmetric with respect to the first circuit block with respect to the second axis as the axis of symmetry, the second axis is perpendicular to the first axis, and the layout of the fourth circuit block is point-symmetric with respect to the layout of the first circuit block with respect to the intersection of the first and second axes.

[0010] Alternatively, in the above embodiment, the drive circuit may include a selection circuit and a readout circuit, wherein the selection circuit has the function of selecting a pixel for acquiring imaging data and a pixel in which imaging data to be read out is held, and the readout circuit has the function of reading out the imaging data held in the selected pixel.

[0011] Alternatively, in the above embodiment, each of the first to fourth circuit blocks may have one input / output circuit, the input / output circuit having the function of distributing a control signal input from the outside to one of the multiple drive circuits, and the input / output circuit having the function of outputting the imaging data read by the readout circuit to the outside.

[0012] Alternatively, in the above embodiment, the imaging device may have a control circuit, which has the function of simultaneously driving the drive circuits of the first circuit block, the second circuit block, the third circuit block, and the fourth circuit block that are symmetrical with respect to the first axis, the second axis, and the intersection.

[0013] Alternatively, in the above embodiment, the imaging device may have a control circuit, which has the function of simultaneously causing the selection circuits of the first, second, third, and fourth circuit blocks to select pixels that are symmetrical with respect to the first axis, second axis, and intersection point, from among the pixels of the first, second, third, third, and fourth pixel blocks, respectively.

[0014] Alternatively, in the above embodiment, the control circuit may have a function to cause imaging data to be acquired for some of the pixels in the first pixel block, the second pixel block, the third pixel block, and the fourth pixel block.

[0015] Alternatively, in the above embodiment, the transistor may have a metal oxide in the channel formation region.

[0016] Alternatively, in the above embodiment, the metal oxide may be indium oxide.

[0017] According to one aspect of the present invention, an imaging device that allows for easy drive control can be provided. Furthermore, according to one aspect of the present invention, an imaging device that allows for easy layout design can be provided. Furthermore, according to one aspect of the present invention, an imaging device with low power consumption can be provided. Furthermore, according to one aspect of the present invention, a low-cost imaging device can be provided. Furthermore, according to one aspect of the present invention, a high-performance imaging device can be provided. Furthermore, according to one aspect of the present invention, a compact imaging device can be provided. Furthermore, according to one aspect of the present invention, a high-resolution imaging device can be provided. Furthermore, according to one aspect of the present invention, a high-speed driven imaging device can be provided. Furthermore, according to one aspect of the present invention, a highly reliable imaging device can be provided. Furthermore, according to one aspect of the present invention, a novel imaging device, etc., can be provided. Furthermore, according to one aspect of the present invention, a driving method for the above-mentioned imaging device can be provided.

[0018] Furthermore, the effects described above do not preclude the existence of other effects. Other effects not described above will become clear from this specification, the drawings, or the claims, and it is possible to extract these other effects from this specification, the drawings, or the claims. Moreover, one aspect of the present invention does not need to possess all of these effects (the effects described above and other effects).

[0019] Figure 1 is a perspective view showing an example of the configuration of an imaging device. Figure 2 is a block diagram showing an example of the configuration of an imaging device. Figures 3A and 3B are schematic diagrams showing the drive modes of the imaging device. Figure 4 is a block diagram showing an example of a drive method for the imaging device. Figure 5 is a block diagram showing an example of a drive method for the imaging device. Figure 6 is a block diagram showing an example of a drive method for the imaging device. Figure 7 is a block diagram showing an example of the configuration of an imaging device. Figure 8 is a diagram showing an example of the configuration of an imaging device. Figures 9A and 9B are circuit diagrams showing an example of the configuration of a pixel. Figures 10A and 10B are schematic diagrams showing an example of a drive method for the imaging device. Figures 11A and 11B are timing charts showing an example of a pixel drive method. Figures 12A and 12B are circuit diagrams showing an example of the configuration of a pixel. Figure 13 is a cross-sectional view showing an example of the configuration of a pixel. Figure 14 is a cross-sectional view showing an example of the configuration of an imaging device. Figures 15A and 15B are cross-sectional views showing an example of the configuration of a transistor. Figure 16 is a cross-sectional view showing an example of the configuration of an imaging device. Figure 17 is a cross-sectional view showing an example of the configuration of an imaging device. Figure 18A is a plan view showing an example of the configuration of a transistor. Figures 18B, 18C, and 18D are cross-sectional views showing examples of transistor configurations. Figure 19 is a cross-sectional view showing an example of transistor configuration. Figures 20A, 20B, and 20C are cross-sectional views showing examples of transistor configurations. Figures 21A and 21B illustrate the carrier concentration dependence of Hall mobility. Figure 21C is a cross-sectional view illustrating an indium oxide film. Figure 22A illustrates a package containing an imaging device. Figure 22B illustrates a module containing an imaging device. Figures 23A, 23B, 23C, 23D, 23E, and 23F illustrate electronic equipment. Figures 24A and 24B illustrate a mobile body. Figures 25A1, 25A2, 25A3, 25A4, 25A5, 25A6, 25A7, 25B1, 25B2, 25B3, 25B4, 25B5, and 25B6 are diagrams that explain "connections".

[0020] In this specification, a semiconductor device is a device that utilizes semiconductor properties, and for example, a circuit containing semiconductor elements (e.g., transistors or diodes, etc.), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits containing semiconductor elements, chips equipped with integrated circuits, electronic components with chips housed in a package, or electronic devices on which electronic components are mounted are examples of semiconductor devices. Furthermore, for example, display devices, light-emitting devices, energy storage devices, optical devices, imaging devices, illumination devices, computing devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, computers, or electronic devices are themselves semiconductor devices and may also contain semiconductor devices.

[0021] The embodiments will be described below with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be easily understood by those skilled in the art that their form and details can be changed in various ways without departing from the spirit and scope. Accordingly, the present invention is not to be construed as being limited to the contents described in the embodiments.

[0022] Furthermore, in this specification, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Also, if multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0023] In addition, in drawings illustrating embodiments of the invention, the same reference numerals may be used across different drawings for identical or functionally similar parts, thereby omitting repeated explanations. Furthermore, in drawings, if similar functions are indicated, for example, the same hatching patterns may be used, and no specific reference numerals may be assigned. Also, in order to facilitate understanding, some components may be omitted in drawings, for example, in perspective views or plan views. Furthermore, some hidden lines may be omitted in drawings. Also, some hatching patterns may be omitted in drawings.

[0024] Furthermore, in drawings, size, layer thickness, or area may be exaggerated for clarity. Therefore, drawings are not limited to, for example, their size or aspect ratio. Also, drawings schematically represent ideal examples and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally reduced due to processes such as etching, but these may not be reflected in the drawings for ease of understanding. Similarly, in actual circuit operation, variations in voltage or current may occur due to noise or timing discrepancies, but these may not be reflected in the drawings for ease of understanding.

[0025] Furthermore, in this specification and the drawings, components may be classified by function and shown as independent elements. However, it is difficult to separate components by function, and there are cases where multiple functions are involved in a single element, or where a single function is involved across multiple elements. Therefore, the elements shown in this specification and the drawings are not limited to their descriptions and may be appropriately rephrased.

[0026] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identification numeral such as "A", "b", "_1", "[n]", or "[m,n]". Also, when describing something common to multiple elements that have been given an identification numeral, or when it is not necessary to distinguish them, the reference numeral may be omitted.

[0027] In this specification, the "conducting state" or "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source and drain (also called a state in which current can flow). For example, in an n-channel transistor, a state in which the voltage between the gate and source is higher than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and source is lower than the threshold voltage, may be referred to as the "conducting state" or "on state." Furthermore, the "non-conducting state," "blocked state," or "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically blocked. For example, in an n-channel transistor, a state in which the voltage between the gate and source is lower than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and source is higher than the threshold voltage, may be referred to as the "non-conducting state," "blocked state," or "off state."

[0028] Furthermore, in this specification, the voltage between the gate and source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the back gate and source (back gate-source) is sometimes referred to as the "back gate voltage." Also, the current flowing between the drain and source is sometimes referred to as the "drain current." Note that in n-channel transistors, descriptions such as "high gate voltage," "high drain voltage," and "high back gate voltage" can be appropriately interpreted as equivalent to descriptions such as "low gate voltage," "low drain voltage," and "low back gate voltage" in p-channel transistors. Similarly, descriptions such as "low gate voltage," "low drain voltage," and "low back gate voltage" in n-channel transistors can be appropriately interpreted as equivalent to descriptions such as "high gate voltage," "high drain voltage," and "high back gate voltage" in p-channel transistors.

[0029] Furthermore, in this specification, unless otherwise specified, the "off-current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification, the off-current, as well as the current flowing between the gate, source, and drain (also called gate leakage current), may be referred to as leakage current.

[0030] (Embodiment 1) In this embodiment, an imaging device according to one aspect of the present invention will be described with reference to the drawings.

[0031] An imaging device according to one aspect of the present invention includes a 2x2 circuit block (first to fourth circuit block) and pixel blocks (first to fourth pixel block) on these circuit blocks. Each of the first to fourth circuit blocks has multiple drive circuits arranged, for example, in a matrix. Each of the first to fourth circuit blocks may also have, for example, one input / output circuit. The input / output circuit functions as an interface.

[0032] The first to fourth pixel blocks each have pixels arranged in a matrix. Each pixel has a photodetector (also called a photodetector) and a transistor. Each of the multiple drive circuits controls the driving of different pixels, specifically pixels located in different regions. Specifically, the drive circuits have the function of controlling the acquisition of imaging data by the pixels and the reading out of said imaging data.

[0033] The layouts of the first to fourth circuit blocks are symmetrical with respect to their respective boundaries. Specifically, the second circuit block is symmetrical with respect to the first circuit block's layout with respect to the first axis. Similarly, the third circuit block is symmetrical with respect to the first circuit block's layout with respect to the second axis, which is perpendicular to the first axis. Furthermore, the fourth circuit block is point-symmetrical with respect to the first circuit block's layout with respect to the intersection of the first and second axes. In other words, the fourth circuit block is symmetrical with respect to the third circuit block's layout with respect to the first axis, and also symmetrical with respect to the second circuit block's layout with respect to the second axis.

[0034] In one embodiment of the present invention, an imaging device has a circuit block with a drive circuit, which is placed on top of the pixels. That is, the circuit block is placed on a different layer from the pixels. This allows for a larger circuit block while miniaturizing the imaging device, compared to, for example, placing the circuit block on the same layer as the pixels. By increasing the size of the circuit block, the number of pixels that can be placed in the pixel block can be increased. Thus, a high-resolution imaging device can be realized.

[0035] Furthermore, by overlapping the drive circuit with the pixels, the wiring distance between the drive circuit and the pixels can sometimes be shortened compared to, for example, when the drive circuit is located on the same layer as the pixels. In this case, the imaging device can be driven at high speed. In addition, the power consumption of the imaging device can be reduced.

[0036] Furthermore, in an imaging device according to one aspect of the present invention, a circuit block having a drive circuit is divided into two-row, two-column circuit blocks (first to fourth circuit blocks), and the layout is symmetrical with respect to the boundary between them. This makes it easier to control the drive of the circuit blocks compared to, for example, when the circuit block having a drive circuit is not divided. For example, the drive of the circuit blocks can be controlled by supplying the same control signal to each of the first to fourth circuit blocks. Thus, an imaging device with low power consumption can be provided.

[0037] Furthermore, in an imaging device according to one aspect of the present invention, only one circuit block among the first to fourth circuit blocks needs to be designed for layout. Therefore, for example, the layout design can be made easier than if the circuit block having a drive circuit were not divided. Consequently, since the layout design can be done at a low cost, an imaging device can be provided at a low cost.

[0038] As described above, an imaging device according to one aspect of the present invention allows for a larger circuit block while easily controlling its drive compared to a circuit block without division of the drive circuit. Furthermore, it facilitates the design of the circuit block's layout. As a result, an imaging device with high resolution, low power consumption, and low cost can be provided.

[0039] <Example of Imaging Device Configuration 1> Figure 1 is a perspective view showing an example of the configuration of an imaging device 10, which is an imaging device according to one aspect of the present invention. As shown in Figure 1, the imaging device 10 has a two-layer structure consisting of a layer 41 and a layer 42 on top of layer 41. A 2x2 circuit block 11 is provided in layer 41. Here, the circuit blocks 11 in the 1st row, 1st column, 1st row, 2nd column, 2nd row, 1st column, and 2nd row, 2nd column are distinguished by being described as circuit block 11[1,1], circuit block 11[1,2], circuit block 11[2,1], and circuit block 11[2,2], respectively.

[0040] Each circuit block 11 includes a plurality of drive circuits 13, one or more lamp signal generation circuits 15, and, for example, one input / output circuit 17. In addition to the circuit blocks 11, layer 41 is also provided with a control circuit 19. Note that the control circuit 19 does not necessarily have to be included in layer 41.

[0041] In the example shown in Figure 1, multiple drive circuits 13 are arranged in a matrix. Figure 1 shows an example where each of the circuit blocks 11[1,1] to 11[2,2] has a drive circuit 13 arranged in a 3x3 grid.

[0042] Furthermore, in the example shown in Figure 1, one lamp signal generation circuit 15 is provided for each row of drive circuits 13. Note that the number and arrangement of lamp signal generation circuits 15 are not limited to the example shown in Figure 1; for example, only one lamp signal generation circuit 15 may be provided for each circuit block 11. Alternatively, the same number of lamp signal generation circuits 15 may be provided as the number of drive circuits 13. In this case, the lamp signal generation circuits 15 may be included within the drive circuits 13.

[0043] Layer 42 is provided with a 2x2 pixel block 31, similar to the circuit block 11. Here, the pixel blocks 31 in the 1st row, 1st column, 1st row, 2nd column, 2nd row, 1st column, and 2nd row, 2nd column are distinguished by being described as pixel block 31[1,1], pixel block 31[1,2], pixel block 31[2,1], and pixel block 31[2,2], respectively. Pixel block 31[1,1] has an area that overlaps with circuit block 11[1,1]. Pixel block 31[1,2] has an area that overlaps with circuit block 11[1,2]. Pixel block 31[2,1] has an area that overlaps with circuit block 11[2,1]. Pixel block 31[2,2] has an area that overlaps with circuit block 11[2,2]. Here, the control circuit 19 can be provided so as to have an area that does not overlap with the pixel blocks 31.

[0044] Pixels 35 are arranged in a matrix within the pixel block 31. Here, the pixel block 31 is provided with the same number of pixel arrays 33 as the drive circuit 13. Furthermore, the pixel arrays 33 are arranged in a matrix, similar to the drive circuit 13.

[0045] Pixel 35 has a light-receiving element. The light-receiving element has the function of supplying an electric current according to the intensity of the irradiated light. By exposing the light-receiving element, pixel 35 can acquire imaging data.

[0046] Examples of light-receiving elements include photodiodes, phototransistors, photoconductive elements, and photomultiplier tubes. Examples of photodiodes include PN photodiodes, PIN photodiodes, and avalanche photodiodes. Examples of materials used in photodiodes include elemental semiconductors whose main component is a single element (silicon, germanium, etc.), compound semiconductors (indium gallium arsenide, etc.), oxide semiconductors, and organic semiconductors.

[0047] The drive circuit 13 has the function of controlling the driving of the pixels 35. Specifically, the drive circuit 13 has the function of controlling the acquisition of imaging data by the pixels 35 and the reading out of said imaging data. Each of the multiple drive circuits 13 controls the driving of pixels 35 provided in different pixel arrays 33. Therefore, each of the multiple pixel arrays 33 can be said to be a region in which the area where pixels 35 are provided is divided according to the drive circuit 13.

[0048] The input / output circuit 17 functions as an interface for inputting signals from outside the circuit block 11 to the drive circuit 13, and for outputting signals from the drive circuit 13 to outside the circuit block 11. The control circuit 19 has the function of controlling the drive of each of the multiple drive circuits 13. For example, the control circuit 19 generates a control signal and supplies it to the input / output circuit 17. The input / output circuit 17 distributes the control signal to the drive circuits 13. In this way, the drive of the drive circuits 13 can be controlled by the control circuit 19.

[0049] The control signal generated by the control circuit 19 includes address information, a clock signal, and the like. The address information represents an address used to identify the drive circuit 13 to be operated from among a plurality of drive circuits 13. By supplying the clock signal and the like to the drive circuit 13 represented by the address information, the drive circuit 13 can be operated.

[0050] As described above, in the imaging device 10, the circuit block 11 having the drive circuit 13 is placed on top of the pixels 35. This allows for a larger circuit block 11 while miniaturizing the imaging device, compared to, for example, placing the circuit block 11 on the same layer as the pixels 35, i.e., on layer 42. By increasing the size of the circuit block 11, the number of pixels 35 provided in the pixel block 31 can be increased. Therefore, a high-resolution imaging device can be realized.

[0051] Furthermore, by stacking the circuit block 11 with the pixels 35, the number of drive circuits 13 in the circuit block 11 can be increased compared to when the circuit block 11 is placed on the same layer as the pixels 35. This makes it easier to acquire imaging data using only some of the pixels 35. Specifically, it becomes easier to acquire imaging data using pixels 35 provided in some of the pixel arrays 33 among the multiple pixel arrays 33. Here, by performing power gating or clock gating on the drive circuits 13 corresponding to the pixel arrays 33 that are not used for acquiring imaging data, the power consumption of the imaging device 10 can be reduced.

[0052] In this specification, the term "drive circuit corresponding to a pixel array" refers to a drive circuit having the function of driving the pixels provided in the pixel array.

[0053] Furthermore, by mounting the drive circuit 13 on top of the pixels 35, the wiring distance between the drive circuit 13 and the pixels 35 can be shortened compared to, for example, mounting the drive circuit 13 on the same layer as the pixels 35. In this case, the imaging device 10 can be driven at high speed. Also, the power consumption of the imaging device can be reduced.

[0054] Figure 2 is a block diagram showing an example of the configuration of layer 41. In Figure 2, the 3x3 drive circuits 13 of the circuit block 11 are distinguished by being labeled as drive circuit 13a, drive circuit 13b, drive circuit 13c, drive circuit 13d, drive circuit 13e, drive circuit 13f, drive circuit 13g, drive circuit 13h, and drive circuit 13i, respectively.

[0055] The drive circuit 13 includes a selection circuit 21 and a readout circuit 23. The selection circuit 21 has the function of selecting pixels 35 to be imaged. The selected pixels 35 can acquire image data. The acquired image data is held by the pixels 35. The selection circuit 21 also has the function of selecting pixels 35 that hold image data to be read out. The selection circuit 21 can select these pixels 35 by generating a selection signal and supplying it to the pixels 35. Here, the selection circuit 21 can sequentially select pixels 35 row by row of pixels 35 arranged in a matrix. The selection circuit 21 includes, for example, a horizontal scanning circuit (also called a scan driver, low driver, etc.).

[0056] The readout circuit 23 has the function of reading out the imaging data acquired by the pixel 35 and outputting it as a signal (imaging signal) to the input / output circuit 17. The readout circuit 23 also has the function of reading out the imaging data held in the pixel 35 selected by the selection circuit 21. The input / output circuit 17 can output the imaging signal to the outside of the imaging device 10.

[0057] The readout circuit 23 includes, for example, a correlated double sampling (CDS) circuit, an analog-to-digital conversion circuit (also called an AD conversion circuit), a latch circuit, a buffer circuit, and a vertical scanning circuit (also called a data driver, column driver, etc.).

[0058] The lamp signal generation circuit 15 has the function of supplying a lamp waveform signal to the AD conversion circuit of the readout circuit 23. The AD conversion circuit can convert the analog signal output from the CDS circuit of the readout circuit 23 into a digital signal by comparing the potential of the signal generated by the lamp signal generation circuit 15 with the potential of the analog signal output from the CDS circuit of the readout circuit 23. This enables AD conversion to be performed on the imaging data acquired by the pixel 35.

[0059] In this specification and other documents, a signal with a ramp waveform is referred to as a ramp signal.

[0060] The layouts of circuit blocks 11[1,1] through 11[2,2] are symmetrical with respect to their respective boundaries. In Figure 2, the boundaries between circuit block 11[1,1] and circuit block 11[1,2], and between circuit block 11[2,1] and circuit block 11[2,2] are shown as axis A-B. The boundaries between circuit block 11[1,1] and circuit block 11[2,1], and between circuit block 11[1,2] and circuit block 11[2,2] are shown as axis C-D. Axis C-D is perpendicular to axis A-B.

[0061] The layout of circuit block 11[1,2] is line-symmetric to the layout of circuit block 11[1,1] with respect to axis A-B. Similarly, the layout of circuit block 11[2,1] is line-symmetric to the layout of circuit block 11[1,1] with respect to axis C-D. Furthermore, the layout of circuit block 11[2,2] is point-symmetric to the layout of circuit block 11[1,1] with respect to the intersection of axis A-B and axis C-D. In other words, the layout of circuit block 11[2,2] is line-symmetric to the layout of circuit block 11[2,1] with respect to axis A-B, and is also line-symmetric to the layout of circuit block 11[1,2] with respect to axis C-D.

[0062] In Figure 2, the same reference numeral is used to indicate drive circuits 13 located symmetrically to each other among the drive circuits 13 in circuit blocks 11[1,1] to 11[2,2]. In the example shown in Figure 2, four drive circuits 13a are provided so as to surround the intersection of axis A-B and axis C-D. Four drive circuits 13b, 13c, and 13d are provided so as to surround the four drive circuits 13a. Furthermore, four drive circuits 13e, 13f, 13g, 13h, and 13i are provided so as to surround the four drive circuits 13b to 13d. Thus, for example, the four drive circuits 13a in circuit blocks 11[1,1] to 11[2,2] are symmetrical with respect to axis A-B, axis C-D, or the intersection of axis A-B and axis C-D. The same applies to drive circuits 13b to 13i.

[0063] As described above, in the imaging device 10, the circuit block 11 having the drive circuit 13 is divided into circuit block 11[1,1] to circuit block 11[2,2], and the layout is symmetrical with respect to the boundary between them. This makes it easier to control the drive of the circuit block 11 than, for example, if the circuit block 11 is not divided. For example, the control circuit 19 can control the drive of the circuit block 11 by supplying the same control signal to each of the circuit block 11[1,1] to circuit block 11[2,2]. Therefore, the imaging device 10 can be an imaging device with low power consumption. The control circuit 19 can be externally attached as a driver IC (Integrated Circuit). Therefore, when designing the layout of the imaging device 10, it is not necessary to design the layout of the control circuit 19.

[0064] Furthermore, in the imaging device 10, only one circuit block 11 from circuit blocks 11[1,1] to circuit blocks 11[2,2] needs to be designed for layout. Therefore, the layout design of the circuit blocks 11 can be made easier than if the circuit blocks 11 were not divided. Consequently, the imaging device 10 can be made into a low-cost imaging device because the layout design can be done at a low cost.

[0065] Here, it is preferable that the wiring distances between the control circuit 19 and circuit block 11[1,1], between the control circuit 19 and circuit block 11[1,2], between the control circuit 19 and circuit block 11[2,1], and between the control circuit 19 and circuit block 11[2,2] are as equal as possible to match the signal transmission delay. This allows the same operation to be performed simultaneously between circuit blocks 11[1,1] to 11[2,2]. Alternatively, the timing difference in operation between circuit blocks 11[1,1] to 11[2,2] can be minimized. As a result, for example, malfunctions of the imaging device 10 can be prevented. Therefore, the reliability of the imaging device 10 can be increased.

[0066] Figures 3A and 3B are schematic diagrams illustrating the drive modes of the imaging device 10. Figure 3A shows an example of imaging performed using a 6x6 pixel array 33.

[0067] Figure 3B shows an example of imaging using a 2x2 pixel array 33 that includes the region R shown in Figure 3A, specifically the center (the intersection of axes A-B and C-D shown in Figure 2). Figure 3B corresponds to the case where the landscape shown in Figure 3A is enlarged, for example, using a digital zoom function.

[0068] In this specification, as shown in Figure 3A, a drive mode in which imaging is performed using all of the pixel arrays 33 is sometimes referred to as the whole imaging mode. Also, as shown in Figure 3B, a drive mode in which imaging is performed using only some of the pixel arrays 33 is sometimes referred to as the partial imaging mode.

[0069] When capturing the image shown in Figure 3B, the image can be captured using the pixels 35 driven by the drive circuit 13a shown in Figure 2. In other words, the drive circuits 13b to 13i do not need to be driven. Here, by arranging the circuit blocks 11[1,1] to 11[2,2] in a symmetrical layout with respect to their respective boundaries, the drive circuits 13a of circuit block 11[1,1], 11[1,2], 11[2,1], and 11[2,2] can be controlled with the same control signal. Specifically, the control circuit 19 can drive the four drive circuits 13a by supplying control signals with the same address information to each of the circuit blocks 11[1,1], 11[1,2], 11[2,1], and 11[2,2], and can drive them simultaneously, for example. In Figure 2, in each of the circuit blocks 11[1,1], 11[1,2], 11[2,1], and 11[2,2], the drive circuits 13 with the same address are assigned the same reference numeral.

[0070] Figures 4 to 6 are block diagrams showing the drive of the drive circuits 13a in circuit block 11[1,1], the drive circuit 13a in circuit block 11[1,2], the drive circuit 13a in circuit block 11[2,1], and the drive circuit 13a in circuit block 11[2,2]. In Figures 4 to 6, these drive circuits 13a are distinguished by being labeled as drive circuit 13a[1,1], drive circuit 13a[1,2], drive circuit 13a[2,1], and drive circuit 13a[2,2], respectively.

[0071] In Figures 4 to 6, the selection circuit 21 and the readout circuit 23 of the drive circuit 13a[1,1] are shown as selection circuit 21a[1,1] and readout circuit 23a[1,1], respectively. Similarly, the selection circuit 21 and the readout circuit 23 of the drive circuit 13a[1,2] are shown as selection circuit 21a[1,2] and readout circuit 23a[1,2], respectively. Furthermore, the selection circuit 21 and the readout circuit 23 of the drive circuit 13a[2,1] are shown as selection circuit 21a[2,1] and readout circuit 23a[2,1], respectively. In addition, the selection circuit 21 and the readout circuit 23 of the drive circuit 13a[2,2] are shown as selection circuit 21a[2,2] and readout circuit 23a[2,2], respectively.

[0072] Furthermore, in Figures 4 to 6, the input / output circuits 17 of circuit block 11[1,1], the input / output circuits 17 of circuit block 11[1,2], the input / output circuits 17 of circuit block 11[2,1], and the input / output circuits 17 of circuit block 11[2,2] are distinguished by being described as input / output circuit 17[1,1], input / output circuit 17[1,2], input / output circuit 17[2,1], and input / output circuit 17[2,2], respectively.

[0073] Figures 4 to 6 show the pixels 35 provided in the pixel array 33 controlled by drive circuit 13a[1,1], the pixel array 33 controlled by drive circuit 13a[1,2], the pixel array 33 controlled by drive circuit 13a[2,1], and the pixel array 33 controlled by drive circuit 13a[2,2]. In Figures 4 to 6, these pixel arrays 33 are distinguished by being labeled as pixel array 33a[1,1], pixel array 33a[1,2], pixel array 33a[2,1], and pixel array 33a[2,2], respectively. Note that in Figures 4 to 6, for the sake of clarity, the pixel arrays 33a are shown not overlapping with the drive circuit 13a, but in reality, the pixel arrays 33a have regions that overlap with the drive circuit 13a.

[0074] The selection circuits 21a[1,1], 21a[1,2], 21a[2,1], and 21a[2,2] are each connected to m (where m is an integer of 3 or more) wires 51. In each of the selection circuits 21a[1,1] through 21a[2,2], the same wire 51 is connected to the same row of pixels 35. In Figures 4 through 6, the m wires 51 are distinguished by being labeled as wire 51<1> through wire 51<m>. In each of the pixel arrays 33a[1,1] through 33a[2,2], the same reference numeral is used to indicate wires 51 connected to the same address of a pixel 35. For example, the wire 51 closest to the readout circuit 23a is labeled as wire 51<1>. Furthermore, the wiring 51 closest to the boundary between pixel array 33a[1,1] and pixel array 33a[2,1], and the boundary between pixel array 33a[1,2] and pixel array 33a[2,2] is indicated as wiring 51<m>. Here, among the pixels 35 in pixel blocks 31[1,1] to 31[2,2], the pixels 35 that are symmetrical with respect to axis A-B, axis C-D, or the intersection of axis A-B and axis C-D shown in Figure 2 are the pixels 35 with the same address.

[0075] The wiring 51 can be configured to include multiple wires, depending on the configuration of the pixels 35. For example, a single wiring 51 can include a wire that outputs a selection signal for selecting a pixel to take an image and a wire that outputs a selection signal for selecting a pixel from which to read the image data. In this case, a single wiring 51 can include two or more wires.

[0076] The readout circuits 23a[1,1], 23a[1,2], 23a[2,1], and 23a[2,2] are each connected to n (where n is an integer greater than or equal to 3) wires 53. In each of the readout circuits 23a[1,1] through 23a[2,2], the same wire 53 is connected to the same row of pixels 35. In Figures 4 through 6, the n wires 51 are distinguished by being labeled as wires 53<1> through 53<n>. In each of the pixel arrays 33a[1,1] through 33a[2,2], the wires 53 connected to the same address of the pixel 35 are given the same designation. For example, the wire 53 closest to the selection circuit 21a is labeled as wire 53<1>. Furthermore, the wiring 53 closest to the boundary between pixel array 33a[1,1] and pixel array 33a[1,2], and the boundary between pixel array 33a[2,1] and pixel array 33a[2,2] is indicated as wiring 53<n>. Note that, depending on the configuration of the pixel 35, a configuration may be used in which multiple wirings are included per wiring 53.

[0077] As described above, each selection circuit 21 is connected to m wires 51, and each readout circuit 23 is connected to n wires 53. Therefore, it can be said that each pixel array 33 has m rows and n columns of pixels 35 arranged in a matrix.

[0078] The readout circuit 23a is connected to the bus wiring 55. The imaging data read out by the readout circuit 23a is supplied to the input / output circuit 17 via the bus wiring 55. In Figures 4 to 6, the bus wiring 55 is shown with a thick solid line. In Figures 4 to 6, examples are shown where the bus wiring 55 connected to readout circuit 23a[1,1], the bus wiring 55 connected to readout circuit 23a[1,2], the bus wiring 55 connected to readout circuit 23a[2,1], and the bus wiring 55 connected to readout circuit 23a[2,2] are all different from each other. In Figures 4 to 6, these bus wirings 55 are distinguished by being labeled as bus wiring 55[1,1], bus wiring 55[1,2], bus wiring 55[2,1], and bus wiring 55[2,2], respectively.

[0079] The bus wiring 55 can be provided, for example, one per row of drive circuits 13 in each of the circuit blocks 11[1,1], circuit block 11[1,2], circuit block 11[2,1], and circuit block 11[2,2] shown in Figure 2. In this case, the read circuits 23 of drive circuit 13a, drive circuit 13b, and drive circuit 13e can be connected to the first bus wiring 55. The read circuits 23 of drive circuit 13c, drive circuit 13d, and drive circuit 13f can be connected to the second bus wiring 55. Furthermore, the read circuits 23 of drive circuit 13g, drive circuit 13h, and drive circuit 13i can be connected to the third bus wiring 55.

[0080] Figures 4 to 6 show an example where the wiring 51 connected to selection circuit 21a[1,1] and the wiring 51 connected to selection circuit 21a[1,2] are separated. Similarly, Figures 4 to 6 show an example where the wiring 51 connected to selection circuit 21a[2,1] and the wiring 51 connected to selection circuit 21a[2,2] are separated. As a result, the number of pixels 35 connected to a single wiring 51 can be reduced compared to the case where these wirings 51 are not separated and form a single wiring 51. Therefore, the load on the wiring 51 can be reduced, and the imaging device 10 can be driven at high speed. Note that, for example, selection circuit 21a[1,1] and selection circuit 21a[1,2] may be connected to the same wiring 51, and selection circuit 21a[2,1] and selection circuit 21a[2,2] may be connected to the same wiring 51.

[0081] Similarly, Figures 4 to 6 show an example where the wiring 53 connected to the readout circuit 23a[1,1] and the wiring 53 connected to the readout circuit 23a[2,1] are separated. Also, Figures 4 to 6 show an example where the wiring 53 connected to the readout circuit 23a[1,2] and the wiring 53 connected to the readout circuit 23a[2,2] are separated. As a result, compared to the case where these wirings 53 are not separated and form a single wiring 53, the number of pixels 35 connected to a single wiring 53 can be reduced. Therefore, the load on the wiring 53 can be reduced, and the imaging device 10 can be driven at high speed. Specifically, the readout of imaging data can be performed at high speed. Note that, for example, the readout circuit 23a[1,1] and the readout circuit 23a[2,1] may be connected to the same wiring 53, and the readout circuit 23a[1,2] and the readout circuit 23a[2,2] may be connected to the same wiring 53.

[0082] Furthermore, Figures 4 to 6 show examples in which bus wiring 55[1,1] and bus wiring 55[1,2] are separated, and bus wiring 55[2,1] and bus wiring 55[2,2] are separated. This reduces the number of readout circuits 23 connected to a single bus wiring 55 compared to the case in which these bus wirings 55 are not separated and form a single bus wiring 55. Therefore, the load on the bus wiring 55 is reduced, and the imaging device 10 can be driven at high speed. Note that, for example, readout circuits 23a[1,1] and readout circuits 23a[1,2] may be connected to the same bus wiring 55, and readout circuits 23a[2,1] and readout circuits 23a[2,2] may be connected to the same bus wiring 55.

[0083] The following describes how to drive the drive circuits 13a[1,1] to 13a[2,2]. First, the selection circuit 21 outputs a selection signal SEL to the wiring 51<1>. This selects the pixel 35 connected to the wiring 51<1>. Figure 4 shows an example in which the selection signal SEL is output to the wiring 51<1> connected to selection circuit 21a[1,1], the wiring 51<1> connected to selection circuit 21a[1,2], the wiring 51<1> connected to selection circuit 21a[2,1], and the wiring 51<1> connected to selection circuit 21a[2,2].

[0084] In Figures 4 to 6, a hatching pattern is applied to the selected pixel 35. The imaging device 10 acquires imaging data using the selected pixel 35. Alternatively, the imaging device 10 reads imaging data from the selected pixel 35 using the readout circuit 23a. Thus, as shown in Figure 4, the pixel 35 connected to wiring 51<1> acquires imaging data, or imaging data is read from the pixel 35 connected to wiring 51<1>.

[0085] Next, the selection circuit 21 outputs a selection signal SEL to the wiring 51<2>. As a result, the pixel 35 connected to wiring 51<2> is selected. Figure 5 shows an example in which the selection signal SEL is output to the wiring 51<2> connected to selection circuit 21a[1,1], wiring 51<2> connected to selection circuit 21a[1,2], wiring 51<2> connected to selection circuit 21a[2,1], and wiring 51<2> connected to selection circuit 21a[2,2]. As a result, the pixel 35 connected to wiring 51<2> acquires imaging data. Alternatively, imaging data is read out from the pixel 35 connected to wiring 51<2>.

[0086] As described above, the selection circuit 21 sequentially outputs the selection signal SEL to wiring 51<1> through wiring 51<m>. This allows the selection circuit 21 to sequentially select pixels 35 row by row. Figure 6 shows an example where the selection signal SEL is output to wiring 51<m>, and the pixel 35 connected to wiring 51<m> is selected. As a result, the imaging device 10 can acquire imaging data and read out the acquired imaging data.

[0087] When the imaging device 10 is driven in the driving mode shown in Figure 3A, not only drive circuit 13a, but all of drive circuits 13b to 13i shown in Figure 2 perform the operations shown in Figures 4 to 6. For example, all of drive circuits 13a to 13i can perform the operations shown in Figures 4 to 6 in parallel. When the imaging device 10 is driven in the driving mode shown in Figure 3B, only some of the drive circuits 13a to 13i perform the operations shown in Figures 4 to 6. For example, only drive circuit 13a performs the operations shown in Figures 4 to 6, and the operations of drive circuits 13b to 13i can be stopped by power gating or clock gating. Alternatively, for example, drive circuits 13a to 13d may perform the operations shown in Figures 4 to 6, and the operations of drive circuits 13e to 13i may be stopped by power gating or clock gating.

[0088] As described above, when the imaging device 10 is driven in the drive mode shown in Figure 3B, the power consumption of the imaging device 10 can be reduced compared to when the imaging device 10 is driven in the drive mode shown in Figure 3A by performing power gating or clock gating on some of the drive circuits 13. Furthermore, the power consumption of the imaging device 10 can be reduced compared to when the imaging device 10 is driven in the drive mode shown in Figure 3B without performing power gating or clock gating.

[0089] Here, the operations shown in Figures 4 to 6 can be performed by the control circuit 19 supplying the same control signal, specifically a control signal with the same address information, to all of the circuit blocks 11[1,1] to 11[2,2]. The address information represents the address of the drive circuit 13. Specifically, as described above, the address information represents the address of the drive circuit 13 to be operated. As a result, the drive control of the drive circuit 13 can be performed more easily than when the control circuit 19 supplies control signals with different address information to each of the circuit blocks 11[1,1] to 11[2,2]. Therefore, the imaging device 10 can be driven with low power consumption.

[0090] As described above, in the imaging device 10, the circuit blocks 11[1,1] to 11[2,2] are arranged symmetrically with respect to their respective boundaries. As a result, even when driven in partial imaging mode as shown in Figure 3B, the control circuit 19 can supply the same control signal to multiple drive circuits 13. Therefore, even when the imaging device 10 is driven in partial imaging mode, the drive control of the drive circuits 13 can be easily performed and driven with low power consumption.

[0091] As described above, the control circuit 19 has the function of causing the drive circuit 13 to perform the operations shown in Figures 4 to 6. Specifically, the control circuit 19 has the function of causing some or all of the operations shown in Figures 4 to 6 to be performed by, for example, some of the drive circuits 13a to 13i. The control circuit 19 has the function of causing the selection circuit 21 of the circuit block 11[1,1], the selection circuit 21 of the circuit block 11[1,2], the selection circuit 21 of the circuit block 11[2,1], and the selection circuit 21 of the circuit block 11[2,2], respectively, to simultaneously select pixels 35 having the same address among the pixels 35 of the pixel block 31[1,1], the pixels 35 of the pixel block 31[1,2], the pixels 35 of the pixel block 31[2,1], and the pixels 35 of the pixel block 31[2,2] shown in Figure 1, respectively. Furthermore, the control circuit 19 has the function of acquiring imaging data for some of the pixels 35 in each of the pixel blocks 31[1,1], 31[1,2], 31[2,1], and 31[2,2]. In other words, the control circuit 19 has the function of driving each of the circuit blocks 11[1,1] to 11[2,2] in both the overall imaging mode and the partial imaging mode.

[0092] As described above, the imaging device 10 allows for a larger circuit block 11 while easily controlling its operation, compared to, for example, a case where the circuit block 11 is not divided. It also facilitates the design of the circuit block 11's layout. In particular, the imaging device 10 arranges the circuit blocks 11[1,1] to 11[2,2] in a symmetrical layout with respect to their respective boundaries. This allows for easy control of the circuit blocks 11's operation even when the imaging device 10 is operating in partial imaging mode. Thus, according to one aspect of the present invention, an imaging device with high resolution, low power consumption, and low cost can be provided.

[0093] Figure 7 shows an example in layer 41 shown in Figure 2 in which no input / output circuits 17 are provided in circuit blocks 11[1,1] to 11[2,2], and a control circuit 19 is provided such that it has a region located at the intersection of axis A-B and axis C-D. In the example shown in Figure 7, one input / output circuit 17 is provided outside of circuit blocks 11[1,1] to 11[2,2]. Also in the example shown in Figure 7, a control circuit 19 is provided between circuit blocks 11[1,1] and 11[1,2], and between circuit blocks 11[2,1] and 11[2,2]. Note that multiple input / output circuits 17 may be provided, for example, two may be provided. Also, for example, a control circuit 19 may be provided between circuit blocks 11[1,1] and 11[2,1], and between circuit blocks 11[1,2] and 11[2,2]. The input / output circuit 17 shown in Figure 7 can output, for example, the imaging data read out by the readout circuit 23 of circuit block 11[1,1], the imaging data read out by the readout circuit 23 of circuit block 11[1,2], the imaging data read out by the readout circuit 23 of circuit block 11[2,1], and the imaging data read out by the readout circuit 23 of circuit block 11[2,2] in parallel. Alternatively, the input / output circuit 17 may output this imaging data after, for example, the control circuit 19 has performed a parallel-to-serial conversion.

[0094] When designing the layout of the configuration shown in Figure 7, first, the layout of circuit block 11[1,1] is designed. Next, circuit blocks 11[1,2], circuit block 11[2,1], and circuit block 11[2,2] are laid out symmetrically to circuit block 11[1,1]. After that, the layout of the input / output circuit 17 and the control circuit 19 is designed. By doing the above, the layout of the configuration shown in Figure 7 can be designed.

[0095] If layer 41 is configured as shown in Figure 7, it is not necessary to provide an input / output circuit 17 for each circuit block 11. Furthermore, the control circuit 19 can be installed so as to overlap with the pixels 35 shown in Figure 1. This allows for miniaturization of the imaging device 10. On the other hand, if layer 41 is configured as shown in Figure 2, it is not necessary to design the layout of the input / output circuit 17 separately from the layout design of the circuit block 11. Furthermore, it is not necessary to design the layout of the control circuit 19. As a result, the layout design of the configuration shown in Figure 2 can be performed more easily than the layout design of the configuration shown in Figure 7.

[0096] <Example of Readout Circuit Configuration> Figure 8 shows an example of the configuration of the readout circuit 23. The readout circuit 23 shown in Figure 8 includes a CDS circuit 400, an AD conversion circuit 410, a latch circuit 420, a buffer circuit 430, and a vertical scanning circuit 440. The CDS circuit 400 includes a resistor 401 for voltage conversion, a capacitive element 402 for capacitive coupling, and a reference potential V ０ The device includes a transistor 403 that supplies power, a transistor 404 that maintains the potential supplied to the AD conversion circuit 410, and a capacitive element 405 for maintaining the potential. The AD conversion circuit 410 includes a comparator circuit COMP and a counter circuit COUNTER.

[0097] The CDS circuit 400 has its input connected to wiring 53 and its output connected to the first input terminal of the comparator circuit COMP.

[0098] The potential of wiring 53 is the reset potential V ｒｅｓ When (pixel 35 is in the reset state), the potential of node N (the connection point of transistor 403, transistor 404, and capacitive element 402) is set to the reference potential V. ０ Let's assume that node N is floating, and the potential of wiring 53 is the data potential V. ｄａｔａ When (pixel 35 outputs imaging data), the potential of node N is V ０ +V ｄａｔａ -V ｒｅｓ Therefore, the CDS circuit 400 can subtract the potential in the reset state from the potential of the imaging data output by the pixel 35. Thus, the noise component of the imaging data, which is represented as an analog signal, can be reduced.

[0099] The second input terminal of the comparator circuit COMP of the AD conversion circuit 410 is connected to the ramp signal generation circuit 15. The ramp signal generation circuit 15 generates a ramp signal RAMP. The ramp signal RAMP is a signal that represents the reference potential in AD conversion.

[0100] In the AD conversion circuit 410, the potential of the analog signal mentioned above is compared with the potential of the ramp signal RAMP. Then, the counter circuit COUNTER operates according to the output of the comparator circuit COMP, and a digital signal is output. As a result, AD conversion can be performed on the image data acquired by the pixel 35.

[0101] The latch circuit 420 has the function of temporarily storing the data represented by the digital signal output by the AD conversion circuit 410. A latch signal LAT can be input to the latch circuit 420. The latch circuit 420 can output the stored data to the buffer circuit 430 according to the latch signal LAT. Note that the latch circuit 420 may be omitted.

[0102] The buffer circuit 430 has the function of amplifying the data output from the latch circuit 420 and outputting it to the bus wiring 55. The buffer circuit 430 can be a tristate buffer. Specifically, the buffer circuit 430 can have multiple tristate buffers. By having the buffer circuit 430 in the readout circuit 23, noise to the digital signal output to the bus wiring 55 can be reduced. As a result, the imaging device 10 can perform imaging with higher accuracy than when the buffer circuit 430 is not present. In addition, the potential of the bus wiring 55 can be rapidly transitioned to the potential corresponding to the data output from the latch circuit 420. As a result, the imaging device 10 can be driven at a higher speed than when the buffer circuit 430 is not present. Note that the buffer circuit 430 may be omitted. In this case, the area occupied by the readout circuit 23 can be reduced compared to when the buffer circuit 430 is present.

[0103] The vertical scanning circuit 440 has the function of generating a control signal (buffer control signal) for controlling the drive of the buffer circuit 430. The vertical scanning circuit 440 can supply the buffer control signal to the buffer circuit 430 when a start pulse signal SP is input to it. Based on the buffer control signal, the buffer circuit 430 can sequentially output digital signals from multiple tristate buffers to the bus wiring 55.

[0104] <Example of Pixel Configuration> Figure 9A is a circuit diagram showing an example of the configuration of a pixel 35. The pixel 35 may include a light-receiving element 101, a transistor 103, a transistor 104, a transistor 105, a transistor 106, and a capacitive element 108. A configuration without the capacitive element 108 is also possible. In this specification, the configuration excluding the light-receiving element 101 is sometimes referred to as a pixel circuit.

[0105] One terminal of the light-receiving element 101 (the cathode in the example shown in Figure 9A) is connected to one of the source and drain of transistor 103. The other source and drain of transistor 103 is connected to one of the source and drain of transistor 104. One of the source and drain of transistor 104 is connected to one electrode of the capacitive element 108. One electrode of the capacitive element 108 is connected to the gate of transistor 105. One of the source and drain of transistor 105 is connected to one of the source and drain of transistor 106.

[0106] Here, the wiring connecting the source and drain of transistor 103, one electrode of capacitive element 108, and the gate of transistor 105 is defined as node FD. Node FD can function as a charge detection unit.

[0107] The other terminal of the light-receiving element 101 (the anode in the example shown in Figure 9A) is connected to wiring 121. The gate of transistor 103 is connected to wiring 127. The other source and drain of transistor 104 are connected to wiring 122. The other source and drain of transistor 105 are connected to wiring 123. The gate of transistor 104 is connected to wiring 126. The gate of transistor 106 is connected to wiring 128. The other electrode of the capacitive element 108 is connected to a reference potential line, such as a GND wire. The other source and drain of transistor 106 are connected to wiring 53. Here, wirings 126, 127, and 128 can be included in the wiring 51 shown in Figures 4 to 6. Note that wiring 126 or wiring 127 does not have to be included in wiring 51.

[0108] Wires 121, 122, and 123 can function as power lines. In the configuration shown in Figure 9A, the cathode side of the light-receiving element 101 is connected to the transistor 103, and the node FD is reset to a high potential for operation; therefore, wire 122 is at a high potential (higher than wire 121).

[0109] Figure 9A shows a configuration in which the cathode of the photodetector 101 is connected to node FD, but as shown in Figure 9B, the anode side of the photodetector 101 may be connected to either the source or drain of the transistor 103.

[0110] In this configuration, since the node FD is reset to a low potential for operation, the wiring 122 is set to a low potential (lower than the wiring 121).

[0111] Transistor 103 has the function of controlling the potential of node FD. Transistor 104 has the function of resetting the potential of node FD. Transistor 105 functions as an element of a source follower circuit and can output the potential of node FD as imaging data to wiring 53. Transistor 106 has the function of selecting the pixel to which imaging data is output.

[0112] It is preferable to use transistors (also called OS transistors) with a metal oxide channel formation region for transistors 103 to 106 in the pixel 35. OS transistors have the characteristic of having an extremely low off-current. In particular, by using transistors with a low off-current for transistors 103 and 104, the period during which charge can be held at node FD can be made extremely long. Therefore, a global shutter method can be applied in which charge accumulation operation is performed simultaneously at all pixels without complicating the circuit configuration and driving method.

[0113] In particular, it is preferable to use transistors 103 to 106 that use indium oxide, a form of metal oxide, in the channel-forming region (also called IO transistors). The higher the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor can be. Therefore, by using IO transistors for transistors 103 to 106, the on-current of transistors 103 to 106 can be increased, and the frequency characteristics can be improved. Note that OS transistors other than IO transistors may also be used for transistors 103 to 106.

[0114] <Method of driving the imaging device> Figure 10A is a schematic diagram of the driving method of the rolling shutter type, and Figure 10B is a schematic diagram of the driving method of the global shutter type. Ej represents the exposure (accumulation operation) of the j-th column (j is an integer between 2 and n-1), and Rj represents the readout operation of the j-th column. Figures 10A and 10B show the operation from the first row to the m-th row.

[0115] The rolling shutter method is a driving method that sequentially performs exposure and data readout, overlapping the readout period of one row with the exposure period of another row. Because the readout operation is performed immediately after exposure, imaging can be performed even with a circuit configuration that has a relatively short data retention period. However, since one frame of image is composed of data that is not captured simultaneously, image distortion occurs when imaging moving objects.

[0116] On the other hand, the global shutter method exposes all pixels simultaneously, stores data in each pixel, and reads the data row by row. Therefore, it can obtain distortion-free images even when capturing moving objects.

[0117] When transistors with relatively high off-current, such as silicon transistors (also called Si transistors) with a channel formation region, are used in the pixel circuit, charge tends to flow out from the charge detection unit, so a rolling shutter method is often used. To realize a global shutter method using Si transistors, complex operations such as storing data in a separate memory circuit must be performed at high speed. On the other hand, when OS transistors are used in the pixel circuit, there is almost no charge flow from the charge detection unit, so a global shutter method can be easily realized. It should be noted that an imaging device according to one aspect of the present invention can also be operated in a rolling shutter method.

[0118] Furthermore, the pixel 35 may be configured by any combination of OS transistors and Si transistors. Alternatively, all transistors may be Si transistors.

[0119] <An Example of Pixel Driving Method> Next, an example of a method for driving the pixel 35 shown in Figure 9A will be explained using the timing chart in Figure 11A. In Figure 11A, high potential is indicated by "H" and low potential by "L". The same notation will be used in the timing charts shown below.

[0120] Wiring 121 is always supplied with a low potential, while wirings 122 and 123 are always supplied with a high potential.

[0121] During period T1, if the potential of wiring 126 is set to a high potential, the potential of wiring 127 is set to a high potential, and the potential of wiring 128 is set to a low potential, transistors 103 and 104 conduct, and the high potential of wiring 122 is supplied to node FD (reset operation).

[0122] During period T2, if the potential of wiring 126 is set to a low potential, the potential of wiring 127 to a high potential, and the potential of wiring 128 to a low potential, transistor 104 becomes non-conductive and the supply of reset potential is cut off. In addition, the potential of node FD decreases in accordance with the operation of the photodetector 101 (accumulation operation).

[0123] During period T3, if the potential of wiring 126, wiring 127, and wiring 128 are set to low potential, transistor 103 becomes non-conductive, and the potential of node FD is fixed and held (holding operation). At this time, by using OS transistors with low off-current for transistors 103 and 104 connected to node FD, unnecessary charge outflow from node FD can be suppressed, and the data holding time can be extended.

[0124] During period T4, if the potential of wiring 126 is set to a low potential, the potential of wiring 127 is set to a low potential, and the potential of wiring 128 is set to a high potential, transistor 106 conducts, and the potential of node FD is read to wiring 53 by the source follower operation of transistor 105 (read operation).

[0125] The above is an example of a method for driving the pixel 35 shown in Figure 9A.

[0126] The pixel 35 shown in Figure 9B can be operated according to the timing chart in Figure 11B. Note that wires 121 and 123 are constantly supplied with a high potential, and wire 122 is constantly supplied with a low potential. The basic operation is the same as described in the timing chart in Figure 11A above.

[0127] Figures 12A and 12B show examples in which transistors 103 to 106 shown in Figure 9A have a back gate. Figure 12A shows a configuration in which the back gate is connected to the front gate, which has the effect of increasing the on current. Figure 12B shows a configuration in which the back gate is connected to wiring that can supply a constant potential, and the threshold voltage of the transistor can be controlled by the potential of the back gate.

[0128] Furthermore, a configuration may be used that allows each transistor to operate appropriately, such as by combining Figures 12A and 12B. Also, the pixel 35 may have transistors that do not have a back gate.

[0129] <Example of Imaging Device Configuration 2> Below, we will describe an example of the cross-sectional configuration of the imaging device 10.

[0130] Figure 13 is a cross-sectional view showing an example of the configuration of a pixel 35 in the imaging device 10. The pixel 35 shown in Figure 13 has a layer Lpd on which a light-receiving element 101 is provided, a layer Lta on which transistors 103 and 104 are provided, and a layer Ltb on which transistors 105 and 106 are provided. In Figure 13, an example is shown in which a capacitive element 108 is provided in layer Ltb.

[0131] Layers Lpd, Lta, and Ltb correspond to layer 42 shown in Figure 1. Specifically, layer 42 has layer Lpd, layer Lta, and layer Ltb. Here, a substrate is provided on layer Lpd.

[0132] Figure 13 shows an example in which layer Lta is provided on layer Lpd on which the substrate is provided, and layer Ltb is provided on layer Lta. Here, when applying the configuration shown in Figure 13 to layer 42 shown in Figure 1, the top and bottom can be reversed. That is, the imaging device 10 can have as layer 42 layer Ltb on layer 41, layer Lta on layer Ltb, and layer Lpd on layer Lta.

[0133] One terminal of the light-receiving element 101 (corresponding here to the region in contact with the conductive layer 208_a in the semiconductor region 444) is connected to a conductive layer having a region that functions as one of the source and drain electrodes of the transistor 103, via conductive layers 208_a, 218_a, 246_a, and 248_a. The other terminal of the light-receiving element 101 (corresponding here to the region in contact with the conductive layer 208_a in the semiconductor region 443) is connected to conductive layers 208_a, 218_a, 246_a, 248_a, 208_b, 218_b, 246_b, and 248_b, etc., which have a region that functions as wiring 121.

[0134] A conductive layer having a region that functions as the other of the source electrode and drain electrode of transistor 103, and a region that functions as one of the source electrode and drain electrode of transistor 104, is connected to a conductive layer having a region that functions as the gate electrode of transistor 105 via conductive layers 248_a, 208_b, 218_b, 246_b, and 248_b, etc., which have a region that functions as a node FD. Note that some conductive layers are omitted from the illustration and are shown with thick dashed lines.

[0135] The conductive layer having a region that functions as one of the source and drain electrodes of transistor 105 is connected to conductive layer 248_b, etc., which has a region that functions as wiring 123. The conductive layer having a region that functions as the other of the source and drain electrodes of transistor 104 is connected to conductive layer 248_a, conductive layer 208_b, conductive layer 218_b, conductive layer 246_b, and conductive layer 248_b, etc., which have regions that function as wiring 122. The conductive layer having a region that functions as the other of the source and drain electrodes of transistor 106 is connected to conductive layer 248_b, etc., which has a region that functions as wiring 53.

[0136] The conductive layer having a region that functions as the gate electrode of transistor 103 has a region that functions as wiring 127. The conductive layer having a region that functions as the gate electrode of transistor 104 has a region that functions as wiring 126. The conductive layer having a region that functions as the gate electrode of transistor 106 has a region that functions as wiring 128.

[0137] Here, the conductive layer having a region that functions as wiring 127 and the conductive layer having a region that functions as wiring 126 are each provided in layer Lta, and the conductive layer having a region that functions as wiring 53 is provided in layer Ltb. Therefore, the parasitic capacitance in the region where the conductive layer having a region that functions as wiring 127 and the conductive layer having a region that functions as wiring 126 overlap with the conductive layer having a region that functions as wiring 53 can be reduced. This makes it possible to improve the readout speed of the imaging device 10 and improve the signal-to-noise ratio, etc.

[0138] Here, Figure 13 shows a configuration in which two transistors, transistor 103 and transistor 104, are provided to share one island-shaped semiconductor layer 230_a. That is, a part of the semiconductor layer 230_a functions as the channel formation region for transistor 103, and the other part functions as the channel formation region for transistor 104. In addition, the region between the two channel formation regions of the semiconductor layer 230_a is shared between the other source region or drain region of transistor 103 and the one source region or drain region of transistor 104. Furthermore, Figure 13 shows a configuration in which two transistors, transistor 105 and transistor 106, are provided to share one island-shaped semiconductor layer 230_b. That is, a part of the semiconductor layer 230_b functions as the channel formation region for transistor 105, and the other part functions as the channel formation region for transistor 106. In addition, the region between the two channel formation regions of the semiconductor layer 230_b is shared between the other source region or drain region of transistor 105 and the one source region or drain region of transistor 106.

[0139] In this configuration, where two transistors share one island-shaped semiconductor layer, the area occupied by the transistors can be reduced compared to a configuration where each of the two transistors has its own island-shaped semiconductor layer (i.e., a configuration where one transistor has its own island-shaped semiconductor layer). Alternatively, a configuration where one transistor has its own island-shaped semiconductor layer is also possible.

[0140] Figure 13 shows an example where the configurations of transistors 103 and 104 provided in layer Lta and transistors 105 and 106 provided in layer Ltb are the same. However, the configurations of transistors 103 and 104 and transistors 105 and 106 may be different. Detailed configuration examples of transistors 103 to 106 will be described in Embodiment 2.

[0141] The transistors 103 and 104 provided in layer Lta and the transistors 105 and 106 provided in layer Ltb may have different materials, film thicknesses, lengths, widths, etc. for each component. This may result in different transistor characteristics for the transistors provided in layer Lta and the transistors provided in layer Ltb.

[0142] Figure 13 shows an example in which transistors 103 and 104 are provided in layer Lta, and transistors 105, 106, and the capacitive element 108 are provided in layer Ltb, but the present invention is not limited to this. For example, transistors 103 to 106 and the capacitive element 108 may be provided in layer Lta. In this case, transistors 103 to 106 can be formed in the same process.

[0143] In layer Ltb, an insulating layer 292 is provided so as to cover a conductive layer 248_b having a region that functions as a node FD. A conductive layer 293 is provided on a part of the insulating layer 292. In the region where the conductive layer 248_b having a region that functions as a node FD and the conductive layer 293 overlap each other, the conductive layer 248_b has a region that functions as one terminal (also called one electrode) of the capacitive element 108, the conductive layer 293 has a region that functions as the other terminal (also called the other electrode) of the capacitive element 108, and the insulating layer 292 has a region that functions as a dielectric of the capacitive element 108.

[0144] Here, each of the above conductive layers may be formed of a conductor that functions as a plug or wiring.

[0145] In this specification, a conductor having the function of a plug or wiring may be represented by the same reference numeral for multiple components. Furthermore, the wiring and the plug may be a single integrated unit. That is, a portion of the conductor may function as wiring, and another portion may function as a plug.

[0146] For each plug or wiring, conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used in a single layer or in a laminated manner.

[0147] In particular, it is preferable to use a high-melting-point material that provides both heat resistance and conductivity for each plug or wiring. For example, tungsten or molybdenum can be used as such materials. It is also preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. For example, aluminum or copper can be used as such materials.

[0148] Furthermore, it is preferable to use an insulator made of a high dielectric constant (high-k) material (a material with a high relative permittivity) for the insulating layer 292. By using an insulator made of a high dielectric constant material as the insulating layer 292, sufficient capacitance of the capacitive element 108 can be ensured.

[0149] As an insulator made of high dielectric constant material, for example, oxides, oxide nitrides, nitride oxides, or nitrides containing one or more metallic elements selected from aluminum, hafnium, zirconium, and gallium can be used. These materials may also contain silicon. Furthermore, insulators made of these materials can be used in laminated form.

[0150] Furthermore, as insulators of high dielectric constant materials, for example, aluminum oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, oxides having silicon and zirconium, oxiditrides having silicon and zirconium, oxides having hafnium and zirconium, or oxiditrides having hafnium and zirconium can be used.

[0151] Furthermore, insulators made of the above materials can be used in a laminated form. In this case, it is preferable to use a configuration in which a high dielectric constant material and a material with a greater dielectric strength than the high dielectric constant material are laminated together.

[0152] As such an insulator, for example, an insulator can be used in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order. Alternatively, for example, an insulator can be used in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order. Alternatively, for example, an insulator can be used in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order. By using a laminated insulator with relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic discharge breakdown of the capacitive element having the insulator can be suppressed.

[0153] [Light-receiving element 101] Next, the light-receiving element 101 provided in the Lpd layer will be described.

[0154] As an example, the light-receiving element 101 is a pn junction type photodiode (also called a Si photodiode) formed on a silicon substrate, and has a p-type semiconductor region 443 and an n-type semiconductor region 444 provided on a part of the silicon substrate surface side (upper side in the drawing) of the semiconductor region 443.

[0155] Furthermore, an insulating layer 442 is provided on the surface side of the silicon substrate in an area that does not overlap with the semiconductor region 444. An insulating layer 441 is provided on the semiconductor region 443, the semiconductor region 444, and the insulating layer 442. An insulating layer 447 is provided on the insulating layer 441. In addition, an insulating layer 445 is provided on the back side (bottom side in the drawing) of the silicon substrate.

[0156] The light-receiving element 101 is, for example, an embedded photodiode, and the dark current can be suppressed and noise reduced by a thin p-type semiconductor region 443 provided on the surface side of the silicon substrate of the n-type semiconductor region 444.

[0157] The insulating layer 441 functions as a blocking layer. The insulating layer 442 functions as an element isolation layer. The insulating layer 447 functions as an interlayer insulating film and a planarizing film. The insulating layer 445 has the function of suppressing carrier outflow.

[0158] The insulating layer 442, which functions as an element isolation layer, can be formed using methods such as the LOCOS (Local Oxidation of Silicon) method or the STI (Shallow Trench Isolation) method.

[0159] Grooves for separating pixels are provided on the back side of the silicon substrate, and the insulating layer 445 is provided on the back side of the silicon substrate and in these grooves. The provision of the insulating layer 445 prevents carriers generated in the photodetector 101 from flowing out to adjacent pixels. The insulating layer 445 also has the function of suppressing the intrusion of stray light. Therefore, the insulating layer 445 can suppress color mixing. An anti-reflective film may be provided between the back side of the silicon substrate and the insulating layer 445.

[0160] For each of the above insulating layers, for example, inorganic insulating films such as silicon oxide and silicon nitride, or organic insulating films such as polyimide and acrylic can be used. The insulating layers may also be in a multilayer configuration.

[0161] Figure 14 is a cross-sectional view showing an example of the configuration of the imaging device 10. In addition to the stacked structure shown in Figure 13, Figure 14 shows layer Lp and layer 41. Here, Figure 14 shows an example in which layer 42 is provided on layer 41, similar to Figure 1. That is, layer 42 shown in Figure 14 is the same as layer 42 shown in Figure 13 but inverted vertically. In the imaging device 10 shown in Figure 14, layer Lp is provided on layer 42, specifically on layer Lpd.

[0162] [Layer LOP] Layer LOP comprises a light-shielding layer 451, an optical filter 450, and a microlens array 455. Layer LOP can also be called an optical conversion layer. As shown by the dotted arrow in Figure 14, light incident on the imaging device 10 is irradiated onto the light-receiving element 101 provided in layer Lpd via the microlens array 455 and optical filter 450 of layer LOP.

[0163] The light-shielding layer 451 can suppress the inflow of light to adjacent pixels. The light-shielding layer 451 can be made of a metal layer such as aluminum or tungsten. Alternatively, a dielectric film having the function of an anti-reflective coating may be laminated with the metal layer.

[0164] For example, a color filter can be used for the optical filter 450. The imaging device 10 can obtain a color image by assigning color filters of colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), and M (magenta) to each pixel.

[0165] Furthermore, for example, by using a wavelength cut filter in the optical filter 450, an imaging device can be created that can obtain images in various wavelength ranges.

[0166] For example, if an optical filter 450 that blocks light with a wavelength equal to or less than that of visible light is used, an infrared imaging device can be obtained. Also, for example, if an optical filter 450 that blocks light with a wavelength equal to or less than that of near-infrared light is used, a far-infrared imaging device can be obtained. Further, for example, if an optical filter 450 that blocks light with a wavelength equal to or greater than that of visible light is used, an ultraviolet imaging device can be obtained.

[0167] Additionally, for example, if a scintillator is used for the optical filter 450, an imaging device that can obtain an image visualizing the intensity of radiation used in an X-ray imaging device or the like can be achieved. When radiation such as X-rays that has passed through the subject enters the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, image data can be acquired by detecting the light with the light-receiving element 101. Also, an imaging device with such a configuration may be used for a radiation detector or the like.

[0168] Further, a scintillator includes a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light. As the scintillator, for example, Gd ２ O ２ S:Tb, Gd ２ O ２ S:Pr, Gd ２ O ２ S:Eu, BaFCl:Eu, NaI, CsI, CaF ２ 、BaF ２ 、CeF ３ 、LiF, LiI, ZnO, etc. dispersed in resin or ceramics can be used.

[0169] A microlens array 455 is provided so as to cover the optical filter 450. By providing the microlens array 455, the collected light can be irradiated onto the light-receiving element 101, and thus, efficient photoelectric conversion can be performed in the light-receiving element 101. The microlens array 455 is preferably formed of a resin or glass that has high translucency for visible light.

[0170] [Layer 41] Layer 41 has a transistor 310. The transistor 310 can be used in the imaging device 10 as a transistor constituting the circuit block 11 shown in Figure 1, etc.

[0171] Let me explain transistor 310.

[0172] As shown in Figures 15A and 15B, the transistor 310 is provided on a substrate 311 and includes a conductive layer 316 that functions as a gate electrode, an insulating layer 315 that functions as a gate insulating film, a semiconductor region 313 that functions as a channel forming region, a low-resistance region 314a that functions as either a source region or a drain region, and a low-resistance region 314b that functions as either a source region or a drain region.

[0173] Furthermore, it has an element isolation layer 318 embedded in the substrate 311. The element isolation layer 318 is provided between two adjacent transistors 310.

[0174] For example, a semiconductor substrate can be used as the substrate 311. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Furthermore, there are substrates on which a semiconductor is provided on an insulating substrate, or substrates on which a semiconductor is provided on a conductive substrate. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0175] In this embodiment, the case in which a single-crystal silicon substrate is used as the substrate 311 will be described as an example.

[0176] When a single-crystal silicon substrate is used as the substrate 311, the transistor 310 can be said to be a Si transistor (a transistor containing silicon in the channel formation region).

[0177] The transistor 310 may be either a p-channel or an n-channel type. For example, by connecting the gate of an n-channel transistor 310 to the gate of a p-channel transistor 310, a CMOS circuit (e.g., a complementary circuit, a CMOS logic gate, or a CMOS logic circuit) can be constructed.

[0178] Furthermore, the transistor 310 can have a so-called Fin-type configuration, for example, as shown in Figure 15B, in which the upper surface and side surface in the channel width direction of a semiconductor region 313, which is part of the substrate 311, are covered by a conductive layer 316 via an insulating layer 315. This increases the effective channel width, thereby improving the on-characteristics of the transistor 310. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-characteristics of the transistor 310.

[0179] The transistor 310 preferably contains a semiconductor such as a silicon-based semiconductor in areas such as the region where the channel of the semiconductor region 313 is formed, the region near thereto, the low-resistance region 314a which is one of the source region or drain region, and the low-resistance region 314b which is the other of the source region or drain region, and preferably contains single-crystal silicon. Alternatively, the transistor 310 may be formed from a material having, for example, germanium, silicon-germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 310 may be configured using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, the transistor 310 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide and gallium aluminum arsenide.

[0180] The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0181] As the conductive layer 316, for example, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used. Alternatively, conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0182] Furthermore, since the work function is determined by the conductive material, the threshold voltage of the transistor can be adjusted by selecting the appropriate conductive material.

[0183] It is preferable to use a material such as titanium nitride or tantalum nitride as the conductive layer 316. Furthermore, in order to achieve both conductivity and embedding properties, it is preferable to laminate and use a metal material such as tungsten or aluminum. In particular, in terms of heat resistance, it is preferable to laminate and use tungsten.

[0184] The transistor 310 is covered by a series of insulating layers: insulating layer 320, insulating layer 322, insulating layer 324, and insulating layer 326.

[0185] For insulating layers 320, 322, 324, and 326, it is preferable to use, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, or aluminum nitride. In particular, silicon oxide or silicon oxide nitride is preferred because it is thermally stable.

[0186] In this specification, silicon oxidizride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride refers to a material in which the nitrogen content is greater than the oxygen content. Furthermore, in this specification, aluminum oxidizride refers to a material in which the oxygen content is greater than the nitrogen content, and aluminum nitride refers to a material in which the nitrogen content is greater than the oxygen content.

[0187] The insulating layer 322 may also function as a planarizing film that flattens any steps caused by transistors 310 or the like located beneath it. For example, the upper surface of the insulating layer 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0188] It is preferable to use an insulator as the insulating layer 324 that has barrier properties to prevent impurities such as hydrogen from diffusing from the substrate 311 or transistor 310, etc., located below the insulating layer 324, to the region located above the insulating layer 324.

[0189] As an insulator having barrier properties against hydrogen, for example, silicon nitride formed by chemical vapor deposition (CVD) can be used. Alternatively, metal oxides such as aluminum oxide, hafnium oxide, or tantalum oxide can be used.

[0190] The dielectric constant of the insulating layer 326 is preferably lower than that of the insulating layer 324. For example, the relative permittivity of the insulating layer 326 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of the insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, than that of the relative permittivity of the insulating layer 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0191] A conductive layer 328 (conductive layer 328a and conductive layer 328b) is embedded in the insulating layer 320, insulating layer 322, and insulating layer 324. A conductive layer 330 (conductive layer 330a and conductive layer 330b) is provided on the conductive layer 328 and on the insulating layer 324. Figure 15A shows an example in which a conductive layer 330a is provided on the conductive layer 328a and on the insulating layer 324, and a conductive layer 330b is provided on the conductive layer 328b and on the insulating layer 324. An insulating layer 326 is provided on the conductive layer 330 (conductive layer 330a and conductive layer 330b) and on the insulating layer 324.

[0192] Each of the conductive layers, 328 and 330, functions as a plug or wiring.

[0193] Note that the transistor 310 shown in Figures 15A and 15B is just one example and is not limited to its configuration.

[0194] [Bonding] Next, the bonding of layer Ltb and layer 41 will be explained using Figure 14.

[0195] As described above, the pixels 35 of the imaging device 10 are provided on a silicon substrate, specifically on layer Lpd, which has a light-receiving element 101, on layer Lta, which has transistors 103 and 104, and on layer Ltb, which has transistors 105 and 106. The circuit block 11 and the like are provided on a layer 41 having a transistor 310, which is provided on a substrate 311 separate from the silicon substrate. As shown in Figure 14, the pixels 35 and the circuit block 11 can be connected to each other by bonding layer Ltb and layer 41 together.

[0196] An insulating layer 431 and a conductive layer 432 are provided on the surface of layer Ltb (the lower surface in the drawing). The conductive layer 432 has a region embedded in the insulating layer 431 and the insulating layer 288. The surfaces of the insulating layer 431 and the conductive layer 432 (the lower surface in the drawing) are flattened so that their heights are the same. The conductive layer 432 also has a region in contact with the conductive layer 248_b.

[0197] An insulating layer 433 and a conductive layer 434 are provided on the surface of layer 41 (the upper surface in the drawing). The conductive layer 434 has a region embedded in the insulating layer 433 and the insulating layer 326. The surfaces of the insulating layer 433 and the conductive layer 434 (the upper surface in the drawing) are flattened so that their heights are the same. The conductive layer 434 also has a region in contact with the conductive layer 330.

[0198] Here, it is preferable that the conductive layer 432 and the conductive layer 434 have the same main component metal element. Furthermore, it is preferable that the insulating layer 431 and the insulating layer 433 are composed of the same component.

[0199] For example, the conductive layer 432 and conductive layer 434 can be made of Cu, Al, Sn, Zn, W, Ag, Pt, or Au. Cu, Al, W, or Au are preferred due to their ease of bonding. The insulating layer 431 and insulating layer 433 can be made of silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, titanium nitride, or the like.

[0200] In other words, it is preferable to use the same metal material as described above for both the conductive layer 432 and the conductive layer 434. It is also preferable to use the same insulating material as described above for both the insulating layer 431 and the insulating layer 433. With this configuration, bonding can be performed with the boundary between the surface of layer Ltb (the lower surface in the drawing) and the surface of layer 41 (the upper surface in the drawing) as the bonding position (also called the bonding surface).

[0201] Furthermore, each of the conductive layer 432 and conductive layer 434 may have a multilayer structure of multiple conductive layers, in which case the conductive layers that form the bonding surface may be made of the same metal material. Also, each of the insulating layer 431 and insulating layer 433 may have a multilayer structure of multiple insulating layers, in which case the insulating layers that form the bonding surface may be made of the same insulating material.

[0202] This bonding process allows for the exchange of electrical signals or potential interactions between the conductive layer 432 and the conductive layer 434. Furthermore, it provides a mechanically strong connection between the insulating layer 431 and the insulating layer 433.

[0203] Here, for joining metal layers, a surface activation bonding method can be used, in which oxide films and impurity adsorption layers on the bonding surfaces are removed by sputtering or other methods, and the cleaned and activated bonding surfaces are brought into contact and joined. Alternatively, a diffusion bonding method can be used, in which temperature and pressure are used in combination to join the bonding surfaces. In both cases, bonding occurs at the atomic level, resulting in a mechanically superior bond.

[0204] Furthermore, for joining insulating layers, a hydrophilic joining method can be used, in which the joining surfaces, which have been treated with hydrophilic properties using oxygen plasma or the like to achieve high flatness through polishing, are brought into contact for temporary joining, and then permanent joining is performed by dehydration through heat treatment. Since bonding occurs at the atomic level in the hydrophilic joining method, a mechanically superior bond can be obtained.

[0205] When layer Ltb and layer 41 are bonded together, an insulating layer and a metal layer are present on each bonding surface. For example, a combination of surface activation bonding and hydrophilic bonding can be used.

[0206] For example, a method can be used in which the bonding surface is cleaned after polishing, an anti-oxidation treatment is applied to the bonding surface of the metal layer, and then a hydrophilic treatment is performed before bonding. Alternatively, the bonding surface of the metal layer may be made of a metal that is difficult to oxidize, such as Au, and then a hydrophilic treatment is performed. In addition, bonding methods other than those described above may also be used.

[0207] Through the above bonding process, the conductive layer 248_b of layer Ltb and the conductive layer 330 of layer 41 can be connected to each other via the conductive layers 432 and 434.

[0208] Figure 16 shows a modified version of the configuration shown in Figure 14. The imaging device 10 shown in Figure 16 differs from the imaging device 10 shown in Figure 14 in that the node FD is formed mainly by bonding layer Lta and layer Lpd.

[0209] In the imaging device 10 shown in Figure 16, conductive layers 208_a, 218_a, 246_a, and 248_a have regions that function as wiring 121. In addition, in the imaging device 10 shown in Figure 16, conductive layer 248_a has a region that functions as wiring 122. Furthermore, conductive layer 218_b of layer Ltb and conductive layer 330 of layer 41 are connected to each other via conductive layer 208_b. In the imaging device 10 shown in Figure 16, conductive layers 432 and 434 used for bonding have regions that function as node FD.

[0210] Figure 17 shows a modified configuration of the one shown in Figure 14. The imaging device 10 shown in Figure 17 differs from the imaging device 10 shown in Figure 14 mainly in the configuration of the light-receiving element 101 provided on the LPD layer. It also differs from the imaging device 10 shown in Figure 14 in that no bonding is performed.

[0211] In one aspect of the present invention, instead of a Si photodiode, a photodiode having an organic photoelectric conversion material (also called an organic photodiode) can be used as the light-receiving element 101. The light-receiving element 101 shown in Figure 17 has a conductive layer 411a, a functional layer 412, a photoelectric conversion layer 413, a functional layer 414, and a conductive layer 415.

[0212] As shown in Figure 17, conductive layers 411a and 411b are provided so as to cover a portion of the insulating layer 416 and have regions that are in contact with the conductive layer 248_a through openings provided in the insulating layer 416 and the insulating layer 288. An insulating layer 417 is provided so as to cover the insulating layer 416, the conductive layer 411a, and the conductive layer 411b. The insulating layer 417 has openings that reach the conductive layer 411a in the region that overlaps with the conductive layer 411a. The insulating layer 417 also has openings that reach the conductive layer 411b in the region that overlaps with the conductive layer 411b. Functional layers 412, 413, and 414 are stacked in this order so as to cover at least a portion of the insulating layer 417 and at least a portion of the conductive layer 411a. An insulating layer 418 is provided so as to cover at least a portion of the insulating layer 417, at least a portion of the functional layer 412, at least a portion of the photoelectric conversion layer 413, and at least a portion of the functional layer 414. A conductive layer 415 is provided so as to cover the functional layer 414, the insulating layer 418, and the conductive layer 411b. An insulating layer 419 is provided so as to cover the conductive layer 415.

[0213] The insulating layer 416 can function as a protective film. The insulating layer 417 can have the function of insulating adjacent conductive layers from each other and insulating adjacent light-receiving elements 101 from each other. The insulating layer 418 can function as a protective film. The insulating layer 419 can function as an interlayer insulating film and a planarizing film.

[0214] In the region where the conductive layer 411a, functional layer 412, photoelectric conversion layer 413, functional layer 414, and conductive layer 415 overlap, the conductive layer 411a corresponds to one terminal of the light-receiving element 101, and the conductive layer 415 corresponds to the other terminal of the light-receiving element 101. The conductive layer 411a is connected to one of the source electrode and drain electrode of the transistor 103. The conductive layer 415 is connected to the conductive layer 411b. The conductive layer 415, conductive layer 411b, and conductive layer 248_a have regions that function as wiring 121.

[0215] One of the functional layers 412 and 414 may function as a hole transport layer, and the other of the functional layers 412 and 414 may function as an electron transport layer. One of the conductive layers 411a and 415 may function as a pixel electrode, and the other of the conductive layers 411a and 415 may function as a common electrode.

[0216] For the hole transport layer (one of the functional layer 412 and functional layer 414), for example, molybdenum oxide can be used. For the electron transport layer (the other of the functional layer 412 and functional layer 414), for example, C ６０ , C ７０ Fullerenes such as the above, or their derivatives, can be used.

[0217] As the photoelectric conversion layer 413, a mixed layer of n-type organic semiconductor and p-type organic semiconductor (bulk heterojunction structure) can be used.

[0218] In addition, in the laminated structure shown in Figure 17, bonding is not required.

[0219] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0220] (Embodiment 2) In this embodiment, an example of the transistor configuration of an imaging device according to one aspect of the present invention will be described with reference to the drawings.

[0221] Using Figures 18A to 20C, examples of transistor 200 configurations applicable to each of transistors 103 to 106 will be explained.

[0222] Although the transistor 200 is configured such that each transistor has one island-shaped semiconductor layer, as described above, it may also be configured such that two transistors share one island-shaped semiconductor layer.

[0223] Figure 18A is a plan view of transistor 200. Figure 18B is a cross-sectional view of the area indicated by the dashed line E1-E2 in Figure 18A, and is also a cross-sectional view of transistor 200 in the channel length direction. Figure 18C is a cross-sectional view of the area indicated by the dashed line E3-E4 in Figure 18A, and is also a cross-sectional view of transistor 200 in the channel width direction. Figure 18D is a cross-sectional view of the area indicated by the dashed line E5-E6 in Figure 18A. Note that some elements have been omitted in the plan view of Figure 18A for clarity. Some elements may also be omitted in subsequent plan views.

[0224] The transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0225] In transistor 200, the conductive layer 260 functions as the first gate electrode (also called the upper gate electrode or top gate electrode), and the insulating layer 250 functions as the first gate insulating film. The conductive layer 205 functions as the second gate electrode (also called the lower gate electrode or bottom gate electrode), and the insulating layers 224, 222, and 221 each function as the second gate insulating film. The conductive layer 242a functions as one of the source electrode and drain electrode, and the conductive layer 242b functions as the other of the source electrode and drain electrode.

[0226] In addition, the transistor 200 does not necessarily have a conductive layer 205. In this case, the conductive layer 260 can simply be called a gate electrode, and the insulating layer 250 can simply be called a gate insulating film.

[0227] An insulating layer 275 is provided on the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided on the insulating layer 275. Openings 289 are formed in the insulating layer 280 and the insulating layer 275, reaching the insulating layer 222 and the semiconductor layer 230, and the openings 289 overlap the region between the conductive layer 242a and the conductive layer 242b. In a top view, the side surface of the insulating layer 280 at the opening 289 coincides with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b.

[0228] The insulating layer 250 and the conductive layer 260 are arranged inside the opening 289. An insulating layer 282 is provided in contact with the upper surface of the insulating layer 280, the upper end of the insulating layer 250, and the upper surface of the conductive layer 260. An insulating layer 283 is provided on top of the insulating layer 282. An insulating layer 216 is provided below the insulating layer 221, an insulating layer 214 is provided below the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided below the insulating layer 214. The insulating layers 212, 214, 280, 282, 283, and 285 function as interlayer films.

[0229] Insulating layers 285, 283, 282, 280, and 275 have openings that reach the conductive layer 242a, and the conductive layer 243a and insulating layer 241a are provided within these openings. The insulating layer 241a is provided in contact with the side wall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. In addition, insulating layers 285, 283, 282, 280, and 275 have openings that reach the conductive layer 242b, and the conductive layer 243b and insulating layer 241b are provided within these openings. The insulating layer 241b is provided in contact with the side wall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias connecting wiring etc. provided on the transistor 200 to the source or drain of the transistor 200.

[0230] The semiconductor layer 230 has a channel formation region and a source region and drain region that are provided so as to sandwich the channel formation region in the transistor 200. In other words, the semiconductor layer 230 has a channel formation region, a source region and a drain region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. The source region and the drain region can be swapped with each other. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration compared to the channel formation region. The semiconductor layer 230 may be a single-layer structure or a stacked structure of two or more layers.

[0231] A transistor according to one aspect of the present invention has a semiconductor layer 230 including a channel-forming region, which contains a metal oxide (also called an oxide semiconductor) that functions as a semiconductor. In other words, this transistor can be called an OS transistor. In this specification, a semiconductor layer having an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 has a metal oxide, the semiconductor layer 230 can be referred to as a metal oxide layer.

[0232] OS transistors have oxygen vacancies (V) in the channel formation region of an oxide semiconductor. Ｏ The presence of oxygen vacancies and impurities can easily lead to fluctuations in electrical properties and reduced reliability. Therefore, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of an oxide semiconductor. In other words, it is preferable that the channel formation region in an oxide semiconductor has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0233] Furthermore, if an excess amount of oxygen is supplied to the semiconductor layer 230, electron traps caused by the excess oxygen are formed in the insulating layer 250. As a result, the OS transistor becomes more susceptible to positive drift degradation in +GBT (Gate Bias-Temperature) stress tests. In other words, the amount of positive drift degradation in +GBT stress tests increases.

[0234] Therefore, in one aspect of the present invention, it is preferable that the impurity concentration in the semiconductor layer 230 is low. It is also preferable that an appropriate amount of oxygen is supplied to the semiconductor layer 230. Furthermore, it is preferable to reduce the excess amount of oxygen in the semiconductor layer 230.

[0235] It is preferable to use indium oxide for the semiconductor layer 230. In this case, the semiconductor layer 230 contains indium and oxygen. For example, it is preferable that the semiconductor layer 230 has an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the higher the field-effect mobility of the transistor can be. Therefore, by using indium oxide for the semiconductor layer 230, the transistor can obtain a large on-current and high frequency characteristics.

[0236] Furthermore, it is preferable that the indium oxide film is crystalline. For example, it is preferable that the indium oxide film has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains. In polycrystalline films, crystal grain boundaries can be observed.

[0237] Furthermore, when a metal oxide contains indium and zinc, it may have a CAAC (c-axis aligned crystal) structure. The CAAC structure has fewer grain boundaries in the a-b plane than the polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also known as IZO®) and indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO).

[0238] In a crystalline oxide semiconductor layer, an indium oxide film is a film that allows hydrogen and / or oxygen to move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film that allows hydrogen and / or oxygen to be supplied more easily and expelled more easily than, for example, an IGZO film. Furthermore, it can be said that an indium oxide film is a film with higher permeability to hydrogen and / or oxygen compared to, for example, an IGZO film. In other words, an indium oxide film is a film with lower barrier properties to hydrogen and / or oxygen compared to, for example, an IGZO film.

[0239] Figures 18A to 18D show an example where the semiconductor layer 230 has a single-layer structure. However, the semiconductor layer 230 can have a stacked structure of two or more layers. For example, when the semiconductor layer 230 has a two-layer structure consisting of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide applicable to the semiconductor layer 230 described above (typically indium oxide) as the first semiconductor layer, and a metal oxide whose conduction band lower edge is located on the vacuum level side of the conduction band lower edge of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path (channel). That is, the first semiconductor layer has a channel-forming region on the surface facing the second semiconductor layer and in its vicinity.

[0240] By using the above configuration, the number of carriers trapped at and near the interface of the first semiconductor layer can be reduced. In addition, the channel can be moved away from the surface of the insulating layer 250, thereby reducing the effects of surface scattering. As a result, the field-effect mobility of the transistor can be increased.

[0241] As metal oxides applicable to the second semiconductor layer, for example, indium gallium oxide (In-Ga oxide), In-Zn oxide, indium tin oxide (In-Sn oxide, also called ITO), indium titanium oxide (In-Ti oxide), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), In-Ga-Zn oxide, indium tin zinc oxide (also written as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium tin oxide containing silicon oxide (also called ITSO), etc. can be used. Alternatively, zinc oxide, aluminum zinc oxide (Al-Zn oxide, also written as AZO), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0242] The In-Zn oxide used in the second semiconductor layer can specifically have a composition of In:Zn = 1:1 [atomic ratio] or close to it, In:Zn = 2:1 [atomic ratio] or close to it, or In:Zn = 4:1 [atomic ratio] or close to it. Furthermore, the IGZO used in the second semiconductor layer can specifically have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to it, In:Ga:Zn = 1:3:2 [atomic ratio] or close to it, or In:Ga:Zn = 1:3:4 [atomic ratio] or close to it. Note that "close to" includes a range of plus or minus 30% of the desired atomic ratio.

[0243] For the analysis of the composition of metal oxides, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods may be used for the analysis.

[0244] The crystallinity of the metal oxide in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may include one or more amorphous semiconductors (semiconductors having an amorphous structure), single-crystal semiconductors (semiconductors having a single-crystal structure), or semiconductors having crystalline properties other than single crystals (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors having crystalline regions in part).

[0245] Although not shown in the figures, in the transistor 200, a crystalline portion may be provided on a part of the insulating layer 224, and a semiconductor layer 230 may be provided so as to cover the crystalline portion.

[0246] The crystalline portion contains crystals. The crystalline portion functions as a seed or nucleus when performing a process to enhance the crystallinity of the semiconductor layer 230. In other words, the crystalline portion functions as a seed or nucleus when the semiconductor layer 230 undergoes crystal growth. In this specification, the crystalline portion, or the crystals contained within the crystalline portion, can be rephrased as a seed crystal or a crystal nucleus.

[0247] Here, the indium oxide crystal has a cubic crystal structure (Bixbite type). When indium oxide is used for the semiconductor layer 230, it is preferable that the crystalline portion has, for example, a hexagonal or trigonal crystal structure. In this case, by having a crystal in the crystalline portion whose crystal orientation with respect to the surface of the crystalline portion or the surface to be formed is <001>, a semiconductor layer 230 having a crystal with a crystal orientation of <111> can be formed. When the crystal orientation of the crystal in the crystalline portion with respect to the surface of the crystalline portion or the surface to be formed is <001>, the c-axis of the crystal is perpendicular to the surface of the crystalline portion or the surface to be formed. Note that a hexagonal or trigonal crystal can sometimes be rephrased as a layered crystal, so the above structure can be understood as a structure in which a semiconductor layer 230 having a cubic crystal is formed on a crystalline portion having a layered crystal. That is, it can also be considered as a layered structure fabricated using heteroepitaxial growth technology, or a technology like heteroepitaxial growth.

[0248] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0249] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface or surface on which the film having the crystal is formed. Therefore, for example, a crystal with a crystal orientation of <100> can be said to be a crystal in which the (100) plane is parallel to the surface or surface on which the film having the crystal is formed.

[0250] Specifically, zinc oxide, In-Ga oxide, gallium zinc oxide (also written as Ga-Zn oxide or GZO), Al-Zn oxide, In-Al-Zn oxide, In-Ga-Zn oxide, or In-Sn-Zn oxide can be used as the crystalline portion. It is preferable to use In-Ga-Zn oxide as the crystalline portion. In this case, the crystalline portion contains indium, gallium, zinc, and oxygen. More specifically, it is preferable to have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, or a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close to that. Metal oxides with these compositions are suitable as crystalline portions because they easily form layered structures.

[0251] In-Ga-Zn oxides and In-Sn-Zn oxides, etc., tend to have a CAAC structure. When oxides with a CAAC structure are used in the crystalline portion, the c-axis of the crystal nucleus is perpendicular to the surface of the crystalline portion or the plane on which it is formed. In other words, by using oxides that tend to have a CAAC structure in the crystalline portion, the controllability of the crystal orientation of the crystal nucleus can be improved.

[0252] When an oxide that readily has a CAAC structure is used in the crystalline portion, a semiconductor layer 230 having a crystal with a crystal orientation of <111> can be formed.

[0253] The crystalline portion can also be made of an oxide whose crystal has a cubic structure. By having the crystal of the crystalline portion have the same crystal structure as the crystal of the semiconductor layer 230, the semiconductor layer 230 can be epitaxially grown using the crystalline portion as a nucleus, thereby increasing the crystallinity of the semiconductor layer 230. Note that the crystals of oxides containing group 3 elements in the periodic table tend to have a cubic structure. Furthermore, the group 3 elements in such crystals mainly exist as trivalent cations. Therefore, it is preferable that the crystalline portion has at least one element that can become a trivalent cation. Preferably, the element that can become a trivalent cation in the crystalline portion is scandium, yttrium, cerium, gadolinium, erbium, or ytterbium.

[0254] As the crystalline portion, for example, oxides containing one or both of yttrium and zirconium, erbium oxide, etc., can be used. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0255] Alternatively, indium oxide may be used as the crystalline portion. By using indium oxide as the crystalline portion, the semiconductor layer 230 can be grown homoepitaxially using the crystalline portion as a nucleus, thereby increasing the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystals in the crystalline portion and the crystal orientation of the crystals in the semiconductor layer 230 coincide.

[0256] The materials applicable to the crystalline portion are not particularly limited. The crystalline portion may be made of an insulating material, a semiconductor material, or a conductive material. When a semiconductor material is used as the crystalline portion, the crystalline portion may be considered as part of the semiconductor layer 230.

[0257] The crystal portion, when viewed from above, can be a roughly circular or elliptical shape, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, a star polygon, or a polygon with rounded corners. Furthermore, the crystal portion may have a region extending along the upper surface of the insulating layer 224. Also, the crystal portion may be provided in contact with the upper surface of the insulating layer 224, or it may be provided to fill recesses or openings in the insulating layer 224. Additionally, the transistor 200 may not have a crystal portion. For example, the crystal portion may be provided outside the transistor formation region, and after processing to enhance the crystallinity of the semiconductor layer 230, the crystal portion may be removed.

[0258] Other metal oxides besides indium oxide may be used as the semiconductor layer 230. For example, gallium oxide or zinc oxide may be used. Preferably, the metal oxide contains at least indium (In) or zinc (Zn). Preferably, the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is a metal or metalloid element with a high bond energy with oxygen, for example, a metal or metalloid element with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M present in the metal oxide is gallium, the metal oxide is preferably one or more selected from indium, gallium, and zinc. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0259] Examples of metal oxides that can be used include In-Zn oxide, In-Sn oxide, In-Ti oxide, In-Ga oxide, indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also written as IGTO), Ga-Zn oxide, Al-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, In-Ti-Zn oxide, In-Ga-Zn oxide, indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. Alternatively, ITSO, gallium tin oxide (Ga-Sn oxide), Al-Sn oxide, etc. can be used.

[0260] When a metal oxide is used as the semiconductor layer 230, the band gap of the metal oxide is preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap as the semiconductor layer 230, the off-current of the transistor 200 can be significantly reduced.

[0261] Other materials besides metal oxides may be used as the semiconductor layer 230. Single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used as the semiconductor layer 230, either individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors may also be used. These semiconductor materials may contain impurities as dopants.

[0262] Furthermore, the semiconductor layer 230 may be a semiconductor made of a single element or a compound semiconductor. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0263] When silicon is used as the semiconductor layer 230, examples of silicon that can be used for the semiconductor layer 230 include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As an example of polycrystalline silicon, low-temperature polysilicon (LTPS) can be used.

[0264] A two-dimensional material that functions as a semiconductor may be used as the semiconductor layer 230 of the transistor. Two-dimensional materials are also called layered materials and are a general term for a group of materials that have a layered crystal structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity as the semiconductor layer 230, a transistor with a large on-current can be provided.

[0265] Examples of the above-mentioned layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as the semiconductor layer 230 of a transistor is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ Examples include:

[0266] Figures 19 to 20C show enlarged cross-sectional views of the transistor 200 shown in Figures 18A to 18D in the channel length direction.

[0267] By providing an insulating layer containing excess oxygen near the oxide semiconductor layer and performing heat treatment, oxygen can be supplied from the insulating layer to the oxide semiconductor layer, thereby reducing oxygen deficiency. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface can lead to variations in the transistor's characteristics. In addition, if the amount of oxygen supplied from the insulating layer to the oxide semiconductor layer becomes excessively large, it may adversely affect the transistor's electrical characteristics and reliability. Moreover, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, causing oxidation of these conductive layers and potentially impairing their conductivity.

[0268] First, it is preferable to form at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having the function of capturing or fixing hydrogen near the semiconductor layer 230, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230 and its vicinity.

[0269] It is preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulating layer against hydrogen. It is also preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulating layer against impurities. Furthermore, it is preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulating layer against oxygen. Note that it is not necessarily required to provide all of the insulating layers 212, 214, 221, 222, 275, 282, and 283. If sufficient barrier properties are provided against hydrogen, impurities, oxygen, etc., the insulating layers can be appropriately selected from insulating layers 212, 214, 221, 222, 275, 282, and 283. For example, the insulating layer 214 can be omitted, and the insulating layer 216 and conductive layer 205 can be formed in contact with the upper surface of the insulating layer 212.

[0270] It is preferable that the insulating layers 212, 221, 275, and 283 have a function to suppress hydrogen diffusion. For example, it is preferable to use silicon nitride, which has higher hydrogen barrier properties, for the insulating layers 212, 221, 275, and 283.

[0271] The insulating layers 214, 222, and 282 preferably have the function of capturing or fixing hydrogen. For example, aluminum oxide is preferably used for the insulating layers 214 and 282. Furthermore, for example, hafnium oxide, which is a material with a high dielectric constant (high-k), is preferably used for the insulating layer 222, which functions as a second gate insulating film.

[0272] As shown in Figure 19, by providing an insulating layer 212 having the function of suppressing hydrogen diffusion beneath the transistor 200, the diffusion of hydrogen from the layer below the transistor 200 can be suppressed. Furthermore, by providing an insulating layer 214 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216, etc., can be captured or fixed to the insulating layer 214. This makes it possible to reduce the hydrogen concentration in and near the semiconductor layer 230.

[0273] Furthermore, by providing an insulating layer 221 having the function of suppressing hydrogen diffusion beneath the semiconductor layer 230, the diffusion of hydrogen from below the semiconductor layer 230 can be suppressed. In addition, by providing an insulating layer 222 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224, etc., can be captured or fixed to the insulating layer 222. This makes it possible to reduce the hydrogen concentration in and near the semiconductor layer 230.

[0274] Furthermore, by providing an insulating layer 275, which has the function of suppressing hydrogen diffusion, so as to cover the semiconductor layer 230, conductive layer 242a, conductive layer 242b, etc., the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, conductive layer 242a, conductive layer 242b, etc. can be suppressed.

[0275] Furthermore, by providing an insulating layer 283 having the function of suppressing hydrogen diffusion on the transistor 200, the diffusion of hydrogen from above the transistor 200 can be suppressed. In addition, by providing an insulating layer 282 having the function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280, etc., can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in and near the semiconductor layer 230.

[0276] In this way, by surrounding the transistor 200 with a barrier insulating layer against hydrogen, the diffusion of hydrogen into the oxide semiconductor can be suppressed, and the hydrogen concentration in the channel formation region can be reduced. This improves the electrical characteristics and reliability of the transistor 200.

[0277] Furthermore, it is preferable to include excess oxygen in the insulating layer 280. By supplying this oxygen to the semiconductor layer 230 via the insulating layer 250 through heat treatment, oxygen deficiencies in the channel formation region can be reduced.

[0278] The insulating layer 282 is preferably formed using a sputtering method in an atmosphere containing oxygen gas. This allows oxygen to be added to the insulating layer 280. The insulating layer 282 may be a single layer or a laminated structure of two or more layers.

[0279] As described above, by performing a heat treatment on the insulating layer 280, which contains excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 via the insulating layer 250. In this heat treatment, insulating layers 282 and 283, which have barrier properties against oxygen, are formed on the insulating layer 280, so it is possible to prevent excess oxygen contained in the insulating layer 280 from diffusing out of the insulating layer 280. Furthermore, since an insulating layer 275, which has barrier properties against oxygen, is formed between the insulating layer 280 and the semiconductor layer 230, conductive layer 242a, and conductive layer 242b, it is possible to prevent excess oxygen contained in the insulating layer 280 from diffusing out of the insulating layer 280. In addition, by performing the heat treatment with openings formed in a part of the insulating layer 280, insulating layer 282, and insulating layer 283, it is also possible to diffuse a portion of the oxygen contained in the insulating layer 280 outward and adjust the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230.

[0280] Figure 19 shows an example where the semiconductor layer 230 has a single-layer structure. However, the semiconductor layer 230 can have a stacked structure of two or more layers. As shown in Figure 20A, the semiconductor layer 230 can have a two-layer structure consisting of semiconductor layer 230_1 and semiconductor layer 230_2 on top of semiconductor layer 230_1.

[0281] Although Figure 20A illustrates a configuration in which the insulating layer 250 is in contact with the upper surface of the semiconductor layer 230_2, the present invention is not limited to this configuration. For example, as shown in Figure 20B, it is possible to remove the semiconductor layer 230_2 in the region overlapping with the opening 289, so that the insulating layer 250 is in contact with the side surface of the semiconductor layer 230_2 and the upper surface of the semiconductor layer 230_1. With such a configuration, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, the electric field from the gate electrode can be suitably applied to the semiconductor layer 230_1.

[0282] It is preferable that the insulating layer 250 is configured to allow oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230, and to suppress oxidation of the conductive layer 242a, conductive layer 242b, and conductive layer 260.

[0283] The insulating layer 250 is formed within the opening 289 in contact with the upper surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and upper surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0284] Figure 18B shows an example where the insulating layer 250 has a single-layer structure. However, the insulating layer 250 can have a laminated structure of two or more layers. In this case, it is preferable that the insulating layer 250 is formed from two or more types of films. By making the insulating layer 250 from two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of functions that the insulating layer 250 may have include the function of extracting excess oxygen from the semiconductor layer 230, the function of extracting hydrogen from the semiconductor layer 230, and the function of suppressing the diffusion of hydrogen into the semiconductor layer 230.

[0285] For example, as shown in Figure 19, the insulating layer 250 preferably has a laminated structure consisting of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 on the insulating layer 250_1, and an insulating layer 250_3 on the insulating layer 250_2.

[0286] As the insulating layer 250_1, any material applicable to the insulating layer 250 described above can be used. For example, if the insulating layer 250_1, which has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has the function of capturing or fixing oxygen, oxidation of the side surfaces of the conductive layer 242a and the conductive layer 242b and the formation of an oxide film on those sides can be suppressed. This can suppress a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Furthermore, with this configuration, the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the semiconductor layer 230, and oxygen deficiency in the channel formation region of the semiconductor layer 230 can be reduced.

[0287] Furthermore, by providing insulating layer 250_1 between insulating layer 280 and insulating layer 250_2, and between insulating layer 250_2 and semiconductor layer 230, it is possible to suppress the excessive supply of oxygen from insulating layer 280 to semiconductor layer 230 and supply an appropriate amount of oxygen to semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, thereby preventing excessive positive shift of transistor 200 and improving reliability. In addition, it is possible to suppress excessive oxidation of the source region and drain region, which can cause a decrease in the on-current of transistor 200 or a decrease in field-effect mobility.

[0288] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Vth is defined as 1nA (1 × 10⁻¹⁶). −９ A) is defined as the current value, and Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is normalized. The normalized drain current (Id) is defined as the current value × the channel width (W) of the transistor / the channel length (L) of the transistor. Vsh is the tangent to the maximum slope of the logarithmically represented drain current (Id) in the Id-Vg characteristic of the transistor and 1 pA (1 × 10⁻¹⁰). −１２ A) The gate voltage (Vg) at the intersection with the axis, or 1 pA (1 × 10) in the Id-Vg characteristic of the transistor. −１２ This is the gate voltage (Vg) at which the axis of A) intersects with the line (tangent) extrapolated from the two points where the slope of log(Id) is maximum. For example, if either Vth and Vsh, or both, are zero or positive, it can be considered a normally-off transistor.

[0289] By adopting the above configuration, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a transistor with good electrical characteristics. Furthermore, with the above configuration, good electrical characteristics can be maintained even when the transistor is miniaturized or highly integrated. In addition, high-frequency characteristics can be improved by miniaturizing the transistor 200. Specifically, the cutoff frequency can be improved.

[0290] Furthermore, a material with a high dielectric constant (high-k) can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulating layer 250_1, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating film. Additionally, it becomes possible to thin the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating film.

[0291] Therefore, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide is preferable because an amorphous film can be formed relatively easily using the ALD method. Aluminum oxide can be suitably used as the insulating layer 250_1 because it has the function of capturing or fixing oxygen and hydrogen. Alternatively, hafnium oxide can be suitably used as the insulating layer 250_1 because it has a high function of capturing or fixing oxygen and hydrogen.

[0292] For example, it is preferable to use a material with a low dielectric constant as the insulating layer 250_2. For example, it is preferable that the insulating layer 250_2 has a silicon oxide film or a silicon oxynitride film.

[0293] Furthermore, silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the leakage current of the transistor. Also, the silicon oxide film or silicon oxynitride film is a film with high hydrogen permeability. Therefore, the insulating layer 250 may be a three-layer structure consisting of insulating layer 250_2, insulating layer 250_1 on insulating layer 250_2, and insulating layer 250_3 on insulating layer 250_1. With this configuration, hydrogen in the semiconductor layer 230 can diffuse to insulating layer 250_1 via insulating layer 250_2, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0294] The insulating layer 250_3 preferably has barrier properties against hydrogen. This configuration suppresses the diffusion of hydrogen into the semiconductor layer 230. Furthermore, the insulating layer 250_3 preferably has barrier properties against oxygen. The insulating layer 250_3 is provided between the channel-forming region of the semiconductor layer 230 and the conductive layer 260. This configuration suppresses the diffusion of oxygen contained in the channel-forming region of the semiconductor layer 230 into the conductive layer 260, preventing the formation of oxygen vacancies in the channel-forming region of the semiconductor layer 230. It also suppresses the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260, preventing the conductive layer 260 from oxidizing. The insulating layer 250_3 preferably has less oxygen permeability than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function to suppress the diffusion of hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0295] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side. Furthermore, the film thicknesses of the hafnium oxide film, silicon oxide film, and silicon nitride film can be set to 2 nm, 2 nm, and 1 nm, respectively. This configuration allows excess oxygen in the semiconductor layer 230 to be discharged into the insulating layer 250, reducing the amount of excess oxygen in the semiconductor layer 230. Additionally, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Alternatively, the insulating layer 250 can also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side.

[0296] Furthermore, as shown in Figure 20C, a structure in which an insulating layer 250_4 is provided on top of the insulating layer 250_2 may also be used. As the insulating layer 250_4, an insulating material applicable to the insulating layer 250_1 can be used. For example, by providing an insulating layer 250_4 having the function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2, etc., can be captured or fixed.

[0297] Preferably, the insulating layer 250 has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the semiconductor layer 230 side. With this configuration, hydrogen in the semiconductor layer 230 diffuses into insulating layer 250_1 or insulating layer 250_4, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0298] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also called the S value) can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0299] Furthermore, the film thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. It is preferable that each layer constituting the insulating layer 250 has at least a portion of the above-mentioned film thickness region.

[0300] In addition, the insulating layer 250 has a four-layer structure, and the insulating layer 250_3 may be omitted. For example, insulating layer 250_1 can be an insulating layer having the function of capturing or fixing oxygen, insulating layer 250_2 can be an insulating layer having a low dielectric constant, and insulating layer 250_4 can be an insulating layer having the function of capturing or fixing hydrogen. Specifically, the insulating layer 250 can be a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in that order from the semiconductor layer 230 side.

[0301] To make the thickness of insulating layers 250_1 to 250_4 as described above, it is preferable to use the ALD method for film formation. Furthermore, to form insulating layers 250_1 to 250_4 with good coverage within the opening 289, it is preferable to use the ALD method for film formation.

[0302] Furthermore, in forming the insulating layer 250 having a laminated structure of multiple insulating films, it is preferable to use the ALD process two or more times. For example, it is preferable that two or more of the multiple insulating films of the insulating layer 250 are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and uniformity of the film thickness of the insulating layer 250 can be improved. In addition, productivity can be increased by continuously forming, for example, two or more insulating films using the ALD process.

[0303] In addition, although the above describes a configuration in which the insulating layer 250 has a three-layer or four-layer structure, the present invention is not limited to these. The insulating layer 250 can have a configuration having at least one of insulating layers 250_1 to 250_4. By configuring the insulating layer 250 with one, two, or three layers from insulating layers 250_1 to 250_4, the transistor manufacturing process can be simplified and productivity can be improved.

[0304] The conductive layer 205 is arranged to overlap with the semiconductor layer 230 and the conductive layer 260. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. Furthermore, it is preferable that the conductive layer 205 extends in the channel width direction, as shown in Figures 18A and 18C. With this configuration, when multiple transistors are provided, the conductive layer 205 functions as wiring.

[0305] As shown in Figure 19, it is preferable that the conductive layer 205 has conductive layer 205_1 and conductive layer 205_2. Conductive layer 205_1 is provided in contact with the bottom surface and side wall of the opening. Conductive layer 205_2 is provided so as to fill the recess of conductive layer 205_1 formed along the opening. Here, the height of the upper surface of conductive layer 205 is the same as the height of the upper surface of insulating layer 216.

[0306] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, it is preferable to have a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0307] By using a conductive material having the function of reducing hydrogen diffusion in the conductive layer 205_1, it is possible to prevent impurities such as hydrogen contained in the conductive layer 205_2 from diffusing into the semiconductor layer 230 via the insulating layer 216, etc. Furthermore, by using a conductive material having the function of suppressing oxygen diffusion in the conductive layer 205_1, it is possible to suppress oxidation of the conductive layer 205_2 and a decrease in conductivity. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can be a single-layer structure or a laminated structure of the above conductive material. For example, it is preferable that the conductive layer 205_1 has titanium nitride.

[0308] Furthermore, it is preferable to use a highly conductive material for the conductive layer 205_2. For example, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductive layer 205_2. For example, it is preferable that the conductive layer 205_2 contains tungsten.

[0309] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductive layer 205, without linking it to the potential applied to the conductive layer 260. In particular, by applying a negative potential to the conductive layer 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductive layer 205 reduces the drain current when the potential applied to the conductive layer 260 is 0V compared to not applying a negative potential.

[0310] Although Figure 19 shows a laminated structure of conductive layer 205_1 and conductive layer 205_2, the present invention is not limited to this, and the conductive layer 205 may be a single layer or a laminated structure of three or more layers. For example, conductive layer 205_1 may be a two-layer structure of a tantalum nitride film and a titanium nitride film on the tantalum nitride film, and conductive layer 205_2 having a tungsten film may be provided on top of conductive layer 205_1. With such a configuration, it is possible to suppress the diffusion of impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 into the conductive layer 205.

[0311] The insulating layer 224 functions as a second gate insulating film together with the insulating layers 221 and 222.

[0312] The insulating layer 224 preferably has, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen deficiency. The insulating layer 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, but may have a laminated structure made of different materials.

[0313] Furthermore, it is preferable to process the insulating layer 224 in an island-like manner, similar to the semiconductor layer 230. This ensures that when multiple transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 is approximately the same. Therefore, variations in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0314] Furthermore, by arranging the insulating layer 224 in an island-like configuration, at least a portion of the lower surface of the conductive layer 260 can be positioned below the lower surface of the semiconductor layer 230 (see Figure 18C). This allows the conductive layer 260 to be positioned opposite the upper and side surfaces of the semiconductor layer 230, thereby enabling the electric field of the conductive layer 260 to act on the upper and side surfaces of the semiconductor layer 230.

[0315] However, although not shown in the diagram, the insulating layer 224 does not necessarily have to be processed into island shapes. When multiple transistors are provided on the same substrate, by forming the insulating layer 224 without processing it into island shapes, the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This reduces variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0316] It is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen as conductive layers 242a and 242b, respectively. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 242a and 242b.

[0317] For the conductive layers 242a and 242b, it is preferable to use metal nitrides, such as tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, tantalum and aluminum nitrides, and titanium and aluminum nitrides. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, ITO, ITSO, In-Zn oxide, etc., may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0318] Furthermore, conductive layers 242a and 242b may each be arranged in a laminated structure. In this case, it is preferable to use the above-mentioned conductive material in the lower layer (the layer with a large contact area with the semiconductor layer 230) of conductive layers 242a and 242b, and to use a conductive material with higher conductivity in the upper layer of conductive layers 242a and 242b. For example, tantalum nitride can be used for the lower layer and tungsten for the upper layer. Alternatively, for example, ITO or ITSO can be used for the lower layer and tungsten for the upper layer.

[0319] The conductive layer 260 is provided within the opening 289, via the insulating layer 250, to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side surface and upper surface of the semiconductor layer 230. Furthermore, the height of the upper surface of the conductive layer 260 coincides with the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0320] The side walls of the opening 289 may be perpendicular to the upper surface of the insulating layer 222, or they may be tapered. By making the side walls tapered, the coverage of the insulating layer 250 provided in the opening 289 is improved, and defects such as porosity can be reduced.

[0321] The conductive layer 260 is preferably provided extending in the channel width direction, as shown in Figures 18A and 18C. With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

[0322] As shown in Figure 18C, in a cross-sectional view of the transistor 200 in the channel width direction, there may be a curved surface between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the edges of the side surface and the edges of the top surface may be curved.

[0323] As shown in Figure 19, it is preferable to have a two-layer structure for the conductive layer 260. Here, it is preferable that the conductive layer 260 has a conductive layer 260_1 and a conductive layer 260_2 disposed on top of conductive layer 260_1. For example, it is preferable that conductive layer 260_1 is arranged to enclose the bottom and sides of conductive layer 260_2.

[0324] For example, it is preferable to use titanium nitride as conductive layer 260_1 and tungsten as conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride as conductive layer 260_1 and copper as conductive layer 260_2. By using such a configuration, the conductivity of conductive layer 260 can be increased.

[0325] Furthermore, the conductive layer 260 may have a laminated structure of three or more layers. For example, the conductive layer 260 may have a three-layer structure consisting of a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0326] It is preferable that the insulating layer 216, insulating layer 280, and insulating layer 285 each have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0327] The insulating layers 216, 280, and 285 can be made of materials with low dielectric constants, for example. Silicon oxide and silicon oxide nitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide nitride, and silicon oxide with vacancies are also preferred because they can easily form regions containing excess oxygen.

[0328] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may be flattened.

[0329] It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0330] The conductive layers 243a and 243b are preferably made of conductive materials mainly composed of, for example, tungsten, copper, or aluminum. Furthermore, the conductive layers 243a and 243b may be arranged in a laminated structure.

[0331] For example, as shown in Figure 19, the conductive layer 243a and conductive layer 243b may be arranged in a two-layer laminated structure. Conductive layer 243a has a conductive layer 243a1 formed along the opening and a conductive layer 243a2 formed inside conductive layer 243a1. Conductive layer 243b has a conductive layer 243b1 formed along the opening and a conductive layer 243b2 formed inside conductive layer 243b1.

[0332] The conductive layers 243a1 and 243b1 can be formed as single layers or in a laminated configuration using a conductive material applicable to conductive layer 205_1. By providing conductive layers 243a1 and 243b1, it is possible to suppress the incorporation of impurities such as water and hydrogen into the semiconductor layer 230 through conductive layers 243a2 and 243b2. Conductive layers 243a2 and 243b2 can use conductive materials applicable to conductive layers 243a and 243b described above.

[0333] Furthermore, as shown in Figure 18B, the height of the upper surfaces of conductive layers 243a and 243b is the same as the height of the upper surface of the insulating layer 285. Also, as shown in Figure 19, the lower part of conductive layer 243a may be formed to be embedded in conductive layer 242a. Similarly, the lower part of conductive layer 243b may be formed to be embedded in conductive layer 242b.

[0334] As insulating layers 241a and 241b, barrier insulating layers applicable to insulating layer 275, etc., can be used. For example, silicon nitride can be used as insulating layer 241a and insulating layer 241b. Insulating layers 241a and 241b are provided in contact with insulating layer 285, insulating layer 283, insulating layer 282, and insulating layer 275. This prevents impurities such as water and hydrogen contained in insulating layer 280, etc., from mixing into semiconductor layer 230 through conductive layer 243a and conductive layer 243b. Silicon nitride is particularly suitable because of its high barrier properties against hydrogen. In addition, it is possible to prevent oxygen contained in insulating layer 280 from being absorbed by conductive layer 243a and conductive layer 243b.

[0335] Furthermore, the insulating layer 241a and the insulating layer 241b may be in a laminated structure. In this case, it is preferable that the first insulating layer in contact with the side wall of the opening such as the insulating layer 280 and the second insulating layer inside it use a combination of an oxygen barrier insulating layer and a hydrogen barrier insulating layer.

[0336] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0337] (Embodiment 3) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in an imaging device according to one aspect of the present invention.

[0338] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0339] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0340] This section describes the carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO. Figure 21A shows silicon (Si) and indium oxide (InO2). Ｘ Figure 21B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0341] First, as indicated by the arrows in Figure 21B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 21A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 21A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 21A.

[0342] In Figure 21A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0343] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0344] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0345] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0346] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain can form in the source and drain regions due to stress on the electrodes in contact with IGZO, sometimes resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 21A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0347] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0348] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using a single-crystal film, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, it offers excellent effects such as suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0349] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0350] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0351] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0352] The channel formation region refers to the region within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0353] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and other elements may be present in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above-mentioned impurities.

[0354] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0355] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0356] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 21C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. Ｏ If oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0357] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0358] Furthermore, as shown in Figure 21C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２It is released as ) or, by reacting with oxygen contained in the membrane, it is released as water molecules.

[0359] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0360] Table 1 shows single crystal indium oxide (here, In ２ O ３ The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0361]

[0362] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0363] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0364] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0365] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0366] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ There are mold structures and their modified mold structures, etc. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ Examples of crystals having a type structure include IGZO.

[0367] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0368] (Embodiment 4) In this embodiment, an example of a package containing an image sensor chip and a camera module will be described. The image sensor chip can use the configuration of an imaging device according to one aspect of the present invention. An example of an electronic device that can use the imaging device according to one aspect of the present invention will also be described.

[0369] <Package and Camera Module> Figure 22A is an external perspective view of the package containing the image sensor chip. The package is a CSP (Chip Size Package) and includes a bare image sensor chip 850, a cover glass 840, and an adhesive 830 that bonds the two together.

[0370] The electrode pads 825, located on the outside of the pixel array 855, are connected to the back electrode 815 via through-electrodes 820. The electrode pads 825 are connected to the circuitry constituting the image sensor by wiring or wires. The bare chip 850 may also be a stacked chip stacked with circuits having various functions.

[0371] Figure 22A illustrates a BGA (Ball Grid Array) in which bumps 810 are formed on the back electrode 815 with solder balls. Note that the configuration is not limited to BGA; LGA (Land Grid Array) or PGA (Pin Grid Array) may also be used. Alternatively, a package in which the bare chip 850 is mounted on a QFN (Quad Flat No-Lead Package) or QFP (Quad Flat Package) may be used.

[0372] Figure 22B is a perspective view of the top surface of a camera module combining an image sensor chip and a lens. The camera module has a lens cover 860 and multiple lenses 870, etc., in addition to the configuration shown in Figure 22A. An optical filter 880 that absorbs light of a specific wavelength is provided between the lens 870 and the cover glass 840 as needed. For example, in the case of an image sensor that mainly captures visible light, an infrared cut filter or the like can be used as the optical filter 880.

[0373] By housing the image sensor chip in the type of package described above, mounting it onto printed circuit boards and other devices becomes easier, allowing the image sensor chip to be incorporated into various semiconductor devices and electronic equipment.

[0374] <Electronic Devices> Examples of electronic devices that can use the imaging device according to one aspect of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game consoles including portable ones, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), photocopiers, facsimile machines, printers, automated teller machines (ATMs), vending machines, and the like. By using the imaging device according to one aspect of the present invention in these electronic devices, high-resolution images can be acquired. Furthermore, the electronic devices can be operated at high speed. Furthermore, the electronic devices can be miniaturized. Specific examples of these electronic devices are shown in Figures 23A to 23F.

[0375] Figure 23A shows an example of a mobile phone, which includes a housing 981, a display unit 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone is equipped with a touch sensor on the display unit 982. All operations, such as making a phone call or entering text, can be performed by touching the display unit 982 with a finger or stylus. An imaging device according to one aspect of the present invention can be applied to this mobile phone.

[0376] Figure 23B shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Information can be input and output using the touch panel function of the display unit 912. In addition, characters can be recognized from images acquired by the camera 919, and these characters can be output as sound by the speaker 913. An imaging device according to one embodiment of the present invention can be applied to this portable data terminal.

[0377] Figure 23C shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light-emitting unit 967, a lens 965, and the like. An imaging device according to one embodiment of the present invention can be applied to this digital camera.

[0378] Figure 23D shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, a camera 939, and the like. The display unit 932 is equipped with a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and have excellent wearability on the body. An imaging device according to one embodiment of the present invention can be applied to this information terminal.

[0379] Figure 23E shows a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. The camera unit 952 is equipped with a rotation mechanism, etc., and when installed on the ceiling, it is possible to capture images of the entire surroundings. An imaging device according to one embodiment of the present invention can be applied to the elements for image acquisition in this camera unit. Note that "surveillance camera" is a conventional name and does not limit its use. For example, a device that functions as a surveillance camera is also called a camera or video camera.

[0380] Figure 23F shows a drive recorder, which includes a frame 941, a camera 942, operation buttons 943, mounting parts 944, etc. By installing it on the front windshield of a car via the mounting parts 944, it can record the scenery ahead while driving. A display panel for showing the recorded image is provided on the back side (not shown). An imaging device according to one embodiment of the present invention can be applied to the camera 942.

[0381] Figure 24A shows a drone, which is an example of a mobile device, and has a frame 921, arms 922, rotor 923, blades 924, camera 925, and battery 926, and has the function of autonomous flight and the function of hovering in the air. An imaging device according to one aspect of the present invention can be applied to the camera 925.

[0382] Figure 24B shows an external view of an automobile as an example of a mobile vehicle. The automobile 890 has multiple cameras 891, etc., and can acquire information from the front, rear, left, right, and above of the automobile 890. An imaging device according to one embodiment of the present invention can be applied to the cameras 891. The automobile 890 is also equipped with various sensors (not shown), such as infrared radar, millimeter-wave radar, and laser radar. The automobile 890 analyzes the images acquired by the cameras 891 for multiple imaging directions 892, determines the surrounding traffic conditions, such as the presence or absence of guardrails or pedestrians, and can perform autonomous driving. It can also be used in systems that perform road guidance, hazard prediction, etc.

[0383] In one embodiment of the present invention, the image imaging device can perform computational processing such as a neural network on the obtained image data, which can then perform processes such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (widening the dynamic range), image restoration of a lensless image sensor, positioning, character recognition, and reduction of reflections.

[0384] In the above, the term "automobile" may refer to any type of vehicle, such as an automobile with an internal combustion engine, an electric vehicle, or a hydrogen vehicle. Furthermore, the term "mobile body" is not limited to automobiles. For example, other examples of mobile bodies include trains, monorails, ships, and aircraft (helicopters, unmanned aerial vehicles, airplanes, rockets). By applying a computer according to one aspect of the present invention to these mobile bodies, a system utilizing artificial intelligence can be provided.

[0385] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0386] (Notes regarding the description in this specification, etc.) The above embodiments and descriptions of each component in the embodiments are provided below.

[0387] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" means, for example, that A and B are connected without the use of a circuit element (e.g., a transistor or a switch; however, wiring is not a circuit element) between them. On the other hand, "A and B are indirectly connected" means, for example, that A and B are connected through one or more circuit elements.

[0388] Here, when we define "A and B are indirectly connected," it refers to the following connection relationship, as an example: That is, assuming the circuit is operating, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then such a circuit can be defined as having "A and B indirectly connected" as a physical object. Even if there are times when no electrical signals are exchanged or potential interactions occur between A and B, if there are times during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined as having "A and B indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as a physical object. Therefore, for example, even if no power supply voltage is supplied to the circuit and the circuit is not operating, the circuit can be defined as having "A and B indirectly connected" as a physical object (however, as an example, this is limited to cases where, when power supply voltage is supplied to the circuit and the circuit is operating, electrical signals are exchanged or potential interactions occur between A and B during the circuit's operation).

[0389] The following are specific examples of "indirect connections". First, an example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in Figures 25A1 and 25A2. Another example of a case where "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected", assuming the circuit is operating, one transistor between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. Note that when "A and B are indirectly connected", this includes cases where one transistor between A and B is in an OFF state or a non-conducting state. When "A and B are indirectly connected" and multiple transistors are connected between A and B, assuming the circuit is operating, each of the multiple transistors between A and B will be in an ON state, conducting state, or a state in which current can flow at least once. In other words, when "A and B are indirectly connected," it is not necessary for all of the transistors to be in an ON state, a conducting state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it includes cases where the transistors between A and B are in an OFF state or a non-conducting state at the same time or at different times. As another example, as shown in Figure 25A3, when A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be discussed later, if a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected," or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0390] Having shown examples of cases where a connection can be considered "indirect" and cases where it cannot, let's look at another example of a case where a connection cannot be considered "indirect." Even if electrical signals are exchanged or potential interactions occur between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of when A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in Figure 25A4. Another example of when A and B are connected via an insulator is when a transistor gate insulating film or the like is interposed between A and B, as shown in Figure 25A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0391] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when there is no timing for the exchange of electrical signals or potential interaction between A and B. For example, as shown in Figures 25A6 and 25A7, multiple transistors are connected via sources and drains in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power source or GND, etc. In this case, it cannot be said that "A and B are indirectly connected," but it can be said that "A and V are indirectly connected," or "B and V are indirectly connected." In Figure 25A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from the power supply or GND, then the connection relationship is the same as in Figures 25A6 and 25A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0392] As shown above, we have provided an example of "indirect connection." As an example, the provisions for "indirect connection" are included in the provisions for "electrical connection," so if "A and B are indirectly connected," then "A and B are electrically connected."

[0393] Next, we will show specific examples of "direct connection." Examples of cases where "A and B are directly connected" include cases where A and B are connected without a circuit element in between, as shown in Figures 25B1, 25B2, and 25B3. Furthermore, as shown in Figures 25B4 and 25B5, when A and B are connected to a power supply that provides a constant potential V, or to GND, etc., without a circuit element in between, we can say that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Furthermore, as shown in Figure 25B6, even when A (or B) is connected to a constant potential V via the source and drain of a transistor, we can say that "A and B are directly connected." Furthermore, since A and V, or B and V, are connected via the source and drain of a transistor, they cannot be said to be directly connected, and we can say that "A and V are indirectly connected," or "B and V are indirectly connected."

[0394] As shown above, an example of "direct connection" has been given, but as an example, since the provisions for "direct connection" are included in the provisions for "electrical connection," if "A and B are directly connected," then "A and B are electrically connected."

[0395] Even if independent components are shown connected in a circuit diagram, a single component may possess the functions of multiple components. For example, if part of a wire also functions as an electrode, a single conductive film possesses the functions of both the wire and the electrode. Therefore, the term "connection" in this specification includes cases where a single conductive film possesses the functions of multiple components.

[0396] Furthermore, in this specification, the term "resistive element" can refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor, diode, or coil through which current flows from drain to source. Therefore, the term "resistive element" can be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistive element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Also, for example, 1 Ω or more and 1 × 10 ９ It may also be less than or equal to Ω.

[0397] Furthermore, when wiring is used as a resistive element, the resistance value of the resistive element may be determined by the length of the wiring. Alternatively, the resistive element may use a conductor with a different resistivity than the conductor used as the wiring. Or, when a semiconductor is used as a resistive element, the resistance value of the resistive element may be determined by doping the semiconductor with impurities.

[0398] Furthermore, in this specification, "capacitive element" may refer to, for example, a circuit element having a capacitance value higher than 0F, a region of wiring having a capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric material contained between the electrodes. "Capacitive element" includes, for example, parasitic capacitance occurring between wiring, or gate capacitance occurring between one of the source and drain of a transistor and the gate. Also, for example, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitive element" can be replaced with, for example, "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Alternatively, for example, it may be set to between 1 pF and 10 μF.

[0399] Furthermore, in this specification, a transistor has three terminals called the gate (also called the gate terminal, gate region, or gate electrode), the source (also called the source terminal, source region, or source electrode), and the drain (also called the drain terminal, drain region, or drain electrode). A transistor also has a region between the drain and the source where a channel is formed (also called the channel-forming region). A transistor can pass current between the source and the drain through the channel-forming region. The channel-forming region is the region where current primarily flows. The gate is a control terminal that controls the amount of current flowing through the channel-forming region between the source and the drain. The two terminals that function as either the source or the drain are the input and output terminals of the transistor.

[0400] The two input / output terminals function as either a source or a drain, depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to its three terminals. Furthermore, the functions of the source and drain may be reversed, for example, when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" are interchangeable. Additionally, when describing the connection relationships of a transistor, the terms "one of the source and drain" (or the first electrode or first terminal) or "the other of the source and drain" (or the second electrode or second terminal) are used.

[0401] Furthermore, depending on its structure, a transistor may have a back gate in addition to the three terminals described above. In this case, in this specification, one of the gates or back gates of the transistor may be referred to as the first gate, and the other of the gates or back gates of the transistor may be referred to as the second gate. In addition, in the same transistor, the terms "gate" and "back gate" may be interchangeable. Also, if a transistor has three or more gates, in this specification, each gate may be referred to as, for example, the first gate, the second gate, or the third gate.

[0402] In this specification, a transistor with a multi-gate structure having two or more gate electrodes can be used. In a multi-gate transistor, the channel formation regions are connected in series, resulting in a structure where multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce the off-current and improve the transistor's breakdown voltage (improve reliability). In addition, when operating in the saturation region, a multi-gate transistor can obtain a voltage-current characteristic with a flat slope, where the current between the drain and source does not change much even when the voltage between the drain and source changes. A transistor with a flat voltage-current characteristic can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor with a flat voltage-current characteristic can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0403] Furthermore, in this specification, when a single circuit element is shown in a circuit diagram, that circuit element may have multiple circuit elements. For example, when one resistor is shown in a circuit diagram, that resistor includes cases where two or more resistors are connected in series. Also, for example, when one capacitor is shown in a circuit diagram, that capacitor includes cases where two or more capacitors are connected in parallel. Also, for example, when one transistor is shown in a circuit diagram, that transistor includes cases where two or more transistors are connected in series and the gates of each transistor are connected to each other. Similarly, for example, when one switch is shown in a circuit diagram, that switch includes cases where two or more transistors are connected in series or in parallel and the gates of each transistor are connected to each other.

[0404] Furthermore, in this specification, the term "node" can be replaced with other terms such as "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit configuration or device structure. Also, for example, "terminal" or "wiring" can be replaced with "node."

[0405] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative. That is, if the reference potential changes, then, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit will also change.

[0406] Furthermore, in this specification, the terms "high-level potential" (also referred to as "high-level potential," "H potential," or "H") or "low-level potential" (also referred to as "low-level potential," "L potential," or "L") do not mean a specific potential. For example, if two wires are both described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are both described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0407] Also, in this specification and the like, "current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, unless otherwise specified, "current" refers to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers. Carriers here include, for example, electrons, holes, anions, cations, or complex ions, etc. Note that the carriers vary depending on the system through which the current flows (such as semiconductors, metals, electrolytic solutions, or vacuum, etc.). Also, for example, the "direction of current" in wiring or the like is defined as the direction in which positive carriers move, and is described with a positive current amount. In other words, the direction in which negative carriers move is the opposite direction to the direction of current, and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no indication regarding the positive or negative of the current (or the direction of the current), for example, a description such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, for example, a description such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0408] Also, in this specification and the like, ordinal numbers such as "first", "second", or "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, a component referred to as "first" may be a component referred to as "second" in other embodiments or the claims, etc. Also, for example, in one of the embodiments of this specification and the like, a component referred to as "first" may be omitted in other embodiments or the claims, etc.

[0409] Furthermore, in this specification, phrases indicating arrangement, such as "above," "below," "upward," or "downward," are sometimes used for convenience to explain the positional relationships between components with reference to the drawings. Also, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the phrases indicating arrangement described in this specification are not limited to those and can be appropriately rephrased. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees. Similarly, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the left (or right) side of the conductor" by rotating the orientation of the drawing shown by 90 degrees.

[0410] Furthermore, the terms "above" or "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0411] Furthermore, in this specification, terms such as "row" or "column" may be used to describe the matrix-like arrangement of components and their positional relationships. The positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" as described in this specification are not limited to these and can be appropriately rephrased. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the diagram shown by 90 degrees.

[0412] Furthermore, in this specification, terms such as "overlapping" do not limit the stacking order or other states of the constituent elements. For example, the expression "electrode B overlapping insulating layer A" is not limited to a state in which electrode B is formed on top of insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, a state in which electrode B is formed below insulating layer A, or a state in which electrode B is formed to the right (or left) of insulating layer A.

[0413] Also, in this specification and the like, the terms "adjacent" or "proximate" do not limit that the components are in direct contact. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B are formed in direct contact, and does not exclude those including other components between insulating layer A and electrode B.

[0414] Also, in this specification and the like, for example, terms such as "film" or "layer" may be interchangeable with each other. For example, the term "conductive layer" may be changed to the term "conductive film" in some cases. For example, the term "insulating film" may be changed to the term "insulating layer" in some cases. Also, for example, terms such as "film" or "layer" may be replaced with other terms without using those terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor" in some cases. Also, the term "conductor" may be changed to the term "conductive layer" or "conductive film" in some cases. For example, the term "insulating layer" or "insulating film" may be changed to the term "insulator" in some cases. Also, the term "insulator" may be changed to the term "insulating layer" or "insulating film" in some cases.

[0415] Also, in this specification and the like, for example, terms such as "electrode", "wiring", or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Further, the terms "electrode" or "wiring" include cases where, for example, a plurality of "electrodes" or "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of a "wiring" or "electrode", and vice versa. Further, the term "terminal" includes cases where, for example, a plurality of "electrodes", "wirings", or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal". Also, for example, a "terminal" can be part of a "wiring" or "electrode". Also, for example, terms such as "electrode", "wiring", or "terminal" may be replaced with terms such as "region".

[0416] Furthermore, in this specification, terms such as "signal line" or "power line" may be changed to the term "wiring." Similarly, terms such as "electric potential" applied to wiring may be changed to the term "signal." And vice versa; for example, terms such as "signal" may be changed to the term "electric potential."

[0417] Furthermore, in this specification, "switch" refers to a device having multiple terminals and a function to switch (select) between continuity and non-continuity between those terminals. For example, if a switch has two terminals and there is continuity between both terminals, the switch is said to be in a "conductive state" or "on state." If there is no continuity between both terminals, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch to either a continuative or non-conductive state, or maintaining either a continuative or non-conductive state, may be referred to as "controlling the continuity state."

[0418] In short, a switch is a device that controls whether or not an electric current flows. Alternatively, a switch is a device that selects and switches the path through which an electric current flows. Examples of switches include electrical switches and mechanical switches. In other words, a switch is not limited to a specific type.

[0419] Furthermore, there are types of switches that are normally non-conductive and can be made conductive by controlling the conductive state; these switches are sometimes called "A-contacts." Also, there are types of switches that are normally conductive and can be made non-conductive by controlling the conductive state; these switches are sometimes called "B-contacts."

[0420] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), or logic circuits combining these. Note that when a transistor is used simply as a switch, its polarity (conductivity type) is not particularly limited.

[0421] One example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and the movement of these electrodes selects between a conductive state and a non-conductive state.

[0422] In this specification, the "channel length" of a transistor may refer, for example, to the distance between the source and drain in the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is ON) and the gate overlap, or to the distance between the source and drain in the region where the channel is formed.

[0423] Furthermore, in this specification, the "channel width" of a transistor may refer, for example, to the length of the portion where the source and drain face each other in the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is ON) and the gate overlap, or to the length of the portion where the source and drain face each other in the region where the channel is formed.

[0424] In this specification, terms such as "substrate," "wafer," or "die" do not functionally limit these components. For example, terms such as "substrate," "wafer," or "die" may be interchangeable.

[0425] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0426] In this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 60 degrees or more and 120 degrees or less. Furthermore, "orthogonal" means a state in which two lines intersect or are connected at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately orthogonal" or "approximately orthogonal" means a state in which two lines intersect or are connected at an angle of 60° or more and 120° or less. Note that "approximately parallel" may also be included in the term "parallel." Similarly, "approximately perpendicular" may also be included in the term "perpendicular." Furthermore, the term "orthogonal" is sometimes used to include "approximately orthogonal."

[0427] In this specification, "heights matching" means that, in a cross-sectional view, the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal. For example, in the manufacturing process of semiconductor devices, planarization may expose the surfaces of one or more layers. In this case, the heights of the surfaces to be planarized will be equal to the reference surface. However, depending on the processing apparatus, processing method, or material of the surface to be processed during the planarization process, the heights of the multiple layers may not be exactly equal. In this specification, this is also referred to as "heights matching." For example, if there are two layers with different heights relative to a reference surface (here, a first layer and a second layer), the heights matching are also referred to if the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less. Therefore, "heights matching" may mean, for example, "heights matching or nearly matching."

[0428] In this specification, "edges coincide" means that, when viewed from above, at least a portion of the contours of the stacked layers overlap. For example, this includes cases in the manufacturing process of semiconductor devices where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this is also referred to as "edges coincide." Therefore, "edges coincide" may mean, for example, "edges coincide or nearly coincide."

[0429] In this specification, when we use terms such as "identical," "same," "equal," "simultaneous," "consistent," or "uniform" (including their synonyms) with respect to count values ​​and measured values, or with respect to objects, methods, and events that can be converted to count values ​​or measured values, these terms shall include an error margin of plus or minus 20%, unless otherwise explicitly stated. Therefore, for example, "identical" may mean "identical or nearly identical," "same" may mean "same or nearly identical," "equal" may mean "equal or nearly equal," "simultaneous" may mean "simultaneous or nearly simultaneous," "consistent" may mean "consistent or nearly identical," and "uniform" may mean "uniform or nearly uniform."

[0430] In this specification, semiconductor impurities refer to elements other than the main components constituting the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent are impurities. The presence of impurities in a semiconductor can lead to, for example, an increase in the defect level density, a decrease in carrier mobility, or a decrease in crystallinity. In the case of an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components of the oxide semiconductor. In particular, examples include hydrogen (which is also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, or nitrogen. In oxide semiconductors, for example, the presence of impurities can lead to the formation of oxygen vacancies in the oxide semiconductor.

[0431] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified, for example, into oxide insulators, oxide conductors (including transparent oxide conductors), or oxide semiconductors (also called oxide semiconductors or simply OS). For example, when a metal oxide is used in a semiconductor including the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide is used to constitute the channel formation region of a transistor having at least one of amplification, rectification, and switching functions, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be replaced with "a transistor having a metal oxide or oxide semiconductor."

[0432] Furthermore, in this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Additionally, metal oxides containing nitrogen may be called metal oxynitrides.

[0433] Furthermore, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" is the direction along the X axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction". Also, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction". Another may be referred to as the "second direction" or "second direction". The remaining one may be referred to as the "third direction" or "third direction".

[0434] 10: Imaging device, 11[1,1]: Circuit block, 11[1,2]: Circuit block, 11[2,1]: Circuit block, 11[2,2]: Circuit block, 11: Circuit block, 13: Drive circuit, 13a: Drive circuit, 13a[1,1]: Drive circuit, 13a[1,2]: Drive circuit, 13a[2,1]: Drive circuit, 13a[2,2]: Drive circuit, 13b: Drive circuit, 13c: Drive circuit, 13d: Drive circuit, 13e: Drive circuit, 13f: Drive circuit, 13g: Drive circuit, 13h: Drive circuit, 13i: Drive circuit, 15: Lamp signal generation circuit, 17[1,1]: Input / output circuit , 17[1,2]: Input / Output circuit, 17[2,1]: Input / Output circuit, 17[2,2]: Input / Output circuit, 17: Input / Output circuit, 19: Control circuit, 21: Selection circuit, 21a: Selection circuit, 21a[1,1]: Selection circuit, 21a[1,2]: Selection circuit, 21a[2,1]: Selection circuit, 21a[2,2]: Selection circuit, 23: Readout circuit, 23a: Readout circuit, 23a[1,1]: Readout circuit, 23a[1,2]: Readout circuit, 23a[2,1]: Readout circuit, 23a[2,2]: Readout circuit, 31[1,1]: Pixel block, 31[1,2]: Pixel block, 3 1[2,1]: Pixel block, 31[2,2]: Pixel block, 31: Pixel block, 33: Pixel array, 33a: Pixel array, 33a[1,1]: Pixel array, 33a[1,2]: Pixel array, 33a[2,1]: Pixel array, 33a[2,2]: Pixel array, 35: Pixel, 41: Layer, 42: Layer, 51: Wiring, 53: Wiring, 55[1,1]: Bus wiring, 55[1,2]: Bus wiring, 55[2,1]: Bus wiring, 55[2,2]: Bus wiring, 55: Bus wiring, 101: Photodetector, 103: Transistor, 104: Transistor, 105: Transistor, 1 06: Transistor, 108: Capacitive element, 121: Wiring, 122: Wiring, 123: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 200: Transistor, 205: Conductive layer, 205_1: Conductive layer, 205_2: Conductive layer, 208_a: Conductive layer, 208_b: Conductive layer, 212: Insulating layer, 214: Insulating layer, 216: Insulating layer, 218_a: Conductive layer, 218_b: Conductive layer, 221: Insulating layer, 222: Insulating layer, 224: Insulating layer, 230: Semiconductor layer, 230_1: Semiconductor layer, 230_2: Semiconductor layer, 230_a: Semiconductor layer, 230_b: Semiconductor layer, 241a: Insulating layer,241b: insulating layer, 242a: conductive layer, 242b: conductive layer, 243a: conductive layer, 243b: conductive layer, 246_a: conductive layer, 246_b: conductive layer, 248_a: conductive layer, 248_b: conductive layer, 250: insulating layer, 250_1: insulating layer, 250_2: insulating layer, 250_3: insulating layer, 250_4: insulating layer, 260: conductive layer, 260_1: conductive layer, 260_2: conductive layer, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 288: insulating layer, 289: opening, 292: insulating layer, 293: conductive layer, 310: transistor, 311: base Plate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316: Conductive layer, 318: Element isolation layer, 320: Insulating layer, 322: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 328a: Conductive layer, 328b: Conductive layer, 330: Conductive layer, 330a: Conductive layer, 330b: Conductive layer, 400: CDS circuit, 401: Resistor, 402: Capacitive element, 403: Transistor, 404: Transistor, 405: Capacitive element, 410: AD conversion circuit, 411a: Conductive layer, 411b: Conductive layer, 412: Functional layer, 413: Photoelectric conversion layer, 4 14: Functional layer, 415: Conductive layer, 416: Insulating layer, 417: Insulating layer, 418: Insulating layer, 419: Insulating layer, 420: Latch circuit, 430: Buffer circuit, 431: Insulating layer, 432: Conductive layer, 433: Insulating layer, 434: Conductive layer, 440: Vertical scanning circuit, 441: Insulating layer, 442: Insulating layer, 443: Semiconductor region, 444: Semiconductor region, 445: Insulating layer, 447: Insulating layer, 450: Optical filter, 451: Light-shielding layer, 455: Microlens array, 810: Bump, 815: Back electrode, 820: Through electrode, 825: Electrode pad, 830: Adhesive, 840: Cover guard Lass, 850: Bare chip, 855: Pixel array, 860: Lens cover, 870: Lens, 880: Optical filter, 890: Automobile, 891: Camera, 892: Imaging direction, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Frame, 922: Arm, 923: Rotor, 924: Blade, 925: Camera, 926: Battery, 932: Display unit, 933: Housing and wristband, 939: Camera, 941: Frame, 942: Camera, 943: Operation button, 944: Mounting parts, 951: Support base, 952: Camera unit,953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light-emitting unit, 981: Housing, 982: Display unit, 983: Operation buttons, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

It comprises a first circuit block, a second circuit block, a third circuit block, a fourth circuit block, a first pixel block, a second pixel block, a third pixel block, and a fourth pixel block, Each of the first to fourth circuit blocks has a plurality of drive circuits, Each of the first to fourth pixel blocks has pixels, each having a light-receiving element and a transistor, arranged in a matrix. The first pixel block is located on the first circuit block, The second pixel block is located on the second circuit block, The third pixel block is located on the third circuit block, The fourth pixel block is located on the fourth circuit block, Each of the multiple drive circuits has the function of controlling the driving of different pixels from each other. The layout of the second circuit block is symmetrical to the layout of the first circuit block with respect to the first axis as the axis of symmetry. The layout of the third circuit block is symmetrical with respect to the first circuit block, with respect to the second axis as the axis of symmetry. The second axis is perpendicular to the first axis, The layout of the fourth circuit block is point-symmetric to the layout of the first circuit block with respect to the intersection of the first axis and the second axis of the imaging device. 　 In claim 1, The aforementioned drive circuit includes a selection circuit and a readout circuit. The selection circuit has the function of selecting the pixel from which to acquire imaging data and the pixel from which to read out the imaging data that is held. The readout circuit is an imaging device having the function of reading out the imaging data held in the selected pixel. 　 In claim 2, Each of the first to fourth circuit blocks has one input / output circuit, The input / output circuit has the function of distributing the control signal input from the outside to one of the multiple drive circuits. The input / output circuit is an imaging device having the function of outputting the imaging data read by the readout circuit to the outside. 　 In claim 1, It has a control circuit, The control circuit has the function of simultaneously driving the drive circuits of the first circuit block, the second circuit block, the third circuit block, and the fourth circuit block, which are symmetrical with respect to the first axis, the second axis, and the intersection point. 　 In claim 2, It has a control circuit, The control circuit has the function of simultaneously causing the selection circuits of the first, second, third, and fourth circuit blocks to select, respectively, the pixels of the first, second, third, and fourth pixel blocks that are symmetrically related with respect to the first axis, the second axis, and the intersection point. 　 In claim 5, The control circuit has a function of causing the imaging device to acquire imaging data for some of the pixels of the first pixel block, the second pixel block, the third pixel block, and the fourth pixel block. 　 In any one of claims 1 to 6, The transistor is an imaging device having a metal oxide in the channel formation region. 　 In claim 7, The imaging device wherein the metal oxide is indium oxide.

Images