Semiconductor device, semiconductor device packaging structure, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a semiconductor device, a semiconductor device packaging structure, and an electronic device. The semiconductor device comprises a semiconductor layer, a metal conductive layer, and a metal silicide layer; the semiconductor layer comprises silicon, for example, the semiconductor layer may be a source and a drain in a silicon substrate, and the metal conductive layer may be a conductive channel in ohmic contact with the source and the drain; the metal silicide layer is stacked between the semiconductor layer and the metal conductive layer, and in the metal silicide layer, the metal content on the side close to the metal conductive layer is greater than that on the side close to the semiconductor layer, which may be understood as that the metal content of the upper layer of the metal silicide layer is greater than the metal content of the lower layer of the metal silicide layer. The metal silicide layer of the present application can be prepared by depositing metal for multiple times, metal formed in a later step diffuses into the metal silicide formed in an earlier step, so as to repair defects in the metal silicide formed in the earlier step, adjusting the linewidth effect, and optimizing the resistance.

Description

Semiconductor devices, semiconductor device packaging structures and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411422641.6, filed on October 11, 2024, entitled "Semiconductor Device, Semiconductor Device Packaging Structure and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, a semiconductor device packaging structure, an electronic device, and a method for fabricating a semiconductor device. Background Technology

[0003] In semiconductor manufacturing, to avoid non-ohmic contacts caused by direct contact between metal and semiconductor, metal silicides can be used as a transition layer for the metal-semiconductor contact in some devices. Metal silicides are metal compounds formed by the reaction of metal and silicon, and their conductivity is between that of metal and silicon.

[0004] As semiconductor technology continues to evolve, metal silicides are also constantly being developed. However, with the compression of process nodes, some technical problems have emerged. For example, the resistance of metal silicides increases rapidly as device size shrinks, resulting in a significant linewidth effect, which causes heat generation when current passes through the device and degrades device performance. Summary of the Invention

[0005] This application provides a semiconductor device, a semiconductor device packaging structure, an electronic device including the semiconductor device packaging structure, and a method for fabricating the semiconductor device. The main objective is to improve the linewidth effect and enhance device performance.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In one aspect, this application provides a semiconductor device, which may include a memory circuit, a logic circuit, or a digital circuit.

[0008] The semiconductor device includes a semiconductor layer, a metal conductive layer, and a metal silicide layer. The semiconductor layer contains silicon, for example, the semiconductor layer can be the source and drain electrodes in a silicon substrate, and the metal conductive layer can be a conductive channel that is in ohmic contact with the source and drain electrodes. The metal silicide is stacked between the semiconductor layer and the metal conductive layer. In the metal silicide layer, the metal content near the metal conductive layer is greater than the metal content near the semiconductor layer. This can be understood as the metal content of the upper layer of the metal silicide being greater than the metal content of the lower layer.

[0009] In the fabrication process of the semiconductor device of this application, to avoid non-ohmic contact caused by direct contact between the metal conductive layer and the semiconductor layer, a metal silicide layer can be prepared on the semiconductor layer before preparing the metal conductive layer. In the example of this application, metal can be deposited on the semiconductor layer for the first time, and the deposited metal can be annealed at low temperature and high temperature to obtain the metal silicide for the first time. For example, when the process node of the semiconductor device is small, even if the annealing temperature is increased, the metal silicide obtained in the first time cannot transform into a low-resistivity phase, resulting in a linewidth effect. In addition, the metal silicide obtained in the first time may also exhibit agglomeration. However, in this application, metal can be deposited a second time on the metal silicide obtained in the first time, and then the deposited metal can be annealed at low temperature and high temperature to obtain the metal silicide for the second time, so that in the fabricated device, the metal content of the upper layer of metal silicide is greater than the metal content of the lower layer.

[0010] By depositing metal again on the metal silicide obtained in the first step and annealing the metal again, the metal can diffuse along the concentration gradient direction to form silicides with different metal concentrations by utilizing the metal concentration gradient and transient high temperature heat. This can repair the defects in the formation process of the metal silicide obtained in the first step, solve technical problems such as linewidth effect and metal silicide agglomeration in advanced process nodes, and thus optimize the performance of the device.

[0011] In one feasible approach, the metal content in the metal silicide layer gradually decreases from the direction of the metal conductive layer to the semiconductor layer, while the silicon content in the metal silicide layer gradually increases.

[0012] This can be understood as follows: in the metal silicide layer, the metal content decreases from the top layer to the bottom layer, while the silicon content increases from the top layer to the bottom layer. This helps the metal silicide transform from a high-resistivity phase to a low-resistivity phase, better improves the linewidth effect of advanced process nodes, weakens the aggregation of metal silicides, and optimizes device performance.

[0013] In one possible implementation, the metal silicide layer has an interface; the metal silicide layer includes: a first metal silicide layer located between the interface and a semiconductor layer, and a second metal silicide layer located between the interface and a metal conductive layer, wherein the metal content of the second metal silicide layer is greater than the metal content of the first metal silicide layer.

[0014] In some feasible processes, two metal depositions can be performed to form metal silicides twice, thus creating a layered interface within the metal silicide layer.

[0015] In some feasible methods, at least two metal depositions can be performed to form metal silicides multiple times, thus creating multiple layered interfaces within the metal silicide layer.

[0016] In some feasible processes, during the second metal deposition and thermal annealing of the metal, a metal concentration gradient can be used to allow the second-deposited metal to diffuse along the concentration gradient direction, forming silicides of different metal concentrations. This repairs defects that occurred during the formation of the first metal silicide. In devices fabricated using this process, the metal content of the second metal silicide layer can be greater than that of the first metal silicide layer. This suppresses metal agglomeration or precipitation in the first-formed metal silicide, improves the silicide morphology, mitigates linewidth effects, and enhances device performance.

[0017] In some feasible ways, the ratio of silicon content to metal content in the second metal silicide layer is less than the ratio of silicon content to metal content in the first metal silicide layer.

[0018] After annealing the second deposited metal, an interface is formed. At this interface, the metal and silicon contents reach an inflection point. The ratio of silicon to metal content in the second metal silicide layer is less than that in the first metal silicide layer. This means that the second deposited metal can diffuse more into the first formed metal silicide, repairing defects such as metal precipitation and agglomeration.

[0019] In some feasible ways, the metal silicide layer includes a metallic element.

[0020] For example, the metal element is cobalt. Cobalt silicides have the advantages of good electrical conductivity and low mismatch rate with silicon. Moreover, CoSi2 is the final phase of cobalt silicides, which has good thermal stability and is well applied in some applications where high-temperature thermal stability is required.

[0021] In some feasible methods, the same metal is deposited multiple times, which can simplify the fabrication process and shorten the device fabrication cycle. In some feasible methods, the silicon to cobalt content ratio in the second metal silicide layer is 1:1, and the silicon to cobalt content ratio in the first metal silicide layer is 2:1.

[0022] CoSi2 has good thermal stability and is well-suited for applications where high-temperature thermal stability is required.

[0023] In some feasible implementations, the cobalt content in the metal silicide layer is greater than or equal to 30% and less than or equal to 55%. For example, the cobalt content is equal to 33%.

[0024] In the method described in this application, multiple metal depositions are performed, resulting in a cobalt content in the formed metal silicide ranging from 30% to 55%. This allows for a more efficient conversion of high-resistivity metal silicides into low-resistivity metal silicides, improving linewidth effects and optimizing device performance.

[0025] In some possible implementations, the metal silicide layer comprises a first metal and a second metal, which are different from each other.

[0026] This can be understood as: the metal deposited in the first deposition can be different from the metal deposited in the second deposition. For example, the first metal may include cobalt, and the second metal may include at least one of nickel or titanium.

[0027] Because the metal deposited in the first deposition is cobalt, the resulting cobalt silicide has a low compatibility with silicon in the semiconductor layer. Furthermore, the metal deposited in the second deposition is not limited to cobalt; any metal element capable of forming self-aligned silicides can be used.

[0028] In some feasible ways, the content of the first metal gradually increases and the content of the second metal gradually decreases from the direction of the metal conductive layer to the semiconductor layer.

[0029] For example, in some processes, the first deposited metal is cobalt, and the second deposited metal is at least one of nickel or titanium. In this way, the first formation is a cobalt silicide, and the second formation is at least one of nickel silicide or titanium silicide. The second formation of nickel silicide or titanium silicide can alleviate the defects in the cobalt silicide formation process, allowing the cobalt silicide to transform from a high-resistivity phase to a low-resistivity phase, better optimizing the linewidth effect of advanced process nodes, and weakening the aggregation phenomenon of metal silicides.

[0030] In some feasible ways, the content of the second metal in the first metal silicide layer is less than the content of the first metal; and the content of the second metal in the second metal silicide layer is greater than the content of the first metal.

[0031] In some processes, the first deposited metal is cobalt, and the second deposited metal is at least one of nickel or titanium. In this way, the content of the second metal in the first metal silicide layer is less than the content of the first metal, and the content of the second metal in the second metal silicide layer is greater than the content of the first metal.

[0032] This means that the metal deposited in the second deposition can diffuse more into the metal silicide formed in the first deposition, repairing the defects of the first metal silicide, such as repairing metal precipitation and metal agglomeration.

[0033] In some possible implementations, the semiconductor device includes a transistor; the semiconductor layer is the source, drain, or gate of the transistor; and the metal conductive layer is a conductive channel electrically connected to the source, drain, or gate.

[0034] For example, the source and drain of the transistor can be fabricated using front-end processes.

[0035] In some possible implementations, the linewidth of the transistor's gate is less than or equal to 65 nm.

[0036] For example, the gate linewidth can be less than 28 nm. This allows the device to meet smaller node requirements.

[0037] Secondly, this application also provides a semiconductor device packaging structure, which includes a substrate and a semiconductor device as described in any of the above implementations, wherein the semiconductor device is disposed on the substrate.

[0038] In the semiconductor device packaging structure provided in this application, the semiconductor device integrated on the substrate has metal silicides that can be obtained by depositing multiple metals. The annealing process of each subsequent metal deposition can repair the defects formed by the previously formed metal silicides, thereby improving the linewidth effect. For example, it can improve the linewidth effect of advanced process nodes, the technical problems of metal silicide agglomeration, and thus optimize the performance of the device.

[0039] Thirdly, this application also provides an electronic device, which includes a circuit board and a semiconductor device packaging structure as described in any of the above implementations, the semiconductor device packaging structure being disposed on the circuit board.

[0040] The electronic device provided in this application includes a semiconductor device in any of the above implementations. The metal silicide in the semiconductor device can be obtained by depositing multiple metals. The annealing treatment of the deposited metal can repair the defects formed by the previously formed metal silicide, thereby solving technical problems such as linewidth effect and metal silicide agglomeration in advanced process nodes, and thus optimizing the performance of the device.

[0041] Fourthly, this application also provides a method for fabricating a semiconductor device, the method comprising:

[0042] A first metal layer is formed on the semiconductor layer, the semiconductor layer comprising silicon;

[0043] Annealing the first metal layer yields an intermediate metal silicide;

[0044] A second metal layer is formed on the intermediate metal silicide;

[0045] The second metal layer was annealed at low temperature and high temperature to obtain metal silicide;

[0046] A metal conductive layer is formed on a metal silicide to form a metal silicide layer between a semiconductor layer and a metal conductive layer. In the metal silicide layer, the metal content near the metal conductive layer is greater than the metal content near the semiconductor layer.

[0047] When fabricating semiconductor devices using the method described in this application, after forming an intermediate metal silicide on the semiconductor layer, it is necessary to deposit metal again and then anneal the deposited metal. During the annealing process of the subsequently deposited metal, the metal concentration gradient and transient high-temperature heat can be used to diffuse the second-deposited metal, thereby repairing defects in the formation process of the intermediate metal silicide. This can solve technical problems such as linewidth effects and metal silicide aggregation in advanced process nodes, thus optimizing the performance of the device.

[0048] In some possible implementations, the metal of the first metal layer and the metal of the second metal layer are the same, and both the first metal layer and the second metal layer include cobalt.

[0049] Alternatively, in some feasible ways, the metals of the first metal layer and the second metal layer are not the same, the first metal layer includes cobalt, and the second metal layer includes at least one of nickel or titanium.

[0050] In some feasible methods, the fabrication process may also include pre-crystallizing the semiconductor layer by ion implantation before forming the first metal layer on the semiconductor layer.

[0051] In this way, amorphous silicon can be formed on the surface of the semiconductor layer, which can improve the nucleation rate of metal silicides, promote the transformation of metal silicides from high-resistivity phase to low-resistivity phase, reduce defects in metal silicide formation, and optimize device performance.

[0052] In some feasible ways, the first metal layer is annealed to obtain an intermediate metal silicide, including: low-temperature annealing and high-temperature annealing of the first metal layer.

[0053] First, the metal layer is subjected to low-temperature annealing to form a high-resistivity metal silicide phase. Then, the high-resistivity metal silicide phase is subjected to high-temperature annealing to form a low-resistivity metal silicide phase, thereby reducing the resistance of the device.

[0054] In some feasible methods, the annealing temperature for the low-temperature annealing of the first metal layer is the same as the annealing temperature for the low-temperature annealing of the second metal layer. For example, the annealing temperature can be between 380°C and 540°C.

[0055] In this way, the low-temperature annealing process for the second metal layer is compatible with the low-temperature annealing process for the first metal layer, and will not pose a significant challenge to the process.

[0056] In some feasible methods, the annealing temperature for the high-temperature annealing of the first metal layer is the same as the annealing temperature for the high-temperature annealing of the second metal layer. For example, the annealing temperature can be between 700°C and 1100°C.

[0057] The high-temperature annealing process for the second metal layer is compatible with the high-temperature annealing process for the first metal layer and does not pose a significant challenge to the process.

[0058] In some feasible ways, the thickness of the first metal layer is less than the thickness of the second metal layer.

[0059] This can be understood as follows: When a semiconductor device is fabricated using the method of the example in this application, metal silicides are formed by multiple metal depositions and multiple annealings. In this way, the thickness of the first deposited metal can be adjusted. For example, the thickness of the first deposited metal can be reduced, which can also reduce the defects formed by the first metal silicide, thereby optimizing the device performance. Attached Figure Description

[0060] Figure 1 is a partial structural diagram of an electronic device according to an example of this application;

[0061] Figure 2 is a partial structural diagram of a semiconductor device according to an example of this application;

[0062] Figure 3 is a partial structural diagram of a semiconductor device provided in an embodiment of this application;

[0063] Figure 4 is a partial structural diagram of a semiconductor device provided in an embodiment of this application;

[0064] Figure 5 is a partial structural diagram of a semiconductor device provided in an embodiment of this application;

[0065] Figure 6 is a partial structural diagram of a semiconductor device provided in an embodiment of this application;

[0066] Figures 7 and 8 are different perspective views of a metal silicide provided in this application;

[0067] Figures 9 to 16 are process structure diagrams corresponding to some steps in the fabrication process of a semiconductor device provided in the embodiments of this application;

[0068] Figure 17 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0069] Figure 18 is a schematic diagram of the structure of a semiconductor device provided by related technologies;

[0070] Figure 19 is a line scan schematic diagram of the metal silicide layer shown in Figure 17;

[0071] Figure 20 is a line scan schematic diagram of the metal silicide layer shown in Figure 18;

[0072] Figure 21 is a line scan schematic diagram of metal silicide layers containing different metals;

[0073] Figure 22 shows the simulation diagram of the ohmic resistance of the conventional scheme and the N-type resistor prepared in this application.

[0074] Figure 23 shows the simulation diagram of the ohmic resistance of the P-type resistor obtained by the conventional scheme and the present application.

[0075] Figure 24 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0076] Figure 25 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0077] Reference numerals: 100-Circuit board; 200-Substrate; 300-Semiconductor device; 400-Electrical connection structure; 11-First electrode; 12-Second electrode; 13-Channel; 14-Gate; 15-Gate sidewall; 16-Conductive channel; 17-Metal silicide layer; 18-First film layer; 19-Amorphous silicon; 20-Metal layer; 21-High-resistivity phase metal silicide; 22-Low-resistivity phase metal silicide; 23-Metal layer; 24-High-resistivity phase metal silicide; 25-Low-resistivity phase metal silicide. Detailed Implementation

[0078] The following embodiments of this application will be described in conjunction with the accompanying drawings.

[0079] The technical solutions of this application can be applied to various electronic devices employing semiconductor devices. For example, the electronic devices in the embodiments of this application can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. The electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc. The embodiments of this application are not limited in this regard.

[0080] As shown in Figure 1, the aforementioned electronic device may include a circuit board 100, such as a printed circuit board (PCB), on which a semiconductor device package structure is disposed. The semiconductor device package structure can be electrically connected to the circuit board 100 via an electrical connection structure 400, thereby enabling the semiconductor device package structure to achieve signal interconnection with other chips or other electronic modules on the circuit board 100.

[0081] In alternative implementations, the electrical connection structure 400 may include a plurality of solder balls, such as a ball grid array (BGA), or a plurality of metal pillars.

[0082] In some examples, as shown in Figure 1, the semiconductor device package structure includes multiple semiconductor devices 300 disposed on a substrate 200, such as on a package substrate. The substrate 200 is disposed on a circuit board 100 via an electrical connection structure 400.

[0083] The semiconductor device 300 shown in Figure 1 can be a single chip or multiple chips stacked in three dimensions.

[0084] In some implementation structures, the semiconductor device 300 may include memory, logic circuits, system on chip (SOC), or analog chips, digital chips, etc.

[0085] Semiconductor devices can include active or passive components. For example, they can include electronic devices such as transistors, resistors, and inductors.

[0086] A semiconductor device may include a plurality of electrically connected P-type transistors; or, a plurality of electrically connected N-type transistors; or, a plurality of electrically connected P-type transistors and N-type transistors.

[0087] Figure 2 is a partial structural schematic diagram of a semiconductor device according to an embodiment of this application. The semiconductor device includes a substrate and multiple transistors; in the example of Figure 2, a P-type transistor (PMOS) and an N-type transistor (NMOS) are shown, with adjacent transistors separated by a shallow trench isolation layer. Figure 2 is one example, but of course, more transistors may be included.

[0088] As shown in Figure 2, the P-type transistor or N-type transistor of this application includes: a first electrode 11, a second electrode 12 and a channel 13, and a gate (G) 14. For example, one of the first electrode 11 and the second electrode 12 can be the drain electrode (D) and the other can be the source electrode (S).

[0089] The first electrode 11, the second electrode 12, and the channel 13 are located in the substrate, with the channel 13 located between the first electrode 11 and the second electrode 12, and the gate 14 located on the channel 13. The transistor illustrated in Figure 2 can be referred to as a planar transistor.

[0090] In some examples, as shown in Figure 2, a gate sidewall 15 can be provided on the peripheral side of the gate 14. The gate sidewall 15 can have a protective function, controlling the distance from the channel during ion implantation in the substrate to form the channel, thereby suppressing short-channel effects.

[0091] In some examples, the substrate contains silicon; for example, the substrate is a silicon substrate.

[0092] The first electrode 11, the second electrode 12, or the gate electrode 14 need to be electrically connected to the peripheral circuit. In some structures, as shown in Figure 3, conductive channels 16 can be provided on the first electrode 11, the second electrode 12, or the gate electrode 14 to bring out these electrodes.

[0093] In some examples, the first electrode 11 and the second electrode 12 can be semiconductor layers, for example, they can be formed by heavy doping in a silicon substrate. In some examples, the gate 14 is a semiconductor layer, for example, the gate 14 can be made of polycrystalline silicon.

[0094] To avoid non-ohmic contact between the conductive channel 16 of the metal conductive layer and the electrodes (such as the first electrode 11, the second electrode 12, or the gate electrode 14) of the semiconductor layer, as shown in Figure 3, a metal silicide layer 17 can be disposed between the semiconductor layer (such as the first electrode 11, the second electrode 12, or the gate electrode 14) and the metal conductive layer (such as the conductive channel 16). For example, the metal silicide layer 17 can be stacked between the first electrode 11 and the conductive channel 16, between the second electrode 12 and the conductive channel 16, and between the gate electrode 14 and the conductive channel 16.

[0095] Figures 4 and 5 are partial structural schematic diagrams of some other semiconductor devices provided in embodiments of this application. These semiconductor devices include: resistors.

[0096] Figure 4 shows a resistor structure disposed in an active region. In this example, the substrate has an N-type or P-type doped region, and a metal silicide layer 17 forming a resistor is disposed on the N-type or P-type doped region. The metal silicide layer 17 can be electrically connected to other electronic devices through conductive channels 16. That is, in this example, the metal silicide layer 17 serves as an active region resistor.

[0097] Figure 5 illustrates a gate (polysilicon) resistor. In this example, a metal silicide layer 17 forming a resistor can be formed above the gate 14 made of polysilicon material. The metal silicide layer 17 can be electrically connected to other electronic devices through conductive channels 16. That is, in this example, the metal silicide layer 17 serves as a gate polysilicon resistor. For example, a polysilicon gate can be disposed on a shallow trench isolation layer, and then the metal silicide layer 17 serving as a resistor can be formed on the polysilicon gate.

[0098] In the examples of Figures 4 and 5, the metal silicide layer 17 forms a resistor and is electrically connected to the peripheral circuit through the conductive channel 16.

[0099] Figure 6 is a partial structural schematic diagram of another semiconductor device according to an embodiment of this application. The semiconductor device includes a transistor, which may be referred to as a three-dimensional transistor. A first electrode 11 and a second electrode 12 are located in a substrate, and a portion of a gate 14 is also located in the substrate. In this example, the gate 14 can be made of a metallic material.

[0100] The first electrode 11 and the second electrode 12 can be electrically connected to other electronic devices through conductive channels 16, respectively.

[0101] In the various semiconductor devices illustrated in Figures 3 to 6 above, a metal silicide layer is disposed between the semiconductor layer and the metal conductive layer. In some feasible processes, when the metal silicide layer 17 is fabricated, a metal layer can be formed on the semiconductor layer, and then the metal layer can be annealed, whereby the metal reacts with the silicon in the semiconductor layer to form a metal silicide.

[0102] As semiconductor device process nodes become more compact, for example, below 65nm, even increasing the annealing temperature to provide more energy cannot effectively convert the metal silicide layer 17 from a high-resistivity phase to a low-resistivity phase. This will increase the resistance of the metal silicide, resulting in a linewidth effect. Furthermore, during high-temperature annealing, the metal silicide will also exhibit metal agglomeration and metal precipitation phenomena as shown in Figures 7 and 8, deteriorating the performance of the semiconductor device.

[0103] In order to better transform metal silicides from high-resistivity phases to low-resistivity phases, improve linewidth effect, and weaken the aggregation and precipitation of metal silicides, embodiments of this application provide some possible methods, as described below.

[0104] The following description, in conjunction with the accompanying drawings, illustrates how this application fabricates a metal silicide layer between a semiconductor layer and a conductive metal layer. For clarity, this application uses the fabrication of a transistor as an example.

[0105] As shown in Figure 9, a metal-oxide-semiconductor field-effect transistor (MOSFET) is formed on a silicon substrate.

[0106] This example demonstrates an N-type metal-oxide-semiconductor field-effect transistor (NMOS) and a P-type metal-oxide-semiconductor field-effect transistor (PMOS). Both the P-type and N-type transistors shown in Figure 9 can be fabricated using front-end processes.

[0107] As shown in Figure 9, in the P-type transistor of this application, the first electrode 11 may include silicon (Si), germanium (Ge), and boron (B), such as a SiGe material containing boron (B). The second electrode 12 may also include silicon (Si), germanium (Ge), and boron (B), such as a SiGe material containing boron (B).

[0108] Due to the lattice constant of germanium (Ge) The lattice constant of silicon (Si) The increase of about 4% will generate a transverse compressive stress F on the channel 13 as shown in Figure 9, which will reduce the Si lattice constant in the channel 13 and reduce the effective hole mass, thereby achieving the purpose of improving the hole mobility.

[0109] Referring to Figure 9, in the P-type transistor, the first electrode 11 further includes a first film layer 18, which comprises silicon (Si) and boron (B). The boron content in the first film layer 18 is greater than the boron content in the first electrode 11 located below the first film layer 18. Because the first film layer 18 has a higher content (or concentration) of boron (B), the resistance of the circuit containing the P-type transistor can be effectively reduced, thus optimizing the circuit performance.

[0110] In the example shown in Figure 9, the linewidth Lg of the gate 14 of the P-type transistor and the N-type transistor can be less than or equal to 65 nm. For example, it can be equal to 28 nm, or it can be less than 28 nm.

[0111] In this example, the gate linewidth Lg can be understood as the size of the gate in a first direction, which is parallel to the arrangement direction of the source and drain electrodes. That is, the first direction is along the arrangement direction of the first electrode 11 and the second electrode 12.

[0112] As shown in Figure 10, amorphous silicon 19 is formed on the electrodes of the transistor by ion implantation pre-amorphization implant (PAI) treatment.

[0113] Pre-amorphization treatment can be understood as: ion implantation is used to make the silicon surface amorphous before metal deposition. This helps to promote the silicide reaction in subsequent processes, improve the interface morphology, reduce defects, and improve the linewidth effect.

[0114] As shown in Figure 10, in an N-type transistor, the first electrode 11, the second electrode 12, and the gate 14 can be pre-amorphized. In this way, amorphous silicon 19 can be formed on the surface of the first electrode 11, the surface of the second electrode 12, and the surface of the gate 14, respectively.

[0115] As shown in Figure 10, in a P-type transistor, the first film layer 18 and the gate 14 can be pre-amorphized. Thus, amorphous silicon 19 is formed on the surface of the first film layer 18 and the surface of the gate 14, respectively.

[0116] Among the available options, an ion implanter can be used for pre-amorphization ion implantation.

[0117] Pre-amorphization implantation ion sources can be neutral or inert ion sources such as silicon (Si), germanium (Ge), argon (Ar), and xenon (Xe), with implantation energies ranging from 1 to 10 electron volts and implantation doses ranging from 2 eV. 14 up to 5e 15 Ions per square centimeter.

[0118] As shown in Figure 11, a metal layer 20 is deposited for the first time, which at least covers the amorphous silicon 19.

[0119] In some possible implementations, the metal layer 20 can be a cobalt metal layer.

[0120] For example, when the gate process node of the transistor is below 65nm, the thickness of the metal layer 20 can be 30nm to 50nm. As another example, when the gate process node of the transistor is above 65nm, the thickness of the metal layer 20 can be greater than 80nm.

[0121] As shown in Figure 12, the metal layer 20 obtained in Figure 11 is subjected to low-temperature annealing to form a high-resistivity metal silicide 21.

[0122] For example, when the metal layer is a cobalt metal layer, cobalt silicide (CoSi2) can be formed. CoSi2 has good conductivity, low mismatch rate with silicon, and is the final phase of cobalt silicide. It has high thermal stability and is well applied in some scenarios where the device needs to have high thermal stability, such as in scenarios where the process temperature is higher than 700°C.

[0123] In some processes, the low-temperature annealing temperature can be between 380°C and 540°C, and the annealing time can be between 30 seconds and 120 seconds.

[0124] After the metal layer obtained in Figure 11 is subjected to low-temperature annealing, the unreacted metal can be removed by selective etching, as shown in Figure 12. The high-resistivity metal silicide 21 located above the electrode is retained, and the remaining unreacted metal can be removed.

[0125] In some optional processes, the selective etching solution can be sulfuric acid.

[0126] For example, wet etching can be used to selectively remove unreacted metal.

[0127] As shown in Figure 13, the high-resistivity metal silicide 21 obtained in Figure 12 is subjected to high-temperature annealing to form a low-resistivity metal silicide 22.

[0128] In some processes, the high-temperature annealing temperature can be 700℃ to 1100℃, and the annealing time can be 3 seconds to 20 seconds.

[0129] After obtaining the low-resistivity phase metal silicide 22 shown in Figure 13, metal agglomeration may occur, leading to linewidth effect. For example, when the gate width Lg of the transistor is less than or equal to 65nm, metal agglomeration occurs, and the linewidth effect becomes more prominent.

[0130] To eliminate the metal agglomeration phenomenon shown in Figure 13 and improve the linewidth effect, the following process steps can be performed.

[0131] As shown in Figure 14, a second metal layer 23 is deposited, which at least covers the low-resistivity metal silicide 22 prepared in Figure 13.

[0132] The metal deposited in this step may include at least one of cobalt, nickel, or titanium. This can be understood as: it may be one of cobalt, nickel, or titanium, or an alloy of at least two of cobalt, nickel, or titanium.

[0133] In addition, the metal deposited in this step includes at least one of cobalt, nickel, or titanium, which are metal elements that can form self-aligned silicides.

[0134] For example, the thickness of the metal layer 23 in this step illustrated in Figure 14 can be greater than the thickness of the metal layer 20 deposited in Figure 11. For instance, the thickness of the metal layer 23 in Figure 14 can be 40 nm to 100 nm, while the thickness of the metal layer 20 in Figure 11 can be 30 nm to 50 nm. In other examples, the thickness of the metal layer 23 in Figure 14 can be equal to the thickness of the metal layer 20 in Figure 11, or the thickness of the metal layer 23 in Figure 14 can be less than the thickness of the metal layer 20 in Figure 11.

[0135] As shown in Figure 15, the metal layer 23 obtained in Figure 14 is subjected to low-temperature annealing to form a high-resistivity metal silicide 24.

[0136] During the annealing heat treatment process, due to the existence of the metal element gradient, the redeposited metal will diffuse downward during the low-temperature annealing of the metal layer 23, which can repair the defects generated in Figure 13, for example, make the metal silicide more flat.

[0137] In some processes, the low-temperature annealing temperature can be between 200℃ and 850℃, and the annealing time can be between 30 seconds and 120 seconds. For example, the low-temperature annealing temperature can be between 380℃ and 540℃.

[0138] For example, when the metal deposited in Figure 14 is cobalt, the low-temperature annealing temperature can be 500°C.

[0139] As another example, when the metal deposited in Figure 14 is titanium, the low-temperature annealing temperature can be above 650°C.

[0140] As another example, when the metal deposited in Figure 14 is nickel, the low-temperature annealing temperature can be 250°C.

[0141] After the metal layer obtained in Figure 14 is subjected to low-temperature annealing, the unreacted metal can be removed by selective etching, as shown in Figure 15. The high-resistivity metal silicide above the high-resistivity metal silicide obtained in the first preparation is retained, and the remaining unreacted metal can be removed.

[0142] In some optional processes, the selective etching solution can be sulfuric acid.

[0143] As shown in Figure 16, the high-resistivity metal silicide 24 obtained in Figure 15 is subjected to high-temperature annealing to form a low-resistivity metal silicide 25.

[0144] In some optional processes, if defects still exist at the metal silicide interface after performing the process steps shown in Figure 16, the steps shown in Figures 14 to 16 can be repeated until the defects at the metal silicide interface are substantially eliminated.

[0145] For example, in some processes, metal can be deposited three times, and each deposited metal can be annealed to form a low-resistivity metal silicide. In other processes, metal can be deposited four or more times, and each deposited metal can be annealed to form a low-resistivity metal silicide, resulting in a smooth metal silicide interface with virtually no defects.

[0146] When metal silicides are prepared using the above method, the metal deposited in the first deposition can be cobalt, the metal deposited in the second deposition, or the metal deposited in the Nth (N>2)th deposition can be at least one of cobalt, nickel, and titanium.

[0147] This can be understood as follows: This application can perform multiple metal depositions and multiple metal silicide treatments, utilizing the concentration gradient between the metal deposited in each subsequent deposition and the metal in the previous metal silicide, so that the subsequent metal can diffuse into the previously formed metal silicide to repair the defects present in the previous metal silicide, thereby improving the device performance.

[0148] The transistors fabricated using the above method can have a gate width of less than or equal to 65nm, or even less than 28nm.

[0149] In some technologies, if a single metal deposition method is used, such as depositing titanium, even with high-temperature annealing, a severe linewidth effect will occur, meaning the resistance of titanium silicide (TiSi) will increase rapidly as the device size shrinks. Similarly, with cobalt deposition, even high-temperature treatment cannot optimize the linewidth effect and cobalt agglomeration occurs, degrading device performance. Furthermore, with nickel deposition, if the annealing temperature is high, the resulting nickel silicide (NiSi) has poor stability, thus limiting the application of this technology in high-temperature process fabrication.

[0150] However, when metal silicides are prepared using the method of the example in this application, even if the fabrication process node is below 65nm or even smaller, the agglomeration and precipitation of metal silicides can be suppressed, resulting in a relatively smooth metal silicide interface. Furthermore, at the annealing temperature, the small linewidth resistance can be converted into a low resistance phase, thus improving the linewidth effect problem.

[0151] Figure 17 is a structural diagram of the metal silicide prepared using the method given in the embodiments of this application above, and Figure 18 is a structural diagram of the metal silicide prepared using related technologies.

[0152] The semiconductor device of this application includes a semiconductor layer, a metal silicide layer, and a metal conductive layer, wherein the metal silicide layer is stacked between the semiconductor layer and the metal conductive layer, and the semiconductor layer includes silicon.

[0153] Comparing Figures 17 and 18, it can be seen that the metal silicide layer interface prepared using related technologies is relatively rough, and the unevenness at the interface between the metal silicide and the semiconductor layer is quite severe. However, the metal silicide layer interface prepared using the example of this application is relatively smooth, and the unevenness at the interface between the metal silicide and the semiconductor layer is significantly alleviated.

[0154] Figure 19 is a line scan schematic diagram of the metal silicide layer shown in Figure 17. Figure 20 is a line scan schematic diagram of the metal silicide layer shown in Figure 18.

[0155] Figures 19 and 20 show the content of silicon and other metal elements in metal silicides. The dashed lines represent the changes in silicon content, and the solid lines represent the changes in the content of other metal elements.

[0156] In Figure 20, when metal silicides are prepared by a single metal deposition method, the content of metal elements in the metal silicide remains essentially unchanged from the direction from the metal conductive layer to the semiconductor layer, for example, along the P direction as shown in Figure 18, and the content of silicon elements in the metal silicide remains essentially unchanged.

[0157] In this application example, when metal silicides are prepared by multiple metal depositions, as shown in Figure 17, the metal content near the conductive metal layer is greater than the metal content near the semiconductor layer in the metal silicide layer. In the example of Figure 17, a darker fill color indicates a higher metal content, and a lighter fill color indicates a lower content.

[0158] For example, in Figure 19, from the metal conductive layer to the semiconductor layer (as shown in the P direction of Figure 17), the metal content in the metal silicide layer gradually decreases, while the silicon content gradually increases. For instance, in fabricating planar transistors, along the direction closer to the silicon substrate, the metal content in the metal silicide layer decreases, while the silicon content increases. This allows sufficient metal to diffuse into the first-formed metal silicide, repairing defects in the first-formed metal silicide and optimizing device performance.

[0159] In some feasible processes, a first metal deposition can be performed, followed by thermal annealing to convert the deposited metal into a low-resistivity metal silicide phase. A second metal deposition is then performed, followed by thermal annealing to convert the deposited metal into a low-resistivity metal silicide phase. During the second thermal annealing process, the second-deposited metal diffuses towards the first-formed low-resistivity metal silicide phase, repairing defects in the first phase and improving the linewidth effect.

[0160] In this application example, in the metal silicide layer, the metal content = number of metal atoms / (number of metal atoms + number of silicon Si atoms), and the silicon Si content = number of silicon Si atoms / (number of metal atoms + number of silicon Si atoms).

[0161] When preparing metal silicides using the multiple metal deposition method described in this application, an interface as shown in Figure 17 can be formed in the final metal silicide layer. This can be understood as follows: the metal silicide layer includes a first metal silicide layer located between the interface and the semiconductor layer, and a second metal silicide layer located between the interface and the metal conductive layer.

[0162] In the example shown in Figure 17, a two-stage metal deposition process is illustrated, thus illustrating one interface. In other examples, a three-stage metal deposition process can result in two interfaces. In still other examples, an N-stage metal deposition process can result in N-1 interfaces.

[0163] As shown in Figure 19, the metal content of the first metal silicide layer is less than that of the second metal silicide layer. The silicon content of the first metal silicide layer is greater than that of the second metal silicide layer.

[0164] During the second metal deposition and the hot annealing of the metal, some of the metal may diffuse into the first metal silicide to repair defects, so that the metal content of the second metal silicide layer, as shown in Figure 19, is greater than the metal content of the first metal silicide layer.

[0165] As shown in Figure 19, the ratio of silicon content to metal content in the second metal silicide layer is less than the ratio of silicon content to metal content in the first metal silicide layer.

[0166] For example, in some cases, when the first deposited metal is cobalt and the second deposited metal is also cobalt, the ratio of silicon content to cobalt content in the second metal silicide layer can be 1:1, and the ratio of silicon content to cobalt content in the first metal silicide layer can be 2:1.

[0167] In the example of this application, the ratio of silicon content to cobalt content in the second metal silicide layer can be 1:1, which can be understood as the ratio of silicon content to cobalt content in the second metal silicide layer being close to 1:1. For example, the ratio can be 1.1:1 or 1.2:1.

[0168] In the example of this application, the ratio of silicon content to cobalt content in the first metal silicide layer can be 2:1, which can be understood as the ratio of silicon content to cobalt content in the first metal silicide layer being close to 2:1. For example, the ratio can be 1.9:1 or 1.8:1.

[0169] As shown in Figure 19, in metal silicides, when the first deposited metal is cobalt and the second deposited metal is also cobalt, the cobalt content is greater than or equal to 30% and less than or equal to 55%. For example, the cobalt content is greater than or equal to 33% and less than or equal to 50%. This allows for a more efficient conversion of high-resistivity metal silicides into low-resistivity metal silicides, resolving the linewidth effect and optimizing device performance.

[0170] As shown in Figure 19, the silicon content curve has an inflection point at the interface of the metal silicide. This can be understood as follows: the slopes of the straight lines on both sides of the inflection point in the silicon content curve are not the same. For example, the slope of the silicon content line in the second metal silicide layer to the left of the inflection point is less than the slope of the silicon content line in the first metal silicide layer to the right of the inflection point.

[0171] As shown in Figure 19, the metal content curve has an inflection point at the interface of the metal silicide. This can be understood as follows: the slopes of the straight lines on both sides of the inflection point in the metal content curve are not the same. For example, the slope of the metal content line in the second metal layer silicide to the left of the inflection point is less than the slope of the metal content line in the first metal layer silicide to the right of the inflection point.

[0172] After the metal is deposited again, the metal atoms diffuse downwards while the silicon atoms diffuse upwards. However, the downward diffusion rate of the metal atoms and the upward diffusion rate of the silicon atoms are different, so an inflection point will be generated at the interface.

[0173] In other feasible preparation methods, the metal deposited in the second deposition can be different from the metal deposited in the first deposition. For example, the metal deposited in the first deposition may be cobalt, and the metal deposited in the second deposition may contain at least one of cobalt, nickel, or titanium. This can be understood as: the first metal deposited in the first deposition may be the same as or different from the second metal deposited in the second deposition.

[0174] For example, Figure 21 shows a line scan schematic of a metal silicide layer in one example. In this example, the first metal deposited in the first deposition is cobalt, and the second metal deposited in the second deposition is nickel.

[0175] From the conductive metal layer to the semiconductor layer, as shown in Figure 21, the content of the first metal gradually increases, while the content of the second metal gradually decreases. For example, if the first metal deposited in the first deposition is cobalt and the second metal deposited is nickel, in the metal silicide layer, the cobalt content is higher and the nickel content is lower near the semiconductor layer, while the nickel content is higher and the cobalt content is lower near the conductive metal layer.

[0176] Continuing with Figure 21, the metal silicide layer has an interface that divides it into a first metal silicide layer and a second metal silicide layer. The second metal silicide layer is closer to the semiconductor layer than the first metal silicide layer. In the first metal silicide layer, the content of the second metal is less than that of the first metal; in the second metal silicide layer, the content of the second metal is greater than that of the first metal.

[0177] As shown in Figure 21, the silicon content curve has an inflection point at the interface of the metal silicide. This can be understood as follows: the slopes of the straight lines on both sides of the inflection point in the silicon content curve are not the same. For example, the slope of the silicon content line in the second metal silicide layer to the left of the inflection point is less than the slope of the silicon content line in the first metal silicide layer to the right of the inflection point.

[0178] As shown in Figure 21, the first metal content curve has an inflection point at the interface of the metal silicide. This can be understood as follows: the slopes of the straight lines on both sides of the inflection point in the first metal content curve are not the same. For example, the slope of the first metal content line in the second metal layer silicide to the left of the inflection point is less than the slope of the first metal content line in the first metal layer silicide to the right of the inflection point.

[0179] As shown in Figure 21, the second metal content curve has an inflection point at the interface of the metal silicide. This can be understood as follows: the slopes of the straight lines on both sides of the inflection point in the second metal content curve are not the same. For example, the slope of the second metal content line in the second metal layer silicide to the left of the inflection point is greater than the slope of the second metal content line in the first metal layer silicide to the right of the inflection point.

[0180] Figures 22 and 23 illustrate the comparison of the resistance values ​​in ohms of N-type and P-type resistors fabricated using the conventional method and the method of this application, respectively. An N-type resistor can be understood as a resistor fabricated on an N-type doped region, and a P-type resistor can be understood as a resistor fabricated on a P-type doped region.

[0181] In Figure 22, the resistance of a 27nm N-type sheet resistor fabricated using the conventional method ranges from 50 ohms per square to 200 ohms per square. However, the resistance of a 27nm N-type sheet resistor fabricated using the example of this application ranges from 25 ohms per square to 50 ohms per square. The resistance of the N-type sheet resistor in the example of this application is significantly reduced, and the resistance reduction is very prominent, indicating a significant improvement in the linewidth effect.

[0182] In Figure 23, the resistance of a 27nm P-type sheet resistor fabricated using the conventional method ranges from 10 ohms per square to 240 ohms per square. However, the resistance of the P-type sheet resistor fabricated using the example of this application ranges from 10 ohms per square to 20 ohms per square. The resistance of the P-type sheet resistor in the example of this application is significantly reduced, and the resistance reduction is very prominent, resulting in a significant improvement in the linewidth effect.

[0183] Therefore, it can be concluded that by using the multiple metal depositions in the example of this application, and using the subsequently formed metal silicides to repair previous defects, the resistance value is reduced and the linewidth effect is improved.

[0184] As shown in Figures 22 and 23, the process node with a gate width Lg of 27nm is demonstrated. It can be seen that the method of this application can not only produce devices with process nodes below 65nm, but also devices with process nodes below 28nm. Furthermore, the linewidth effect is significantly improved, the silicide resistance is significantly reduced, and the performance of the integrated circuit is significantly optimized.

[0185] Semiconductor devices with different structures based on the above examples, and their corresponding fabrication methods, can be fabricated according to the process flow diagram shown in Figure 24.

[0186] Step S1: Form a first metal layer on a semiconductor layer, the semiconductor layer comprising silicon.

[0187] In some examples, the semiconductor layer can be the source / drain of a transistor, or the gate, which can be fabricated by heavy doping in a silicon substrate.

[0188] In some feasible processes, the metal of the first metal layer can be cobalt. For example, the first metal layer can be prepared using physical vapor deposition (PVD).

[0189] Step S2: Anneal the first metal layer to obtain an intermediate metal silicide.

[0190] For example, the first metal layer can be annealed at a low temperature to form a high-resistivity metal silicide; then it can be annealed at a high temperature to form a low-resistivity metal silicide.

[0191] Step S3: Form a second metal layer on the intermediate metal silicide.

[0192] In some feasible processes, the metal of the second metal layer can be the same as or different from the metal of the first metal layer. For example, the metal of the second metal layer can be at least one of cobalt, nickel, or titanium.

[0193] In some processes, a second metal layer can be fabricated using physical vapor deposition (PVD).

[0194] Step S4: The second metal layer is annealed at low temperature and high temperature to obtain metal silicide.

[0195] Low-temperature annealing forms a high-resistivity metal silicide phase; high-temperature annealing forms a low-resistivity metal silicide phase. This process allows metal to diffuse into the intermediate metal silicide, repairing defects and reducing resistance.

[0196] Step S5: A metal conductive layer is formed above the metal silicide to form a metal silicide layer between the semiconductor layer and the metal conductive layer. In the metal silicide layer, the metal content near the metal conductive layer is greater than the metal content near the semiconductor layer.

[0197] In some processes, before forming the first metal layer on the semiconductor layer, the fabrication method may further include: pre-crystallizing the semiconductor layer by ion implantation. For example, when the semiconductor layer is a silicon substrate, pre-amorphization implantation (PAI) is performed before metal deposition, where the underlying silicon substrate is bombarded with an ion beam to become amorphous, thereby increasing the nucleation rate of metal silicides, promoting the transformation of metal silicides from a high-resistivity phase to a low-resistivity phase, and optimizing the linewidth effect.

[0198] In the preparation method of this application, since the metal silicide is obtained by multiple metal depositions, the film thickness during the first metal deposition can be controlled. For example, the thickness of the first deposited metal film can be reduced, thereby improving the thermal stability of the first-formed metal silicide (such as cobalt silicide) due to the surface tension of the film, and also optimizing the linewidth effect.

[0199] As shown in Figure 25, this is a semiconductor device fabricated using a two-stage metal deposition process, where the thickness of the first deposited metal is less than that of the second deposited metal. In the final metal silicide layer, the interface is closer to the semiconductor layer than the conductive metal layer.

[0200] When metal silicides are fabricated using the method exemplified in this application, devices with process nodes above 65 nm can be fabricated, as well as devices with process nodes below 65 nm, thus improving the linewidth effect and reducing metal agglomeration and precipitation. Of course, in the methods exemplified above, to further adjust the linewidth effect, the annealing temperature can be increased; for example, a high-temperature annealing temperature can be increased to optimize device performance.

[0201] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0202] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor layer, the semiconductor layer comprising silicon; Metal conductive layer; A metal silicide layer, the metal silicide layer being stacked between the semiconductor layer and the metal conductive layer; In the metal silicide layer, the metal content near the metal conductive layer is greater than the metal content near the semiconductor layer.

2. The semiconductor device according to claim 1, characterized in that, From the metal conductive layer to the semiconductor layer, the metal content in the metal silicide layer gradually decreases, and the silicon content in the metal silicide layer gradually increases.

3. The semiconductor device according to claim 1 or 2, characterized in that, The metal silicide layer has an interface; The metal silicide layer includes: a first metal silicide layer located between the interface and the semiconductor layer, and a second metal silicide layer located between the interface and the metal conductive layer; The metal content of the second metal silicide layer is greater than the metal content of the first metal silicide layer.

4. The semiconductor device according to claim 3, wherein The metal silicide layer includes a metal, including cobalt.

5. The semiconductor device according to claim 4, characterized in that, The ratio of silicon content to cobalt content in the second metal silicide layer is 1:1, and the ratio of silicon content to cobalt content in the first metal silicide layer is 2:

1.

6. The semiconductor device according to claim 4 or 5, characterized by The cobalt content in the metal silicide layer is greater than or equal to 30% and less than or equal to 55%.

7. The semiconductor device according to claim 3, characterized in that, The metal silicide layer includes a first metal and a second metal, wherein the first metal and the second metal are different, the first metal includes cobalt, and the second metal includes at least one of nickel or titanium.

8. The semiconductor device according to claim 7, characterized in that, From the direction of the metal conductive layer to the semiconductor layer, the content of the first metal gradually increases, and the content of the second metal gradually decreases.

9. The semiconductor device according to claim 7 or 8, characterized in that, In the first metal silicide layer, the content of the second metal is less than the content of the first metal; In the second metal silicide layer, the content of the second metal is greater than the content of the first metal.

10. The semiconductor device according to any one of Claims 3 to 9, wherein The interface is closer to the semiconductor layer than the metal conductive layer.

11. The semiconductor device according to any one of Claims 1-10, wherein The semiconductor device includes a transistor; The semiconductor layer is the source, drain, or gate of the transistor; The metal conductive layer is a conductive channel electrically connected to the source, the drain, or the gate.

12. A semiconductor device package structure, comprising: include: The semiconductor device as described in any one of claims 1-11; A substrate on which the semiconductor device is disposed.

13. An electronic device, characterized in that, include: Circuit board; The semiconductor device packaging structure as described in claim 12; The semiconductor device packaging structure is disposed on the circuit board.

14. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A first metal layer is formed on a semiconductor layer, the semiconductor layer comprising silicon; Annealing the first metal layer yields an intermediate metal silicide; A second metal layer is formed on the intermediate metal silicide; The second metal layer is annealed at low temperature and high temperature to obtain a metal silicide; A metal conductive layer is formed over the metal silicide to form a metal silicide layer between the semiconductor layer and the metal conductive layer. In the metal silicide layer, the metal content near the metal conductive layer is greater than the metal content near the semiconductor layer.

15. The method of producing a semiconductor device according to Claim 14, wherein The first metal layer and the second metal layer are the same metal, and both the first metal layer and the second metal layer include cobalt.

16. The method of fabricating a semiconductor device according to claim 14, wherein The metals of the first metal layer and the second metal layer are different. The first metal layer includes cobalt, and the second metal layer includes at least one of cobalt, nickel, or titanium.

17. The method of manufacturing a semiconductor device according to any one of Claims 14-16, wherein The thickness of the first metal layer is less than the thickness of the second metal layer.

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