Semiconductor structure and manufacturing method therefor

Abstract

Provided in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor. The method comprises: providing a first substrate having a central region and an edge region; forming a first dielectric layer covering the central region and the edge region, wherein in the direction away from the central region, the thickness of the first dielectric layer covering the edge region gradually decreases; forming a first filling layer covering the first dielectric layer in the edge region; and planarizing the first filling layer to form, on the surface of the first filling layer, a first edge region which is flush with the surface of the first dielectric layer in the central region. The semiconductor structure obtained in the embodiments of the present disclosure can effectively alleviate the problem of a large area of an uneven region in edge and central regions, thereby further increasing the effective usage area of the substrate.

Description

Semiconductor structure and manufacturing method

[0001] This disclosure claims priority to Chinese Patent Application No. 202411454625.5, filed on October 17, 2024, entitled "Semiconductor Structure and Manufacturing Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0003] With the rapid growth in data capacity demand, increasing packaging density to improve integration and thus obtain higher storage capacity has become an important goal of integrated circuit manufacturing at present. Under this prospect, 3D-IC (three-dimensional integrated circuit) technology has been widely used. It involves stacking and bonding wafers with the same or different functions together. This technology has the advantages of high performance, low cost and high integration.

[0004] Stacking bonding is a key process in 3D packaging technology, used to vertically stack multiple wafers or chips and achieve electrical interconnection. This technology can significantly improve chip integration density, shorten signal transmission paths, reduce power consumption, and reduce package size, making it an important technology in high-performance computing, storage, and mobile devices. The strength of the bonding surfaces directly affects the yield of the stacking bonding process. If there are bonding defects between the bonded surfaces, risks such as wafer cracking and bonding failure will exist in subsequent thinning or other processes. Summary of the Invention

[0005] This disclosure provides a semiconductor structure with higher integration and a method for manufacturing the same.

[0006] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] Some embodiments of this disclosure provide a method for manufacturing a semiconductor structure, including: providing a first substrate having a central region and an edge region; forming a first dielectric layer covering the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a first filling layer covering the first dielectric layer of the edge region; planarizing the first filling layer and forming a first edge region on the surface of the first filling layer that is flush with the surface of the first dielectric layer of the central region.

[0008] The method for manufacturing a semiconductor structure provided in some embodiments of this disclosure further includes: providing a second substrate having a central region and an edge region; forming a second dielectric layer covering the central region and the edge region on the second substrate, wherein the thickness of the second dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a second filling layer covering the second dielectric layer on the edge region; planarizing the second filling layer and forming a second edge region flush with the surface of the second dielectric layer in the central region on the surface of the second filling layer; and aligning and bonding the second substrate to a first substrate such that the central region of the first substrate is bonded to the central region of the second substrate, and the first edge region is bonded to the second edge region.

[0009] The method for manufacturing a semiconductor structure provided in some embodiments of this disclosure further includes: performing a first edge trimming on the bonded first substrate and second substrate, removing a portion of the edge region of the first substrate and a portion of the edge region of the second substrate, while also removing a portion of the first edge region and a portion of the second edge region; thinning the first substrate to form a first bond.

[0010] The method for manufacturing a semiconductor structure provided in some embodiments of this disclosure further includes: bonding a plurality of first bonds to each other to form a second bond.

[0011] In some embodiments of this disclosure, the method for manufacturing a semiconductor structure includes, before bonding multiple first bonding bodies to each other to form a second bonding body, and after thinning a first substrate, the method further includes: forming a first bonding surface on the surface of the thinned first substrate. The step of forming the first bonding surface includes: depositing a third dielectric layer covering a central region and an edge region on the surface of the thinned first substrate, wherein the thickness of the third dielectric layer gradually decreases in the direction away from the central region; depositing a third filler layer on the third dielectric layer in the edge region; planarizing the third filler layer; and forming a third edge region on the surface of the third filler layer that is flush with the surface of the third dielectric layer in the central region. Bonding multiple first bonding bodies to each other to form a second bonding body includes: bonding the central regions of multiple first bonding bodies to each other; and bonding the third edge regions of multiple first bonding bodies to each other.

[0012] The method for manufacturing a semiconductor structure provided in some embodiments of this disclosure further includes: performing a second edge trimming on the second bond, removing a portion of the edge region and a portion of the third edge region retained by the second substrate in each first bond after the first edge trimming, wherein the width of the edge region removed in the first edge trimming of the second substrate is the same as the width of the edge region removed in the second edge trimming.

[0013] In the semiconductor structure manufacturing method provided by some embodiments of this disclosure, after bonding the central regions of a plurality of first bonds to each other and bonding the third edge regions of a plurality of first bonds to each other, the method further includes: thinning a second substrate to form a second bond.

[0014] The method for manufacturing a semiconductor structure provided in some embodiments of this disclosure further includes: providing a third substrate having a central region and an edge region; forming a fourth dielectric layer covering the central region and the edge region, wherein the thickness of the fourth dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a fourth filling layer covering the fourth dielectric layer of the edge region; planarizing the fourth filling layer and forming a fourth edge region flush with the surface of the fourth dielectric layer of the central region on the surface of the fourth filling layer; forming a second bonding surface on the surface of the thinned second bond; and aligning and bonding the third substrate with the second bond, such that the central region and the fourth edge region of the third substrate are bonded to the second bonding surface.

[0015] In some embodiments of this disclosure, the method for manufacturing a semiconductor structure, after the second substrate and the first substrate are aligned and bonded, further includes filling a first bonding layer between the first substrate and the second substrate, wherein the first bonding layer at least covers the first dielectric layer, the second dielectric layer, and the unbonded surfaces of the first filling layer and the second filling layer.

[0016] In the semiconductor structure manufacturing method provided in some embodiments of this disclosure, after forming the first bonding layer, the first substrate is thinned to form the first bond.

[0017] The method for manufacturing a semiconductor structure provided in some embodiments of this disclosure further includes: bonding a plurality of first bonds together to form a second bond.

[0018] In some embodiments of this disclosure, the method for manufacturing a semiconductor structure includes, before bonding multiple first bonding bodies to each other to form a second bonding body, and after thinning a first substrate, the method further includes: forming a first bonding surface on the surface of the thinned first substrate. The step of forming the first bonding surface includes: depositing a third dielectric layer covering a central region and an edge region on the surface of the thinned first substrate, wherein the thickness of the third dielectric layer gradually decreases in the direction away from the central region; depositing a third filler layer on the third dielectric layer in the edge region; planarizing the third filler layer; and forming a third edge region on the surface of the third filler layer that is flush with the surface of the third dielectric layer in the central region. Bonding multiple first bonding bodies to each other to form a second bonding body includes: bonding the central regions of multiple first bonding bodies to each other; and bonding the third edge regions of multiple first bonding bodies to each other.

[0019] In the semiconductor structure manufacturing method provided by some embodiments of this disclosure, after the central regions of a plurality of first bonded bodies are bonded to each other and the third edge regions of a plurality of first bonded bodies are bonded to each other, a second bonding layer is filled between each first bonded body.

[0020] In the semiconductor structure manufacturing method provided by some embodiments of this disclosure, after forming a first dielectric layer covering the central region and the edge region and before forming a first filling layer covering the first dielectric layer of the edge region, the manufacturing method further includes: forming a first bonding pad in the first dielectric layer of the central region; and after forming the first bonding pad, planarizing the first dielectric layer such that the surface of the first bonding pad is flush with the surface of the first dielectric layer.

[0021] In some embodiments of this disclosure, the method for manufacturing a semiconductor structure, after forming a first edge region, further includes: forming a first bonding pad in a first dielectric layer, wherein the surface of the first bonding pad is flush with the surface of the first dielectric layer.

[0022] Some embodiments of this disclosure also provide a semiconductor structure, including: a first substrate having a central region and an edge region; a first dielectric layer covering the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region; and a first filling layer formed above the first dielectric layer in the edge region, the surface of the first filling layer being flush with the surface of the first dielectric layer in the central region.

[0023] The semiconductor structure provided in some embodiments of this disclosure further includes: a second substrate, the first substrate having a central region and an edge region; a second dielectric layer covering the central region and the edge region of the second substrate, wherein the thickness of the second dielectric layer covering the edge region gradually decreases in a direction away from the central region; a second filler layer formed above the second dielectric layer in the edge region, the surface of the second filler layer being flush with the surface of the second dielectric layer in the central region; the first dielectric layer in the central region of the first substrate being aligned and bonded to the second dielectric layer in the central region of the second substrate, and the first filler layer being aligned and bonded to the second filler layer.

[0024] The semiconductor structure provided in some embodiments of this disclosure further includes: a first bonding layer disposed between a bonded first substrate and a second substrate, wherein the first bonding layer at least covers the unbonded surfaces of the first filling layer and the second filling layer.

[0025] In the semiconductor structure provided by some embodiments of this disclosure, the maximum radial distance from the center region to the center of the center region is R1, the maximum radial distance from the first filling layer to the center of the center region is R2, and the maximum radial distance from the first bonding layer to the center of the center region is R3, wherein the difference between R2 and R1 is greater than the difference between R3 and R2.

[0026] The manufacturing method provided in this disclosure results in a semiconductor structure with a larger flat area, which can effectively improve the problem of large uneven areas at the edges and center, and further increase the effective usable area of ​​the substrate or wafer. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0028] Figure 1 is a flowchart illustrating the manufacturing method of a semiconductor structure provided in an embodiment of this disclosure; Figures 2-10 are cross-sectional views of a semiconductor structure provided in an embodiment of this disclosure; Figure 11 is a flowchart illustrating the manufacturing method of a semiconductor structure provided in an embodiment of this disclosure; Figures 12-18 are cross-sectional views of a semiconductor structure provided in an embodiment of this disclosure; Figure 19 is a flowchart illustrating the manufacturing method of a semiconductor structure provided in an embodiment of this disclosure; Figures 20-22 are cross-sectional views of a semiconductor structure provided in an embodiment of this disclosure; Figure 23 is a top cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0029] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0030] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant disclosure and not for limiting the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0031] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a schematic flowchart of a semiconductor structure manufacturing method provided in an embodiment of this disclosure. Referring to Figure 1, the method includes the following steps: S101, providing a first substrate, the first substrate having a central region and an edge region. Referring to Figure 2. In an embodiment of this disclosure, the first substrate can be a wafer substrate. As shown in Figure 2, the first substrate 10 has a central region 101 and an edge region 102, the edge region 102 surrounding the central region 101. The central region 101 can be a region in the first substrate 10 where a semiconductor device 20 is disposed, and the edge region 102 can be the outer peripheral edge region of the wafer where a semiconductor device is disposed or not.

[0033] Semiconductor device 20 may be a CMOS device, a memory device, and / or other passive device. The memory device may include volatile memory or non-volatile memory, and volatile memory may include, for example, DRAM. In some embodiments, when semiconductor device 20 is a DRAM memory device, it may be a memory element consisting of a transistor and a capacitor, or it may be a collection of multiple memory elements.

[0034] S102, a first dielectric layer is formed on the first substrate, covering the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in the direction away from the central region. Referring again to FIG2, a first dielectric layer 40 is formed on the first substrate 10, covering the central region 101 and the edge region 102. The central region 101 is also provided with an interconnect layer 30 electrically connected to the semiconductor device 20, the interconnect layer 30 being disposed within the first dielectric layer 40. A first bonding pad 70 is disposed within the first dielectric layer 40, the first bonding pad 70 having a surface exposed to the first dielectric layer 40.

[0035] In some embodiments, the formation of an isolation medium occurs during the formation of the interconnect layer 30. Therefore, the first dielectric layer 40 may be a dielectric layer formed after the interconnect layer 30 is formed. In this case, the first dielectric layer 40 is formed on the interconnect layer 30.

[0036] The interconnect layer 30 may include one or more conductive layers, vias connecting each conductive layer, and contact plugs connecting to the semiconductor device 20. The interconnect layer 30 may be made of a metallic material, such as tungsten, aluminum, or copper.

[0037] The first bonding pad 70 may include one or more conductive layers and vias connecting the conductive layers. The first bonding pad 70 may be made of a metallic material, such as copper, tin, gold, tungsten or their alloys.

[0038] The first dielectric layer 40 can be a stacked structure formed of isolation material, including interlayer dielectric layers, intermetallic dielectric layers, etc. The isolation material can be one or more combinations of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, LK dielectric material, etc., used to provide electrical isolation for each conductive layer, via, contact plug, etc. in the interconnect layer 30. When the first dielectric layer 40 is located on the interconnect layer 30, the first dielectric layer 40 can be a stacked structure or a single-layer structure formed of isolation material, mainly providing isolation for the first bonding pad 70 and providing a bonding dielectric surface.

[0039] The first substrate 10 also includes a through-hole interconnect structure 80, such as a TSV, that extends through the first substrate 10. The through-hole interconnect structure 80 is connected to the interconnect layer 30.

[0040] The central region 101 of the first substrate 10 has a relatively flat surface, while the edge region 102 is not as flat as the central region 101 and is a curved surface with a certain curvature. This is because, in the fabrication of the semiconductor device 20, multiple thin film deposition and photoresist spin coating processes are required. Due to the uneven distribution of deposited reactive gases or photoresists at the wafer center and wafer edge, the thickness of the material in the edge region differs from that in the central region. This may affect the accuracy of subsequent processes and the performance of the device. Therefore, the edge region of the wafer is usually not equipped with the same semiconductor devices as the central region, but may be equipped with some test structures to monitor process quality.

[0041] Because the surfaces of the central region 101 and the edge region 102 of the first substrate 10 are uneven, for the same reason, when the first dielectric layer 40 is formed, the thickness of the first dielectric layer 40 covering the edge region 102 gradually decreases in the direction away from the central region 101.

[0042] In some embodiments, the first substrate 10 may be a circular substrate or wafer, and the direction away from the central region 101 is the radial direction from the center of the first substrate 10 to the edge.

[0043] In some embodiments, because the surface of the first dielectric layer 40 at the edge region 102 is uneven compared to the surface at the center region 101, this unevenness will affect the yield of subsequent processes. For example, when the first substrate 10 is bonded to another substrate or wafer, this edge unevenness will lead to uneven bonding surfaces, which will directly cause bonding failure in the edge region 102, forming bonding smear. This failed bonding will cause material peeling (chipping) on ​​the unbonded edge region during subsequent processes, such as when the first substrate 10 is thinned. To prevent such problems, an edge trimming process can be used to remove the edge region 102 by cutting, as shown in Figure 3. An edge trimming process is performed on the first substrate 10 and the first dielectric layer 40 to remove the edge region 102 and the first dielectric layer 40 with an uneven surface on the edge region 102. For example, the edge region 102 with a width of D1 is removed, and only the central region 101 and its corresponding part are retained. Since the central region 101 has a relatively flat surface, the stability of subsequent processes can be guaranteed.

[0044] While edge trimming can eliminate yield issues caused by unevenness at the surface edges, the total area of ​​the substrate or wafer is limited and precious. For example, a 12-inch wafer typically has a diameter of 300 mm (approximately 11.81 inches), or a radius of about 150 mm. Research by the inventors of this disclosure has shown that when the radial distance varies from 147 mm or 147.5 mm to 150 mm, the thickness difference of the first dielectric layer 40 on its surface is no less than 2.5 micrometers. In other words, to eliminate edge unevenness, edge trimming requires removing at least 2.5 mm to 3 mm of radially spaced area from the edge of the first substrate. This means that the effective area in the first substrate used for fabricating semiconductor devices will be reduced.

[0045] In some embodiments, the edge trimming process can occur after the first substrate 10 and the other substrate have been bonded. As shown in FIG4, the other substrate has the same or similar structure as the first substrate 10. A semiconductor device 20' and an interconnect layer 30' connecting the semiconductor device 20' are disposed in the first dielectric layer 40' of the central region 101' of the other substrate. A first bonding pad 70' is disposed in the first dielectric layer 40'. A through-hole interconnect structure 80' is disposed in the other substrate, and the through-hole interconnect structure 80' is connected to the interconnect layer 30'.

[0046] When the first substrate 10 is bonded to the other substrate, the central region 101 and the central region 101' are aligned and bonded, realizing the bonding of the first bonding pad 70 to the first bonding pad 70' and the bonding of the first dielectric layer 40 to the first dielectric layer 40'. After bonding is completed, the edge region 102' of the other substrate 10' and the first dielectric layer 40' located on the edge region 102' are trimmed away through an edge trimming process. At the same time, the edge region 102 of the first substrate 10 and the first dielectric layer 40 on it are also trimmed, thereby removing the bonding failure area between the edge region 102 and the edge region 102'. The width of the trimmed area is also D1, thereby reducing the risk of subsequent processes.

[0047] In some embodiments, three or more substrates or wafers can be bonded to each other, as shown in FIG5, which illustrates a schematic diagram of three semiconductor substrates or wafers bonded to each other. Another substrate 200 is provided, having the same or similar structure as the first substrate 10. It has a central region 201 and an edge region 202, with a first dielectric layer 203 disposed in both the central and edge regions 201 and 202. A semiconductor device 204 and an interconnect layer 205 connecting the semiconductor device 204 are disposed in the first dielectric layer 203 of the central region 201. A first bonding pad 206 is disposed in the first dielectric layer 203, and a through-hole interconnect structure 207 is formed in the substrate 200 and connected to the interconnect layer 205. Before bonding substrate 10', another substrate on the first substrate 10 is thinned to expose the via interconnect structure 80'. Another bonding pad 70' is formed on the surface of the exposed via interconnect structure 80'. Using the thinned surface of the other substrate as the bonding surface, the other bonding pad 70' is bonded to the first bonding pad 206 on the surface of substrate 200. To ensure bonding effectiveness, the edges of substrate 200 are trimmed before bonding. The width of the trimmed area is D2, which is greater than D1. This is because it is difficult to keep the widths of the trimmed edges of substrate 200 and substrate 10 perfectly consistent. To avoid bonding defects caused by trimming errors, the edges of substrate 200 are generally trimmed further to ensure good bonding between substrate 200 and the surface of the other substrate. Therefore, when multiple substrates or wafers are stacked and bonded, the area of ​​the trimmed region on the substrate or wafer gradually increases to ensure bonding effectiveness. This results in wasted substrate or wafer area, a reduced number of effective chips on the substrate or wafer, and increased production costs.

[0048] After completing the interconnect layer 30 and the first dielectric layer 40, the manufacturing method of this embodiment further includes: S103, forming a first filler layer covering the first dielectric layer of the edge region. As shown in FIG6, a first filler layer 50 is deposited on the surface of the first dielectric layer 40 in the edge region 102. The formation of the first filler layer 50 can be achieved by means of an annular mold, which can be an annular ring covering the central region 101, that is, the central region 101 is covered by the annular ring, and the edge region 102 is exposed outside the annular ring, and then the first filler layer 50 is formed on the edge region 102 by deposition or other methods. The first filler layer 50 has a surface higher than the surface of the first dielectric layer 40 on the central region 101, that is, the first filler layer 50 has a portion protruding relative to the first dielectric layer 40 on the central region 101. The first filler layer 50 may include an oxide, such as silicon oxide. "Silicon oxide" is referred to herein as a compound containing silicon and oxygen atoms, including any and all stoichiometric possibilities of Si. x O y x and y can be integers or non-integers.

[0049] S104, planarize the first filler layer, forming a first edge region on the surface of the first filler layer that is flush with the surface of the first dielectric layer in the central region. As shown in Figure 7, after forming the first filler layer 50, a planarization process is performed to planarize the first filler layer 50, forming a first edge region 103 on the surface of the first filler layer 50. The first edge region 103 has a surface flush with the first dielectric layer 40 on the central region 101. Due to process limitations, this flushing can be completely flush or substantially flush. The planarization process can be chemical mechanical polishing (CMP) or etching planarization. The planarization process can also simultaneously planarize the first dielectric layer 40 on the central region 101, so that the first dielectric layer 40 and the first filler layer 50 on the central region 101 form a flat surface.

[0050] The manufacturing method provided in this disclosure results in a semiconductor structure with a larger flat surface area, effectively improving the problem of large uneven areas at the edges and further increasing the effective usable area of ​​the substrate or wafer. Taking a 12-inch wafer as an example, the edge region with a radial distance ranging from 147 mm or 147.5 mm to 150 mm has an uneven surface. After applying the manufacturing method of the above embodiment to this uneven region, the edge region with a radial distance ranging from 147 mm or 147.5 mm to 149 mm or 149.5 mm will obtain a surface flush with or relatively flush with the center region, effectively improving the morphology of the edge region.

[0051] In some embodiments, after forming a first dielectric layer covering the central region and the edge regions, and before forming a first filler layer covering the first dielectric layer covering the edge regions, a first bonding pad is further formed in the first dielectric layer covering the central region. The process of forming the first bonding pad is described in detail below with reference to the accompanying drawings. As shown in FIG8, a first dielectric layer 40 covering the central region 101 and the edge region 102 is formed. Referring again to FIG9, after forming the first dielectric layer 40, the first dielectric layer 40 is patterned, and a first bonding material layer 701 is formed in the first dielectric layer 40 covering the central region 101. The process of forming the first bonding material layer 701 can employ processes such as deposition and electroplating. After forming the first bonding material layer 701, the first bonding material layer 701 is planarized, and a first bonding pad 70 is formed in the first dielectric layer 40, which is isolated from each other and has a surface exposed to the first dielectric layer 40. The surface of the first bonding pad 70 is flush or substantially flush with the surface of the first dielectric layer 40, as shown in FIG2. In some embodiments, there is a specific height difference between the surface of the first bonding pad 70 and the surface of the first dielectric layer 40, which is also considered in this disclosure as a flush situation.

[0052] In some embodiments, after the first bonding pad 70 is formed, the steps of forming a first filling layer 50 on the surface of the first dielectric layer 40 on the edge region 102 of the first substrate 10 and subsequently planarizing the first filling layer 50 to form the first edge region 103 are performed, as shown in FIG6 and FIG7.

[0053] In the method for forming the first bonding pad provided in the above embodiments, the first bonding pad is formed before the first filler layer is formed. That is, a surface planarization process is performed to planarize the first bonding material and the first dielectric layer before the first filler layer is formed. After the first filler layer is formed, a planarization process is then performed on the surface of the first filler layer.

[0054] The embodiments of this disclosure also provide another method for forming the first bonding pad. The process of forming the first bonding pad is described in detail below with reference to the accompanying drawings. Referring first to Figures 6 and 7, a first dielectric layer 40 and a first filler layer 50 are first formed. Then, the first filler layer 50 is planarized, and a first edge region 103 flush with the surface of the first dielectric layer 40 in the central region 101 is formed on the surface of the first filler layer 50. During this planarization process, the surface of the first dielectric layer 40 in the central region 101 can also be planarized simultaneously.

[0055] Referring again to Figure 10, after planarizing the surfaces of the first dielectric layer 40 and the first filler layer 50 to form a first edge region 103, the first dielectric layer 40 is patterned, and a first bonding material layer 701 is formed in the first dielectric layer 40 in the central region 101. The formation of the first bonding material layer 701 can be achieved using processes such as deposition or electroplating. After forming the first bonding material layer 701, the first bonding material layer 701 is planarized, and first bonding pads 70, which are isolated from each other and have surfaces exposed to the first dielectric layer 40, are formed in the first dielectric layer 40. The surfaces of the first bonding pads 70 are flush with or substantially flush with the surface of the first dielectric layer 40, as shown in Figure 7.

[0056] In the method for forming the first bonding pad provided in the above embodiments, the first bonding pad is formed after the surface of the first filler layer is planarized to make the surface of the first filler layer substantially flush with the surface of the first dielectric layer. That is, there is no need to perform a surface planarization process on the first dielectric layer before forming the first filler layer, saving the cost of the planarization process. After the first filler layer is formed, a single surface planarization process can be performed to make the surfaces of the first filler layer and the first dielectric layer substantially flush. After the first bonding material layer is formed, another surface planarization process is performed to obtain the first bonding pad.

[0057] In some embodiments, the first bonding pad further includes a portion of the first bonding pad connected to the interconnect layer and a portion of the first bonding pad not connected to the interconnect layer. The portion of the first bonding pad connected to the interconnect layer is used to extract interconnect layer signals, while the portion of the first bonding pad not connected to the interconnect layer is mainly provided to increase the density of the first bonding pad or for other bonding performance considerations. In some embodiments, the first bonding pads of this disclosure may also be entirely connected to the interconnect layer, without being limited to the structure shown in the figures.

[0058] Other embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, as shown in FIG11, which is a schematic flowchart of the method for manufacturing a semiconductor structure provided in the embodiments of this disclosure. The steps are listed below.

[0059] S201 provides a second substrate having a central region and an edge region.

[0060] S202, a second dielectric layer covering the central region and the edge region is formed on the second substrate, and the thickness of the second dielectric layer covering the edge region gradually decreases in the direction away from the central region.

[0061] S203, a second filling layer covering the second dielectric layer is formed on the edge region.

[0062] S204, planarize the second filler layer, and form a second edge region on the surface of the second filler layer that is flush with the surface of the second dielectric layer in the central region.

[0063] The second substrate can adopt the same structure and the same manufacturing method as the first substrate. Steps S201 to S204 correspond to steps S101 to S104. Therefore, steps S201 to S204 will not be described in detail here.

[0064] The specific structure of the second substrate is shown in Figure 12. The second substrate 11 includes a central region 111 and an edge region 112, with the edge region 112 surrounding the central region 111. A second dielectric layer 41 is formed simultaneously in the central region 111 and the edge region 112. The thickness of the second dielectric layer 41 on the edge region 112 gradually decreases in the direction away from the central region 111. A second filler layer 51 is formed on the surface of the second dielectric layer 41 on the edge region 112, and it has a second edge region 113 flush with the surface of the second dielectric layer 41 in the central region 111. The material of the second filler layer 51 and the first filler layer 50 can be the same. A semiconductor device 21 is also disposed in the central region 111, while a semiconductor device may or may not be disposed in the edge region 112. The semiconductor device 21 can be the same type as the semiconductor device 20, or it can be a different type of device. The central region 111 also includes an interconnect layer 31 connecting the semiconductor device 21, and the interconnect layer 31 is disposed in the second dielectric layer 41. Interconnect layer 31 can have the same structure and be obtained using the same process as interconnect layer 30; a second bonding pad 71 is disposed in the second dielectric layer 41 of the central region 111, and the second bonding pad 71 is connected to interconnect layer 31. The second bonding pad 71 can have the same structure and be obtained using the same process as the first bonding pad 70. The central region 111 of the second substrate 11 also includes a through-hole interconnect structure 81 that penetrates the second substrate 11, and the interconnect layer 31 is connected through the interconnect structure 81.

[0065] Referring again to Figures 11 and 12, after the first substrate and the second substrate have been processed, step S301 is performed, that is, the first substrate and the second substrate are aligned and bonded, so that the central region of the first substrate is bonded to the central region of the second substrate, and the first edge region is bonded to the second edge region.

[0066] The central regions of the first substrate and the central regions of the second substrate can be bonded using a direct dielectric-to-dielectric bonding process, or using a dielectric-to-dielectric or metal-to-metal bonding process. For example, the first bonding pad in the central region of the first substrate and the second bonding pad in the central region of the second substrate can be bonded to each other. The first edge region and the second edge region can be bonded using a direct dielectric-to-dielectric bonding process.

[0067] Referring again to Figures 11 and 13, after bonding the first substrate and the second substrate, step S302 is performed: a first edge trimming is performed on the bonded first and second substrates, removing a portion of the edge regions of the first substrate and the second substrate, and thinning the first substrate to form a first bonded body. During the first edge trimming process, a portion of the first edge region and a portion of the second edge region are also removed, ultimately forming the first bonded body 200. The width of the first edge trimming is D3. The edge region 102 of the first substrate 10 is partially removed, while a portion of the edge region 102 is retained; the first edge region 103 is also partially removed, retaining a portion of the first filler layer 50. The edge region 112 of the second substrate 11 is also partially removed, while a portion of the edge region 112 is retained; the second edge region 113 is also partially removed, retaining a portion of the second filler layer 51. The retained portions of the first filler layer 50 and the retained portions of the second filler layer 51 are bonded to each other. In some embodiments, the first edge region 103 and the second edge region 113 can also be entirely retained; that is, the first edge trimming only requires removing a portion of the edge regions 102 and 112 other than the first edge region 103 and the second edge region 113. Trimming and removing a portion of the first edge region 103 and a portion of the second edge region 113 after the first substrate 10 and the second substrate 11 are bonded can further improve the yield of the bonded edges.

[0068] In some embodiments, continuing to refer to FIG13, after the first edge trimming, the first substrate is thinned to expose the other end of the via interconnect structure 80 in the central region 101 of the first substrate 10, and the first substrate 10 reaches a predetermined thickness, thereby forming the first bond 200. The thinning process mainly includes two methods: grinding and chemical mechanical polishing (CMP). Grinding removes material from the wafer surface mechanically to achieve thinning. Chemical mechanical polishing is a finer thinning method that combines the effects of chemical reaction and mechanical friction, enabling high-precision thinning and planarization. CMP can provide higher surface quality and more precise thickness control, but the process is relatively slow and costly. The first bond formed after thinning the first substrate can be further used for three-dimensional packaging to obtain products with smaller package sizes and higher integration.

[0069] In some embodiments, after forming the first bond 200, the first bond 200 is further monolithized using a cutting tool, such as a cutting blade or a laser.

[0070] Referring again to Figures 11 and 14, after forming the first bonded body 200, step S303 is performed to form a first bonding surface on the surface of the thinned first substrate. The specific process for forming the first bonding surface is as follows:

[0071] As shown in Figure 14, a third dielectric layer 42 covering the central region 101 and the edge region 102 is formed on the thinned surface of the first substrate 10. The third dielectric layer 42 has a gradually decreasing thickness in the direction away from the central region 101; that is, the thickness of the third dielectric layer 42 above the edge region 102 gradually decreases with increasing radial distance. This is because, during the thinning process of the first substrate 10, the surface of the edge region 102 will still be uneven with the central region 101. Even if the central region 101 and the edge region 102 of the first substrate 10 are flush with each other, after the formation of the third dielectric layer 42, surface planarization processing is required. Again, due to process limitations, the thickness of the third dielectric layer 42 in the edge region 102 will decrease with increasing radial distance. Therefore, after forming the third dielectric layer 42, a third filler layer 52 is covered over the third dielectric layer 42 in the edge region 102 to planarize the third filler layer 52, thereby forming a third edge region 213 on the surface of the third filler layer 52 in the edge region 102 that is flush with the surface of the third dielectric layer 42 in the central region 101. A first bonding surface 201 is formed on the surfaces of the third edge region 213 and the third dielectric layer 42 in the central region 101.

[0072] The third dielectric layer 42 may have the same composition and be formed using the same process as the first dielectric layer 40 and the second dielectric layer 41, and the third filler layer 52 may have the same composition and be formed using the same process as the first filler layer 50 and the second filler layer 51.

[0073] The process of forming the first bonding surface 201 also includes the process of forming the third bonding pad 702. The third bonding pad 702 is formed in the third dielectric layer 42. The formation of the third bonding pad 702 can refer to the aforementioned process of forming the first bonding pad 70, and will not be repeated here.

[0074] Referring again to Figures 11, 15 and 16, after the first bonding surface is formed, step S304 is performed to bond multiple first bonding bodies together to form a second bonding body.

[0075] As shown in Figure 15, two first bonded bodies 200 are bonded to each other through first bonding surfaces 201 to form a second bonded body 1. That is, the third dielectric layers 42 of the central region 101 are aligned and bonded to each other, and the third filling layers 52 of the third edge region 213 are bonded to each other. The bonding of the central regions 101 can include dielectric-to-dielectric direct bonding and metal-to-metal direct bonding, such as the bonding of the third dielectric layers 42 and the bonding of the third bonding pads 702. The bonding of the third edge region 213 can include dielectric-to-dielectric direct bonding.

[0076] Figure 15 illustrates two first bonded bodies bonded together. In some embodiments, two or more first bonded bodies can be bonded together to form a bonded body with higher integration. The bonded body with higher integration can be obtained by bonding multiple second bonded bodies or by bonding two or more first bonded bodies. Whether it is a bonded body with two or more first bonded bodies or a bonded body with multiple second bonded bodies, the steps of thinning and forming the third dielectric layer and the third filler layer described above are repeated to form the first bonding surface, which will not be repeated here. In some embodiments, the bonded body with higher integration includes four or more first bonded bodies or two or more second bonded bodies.

[0077] In some embodiments, in step S302, during the thinning of the first substrate, the structure to be bonded in the first substrate is exposed. After the thinning is completed, multiple first bonding bodies can be directly bonded, thereby omitting the step of forming the first bonding surface and saving process costs.

[0078] Referring again to Figure 16, after the two first bonding bodies 200 are bonded together to form the second bonding body 1, the second bonding body 1 undergoes a second edge trimming. This involves removing a portion of the edge region 112 and a portion of the third edge region 213 of the second substrate 10 retained after the first edge trimming in each of the first bonding bodies 200, thus completing the second edge trimming. The width of the second edge trimming is D4. In some embodiments, the width D3 of the first edge trimming is the same as the width D4 of the second edge trimming. This is because, since the surface of each first bonding body 200 forms a flat first bonding surface extending to the edge region 102, a third edge region 213 flush with the third dielectric layer 52 of the central region 101 is formed in the edge region 102 of the first substrate 10 by forming a third filling layer 52. This ensures that the two first bonding bodies can achieve stable bonding through the first bonding surface, eliminating the need to remove more edge regions during the second edge trimming process. This ensures bonding yield while avoiding wasting the usable area of ​​the substrate or wafer due to edge trimming.

[0079] Referring again to Figure 17, in some embodiments, after the second edge trimming of the second bond 1 is completed, the second substrate 11 is further thinned to a target thickness to ultimately form the second bond 1. Thinning the second substrate 11 means that the via interconnect structure 81 in the second substrate 11 is exposed from the other side of the second substrate 11. Figure 17 shows a schematic diagram of the structure after partial thinning of the second substrate 11. In some embodiments, all of the second substrates 11 in the second bond 1 are thinned. In some embodiments, the second substrate 11 is thinned to the same thickness as the first substrate 10.

[0080] In some embodiments, after the second bond body is formed, multiple second bond bodies can be bonded together to form a bond structure with higher integration. Before each second bond body is bonded, the same process steps as those for forming the first bond surface can be used to form the bond surface of each second bond body to achieve the bonding of each second bond body. The specific implementation process will not be described in detail.

[0081] In some embodiments, after forming the second bond 1, the second bond 1 is further monolithized using a cutting tool, such as a cutting blade or a laser.

[0082] In some embodiments, after the second bond is formed, a third substrate is provided and bonded to the second bond, as shown in FIG17, which is a schematic diagram of the structure of the third substrate and the second bond. The third substrate 12 includes a central region 121 and an edge region 122, with the edge region 122 surrounding the central region 121. A fourth dielectric layer 43 is formed simultaneously in the central region 121 and the edge region 122, and the thickness of the fourth dielectric layer 43 on the edge region 122 gradually decreases in the direction away from the central region 121. A fourth filler layer 53 is formed on the surface of the fourth dielectric layer 43 on the edge region 122, having a fourth edge region 313 flush with the surface of the fourth dielectric layer 43 in the central region 121. The material of the fourth filler layer 53 and the first filler layer 50 can be the same. A semiconductor device 22 is also disposed in the central region 121, and a semiconductor device may or may not be disposed in the edge region 122. The semiconductor device 22 can be the same type of device as the semiconductor device 20, or it can be a different type of device. The semiconductor device 22 shown in Figure 14 differs from semiconductor devices 20 and 21. The central region 121 also includes an interconnect layer 32 connecting the semiconductor device 22, which is disposed within a fourth dielectric layer 43. The interconnect layer 32 may be an interconnect layer composed of multiple layers of metal wires. A fourth bonding pad 72 is disposed in the fourth dielectric layer 43, and the fourth bonding pad 72 may or may not be connected to the interconnect layer 32. A through-hole interconnect structure 82 penetrating the third substrate 12 is disposed in the central region 121 of the third substrate 12, and the through-hole interconnect structure 82 is connected to the interconnect layer 32.

[0083] The third substrate 12 has the same structural features as the first substrate 10 and the second substrate 11. The fourth dielectric layer 43, the fourth filling layer 53 and the fourth edge region 313 are formed by the same method as the method for forming each filling layer and each edge region on the surface of the first substrate 10 and the second substrate 11 in the previous embodiment. The fourth bonding pad 72 has the same method as the first bonding pad 70, and will not be described again here.

[0084] Referring again to Figure 17, after thinning the second substrate 11 in the second bonding body, a second bonding surface 202 is formed on the surface of the thinned second substrate 11. The method for forming the second bonding surface 202 can refer to the method for forming the first bonding surface 201 shown in Figure 11. The second bonding surface 202 includes the surface of the fifth dielectric layer 44 located on the central region 111 of the second substrate 11, the surface of the fifth filling layer 54 located on the edge region 112 of the second substrate 11, and a fifth bonding pad 703 located in the fifth dielectric layer 44. The fifth bonding pad 703 is connected to the via interconnect structure 81 in the central region 111 of the second substrate 11. The structure and formation method of the fifth bonding pad 703 are the same as those of the third bonding pad 702, and will not be described again here.

[0085] After the second bond 1 is bonded to the third substrate 12, a third edge trimming is performed, and the semiconductor structure shown in Figure 18 is finally obtained. During the third edge trimming, a portion of the edge region 122 of the third substrate 12 and the portion of the second bonding surface 202 of the second bond 1 that is not fully bonded to the fourth edge region on the third substrate 12 are removed. The width of the third edge trimming is the same as the width of the first edge trimming and the second edge trimming.

[0086] In some embodiments, the semiconductor devices in the second bonding body 1 are memory devices, such as DRAM, and the semiconductor devices in the third substrate 12 are logic devices.

[0087] In some embodiments, after the second bond body is bonded to the third substrate, the bonding structure formed by the second bond body and the third substrate is further monolithized using a cutting tool, such as a cutting blade or a laser.

[0088] This disclosure also provides a schematic flowchart of another semiconductor structure manufacturing method. Referring to Figures 11 and 19, after the first substrate and the second substrate are aligned and bonded, i.e. after step S301, step S401 is performed on the bonded first substrate and the second substrate.

[0089] S401, a first bonding layer is filled between the first substrate and the second substrate. The first bonding layer at least covers the first dielectric layer, the second dielectric layer, and the unbonded surfaces of the first filler layer and the second filler layer. As shown in Figure 20, Figure 20 is a schematic diagram of the structure after the first substrate 10 and the second substrate 11 in Figure 12 have been bonded. The first bonding layer 60 is formed between the first substrate 10 and the second substrate 11. Specifically, the first bonding layer 60 is formed between the bonded first substrate 10 and the second substrate 11, and at least covers the unbonded surfaces of the first dielectric layer 40, the second dielectric layer 41, and the first filler layer 50 and the second filler layer 51. Since the outer surface of part of the first dielectric layer 40 in the edge region 102 of the first substrate 10 is not completely covered by the first filling layer 50 when the first filling layer 50 is formed, the outer surface of part of the first dielectric layer 40 in the edge region 102 of the first substrate 10 after bonding and the unbonded surface of the first filling layer 50 will be exposed. Similarly, after the second filling layer 51 is formed, the outer surface of part of the second dielectric layer 41 in the edge region 112 of the second substrate 11 and the unbonded surface of the second filling layer 51 will also be exposed.

[0090] In some embodiments, after forming the first bonding layer, step S402 is performed to thin the first substrate to form the first bond. Continuing to refer to FIG20, after forming the first bonding layer 60, a thinning process is performed on the first substrate 10 to form the first bond 300. The thinning of the first substrate 10 is performed from the surface away from the first dielectric layer 40, and the thinning process mainly includes grinding and chemical mechanical polishing (CMP). The purpose is to thin the first substrate 10 to a target thickness to meet the requirements of product miniaturization.

[0091] In some embodiments, the first bonding layer 60 is a material with good flowability that can fill well between the first substrate 10 and the second substrate 11, such as an underfill adhesive. The first bonding layer 60 can be applied between the first substrate 10 and the second substrate 11 by a dispensing process.

[0092] In embodiments of this disclosure, by applying a first bonding layer between the bonded first substrate and the second substrate, a support layer can be further formed between the edge regions of the first substrate and the second substrate to fill and support the edge regions of the first substrate and the second substrate, thereby further improving the edge stability of the first bond.

[0093] In some embodiments, after forming the first bonded body 300, step S403 is performed to bond multiple first bonded bodies together to form a second bonded body. As shown in FIG21, FIG21 is a schematic diagram of the structure of the second bonded body 400 formed after the two first bonded bodies 300 shown in FIG20 are bonded. In some embodiments, before bonding the two first bonded bodies 300, a first bonding surface is first formed on the thinned surface of the first substrate 10 in the first bonded body 300. The specific process of forming the first bonding surface is the same as FIG15 and its corresponding description, and will not be repeated here.

[0094] Referring again to Figure 21, after the bonding of the two first bonded bodies 300 is completed, that is, after the central regions of each first bonded body 300 are bonded to each other and the third edge regions of each first bonded body 300 are bonded to each other, a second bonding layer 61 is filled into the gap between the two first bonded bodies 300 to form a second bonded body 400. The material and formation method of the second bonding layer 61 are the same as those of the first bonding layer 60, and will not be described again here.

[0095] In some embodiments, after the second bonded body 400 is formed, the thickness of the second substrate 11 is further reduced to form a bonding surface on the surface of the second substrate 11, thereby achieving the bonding of multiple second bonded bodies 400. The formation of the bonding surface on the surface of the second substrate 11 can refer to the aforementioned process for forming the second bonding surface, and will not be repeated here. After the multiple second bonded bodies 400 are bonded, a third bonding layer can be filled between the bonded bodies. The formation process and material of the third bonding layer are the same as those of the first and second bonding layers.

[0096] In some embodiments, multiple second bond bodies 400 can be further bonded to form a bond structure with higher integration.

[0097] In some embodiments, before further bonding of the plurality of second bond bodies 400, the second bond bodies 400 are further thinned. The thinning of the second bond body 400 can be performed on only one side of the second substrate 11, or on both sides of the second bond body 400. As shown in FIG22, FIG22 is a schematic diagram of the structure obtained after thinning both sides of the second bond body 400. A fourth dielectric layer 43, a fourth filler layer 53, and a fifth bonding pad 703 are formed on the surface of the thinned second substrate 11. The fourth dielectric layer 43, the fourth filler layer 53, and the fifth bonding pad 703 are used for subsequent bonding between the plurality of second bond bodies 400.

[0098] In some embodiments, after forming the second bond 400, the second bond 400 is further monolithized using a cutting tool, such as a cutting blade or a laser.

[0099] In the above embodiments, during the formation of the first bond body 300 and the second bond body 400, in addition to improving the bonding effect between the substrates by utilizing each filler layer, each bonding layer is further formed in the gaps of the bond body to cover and fix the uneven parts that still exist at the edges of each substrate. Thus, the edge trimming of each bond body can be omitted because the unbonded or not firmly bonded parts at the edges of each substrate have been fixed by each bonding layer. In subsequent thinning and other processing steps, the problem of edge material peeling will not occur, thereby eliminating the edge trimming step and reducing production costs.

[0100] In some embodiments, referring to Figures 20 and 23, Figure 23 is a cross-sectional top view along the A1-A2 direction in Figure 20. The first substrate 10 includes a first dielectric layer 40 disposed on a central region 101 and a first filler layer 50 disposed on an edge region 102. A first bonding layer 60 is also disposed around the first filler layer 50. A plurality of first bonding pads 70 are disposed in the first dielectric layer 40. The first bonding pads 70 can be uniformly or non-uniformly distributed in the first dielectric layer 40, and their shape can be circular, rectangular, or other shapes. The outermost edge of the first dielectric layer 40 in the central region 101 has a radial distance R1 to the center of the first substrate 10. The maximum radial distance from the outermost edge of the first filler layer 50 to the center of the central region 101 of the first substrate 10 is R2. The maximum radial distance from the outermost edge of the first bonding layer 60 to the center of the central region 101 of the first substrate 10 is R3, wherein the difference between R3 and R2 is less than the difference between R2 and R1. Taking a 12-inch wafer as an example, the difference between R2 and R1 ranges from 1.5mm to 2.5mm, and the difference between R3 and R2 ranges from 0.1mm to 0.5mm. That is, the value of R1 ranges from 147mm to 147.5mm, the value of R2 ranges from 148.5mm to 149.5mm, and the value of R3 is greater than or equal to 150mm. Therefore, in this embodiment, by forming the first filling layer 50, a flat area with a width of 1.5mm to 2.5mm can be formed on the edge region 102, improving the bonding stability of the edge region of the first substrate 10. The 0.5mm non-flat area at the outermost edge can be leveled and sealed by filling with the first bonding layer, eliminating the need for edge trimming of the first substrate 10 and improving the bonding yield.

[0101] Embodiments of this disclosure also provide a semiconductor structure. As shown in FIG7, the semiconductor structure includes: a first substrate 10 having a central region 101 and an edge region 102 surrounding the central region 101. In some embodiments, the first substrate 10 may be a wafer or a portion of a wafer, the central region 101 may be a region in the wafer or a portion of the wafer in which a semiconductor device 20 is disposed, and the edge region 102 may be an edge region of the wafer or a portion of the wafer, wherein the semiconductor device 20 may not be disposed.

[0102] A first dielectric layer 40 covers a central region 101 and an edge region 102, wherein the thickness of the first dielectric layer 40 covering the edge region 102 gradually decreases in the direction away from the central region 101. That is, the thickness of the first dielectric layer 40 on the edge region 102 is non-uniform, and the thickness of the first dielectric layer 40 on the edge region 102 is smaller the further away from the central region 101 it is.

[0103] A first filler layer 50 is formed above the first dielectric layer 40 in the edge region 102, that is, the first filler layer 50 covers the first dielectric layer 40 in the edge region 102. The surface of the first filler layer 50 is flush with the surface of the first dielectric layer 40 in the center region 101. Here, "flush" can mean that the surfaces of the two are substantially flush or that the height difference between the surfaces of the two is within a predetermined range.

[0104] In some embodiments, another semiconductor structure is provided, as shown in FIG13, which further includes a second substrate 11 having a central region 111 and an edge region 112 surrounding the central region 111. The second substrate 11 has the same or similar structural features as the first substrate 10. The central region 111 may be a region of a wafer or a portion thereof where a semiconductor device 21 is disposed, and the edge region 112 may be an edge region of a wafer or a portion thereof, wherein a semiconductor device 21 may not be disposed. The semiconductor device 21 and the semiconductor device 20 may be the same type of semiconductor device or different types of semiconductor devices.

[0105] A second dielectric layer 41 covers the central region 111 and the edge region 112. The thickness of the second dielectric layer 41 covering the edge region 112 gradually decreases in the direction away from the central region 111. That is, the thickness of the second dielectric layer 41 on the edge region 112 is non-uniform, and the thickness of the second dielectric layer 41 on the edge region 112 is smaller the further away from the central region 111.

[0106] A second filler layer 51 is formed above the second dielectric layer 41 in the edge region 112, that is, the second filler layer 51 covers the second dielectric layer 41 in the edge region 112. The surface of the second filler layer 51 is flush with the surface of the second dielectric layer 41 in the central region 111. Here, "flush" can mean that the surfaces of the two layers are substantially flush or that the height difference between the surfaces of the two layers is within a predetermined range.

[0107] The first dielectric layer 40 of the central region 101 of the first substrate 10 is aligned and bonded to the second dielectric layer 41 of the central region of the second substrate 11, and the first filling layer 50 and the second filling layer 51 are aligned and bonded to form a semiconductor structure.

[0108] In some embodiments, the semiconductor structure further includes a first bonding pad. As shown in FIG7, an interconnect layer 30 is further disposed in the central region 101 of the first substrate 10. The interconnect layer 30 is connected to the semiconductor device 20. The first bonding pad 70 is formed in the first dielectric layer 40 and passes through the first dielectric layer 40 to connect with the interconnect layer 30. In some embodiments, the first bonding pad 70 may not be connected to the interconnect layer 30. The first bonding pad 70 is used for the signal outgoing structure of the interconnect layer 30 in the central region of the first dielectric layer 40 and for subsequent bonding interconnection structures.

[0109] In some embodiments, the semiconductor structure further includes a second bonding pad, as shown in Figures 13 to 18, where the second bonding pad 71 is aligned and bonded to the first bonding pad 70. The second bonding pad 71 is connected to an interconnect layer 31 disposed in the central region 111 of the second substrate 11, and the interconnect layer 31 is connected to the semiconductor device 21. The second bonding pad 71 is disposed in the second dielectric layer 41, passes through the second dielectric layer 41, and is connected to the interconnect layer 31. The first bonding pad 70 and the second bonding pad 71 bonded in the semiconductor structure realize the electrical connection between the semiconductor device 20 and the semiconductor device 21.

[0110] Referring again to Figures 7 and 13 through 18, in some embodiments, the semiconductor structure further includes a through-hole interconnect structure 80 disposed in the first substrate 10 and a through-hole interconnect structure 81 disposed in the second substrate 11. The through-hole interconnect structure 80 is disposed in the central region 101 of the first substrate 10, penetrates or partially penetrates the first substrate 10, and is connected to the interconnect layer 30, ultimately connected to the first bonding pad 70. The through-hole interconnect structure 81 is disposed in the central region 111 of the second substrate 11, penetrates or partially penetrates the second substrate 11, and is connected to the interconnect layer 31, ultimately connected to the second bonding pad 71.

[0111] In some embodiments, the semiconductor structure further includes a first bonding layer, as shown in Figures 20 to 23. The first bonding layer 60 is disposed between the bonded first substrate 10 and second substrate 11, and the first bonding layer 60 at least covers the unbonded surfaces of the first filler layer 50 and the second filler layer 51. In some embodiments, the first bonding layer 60 covers portions of the outer edges of the first filler layer 50 and the second filler layer 51. The first bonding layer 60 also covers portions of the outer edges of the first dielectric layer 40 and the second dielectric layer 41. In some embodiments, the material of the first bonding layer 60 may be a flowable filler material, such as an underfill adhesive.

[0112] In some embodiments, referring to Figures 20 and 23, the maximum radial distance from the center region 101 of the first substrate 10 to the center of the center region 101 in the semiconductor structure is R1, the maximum radial distance from the first filling layer 50 to the center of the center region 101 is R2, and the maximum radial distance from the first bonding layer 60 to the center of the center region 101 is R3, wherein the difference between R2 and R1 is greater than the difference between R3 and R2. In some embodiments, the difference between R2 and R1 ranges from 1.5 mm to 2.5 mm, and the difference between R3 and R2 ranges from 0.1 mm to 0.5 mm.

[0113] In some embodiments, the number of first and second substrates in the semiconductor structure can be multiple, such as 6, 8, 12 or even more.

[0114] The semiconductor structure provided in this disclosure has a first filling layer in the edge region that is flush with the surface of the central region, which can further increase the surface area of ​​the flat area in the edge region and improve the bonding yield during subsequent surface bonding.

[0115] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A first substrate (10) is provided, the first substrate (10) having a central region (101) and an edge region (102); A first dielectric layer (40) is formed covering the central region (101) and the edge region (102), wherein the thickness of the first dielectric layer (40) covering the edge region (102) gradually decreases in the direction away from the central region (101); A first filling layer (50) is formed to cover the first dielectric layer (40) covering the edge region (102); The first filler layer (50) is planarized, and a first edge region (103) is formed on the surface of the first filler layer (50) that is flush with the surface of the first dielectric layer (40) of the central region (101).

2. The manufacturing method according to claim 1, characterized in that, Also includes: A second substrate is provided, the second substrate having a central region and an edge region; A second dielectric layer covering the central region and the edge region is formed on the second substrate, and the thickness of the second dielectric layer covering the edge region gradually decreases in the direction away from the central region; A second filler layer covering the second dielectric layer is formed on the edge region; The second filler layer is planarized, and a second edge region is formed on the surface of the second filler layer that is flush with the surface of the second dielectric layer in the central region. The second substrate is aligned and bonded to the first substrate such that the central region of the first substrate is bonded to the central region of the second substrate, and the first edge region is bonded to the second edge region.

3. The manufacturing method according to claim 2, characterized in that, Also includes: The first substrate and the second substrate after bonding are subjected to a first edge trimming, which removes part of the edge region of the first substrate and part of the edge region of the second substrate, and at the same time, part of the first edge region and part of the second edge region are also removed; The first substrate is thinned to form a first bond.

4. The manufacturing method according to claim 3, characterized in that, Multiple first bonds are bonded together to form a second bond.

5. The manufacturing method according to claim 4, characterized in that, Before joining multiple first bonds together to form a second bond, after thinning the first substrate, the method further includes: forming a first bonding surface on the surface of the thinned first substrate, wherein the step of forming the first bonding surface includes: A third dielectric layer is deposited on the surface of the thinned first substrate, covering the central region and the edge region, wherein the thickness of the third dielectric layer gradually decreases in the direction away from the central region; A third filler layer is deposited on the third dielectric layer in the edge region, the third filler layer is planarized, and a third edge region is formed on the surface of the third filler layer that is flush with the surface of the third dielectric layer in the central region. Bonding a plurality of first bonded bodies together to form a second bonded body includes: bonding the central regions of the plurality of first bonded bodies together, and bonding the third edge regions of the plurality of first bonded bodies together.

6. The manufacturing method according to claim 5, characterized in that, Also includes: The second bond is subjected to a second edge trimming, which removes a portion of the edge region and a portion of the third edge region retained by the second substrate in each of the first bonds after the first edge trimming, wherein the width of the edge region removed by the second substrate in the first edge trimming is the same as the width of the edge region removed in the second edge trimming.

7. The manufacturing method according to claim 5, characterized in that, After bonding the central regions of the plurality of first bonded bodies to each other and bonding the third edge regions of the plurality of first bonded bodies to each other, the method further includes: thinning the second substrate to form the second bonded body.

8. The manufacturing method according to claim 7, characterized in that, A third substrate is provided, the third substrate having a central region and an edge region; A fourth dielectric layer is formed covering the central region and the edge region, wherein the thickness of the fourth dielectric layer covering the edge region gradually decreases in the direction away from the central region; A fourth filler layer is formed to cover the fourth dielectric layer of the edge region; The fourth filler layer is planarized, and a fourth edge region is formed on the surface of the fourth filler layer that is flush with the surface of the fourth dielectric layer in the central region; A second bonding surface is formed on the surface of the thinned second bond body; The third substrate is aligned and bonded to the second bonding body, such that the central region and the fourth edge region of the third substrate are bonded to the second bonding surface.

9. The manufacturing method according to claim 2, characterized in that, After the second substrate is aligned and bonded to the first substrate, the process further includes: A first bonding layer is filled between the first substrate and the second substrate, the first bonding layer at least covering the first dielectric layer, the second dielectric layer and the unbonded surfaces of the first filling layer and the second filling layer.

10. The manufacturing method according to claim 9, characterized in that, After the first bonding layer is formed, the first substrate is thinned to form the first bond.

11. The manufacturing method according to claim 10, characterized in that, Multiple first bonds are joined together to form a second bond.

12. The manufacturing method according to claim 11, characterized in that, Before joining multiple first bonds together to form a second bond, after thinning the first substrate, the method further includes: forming a first bonding surface on the surface of the thinned first substrate, wherein the step of forming the first bonding surface includes: A third dielectric layer is deposited on the surface of the thinned first substrate, covering the central region and the edge region, wherein the thickness of the third dielectric layer gradually decreases in the direction away from the central region; A third filler layer is deposited on the third dielectric layer in the edge region, the third filler layer is planarized, and a third edge region is formed on the surface of the third filler layer that is flush with the surface of the third dielectric layer in the central region. Bonding a plurality of first bonded bodies together to form a second bonded body includes: bonding the central regions of the plurality of first bonded bodies together, and bonding the third edge regions of the plurality of first bonded bodies together.

13. The manufacturing method according to claim 12, characterized in that, After the central regions of the plurality of first bonded bodies are bonded to each other and the third edge regions of the plurality of first bonded bodies are bonded to each other, a second bonding layer is filled between each of the first bonded bodies.

14. The manufacturing method according to any one of claims 1-13, characterized in that, After forming a first dielectric layer covering the central region and the edge region, and before forming a first filler layer covering the first dielectric layer covering the edge region, the manufacturing method further includes: A first bonding pad is formed in the first dielectric layer in the central region; After the first bonding pad is formed, the first dielectric layer is planarized so that the surface of the first bonding pad is flush with the surface of the first dielectric layer.

15. The manufacturing method according to any one of claims 1-13, characterized in that, After forming the first edge region, the manufacturing method further includes: A first bonding pad is formed in the first dielectric layer, and the surface of the first bonding pad is flush with the surface of the first dielectric layer.

16. A semiconductor structure, characterized in that, include: A first substrate, the first substrate having a central region and an edge region; A first dielectric layer covers the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in the direction away from the central region; A first filler layer is formed above the first dielectric layer in the edge region, and the surface of the first filler layer is flush with the surface of the first dielectric layer in the central region.

17. The semiconductor structure according to claim 16, characterized in that, Also includes: A second substrate, wherein the first substrate has a central region and an edge region; A second dielectric layer covers the central region and the edge region of the second substrate, wherein the thickness of the second dielectric layer covering the edge region gradually decreases in the direction away from the central region; A second filler layer is formed above the second dielectric layer in the edge region, and the surface of the second filler layer is flush with the surface of the second dielectric layer in the center region. The first dielectric layer in the central region of the first substrate is aligned and bonded to the second dielectric layer in the central region of the second substrate, and the first fill layer is aligned and bonded to the second fill layer.

18. The semiconductor structure according to claim 17, characterized in that, It also includes a first bonding layer disposed between the bonded first substrate and the second substrate, the first bonding layer covering at least the unbonded surfaces of the first filler layer and the second filler layer.

19. The semiconductor structure according to claim 18, characterized in that, The maximum radial distance from the center region to the center of the center region is R1, the maximum radial distance from the first filling layer to the center of the center region is R2, and the maximum radial distance from the first bonding layer to the center of the center region is R3, wherein the difference between R2 and R1 is greater than the difference between R3 and R2.

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