Semiconductor structure and manufacturing method therefor

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor. The structure comprises: a first dielectric layer provided on a substrate, the first dielectric layer having a first surface away from the substrate; a first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad passing through the first surface and extending to a second depth below the first surface, wherein the second depth is less than the first depth; and a second dielectric layer provided on the first surface, wherein the second dielectric layer is provided with a first gap and a second gap, the first gap exposes the top surface of the first bonding pad, and the second gap exposes the top surface of the second bonding pad. The embodiments of the present disclosure avoid use of a high-accuracy surface planarization process, so that the surface indentation values of the first bonding pad and the second bonding pad in the semiconductor structure are kept consistent.

Description

Semiconductor structure and manufacturing method

[0001] This disclosure claims priority to Chinese Patent Application No. 202411450961.2, filed on October 17, 2024, entitled "Semiconductor Structure and Manufacturing Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Technology

[0003] With the continued rapid growth in data capacity demand, increasing packaging density to improve integration and thus obtain higher storage capacity has become an important goal of integrated circuit manufacturing at this stage. Under this prospect, 3D-IC (three-dimensional integrated circuit) technology has been widely used. It involves stacking and bonding wafers with the same or different functions together. This technology has the advantages of high performance, low cost and high integration.

[0004] Hybrid bonding is a key process in 3D packaging technology, used to stack multiple wafers or chips vertically and achieve electrical connections. This technology can significantly improve chip integration density, shorten signal transmission paths, reduce power consumption, and reduce package size, making it an important technology in high-performance computing, storage, and mobile devices. The high-quality treatment of the bonding surfaces during the bonding process directly affects the bonding yield. For example, to ensure that the metal pads on the bonding surfaces expand at a uniform height during bonding, the surface planarization process requires extremely high precision; otherwise, poor bonding will occur between the bonded surfaces. Summary of the Invention

[0005] This disclosure provides semiconductor structures with higher bonding yields and methods for manufacturing the same.

[0006] The technical spirit of this disclosure aims to solve problems not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0007] Some embodiments of this disclosure provide a semiconductor structure including: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer having a first surface remote from the substrate; a first bonding pad extending through the first surface to a first depth below the first surface; a second bonding pad extending through the first surface of the first dielectric layer to a second depth below the first surface, the second depth being less than the first depth; and a second dielectric layer disposed on the first surface, the second dielectric layer having a first gap and a second gap, the first gap exposing the top surface of the first bonding pad and the second gap exposing the top surface of the second bonding pad.

[0008] In a semiconductor structure provided by some embodiments of this disclosure, the top surfaces of the first bonding pad and the second bonding pad are flush with the first surface.

[0009] In a semiconductor structure provided by some embodiments of this disclosure, the surface area of ​​the top surface of a first bonding pad exposed by a first gap is smaller than the surface area of ​​the top surface of a second bonding pad exposed by a second gap.

[0010] In a semiconductor structure provided by some embodiments of this disclosure, a first dielectric layer has a first thickness, a second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

[0011] The semiconductor structure provided in some embodiments of this disclosure further includes: a first interconnect structure and a second interconnect structure disposed in a first dielectric layer, wherein the bottom surface of the first bonding pad is connected to the first conductive layer through the first interconnect structure, and the bottom surface of the second bonding pad is connected to the second conductive layer through the second interconnect structure.

[0012] In a semiconductor structure provided by some embodiments of this disclosure, the top surface of the first conductive layer and the top surface of the second conductive layer are at different horizontal planes.

[0013] Some embodiments of this disclosure also provide a semiconductor structure, including: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer having a first surface remote from the substrate; a first bonding pad passing through the first surface and extending to a first depth below the first surface; a second bonding pad passing through the first surface and extending to a second depth below the first surface, the second depth being less than the first depth; and a second dielectric layer disposed on the first surface, the first bonding pad and the second bonding pad further extending into the second dielectric layer, the first bonding pad and the second bonding pad extending to the same depth in the second dielectric layer.

[0014] In a semiconductor structure provided by some embodiments of this disclosure, the top surfaces of a first bonding pad and a second bonding pad are exposed to the top surface of a second dielectric layer, and the surface area of ​​the top surface of the first bonding pad is smaller than the surface area of ​​the top surface of the second bonding pad.

[0015] In a semiconductor structure provided by some embodiments of this disclosure, the top surfaces of the first bonding pad and the second bonding pad are flush.

[0016] A semiconductor structure provided in some embodiments of this disclosure further includes: a first conductive layer and a second conductive layer disposed in a substrate, wherein the first conductive layer is connected to the bottom surface of a first bonding pad, and the second conductive layer is connected to the bottom surface of a second bonding pad.

[0017] Some embodiments of this disclosure also provide a semiconductor structure, including: a first substrate; a first dielectric layer disposed on the first substrate, the first dielectric layer having a first surface remote from the first substrate; a first bonding pad extending through the first surface to a first depth below the first surface; a second bonding pad extending through the first surface to a second depth below the first surface, the second depth being less than the first depth; a second dielectric layer disposed on the first surface, the first bonding pad and the second bonding pad further extending into the second dielectric layer, the first bonding pad and the second bonding pad having the same extension depth in the second dielectric layer, the surface area of ​​the top surface of the first bonding pad being less than the surface area of ​​the top surface of the second bonding pad; and a second substrate on which a first dielectric layer is disposed. There is a third dielectric layer having a second surface remote from the second substrate; a third bonding pad extending through the second surface to a third depth below the second surface; a fourth bonding pad extending through the second surface to a fourth depth below the second surface, the fourth depth being less than the third depth; a fourth dielectric layer disposed on the second surface, the third and fourth bonding pads further extending into the fourth dielectric layer, the third and fourth bonding pads having the same extension depth in the fourth dielectric layer, the surface area of ​​the top surface of the first bonding pad being less than the surface area of ​​the top surface of the second bonding pad; the first bonding pad and the third bonding pad are aligned and bonded, the second bonding pad and the fourth bonding pad are aligned and bonded, and the second dielectric layer and the fourth dielectric layer are aligned and bonded.

[0018] Some embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a first dielectric layer on the substrate, the first dielectric layer having a first surface remote from the substrate; patterning the first dielectric layer; forming a first trench having a first depth and a second trench having a second depth below the first surface, the second depth being less than the first depth; filling the first trench and the second trench to form a first bonding pad and a second bonding pad, respectively; forming a second dielectric layer covering the first surface and the top surfaces of the first and second bonding pads; and etching the second dielectric layer to form a first gap exposing the top surface of the first bonding pad and a second gap exposing the top surface of the second bonding pad.

[0019] In a semiconductor structure manufacturing method provided by some embodiments of this disclosure, the steps of patterning a first dielectric layer and forming a first trench with a first depth and a second trench with a second depth below a first surface include: forming a first mask layer on the first surface, patterning the first mask layer, forming a first mask pattern in the first mask layer, etching downward along the first mask pattern, and forming a first initial trench below the first surface; forming a second mask layer on the first dielectric layer, patterning the second mask layer, forming a second mask pattern in the second mask layer, etching the first dielectric layer along the second mask pattern and the first initial trench, and forming the second trench and the first trench respectively in the first dielectric layer.

[0020] In a method for manufacturing a semiconductor structure provided by some embodiments of this disclosure, the step of filling a first trench and a second trench to form a first bonding pad and a second bonding pad respectively includes: forming an initial conductive layer covering the first trench and the second trench, the initial conductive layer simultaneously covering a first surface; planarizing the initial conductive layer, and forming a first bonding pad and a second bonding pad flush with the first surface in the first trench and the second trench respectively, wherein the area of ​​the top surface of the first bonding pad exposed by the first gap is larger than the area of ​​the top surface of the second bonding pad exposed by the second gap.

[0021] In a method for manufacturing a semiconductor structure provided by some embodiments of this disclosure, a first conductive layer and a second conductive layer are formed in a substrate before patterning a first dielectric layer. When etching the first dielectric layer to form a first trench and a second trench, the bottom of the first trench exposes the first conductive layer, and the bottom of the second trench exposes the second conductive layer.

[0022] In a method for manufacturing a semiconductor structure provided by some embodiments of this disclosure, before patterning a first dielectric layer, a first conductive layer and a second conductive layer are formed in a substrate. When etching the first dielectric layer to form a first trench and a second trench, a first interconnect trench and a second interconnect trench are also formed. The top of the first interconnect trench is connected to the bottom of the first trench, and the bottom of the first interconnect trench exposes the first conductive layer. The top of the second interconnect trench is connected to the bottom of the second trench, and the bottom of the second interconnect trench exposes the second conductive layer.

[0023] In a method for manufacturing a semiconductor structure provided by some embodiments of this disclosure, after forming a first gap and a second gap, a bonding process is performed, such that a first bonding pad fills the first gap and a second bonding pad fills the second gap.

[0024] The semiconductor structure provided in this disclosure has its top surfaces, namely the first bonding pad and the second bonding pad, exposed by the first gap and the second gap located in the second dielectric layer, respectively. That is, the surface depression values ​​of the first and second bonding pads relative to the second dielectric layer are uniformly determined by the thickness of the second dielectric layer itself. In other words, the surface depression values ​​of the first and second bonding pads can be made the same by controlling the thickness of the second dielectric layer. This avoids the need to use high-precision surface planarization processes to control the surface depression values ​​of the first and second bonding pads. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0026] Figure 1 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0027] Figure 2 is a schematic cross-sectional view of the semiconductor structure provided in an embodiment of this disclosure.

[0028] Figure 3 is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure.

[0029] Figure 4 is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure.

[0030] Figure 5 is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure.

[0031] Figure 6 is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure.

[0032] Figure 7 is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure.

[0033] Figure 8 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0034] Figure 9 is a schematic cross-sectional view of the semiconductor structure provided in the embodiments of this disclosure.

[0035] Figure 10 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0036] Figure 11 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0037] Figure 12 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0038] Figure 13 is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure.

[0039] Figure 14 is a schematic flowchart of a semiconductor structure manufacturing method provided in an embodiment of this disclosure.

[0040] Figure 15 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0041] Figure 16 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0042] Figure 17 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0043] Figure 18 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0044] Figure 19 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0045] Figure 20 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0046] Figure 21 is a schematic cross-sectional view of the semiconductor structure corresponding to the corresponding step in the semiconductor structure manufacturing method provided in the embodiments of this disclosure.

[0047] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0048] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant disclosure and not for limiting the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described.

[0049] When forming a bonding layer over a semiconductor device using hybrid bonding technology, it typically involves forming a dielectric layer and bonding pads embedded within the dielectric layer. The formation of the dielectric layer and bonding pads is accompanied by surface planarization processes, such as chemical mechanical polishing (CMP), to remove excess material from the bonding layer surface, resulting in a flat bonding layer surface. The semiconductor device with the bonding layer formed can then be fabricated to be directly bonded to another semiconductor device or apparatus without the use of an intermediate adhesive. However, stress mismatch occurs due to thermal expansion mismatch between the bonding pads and the dielectric layer; for example, the bonding pads are subjected to tensile stress while the dielectric layer material is subjected to compressive stress. This stress unevenness can cause deformation and / or warping of semiconductor devices (e.g., device dies or chips, wafers) due to stress concentration. Therefore, it is necessary to continuously reduce stress in the bonding layer and control the deformation of the semiconductor device.

[0050] To reduce stress and deformation in the bonding layer caused by thermal expansion mismatch between the bonding pads and the dielectric layer, in some embodiments, virtual bonding pads (non-functional bonding pads) and active bonding pads (functional bonding pads) are distributed relatively uniformly in the dielectric layer. The aim is to overcome these stresses and deformations by making the bonding pads more evenly distributed in the dielectric layer. This is because if the two materials are evenly distributed, the expansion of one material can be absorbed or offset by the contraction of the other, thereby reducing or controlling tensile and compressive stresses. Therefore, a uniform or near-uniform distribution of bonding pads (including virtual and active bonding pads) in the dielectric layer helps alleviate stress caused by thermal expansion mismatch and reduces deformation. Furthermore, to ensure that all bonding pads expand consistently after thermal expansion, the surface planarization process requires high precision, needing to control the surface depression value of each bonding pad within a very small window, such as the nanometer scale. Furthermore, to ensure that each bonding pad achieves the same surface depression value, the bonding pads must be designed to be the same size. This limits design freedom; for example, when bonding pads of different areas are needed to meet current density requirements, the only solution is to increase the number of bonding pads. In addition, the added virtual bonding pads increase the metal density in the bonding layer. This increased metal density presents additional challenges to controlling the warpage of semiconductor devices. Excessive metal density can also lead to a smaller dielectric layer area, weakened wafer bonding strength, and increased risk of slippage during bonding.

[0051] At least based on the aforementioned problems, there is an incentive to use simpler and more efficient bonding layer structure designs and processes to reduce bonding difficulty and improve process yield. Figure 1 is a schematic cross-sectional view of a semiconductor structure provided in some embodiments of this disclosure. The embodiments of this disclosure will be described in detail below with reference to Figure 1.

[0052] As shown in Figure 1, the semiconductor structure includes a substrate 10, in which a semiconductor device 20 is disposed. A first dielectric layer 50 is disposed on the substrate 10, and the first dielectric layer 50 has a first surface 51 away from the substrate 10. A first bonding pad 70 is disposed in the first dielectric layer 50 and extends through the first surface 51 of the first dielectric layer 50 to below the first surface 51, having a first depth D1 below the first surface 51. A second bonding pad 71 is disposed in the first dielectric layer 50 and extends through the first surface 51 of the first dielectric layer 50 to below the first surface 51, having a second depth D2 below the first surface 51. The second depth D2 is less than the first depth D1.

[0053] The semiconductor structure further includes a second dielectric layer 60 disposed on a first surface 51 of the first dielectric layer 50. The second dielectric layer 60 has a first gap 601 and a second gap 602 disposed therein. The first gap 601 exposes the top surface 701 of the first bonding pad 70, and the second gap 602 exposes the top surface 711 of the second bonding pad 71. In some embodiments, the top surface 701 of the first bonding pad 70 is flush with or substantially flush with the top surface 711 of the second bonding pad 71.

[0054] In some embodiments, substrate 10 may be a silicon substrate wafer, a substrate wafer with an epitaxial layer, or a silicon-on-insulator (SOI) substrate wafer. In some embodiments, substrate 10 may also be part of a wafer, such as a die or a chip.

[0055] In some embodiments, the semiconductor device 20 may be a CMOS device, a memory device, and / or other passive device. The memory device may include volatile memory or non-volatile memory, and the volatile memory may include DRAM, etc. In some embodiments, when the semiconductor device 20 is a DRAM memory device, it may be a memory element consisting of a transistor and a capacitor, or it may be a collection of multiple memory elements.

[0056] In some embodiments, the first dielectric layer 50 may be a single-layer dielectric layer formed from a single dielectric or a composite dielectric layer composed of multiple dielectrics. The second dielectric layer 60 may also be a single-layer dielectric layer formed from a single dielectric or a composite dielectric layer composed of multiple dielectrics. In some embodiments, both the first dielectric layer 50 and the second dielectric layer 60 are single-layer dielectric layers formed from a single dielectric; in other embodiments, the first dielectric layer 50 is a multilayer dielectric layer formed from multiple dielectrics, and the second dielectric layer 60 is a single-layer dielectric layer formed from a single dielectric. The first dielectric layer 50 and the second dielectric layer 60 may contain the same dielectric material or may contain different dielectric materials. In some embodiments, the second dielectric layer 60 is a dielectric layer suitable for low-temperature direct bonding. In some embodiments, the first dielectric layer 50 comprises an oxide, such as silicon oxide. "Silicon oxide" is referred to herein as a compound containing silicon and oxygen atoms, including any and all stoichiometric possibilities of Si. x O y x and y can be integers or non-integers. The second dielectric layer 60 includes oxides or nitrides, such as silicon oxide or silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc. In some embodiments, the first dielectric layer 50 includes Si x O y The second dielectric layer 60 comprises SiCN. In some embodiments, the first dielectric layer 50 comprises Si x O yThe stacked structure consists of SiCN, and the second dielectric layer 60 includes SiCN.

[0057] In the above embodiments, the first bonding pad 70 and the second bonding pad 71 are bonding pads used for subsequent direct bonding of the semiconductor structure, such as copper-containing metal pads or other bonding pads that can be used for low-temperature direct bonding. The first bonding pad 70 may be an active bonding pad, which is at least electrically connected to the semiconductor device 20. The second bonding pad 71 may be a dummy bonding pad, which is disposed in the first dielectric layer 50 and does not establish an electrical connection with the semiconductor device 20. In some embodiments, the densities of the first bonding pad 70 and the second bonding pad 71 are not the same per unit area of ​​the first dielectric layer 50, and the number of first bonding pads 70 may be greater than the number of second bonding pads 71. In some embodiments, the number of first bonding pads 70 may also be less than the number of second bonding pads 71.

[0058] In the above embodiments, the first gap 601 and the second gap 602 can completely expose the top surface 701 of the first bonding pad 70 and the top surface 711 of the second bonding pad 71, respectively. In some embodiments, the first gap 601 and the second gap 602 can also expose a portion of the top surface of the first bonding pad 70 and the second bonding pad 71.

[0059] Referring again to Figure 1, in some embodiments, the semiconductor structure further includes an interlayer insulating layer 30 disposed on the substrate 10. The interlayer insulating layer 30 contains multilayer metal wiring for connecting the semiconductor device 20. The multilayer metal wiring includes a first conductive layer 40, and the first bonding pad 70 is electrically connected to the semiconductor device 20 through the first conductive layer 40. In some embodiments, the first conductive layer 40 may be the topmost metal wiring in the multilayer metal wiring, or it may be a metal wiring second only to the topmost metal wiring. In some embodiments, the bottom surface of the first bonding pad 70 is directly connected to the first conductive layer 40.

[0060] Some embodiments of this disclosure also provide a semiconductor structure, as shown in FIG2, which is a schematic cross-sectional view of the semiconductor structure provided in some embodiments of this disclosure. Unlike the embodiment shown in FIG1, the first bonding pad 70 and the second bonding pad 71 are both virtual bonding pads, that is, neither the first bonding pad 70 nor the second bonding pad 71 is electrically connected to the semiconductor device 20. The first bonding pad 70 extends to a first depth D1 below the first surface 51, and the second bonding pad 71 extends to a second depth D2 below the first surface 51, where the first depth D1 is greater than the second depth D2. At this time, an active bonding pad 72 electrically connected to the semiconductor device 20 is also provided in the first dielectric layer 50, extending to a depth D3 below the first surface 51. The depth D3 is greater than the first depth D1 and the second depth D2.

[0061] This disclosure also provides a semiconductor structure in some embodiments, as shown in FIG3, which is a schematic cross-sectional view of the semiconductor structure provided in some embodiments of this disclosure. The interlayer insulating layer 30 further includes a second conductive layer 41. Unlike the semiconductor structure shown in FIG1, in these embodiments, both the first bonding pad 70 and the second bonding pad 71 are active bonding pads electrically connected to the semiconductor device 20. In these embodiments, the second conductive layer 41 can be a metal wiring layer on the same layer as the first conductive layer 40. That is, both the first conductive layer 40 and the second conductive layer 41 are the topmost metal wiring in a multilayer metal wiring system, and the top surfaces of the first conductive layer 40 and the second conductive layer 40 are at the same horizontal plane. In these embodiments, the bottom surface of the first bonding pad 70 is directly connected to the first conductive layer 40, and the bottom surface of the second bonding pad 71 is connected to the second conductive layer 41 through a second interconnect structure 712.

[0062] This disclosure also provides a semiconductor structure in some embodiments, as shown in FIG4, which is a schematic cross-sectional view of the semiconductor structure provided in some embodiments of this disclosure. Unlike the embodiment shown in FIG3, in these embodiments, the first bonding pad 70 in the semiconductor structure is electrically connected to the first conductive layer 40 through a first interconnect structure 702.

[0063] In the embodiments shown in Figures 3 and 4, the first interconnect structure 702 and the second interconnect structure 712 may use the same conductive material as the first bonding pad 70 and the second bonding pad 71, such as copper-containing metal.

[0064] In some embodiments, the first interconnect structure 702 may be formed only in the interlayer insulating layer 30, while the second interconnect structure 701 is formed in both the first dielectric layer 50 and the interlayer insulating layer 30.

[0065] This disclosure also provides a semiconductor structure in some embodiments, as shown in FIG5, which is a schematic cross-sectional view of the semiconductor structure provided in some embodiments of this disclosure. In these embodiments, the multilayer metal wiring includes a first conductive layer 40 and a second conductive layer 41, wherein the first conductive layer 40 and the second conductive layer 41 are non-co-layer metal wirings, that is, their top surfaces are at different horizontal planes. For example, the first conductive layer 40 is the second-to-last layer metal wiring, and the second conductive layer 41 is the top layer metal wiring. In these embodiments, a first bonding pad 70 is connected to the first conductive layer 40, and a second bonding pad 71 is connected to the second conductive layer 41. The bottom surface of the first bonding pad 70 may be directly or indirectly connected to the first conductive layer 40, and the bottom surface of the second bonding pad 71 may also be directly or indirectly connected to the second conductive layer 41. When the bottom surface of the first bonding pad 70 is directly connected to the first conductive layer 40, the first bonding pad 70 has a portion extending into the interlayer insulating layer 30, and its first depth D1 below the first surface 51 includes the depth extending in the first dielectric layer 50 and the depth extending in the interlayer insulating layer 30. When the bottom surface of the second bonding pad 71 is directly connected to the second conductive layer 41, the second bonding pad 71 may also have a portion extending into the interlayer insulating layer 30. In this case, the second depth D2 of the second bonding pad 71 below the first surface 51 includes the depth extending in the first dielectric layer 50 and the depth extending in the interlayer insulating layer 30. In some embodiments, the second bonding pad 71 can be directly connected to the second conductive layer 41 simply by extending through the first dielectric layer 50. The specific connection method is not limited to the structure shown in FIG. 5. In other embodiments, the first bonding pad 70 and the second bonding pad 71 can also be electrically connected to the first conductive layer 40 and the second conductive layer 41 by means of the first interconnect structure 702 and the second interconnect structure 712 shown in FIG. 4.

[0066] In the semiconductor structures provided in the above embodiments, the top surfaces of the first bonding pad 70 and the second bonding pad 71 are exposed by the first gap 601 and the second gap 602 located in the second dielectric layer 60, respectively. That is, for the first bonding pad 70 and the second bonding pad 71, their surface depression values ​​relative to the second dielectric layer 60 are uniformly determined by the thickness of the second dielectric layer 60 itself. The surface depression values ​​of the first bonding pad 70 and the second bonding pad 71 can be made the same by controlling the thickness of the second dielectric layer 60, thereby avoiding the need to use a high-precision surface planarization process to control the surface depression values ​​of the first bonding pad 70 and the second bonding pad 71.

[0067] Referring again to Figures 1 through 5, in some embodiments, the top surface 701 of the first bonding pad 70 and the top surface 711 of the second bonding pad 71 are flush with or substantially flush with the first surface 51 of the first dielectric layer 50. In embodiments of this disclosure, by pre-controlling the top surface 701 of the first bonding pad 70 and the top surface 711 of the second bonding pad 71 to be flush with or substantially flush with the first surface 51 of the first dielectric layer 50, it is ensured that the first bonding pad 70 and the second bonding pad 71 have the same surface depression value relative to the second dielectric layer 60.

[0068] Referring again to Figures 1 through 5, in some embodiments, the surface area of ​​the top surface 701 of the first bonding pad 70 exposed by the first gap 601 is smaller than the surface area of ​​the top surface 711 of the second bonding pad 71 exposed by the second gap 602. In these embodiments, the first gap 601 completely exposes the top surface 701 of the first bonding pad 70, and the second gap 602 completely exposes the top surface 711 of the second bonding pad 71. That is, the dimension of the top surface 701 of the first bonding pad 70 in the horizontal plane is smaller than the dimension of the top surface 711 of the second bonding pad 71 in the horizontal plane. In these embodiments, by providing first bonding pads 70 and second bonding pads 71 ​​with different surface areas, and controlling the first bonding pads 70 and second bonding pads 71 ​​to have different extension depths, the relationship between the two can be controlled so that the first bonding pads 70 and second bonding pads 71 ​​obtain the same amount of expansion during subsequent bonding processes. The expansion amount of the first bonding pads 70 and second bonding pads 71 ​​fills the first gap 601 and the second gap 602, achieving equal expansion of the first bonding pads 70 and second bonding pads 71. In some embodiments, the second bonding pad 72 with a relatively large surface area can be an active bonding pad requiring a high flux density.

[0069] Referring again to Figures 1 through 5, in some embodiments, the first dielectric layer 50 has a first thickness, and the second dielectric layer 60 has a second thickness, wherein the first thickness is greater than the second thickness. In some embodiments, the ratio of the first thickness to the second thickness can range from 100 to 2000. For example, the numerical range of the first thickness can be from 2 micrometers to 100 nanometers, and the numerical range of the second thickness can be from 5 nanometers to 0.5 nanometers.

[0070] Referring again to Figures 3 and 4, in some embodiments, the dimensions of the first interconnect structure 702 and / or the second interconnect structure 712 are smaller than those of the first bonding pad 70 and the second bonding pad 70. These dimensions can be physical quantities such as the depth, width, and top surface area of ​​the first interconnect structure 702 and / or the second interconnect structure 712.

[0071] The semiconductor structures provided in the above embodiments provide the necessary gaps for the expansion of each bonding pad through a second dielectric layer, reducing the difficulty of the planarization process that forms the surface depressions of the bonding pads. Each bonding pad can be designed with different sizes. By controlling the depth of bonding pads with different surface areas, it is ensured that bonding pads with different surface areas expand to the same height during the heating and expansion process. This allows for the design of combinations of bonding pads of different sizes, as bonding pads with larger surface areas show good application prospects in terms of current density, bonding strength, and heat dissipation. Furthermore, the semiconductor structures provided in this disclosure can reduce the number of virtual bonding pads and decrease the metal content on the bonding surface, which will help control the warpage of the semiconductor structure and increase the stability of the bonding process.

[0072] Some embodiments of this disclosure also provide other semiconductor structures. Referring again to Figures 6 to 10, which are schematic cross-sectional views of the semiconductor structures provided in the embodiments of this disclosure. After the semiconductor structures shown in Figures 1 to 5 are formed, a bonding process is performed. During this process, the first bonding pad 70 and the second bonding pad 71 expand due to heat, thereby filling the first gap 601 and the second gap 602, ultimately forming the semiconductor structures shown in Figures 6 to 10. The semiconductor structure shown in Figure 1, after bonding, forms the semiconductor structure shown in Figure 6; the semiconductor structure shown in Figure 2, after bonding, forms the semiconductor structure shown in Figure 7; the semiconductor structure shown in Figure 3, after bonding, forms the semiconductor structure shown in Figure 8; the semiconductor structure shown in Figure 4, after bonding, forms the semiconductor structure shown in Figure 9; and the semiconductor structure shown in Figure 5, after bonding, forms the semiconductor structure shown in Figure 10. In these semiconductor structures, the first bonding pad 70 and the second bonding pad 71 expand and extend into the second dielectric layer 60, respectively. The first bonding pad 70 and the second bonding pad 71 extend to the same depth in the second dielectric layer 60, making their expanded top surfaces 701 and 711 flush. Ultimately, the extension depth of the first bonding pad 70 is D1', and the extension depth of the second bonding pad 71 is D2'. In the semiconductor structure shown in Figure 7, the active bonding pad 72 also expands and extends into the second dielectric layer 60, with an extension depth of D3'.

[0073] In some embodiments, the surface area of ​​the top surface 701 of the expanded first bonding pad 70 is smaller than the surface area of ​​the top surface 711 of the second bonding pad 71.

[0074] The other parts of the semiconductor structure after bonding are the same as those shown in Figures 1 to 5 and their corresponding embodiments, and will not be described again here.

[0075] Some embodiments of this disclosure also provide a semiconductor structure, as shown in Figures 11 to 13, which are schematic cross-sectional views of the semiconductor structure provided in the embodiments of this disclosure. As shown in Figure 11, the semiconductor structure includes a first substrate 10 and a second substrate 11. A semiconductor device 20 is disposed in the first substrate 10. An interlayer insulating layer 30 is disposed above the first substrate 10. Multilayer metal wiring connected to the semiconductor device 20 is disposed in the interlayer insulating layer 30, including a first conductive layer 40. A first dielectric layer 50 is disposed on the interlayer insulating layer 30, and a second dielectric layer 60 is disposed on the first dielectric layer 50. A first bonding pad 70 and a second bonding pad 71 extend through a first surface 51 of the first dielectric layer 50 and extend into the second dielectric layer 60. The first bonding pad 70 extends to a first depth D1 below the first surface 51 of the first dielectric layer 50, and the second bonding pad 71 extends to a second depth D2 below the first surface 51 of the first dielectric layer 50, where D2 is less than D1. The first bonding pad 70 extends to be electrically connected to the first conductive layer 40, while the second bonding pad 71 is not electrically connected to the first conductive layer 40. The first bonding pad 70 and the second bonding pad 71 extend to the same depth in the second dielectric layer 60, such that the top surfaces of the first bonding pad 70 and the second bonding pad 71 are flush with or substantially flush with the top surface of the second dielectric layer 60. The surface area of ​​the top surface of the first bonding pad 70 is smaller than the surface area of ​​the top surface of the second bonding pad 71.

[0076] The second substrate 11 includes a semiconductor device 21 disposed therein and an interlayer insulating layer 31 disposed on the second substrate 11. The interlayer insulating layer 31 has multilayer metal wiring connected to the semiconductor device 21, including a conductive layer 42. A third dielectric layer 52 is disposed on the interlayer insulating layer 31, and a fourth dielectric layer 61 is disposed on the third dielectric layer 52. A third bonding pad 73 and a fourth bonding pad 74 extend through a second surface 53 of the third dielectric layer 52 and into the fourth dielectric layer 61. The third bonding pad 73 extends to a third depth D4 below the second surface 53 of the third dielectric layer 52, and the fourth bonding pad 74 extends to a fourth depth D5 below the second surface 53 of the third dielectric layer 52, where D5 is less than D4. The third bonding pad 73 extends to be electrically connected to the conductive layer 42, while the fourth bonding pad 74 is not electrically connected to the conductive layer 42. The third bonding pad 73 and the fourth bonding pad 74 extend to the same depth in the fourth dielectric layer 61, such that the top surfaces of the third bonding pad 73 and the fourth bonding pad 74 are flush with or substantially flush with the top surface of the fourth dielectric layer 61. The surface area of ​​the top surface of the third bonding pad 73 is smaller than the surface area of ​​the top surface of the fourth bonding pad 74.

[0077] The first bonding pad 70 and the third bonding pad 73 are aligned and bonded, the second bonding pad 71 and the fourth bonding pad 74 are aligned and bonded, and the second dielectric layer 60 and the fourth dielectric layer 61 are aligned and bonded to form the semiconductor structure of the present disclosure embodiment.

[0078] In some embodiments, semiconductor device 20 and semiconductor device 21 may be the same semiconductor device or different semiconductor devices. The first substrate 10 and the second substrate 11 may be substrate wafers of the same type or different types.

[0079] In some embodiments, the first bonding pad 70 and the third bonding pad 73 may not be electrically connected to the conductive layer, as shown in FIG12. Unlike FIG11, in this case, the first bonding pad 70 and the third bonding pad 73 are both virtual bonding pads, and the first substrate 10 and the second substrate 11 are electrically connected through the bonded active bonding pads 72 and 75.

[0080] In some embodiments, the first bonding pad 70, the second bonding pad 71, the third bonding pad 73, and the fourth bonding pad 74 are each connected to a corresponding conductive layer, as shown in FIG13. Unlike FIG12, in this case, the first bonding pad 70, the second bonding pad 71, the third bonding pad 73, and the fourth bonding pad 74 are all active bonding pads. The first bonding pad 70 is connected to the first conductive layer 40, the second bonding pad 71 is connected to the second conductive layer 41, the third bonding pad 73 is connected to the conductive layer 42, and the fourth bonding pad 74 is connected to the conductive layer 43. The conductive layers 42 and 43 can be metal wiring on the same layer or metal wiring on different layers. FIG13 shows the case where the conductive layers are metal wiring on different layers.

[0081] In the semiconductor structures provided by the above embodiments, each bonding pad in the first substrate and the second substrate can achieve a good surface bonding effect, and the size of each bonding pad can be set to be different, which improves the flexibility of bonding pad design.

[0082] In some embodiments, each bonding pad in each substrate may have further design forms, as detailed in Figures 3 and 4, and the resulting semiconductor structure is also included in this disclosure, which will not be described in detail here.

[0083] Some embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, which will now be described in detail with reference to the accompanying drawings.

[0084] Refer to Figure 14, which is a flowchart of the semiconductor structure manufacturing process. The semiconductor structure manufacturing method includes:

[0085] Step S101 is performed, providing a substrate. As shown in FIG15, a substrate 10 is provided, in which a semiconductor device 20 is disposed. An interlayer insulating layer 30 is also disposed on the substrate 10, and multiple layers of metal wiring, including a first conductive layer 40, are disposed in the interlayer insulating layer 30. The substrate 10 may be a silicon substrate wafer, a substrate wafer with an epitaxial layer, or a silicon-on-insulator wafer. In some embodiments, the substrate 10 may also be a part of a wafer, such as a die or a chip. The semiconductor device 20 may be a CMOS device, a memory device, and / or other passive devices. The memory device may include volatile memory or non-volatile memory, etc., and the volatile memory may include, for example, DRAM. In some embodiments, when the semiconductor device 20 is a DRAM memory device, it may be a memory element consisting of a transistor and a capacitor, or it may be a collection of multiple memory elements.

[0086] In step S102, a first dielectric layer is formed on the substrate. The first dielectric layer has a first surface away from the substrate. The first dielectric layer is patterned, and a first trench with a first depth and a second trench with a second depth, the second depth being less than the first depth, are formed below the first surface. See Figure 15 for details. A first dielectric layer 50 is formed on the substrate 10, and the first dielectric layer 50 covers the interlayer insulating layer 30. The first dielectric layer 50 has a first surface 51 away from the substrate 10. The first dielectric layer 50 is patterned, and a first trench 703 with a first depth D1 and a second trench 713 with a second depth D2 are formed below the first surface 51 of the first dielectric layer 50.

[0087] In some embodiments, the steps of patterning a first dielectric layer and forming a first trench with a first depth and a second trench with a second depth below a first surface are shown in Figures 16 to 18. Figures 16 to 18 are schematic cross-sectional views of the semiconductor structure corresponding to the respective steps in manufacturing the semiconductor structure.

[0088] Referring first to Figure 16, a first mask layer 80 is formed on the first surface 51 of the first dielectric layer 50. The first mask layer 80 is patterned using photolithography, etching, and other processes, forming a first mask pattern 801 within it. The first mask pattern 801 exposes the first surface 51 of the first dielectric layer 50. Referring further to Figure 17, after forming the first mask pattern 801, the first dielectric layer 50 is etched downwards along the first mask pattern 801, forming a first initial trench 802 below the first surface 51 of the first dielectric layer 50. Referring further to Figure 18, after forming the first initial trench 802, the first mask layer 80 can be removed, leaving only the first initial trench 802. Subsequently, a second mask layer 81 is formed on the first surface 51 of the first dielectric layer 50. The second mask layer 81 is patterned using photolithography, etching, and other processes, forming a second mask pattern 810 within it. In some embodiments, a third mask pattern 803 is also formed in the second mask layer 81, and the third mask pattern 803 exposes the first initial trench 802. After the second mask pattern 810 and the third mask pattern 803 are formed, the second mask layer 81 is etched downwards to finally form the first trench 703 and the second trench 713 as shown in FIG15.

[0089] Through the above steps, the extension depth and lateral dimensions of the first trench 703 and the second trench 713 can be controlled more flexibly, thereby obtaining bonding pads with different top surface areas.

[0090] In step S103, the first trench and the second trench are filled to form the first bonding pad and the second bonding pad, respectively. Specifically, referring to Figure 19, after forming the first trench 703 and the second trench 713, an initial conductive layer 90 covering the first trench 703 and the second trench 713 is formed on the first surface 51 of the first dielectric layer 50. Next, referring to Figure 20, after forming the initial conductive layer 90, a planarization process is performed on the initial conductive layer 90, removing the initial conductive layer 90 from the first surface 51 of the first dielectric layer 50, retaining the initial conductive layer 90 located in the first trench 703 and the second trench 713, ultimately forming the first bonding pad 70 and the second bonding pad 71. The process for forming the first bonding pad 70 and the second bonding pad 71 can employ a damascus process. During this process, by performing a surface planarization process, such as CMP, the first bonding pad 70, the second bonding pad 71, and the first surface of the first dielectric layer 50 are ultimately flush. In this surface planarization step, there is no need to control the surface depression values ​​of the first bonding pad 70 and the second bonding pad 71; it is only necessary to achieve that their surfaces are flush, which reduces the difficulty of the planarization process.

[0091] Continuing with step S104, a second dielectric layer is formed covering the first surface and the top surfaces of the first and second bonding pads. Specifically, as shown in Figure 21, after forming the first bonding pad 70 and the second bonding pad 71, a second dielectric layer 60 is formed on the first surface 51 of the first dielectric layer 50 and on the top surfaces of the first and second bonding pads 70 and 71. The second dielectric layer 60 can be formed using thin film deposition processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD) to obtain a thin film with precisely controlled thickness, uniform thickness, and density.

[0092] In some embodiments, the first dielectric layer 50 may be Si x O y The second dielectric layer 60 comprises an oxide or nitride, such as silicon oxide or silicon nitride (Si3N4), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc. In some embodiments, the first dielectric layer 50 comprises Si x O y The second dielectric layer 60 comprises SiCN. In some embodiments, the first dielectric layer 50 comprises Si x O y The stacked structure consists of SiCN, and the second dielectric layer 60 includes SiCN.

[0093] In step S105, the second dielectric layer is etched to form a first gap exposing the top surface of the first bonding pad and a second gap exposing the top surface of the second bonding pad. Based on the semiconductor structure shown in Figure 21, that is, after the formation of the second dielectric layer 60, a combination of photolithography, etching and other processes are performed on the second dielectric layer 60 to form a first gap 601 and a second gap 602 in the second dielectric layer 60, and the final structure is shown in Figure 1.

[0094] In the semiconductor structure manufacturing method illustrated in the above embodiments, only one surface planarization process is required when forming the first bonding pad and the second bonding pad to make the surfaces of the first bonding pad, the second bonding pad and the first dielectric layer flush. Subsequently, a thin film deposition process is used to form a second dielectric layer with a predetermined thickness. There is no need to use a surface planarization process to control the surface depression value of the second dielectric layer and the first bonding pad and the second bonding pad, thus omitting the expensive and complex surface planarization process steps.

[0095] In some embodiments, the first trench 703 and the second trench 713 may expose the corresponding metal wiring in the interlayer insulating layer 30, and the resulting first bonding pad 70 and second bonding pad 71 are respectively connected to the corresponding conductive layer in the multilayer metal wiring, as shown in FIG5. In other embodiments, neither the first trench 703 nor the second trench 713 exposes the corresponding metal wiring in the interlayer insulating layer 30, and the resulting first bonding pad 70 and second bonding pad 71 are not connected to the corresponding conductive layer in the multilayer metal wiring, as shown in FIG2.

[0096] In some embodiments, before patterning the first dielectric layer, a first conductive layer and a second conductive layer are also formed in the substrate. The configuration of the first and second conductive layers is shown in Figures 3 and 4. During the etching of the first trench 703 and the second trench 713, a first interconnect trench and a second interconnect trench connected to the bottom of the first trench and / or the second trench are formed below the first trench and / or the second trench. The first interconnect trench and the second interconnect trench respectively expose their respective conductive layers; for example, the first interconnect trench exposes the first conductive layer, and the second interconnect trench exposes the second conductive layer. When the initial conductive layer is subsequently formed, the initial conductive layer is also simultaneously filled into the first interconnect trench and / or the second interconnect trench, resulting in the structure shown in Figures 3 and 4. The first trench and the first interconnect trench, as well as the second trench and the second interconnect trench, can be formed using a double damask process.

[0097] In some embodiments, after performing step S105, the method further includes: performing a bonding process such that a first bonding pad fills a first gap and a second bonding pad fills a second gap. After the bonding process, the semiconductor structure shown in Figures 6 to 13 is finally formed.

[0098] The bonding process involves a heating process, with the bonding temperature typically between 200°C and 400°C. After initial bonding is achieved at the bonding temperature, the bonded structure undergoes annealing to further enhance the mechanical and electrical connections at the bonding interface, improving the reliability and durability of the bond. During these processes, the first and second bonding pads expand due to heat, and the expanded portion fills the first and second gaps, thereby forming a good bonding interface and enabling successful bonding with another semiconductor.

[0099] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, comprising: Substrate (10); A first dielectric layer (50) disposed on the substrate (10) has a first surface (51) away from the substrate (10); A first bonding pad (70) extends through the first surface (51) and to a first depth (D1) below the first surface (51); A second bonding pad (71) passes through the first surface (51) and extends to a second depth (D2) below the first surface (51), the second depth (D2) being less than the first depth (D1); A second dielectric layer (60) is disposed on the first surface (51). The second dielectric layer (60) has a first gap (601) and a second gap (602). The first gap (601) exposes the top surface (701) of the first bonding pad (70), and the second gap (602) exposes the top surface (711) of the second bonding pad (71).

2. The semiconductor structure according to claim 1, characterized in that, The top surface of the first bonding pad and the top surface of the second bonding pad are flush with the first surface.

3. The semiconductor structure according to claim 1, characterized in that, The surface area of ​​the top surface of the first bonding pad exposed by the first gap is smaller than the surface area of ​​the top surface of the second bonding pad exposed by the second gap.

4. The semiconductor structure according to claim 1, characterized in that, The first dielectric layer has a first thickness, the second dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: A first conductive layer and a second conductive layer are disposed in the substrate, wherein the first conductive layer is connected to the bottom surface of the first bonding pad, and the second conductive layer is connected to the bottom surface of the second bonding pad.

6. The semiconductor structure according to claim 5, characterized in that, Also includes: A first interconnect structure and a second interconnect structure are disposed in the first dielectric layer, wherein the bottom surface of the first bonding pad is connected to the first conductive layer through the first interconnect structure, and the bottom surface of the second bonding pad is connected to the second conductive layer through the second interconnect structure.

7. The semiconductor structure according to claim 5, characterized in that, The top surface of the first conductive layer and the top surface of the second conductive layer are on different horizontal planes.

8. A semiconductor structure, comprising: Substrate; A first dielectric layer disposed on the substrate, the first dielectric layer having a first surface remote from the substrate; A first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; A second bonding pad passes through the first surface and extends to a second depth below the first surface, the second depth being less than the first depth; A second dielectric layer is disposed on the first surface, and the first bonding pad and the second bonding pad extend into the second dielectric layer respectively, with the first bonding pad and the second bonding pad having the same extension depth in the second dielectric layer.

9. The semiconductor structure according to claim 8, characterized in that, The top surfaces of the first bonding pad and the second bonding pad are exposed to the top surface of the second dielectric layer, and the surface area of ​​the top surface of the first bonding pad is smaller than the surface area of ​​the top surface of the second bonding pad.

10. The semiconductor structure according to claim 9, characterized in that, The top surface of the first bonding pad and the top surface of the second bonding pad are flush.

11. The semiconductor structure according to claim 8, characterized in that, Also includes: A first conductive layer and a second conductive layer are disposed in the substrate, wherein the first conductive layer is connected to the bottom surface of the first bonding pad, and the second conductive layer is connected to the bottom surface of the second bonding pad.

12. A semiconductor structure, comprising: First substrate; A first dielectric layer disposed on the first substrate, the first dielectric layer having a first surface remote from the first substrate; A first bonding pad, the first bonding pad passing through the first surface and extending to a first depth below the first surface; A second bonding pad passes through the first surface and extends to a second depth below the first surface, the second depth being less than the first depth; A second dielectric layer is disposed on the first surface. The first bonding pad and the second bonding pad extend into the second dielectric layer respectively. The first bonding pad and the second bonding pad extend to the same depth in the second dielectric layer. The surface area of ​​the top surface of the first bonding pad is smaller than the surface area of ​​the top surface of the second bonding pad. A second substrate, wherein a third dielectric layer is disposed on the second substrate, the third dielectric layer having a second surface away from the second substrate; A third bonding pad, the third bonding pad passing through the second surface and extending to a third depth below the second surface; A fourth bonding pad passes through the second surface and extends to a fourth depth below the second surface, the fourth depth being less than the third depth; A fourth dielectric layer is disposed on the second surface. The third bonding pad and the fourth bonding pad extend into the fourth dielectric layer respectively. The third bonding pad and the fourth bonding pad extend to the same depth in the fourth dielectric layer. The surface area of ​​the top surface of the first bonding pad is smaller than the surface area of ​​the top surface of the second bonding pad. The first bonding pad is aligned and bonded to the third bonding pad, the second bonding pad is aligned and bonded to the fourth bonding pad, and the second dielectric layer is aligned and bonded to the fourth dielectric layer.

13. A method for manufacturing a semiconductor structure, characterized in that, include: Provide substrate; A first dielectric layer is formed on the substrate, the first dielectric layer having a first surface remote from the substrate, the first dielectric layer is patterned, and a first trench having a first depth and a second trench having a second depth are formed below the first surface, the second depth being less than the first depth; The first trench and the second trench are filled to form a first bonding pad and a second bonding pad, respectively. A second dielectric layer is formed covering the first surface, the top surface of the first bonding pad, and the top surface of the second bonding pad; The second dielectric layer is etched to form a first gap exposing the top surface of the first bonding pad and a second gap exposing the top surface of the second bonding pad.

14. The manufacturing method according to claim 13, characterized in that, The step of graphically representing the first dielectric layer and forming a first trench with a first depth and a second trench with a second depth below the first surface includes: A first mask layer is formed on the first surface, the first mask layer is patterned, a first mask pattern is formed in the first mask layer, and etching is performed downward along the first mask pattern to form a first initial trench below the first surface. A second mask layer is formed on the first dielectric layer, the second mask layer is patterned, a second mask pattern is formed in the second mask layer, the first dielectric layer is etched along the second mask pattern and the first initial trench, and the second trench and the first trench are formed in the first dielectric layer, respectively.

15. The manufacturing method according to claim 13, characterized in that, The steps of filling the first trench and the second trench to form the first bonding pad and the second bonding pad respectively include: An initial conductive layer is formed covering the first trench and the second trench, and the initial conductive layer also covers the first surface; The initial conductive layer is planarized by forming a first bonding pad and a second bonding pad flush with the first surface in the first trench and the second trench, respectively, wherein the area of ​​the top surface of the first bonding pad exposed by the first gap is greater than the area of ​​the top surface of the second bonding pad exposed by the second gap.

16. The manufacturing method according to claim 13, characterized in that, Before patterning the first dielectric layer, a first conductive layer and a second conductive layer are formed in the substrate. When etching the first dielectric layer to form the first trench and the second trench, the bottom of the first trench exposes the first conductive layer, and the bottom of the second trench exposes the second conductive layer.

17. The manufacturing method according to claim 13, characterized in that, Before patterning the first dielectric layer, a first conductive layer and a second conductive layer are formed in the substrate. When etching the first dielectric layer to form the first trench and the second trench, a first interconnect trench and a second interconnect trench are also formed. The top of the first interconnect trench is connected to the bottom of the first trench, and the bottom of the first interconnect trench exposes the first conductive layer. The top of the second interconnect trench is connected to the bottom of the second trench, and the bottom of the second interconnect trench exposes the second conductive layer.

18. The manufacturing method according to claim 13, characterized in that, After the first gap and the second gap are formed, a bonding process is performed so that the first bonding pad fills the first gap and the second bonding pad fills the second gap.

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