Manufacturing of semiconductor devices using an ETCH stop layer in fluorine-based plasma etching

Abstract

The disclosure concerns a method of producing high aspect ratio (HAR) features for substrates used in semiconductor devices and related method of manufacturing a semiconductor device. In the method, an yttria etch stop layer (ESL) (11) is formed over a substrate (20) surface, and HAR features (31) are etched in the substrate using a fluorine-based plasma (14), wherein the ESL (11) becomes exposed to the fluorine-based plasma. Fluorination of yttria of the ESL layer results in formation of a fluorinated film (15) at the bottom of HAR features, which film provide better resistance to etching gases, in particular, at higher substrate biases.

Description

[0001] MANUFACTURING OF SEMICONDUCTOR DEVICES USING AN ETCH STOP LAYER IN FLUORINE-BASED PLASMA ETCHING

[0002] FIELD OF THE INVENTION

[0003] The present invention generally relates to three-dimensional integrated circuit technology for semiconductor fabrication processes. In particular, the invention concerns improved techniques for producing high aspect ratio features, such as through-substrate vias, using an etch stop layer in semiconductor fluorine-based plasma etching processes.

[0004] BACKGROUND OF THE INVENTION

[0005] Through-substrate vias (TSVs) represent a critical enabling technology in fabrication of three-dimensional integrated circuits (ICs), as they are required for 3D stacking of multiple semiconductor chips or dies resulting in an advanced form of (micro)electronic device packaging with increased functionality per volume. A through-substrate via is a hole in a substrate, such as for example silicon, which is filled with a conductive material, such as copper, to enable electrical routing. These through-substrate interconnects provide electrical contact between conductive components to allow electronic devices to be stacked vertically for a broad range of applications, including biomedical, optoelectronic, photonic, display technologies, and microelectromechanical systems (MEMSs). TSVs enable direct signal routing vertically between chips, which results in shorter electrical path lengths, and hence reduces unwanted resistive, capacitive and inductive effects that occur in electrical circuits.

[0006] TSVs are typically produced using a combination of halogen / halide gases and plasma as etchants. Several gases are capable of etching of semiconductor substrates; however, fluorine-based etches may be preferred because of their high etch rates and an absence of toxicity concerns, as compared to chlorine (Cb) gas and hydrogen bromide (HBr) gas, for example.

[0007] In order to produce anisotropic etching profiles required to create high aspect ratio (HAR) features, such as deep trenches and through-substrate via holes, deep reactive ion etching (DRIE) techniques along with etched surface passivation have been utilized. Most commonly utilized modifications of DRIE include a pulsed- mode process (Bosch process), in which etching gases and passivation gases are supplied into a reaction space in alternating steps, and a mixed-mode process, in which both etching and passivation gases are supplied simultaneously. Nevertheless, one of the downsides of the Bosch process is that etch- and passivation steps result in etched features with characteristic scalloped sidewalls. These sidewall scallops are eliminated in the mixed-mode process, but that process requires more complex control and takes more overall time. Some other issues that arise from conventional DRIE processes include poor etch sidewall profile control, nonuniform etch depth, as well as etch size variations across the substrate.

[0008] Control over the etched profile depth uniformity can be improved by using etch stop layers (ESLs). ESLs are thin films applied over a substrate or other layers of a semiconductor stack, which stop the etch at a predetermined depth thus preventing over-etching and ensuring a uniform depth for etched features, such as etches TSVs. Common materials for ESLs in TSV technology include silicon nitride (SisN^, silicon oxynitride (SiON), silicon dioxide (SiCh), aluminium oxide (AI2O3), and titanium nitride (TiN), for example. However, some conventional ESLs, such as silicon dioxide and silicon (oxy)nitrides, fail to maintain integrity under the stress of prolonged etching and higher voltages applied to substrates during plasma etching processes (substrate biases), leading to issues in fabrication processes, such as inconsistent profiles and wafer surface contamination, and hence compromising electrical performance of the semiconductor device.

[0009] In this regard, as we continue to advance in the field of three-dimensional circuit integration and packaging, it becomes increasingly important to explore enhanced methods for creating high aspect ratio features. Therefore, the use of etch stop layers in plasma etching processes warrants further investigation.

[0010] SUMMARY OF THE INVENTION

[0011] An objective of the present invention is to solve or to at least alleviate each of the problems arising from the limitations and disadvantages of the related art. The objective is achieved by various embodiments of a method of producing a substrate structure with high aspect ratio features etched in a substrate, a related substrate structure for use in a semiconductor device, a method of manufacturing a semiconductor device, and a related semiconductor device, respectively. In an aspect, a method of manufacturing a semiconductor device is provided, according to what is defined in independent claim 1.

[0012] In an embodiment, the method of manufacturing a semiconductor device comprises:

[0013] - obtaining a substrate;

[0014] - forming an etch stop layer (ESL) over a substrate surface, wherein the etch stop layer comprises or consists of yttrium oxide;

[0015] - forming etched features in the substrate with a fluorine-based plasma until the etch stop layer is reached; and

[0016] - exposing the etch stop layer to the fluorine-based plasma.

[0017] In an embodiment, the method comprises formation of the etch stop layer using any one of Atomic Layer Deposition (ALD), Chemical Vapour Deposition (CVD), or Physical Vapour Deposition.

[0018] In embodiments, the fluorine-based plasma is generated from a fluorine-based gas selected from the group consisting of: sulfur hexafluoride (SFe), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), hexafluorobutadiene (C4F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), and any combination thereof.

[0019] In an embodiment, formation of etched features with the fluorine-based plasma is conducted using dry etching techniques, selected from any one of: plasma etching, reactive ion etching (RIE), and plasma sputtering.

[0020] In an embodiment, the at least one etched feature is a high aspect ratio (HAR) feature.

[0021] In an embodiment, the etched feature, such as the etched HAR feature, is an opening configured to extend vertically through the substrate and having a bottom formed with the etch stop layer and a sidewall.

[0022] In an embodiment, in said method, yttrium oxide of the etch stop layer reacts with fluorine reactive species contained in the fluorine-based etching plasma and undergoes fluorination with formation, on the ESL surface, of a fluorinated layer or film composed of yttrium oxyfluoride (YOF) and / or yttrium fluoride (YF3).

[0023] In an embodiment, the thickness of the fluorinated film formed on the surface of the ESL is within a range of about 0.01 nm to about 50 nm.

[0024] In an embodiment, the substrate comprises or consists of an element semiconductor, a compound semiconductor, an alloy semiconductor, a doped semiconductor, or any combination thereof. In embodiments, the substrate is selected from the group consisting of: glass, gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), gallium oxide (Ga2CF), aluminium oxide (AI2O3), silicon (Si), polycrystalline silicon (poly-Si), silicon dioxide (SiCh), silicon carbide (SiC), silicon-on-insulator (SOI), a doped silicon, a silicon alloy, a doped silicon alloy, and combination thereof.

[0025] In an embodiment, the method further comprises removal of the etch stop layer. In an embodiment, the method comprises selective removal of the etch stop layer from the bottom(s) of the etched feature(s).

[0026] In an embodiment, the method further comprises filling the etched feature with a conductive material to produce a conductive component, such as a through- substrate via.

[0027] In another aspect, a method of producing high aspect ratio features in a substrate is provided, according to what is defined in the independent claim 12.

[0028] In a further aspect, a substrate structure for use in semiconductor devices is provided, according to what is defined in independent claim 16.

[0029] In still a further aspect, a semiconductor device comprising a substrate structure, according to some previous aspect and related embodiments is provided, according to what is defined in the independent claim 17.

[0030] The utility of the present invention arises from a variety of reasons depending on each particular embodiment thereof.

[0031] Overall, the invention allows for improving resistance of the ESL to active plasma species during formation of HAR features in the substrate / wafer using dry etching methods. The ESL acts as a barrier for etching gases, ensuring that all HAR features, such as via holes, are etched to the same depth. By enhancing resistance to active plasma species, the integrity of the etch stop layer (ESL) can be preserved during plasma-based etching, even for longer etching periods and / or procedures conducted under higher substrate biases.

[0032] The method proposed herewith is straightforward and can be integrated into existing methods and equipment used for substrate processing in semiconductor manufacturing.

[0033] In the present disclosure, materials with a layer thickness below 100 micrometer (pm) are referred to as “thin films”.

[0034] The term “substrate” generally refers, in the present disclosure, to a base material, upon which further processes, such as patterning and deposition of various thin films and creation of nano- and / or microstructures, take place.

[0035] The expression “a number of’ refers herein to any positive integer starting from one (1), e.g. to one, two, or three; whereas the expression “a plurality of’ refers herein to any positive integer starting from two (2), e.g. to two, three, or four.

[0036] BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Fig. 1 illustrates, at steps (a-e), a process of manufacturing a semiconductor device, according to the embodiments.

[0038] Fig. 2 schematically illustrates a reaction between an etch stop layer and a fluorinebased plasma taking place during the process shown on Fig. 1.

[0039] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0040] Fig. 1 depicts a method for manufacturing a semiconductor device 10, according to the embodiments. The method comprises at least steps (a-e) which outline the phases of substrate processing and generation of etched patterns in the production of semiconductor devices.

[0041] The method begins at (a) with providing a substrate 20, which can be made of silicon or other suitable semiconductor material or a combination of materials. In embodiments, the substrate 20 may comprise or consist of: an element semiconductor, a compound semiconductor, an insulator, an alloy semiconductor, a doped semiconductor, or any combination thereof.

[0042] In embodiments, the substrate consists of silicon or comprises silicon or silicon- based compounds. The substrate 20 may thus consist of or comprise silicon (Si), polycrystalline silicon (poly-Si), silicon dioxide (SiCh), silicon carbide (SiC), silicon-on-insulator (SOI), or any combination thereof. The substrate 20 may consist of or comprise an alloy semiconductor, such as silicon-germanium (SiGe) or aluminium-silicon (AlSi). The substrate may consist of or comprise a doped semiconductor, such as silicon doped with trivalent elements (e.g. boron, aluminium, gallium, indium) or pentavalent elements (e.g. phosphorus, arsenic, or antimony) resulting in p- or n-type semiconductors, respectively, or a doped semiconductor alloy.

[0043] In exemplary embodiments of the method shown on Figs. 1 and 2 the substrate 20 is silicon (Si).

[0044] An etch stop layer (ESL) 11 is formed over a substrate surface (Fig la). In preferred embodiments, the ESL 11 comprises or consists of yttrium oxide Y2O3 (yttria). The ESL can be deposited by any one of Atomic Layer Deposition (ALD), Chemical Vapour Deposition (CVD), or Physical Vapour Deposition (PVD). Alternatively, the yttria layer may be deposited using for example sputtering techniques.

[0045] In preferred embodiment, the yttria ESL 11 is deposited using ALD, which term is intended to cover both thermal ALD and energy-enhanced ALD, such as plasma- enhanced ALD or photon-enhanced ALD.

[0046] In thermal ALD, the substrate is typically exposed to temporally separated reactive precursor and co-reactant pulses in a reaction vessel to deposit material on substrate surfaces by sequential self-saturating surface reactions. In energy- enhanced ALD, a co-reactant, typically water or ozone, is substituted with reactive plasma species (ions, atoms, radicals, etc.) generated by applying electrical fields to a flux of gas, such as H2, O2, N2, or NFL. Thin films grown by ALD are dense, pinhole free and have uniform thickness.

[0047] Deposition setup may be the one based on an ALD installation described in the U.S. patent no. 8211235 (Lindfors), for example, or on any installation, such as Picosun® R-200, P-300 or P-1000 ALD systems for thermal and energy-assisted processes, available from Picosun Oy, Finland. Any other suitable deposition equipment can be utilized.

[0048] An exemplary ALD reactor comprises a reaction chamber that establishes reaction space (deposition space), in which the substrates, such as silicon wafers, for example, can be deposited with thin film coatings. Reactor further comprises a number of appliances, such as intake lines and related switches and controls, configured to mediate the flow of inert and reactive gases into / from the reaction chamber. Withdrawal of fluids from the chamber is mediated by a vacuum pump. PE- ALD setup comprises a plasma source, configured as any one of capacitively coupled plasma (CCP) source, inductively coupled plasma (ICP) source, or a microwave plasma: source. The reactor / reaction chamber is preferably configured to implement a top-to-bottom flow; however other solutions are not excluded.

[0049] Substrates to be coated are typically loaded on a substrate holder, which, in turn, is provided inside the reaction chamber. The substrate holder may be configured as a movable table platform, or incorporate several shelves arranged into a vertical rack. Substrate holders of any other configuration may be utilized, depending on substrates to be coated and / or on implementation of a reactor apparatus in which the coating process is conducted (e.g. batch reactor with vertical or horizontal loading, reactor configured for continuous coating, etc.), which configurations may include, but are not limited to horizontal platforms, sample trays, racks of various design, and the like.

[0050] Overall, each ALD deposition cycle results in formation of 0.05-0.2 nm thick sublayer. This sequence is repeated until the desired material thickness is achieved. By way of example, a 20 nm coating layer may thus be deposited in 100 or 200 deposition cycles with exemplary growth rate 0.2 nm or 0.1 nm per deposition cycle, respectively.

[0051] Deposition sequence formed with deposition cycles that is controlled by a logic unit or a microprocessor. The deposition setup thus comprises a process control system configured to monitor and regulate its operation. The control system comprises at least one processor configured to at least control the deposition process, and at least one memory comprising a computer program, or a set of programs collectively referred to as software. The program or the software includes instructions or a program code to be executed by the processor to control the deposition setup. The process control system may be configured as a computerized system, which uses one or more computers.

[0052] ALD-growth of yttrium oxide ESL films 11 on substrate(s) 20, such as for example silicon wafers, can be achieved using a precursor for yttrium, and water or ozone as an oxygen source. Exemplary precursors for yttrium include for example yttrium tris(2,2,6,6-tetramethyl-3,5-heptanedionate) (Y(thd)3), yttrium tris(hexafluoracetylacetonate) (Y(hfac)3), and cyclopentadienyl-type yttrium compounds, such as (CFfiCp^Y and Cp;Y (CpdCsHs). An exemplary 100 nm Y2O3 film 11 can be deposited using multiple deposition cycles as required to achieve the desired thickness. Deposition temperature may vary within a range of about 50 °C to about 800 °C.

[0053] Fig. 1(a) schematically illustrate formation, on the substrate 20, of a redistribution layer (RDL) 12 typically made of a dielectric material, such as polymer, and comprising (metal) landing pads 13 for TSV. Formation of the RDL may be accomplished by any method known in the art. The substrate wafer 20 (with the RDL) is then flipped and bonded to a supporting substrate 22, also known as a carrier substrate, using a temporary adhesive 21, as shown on Fig. 1(b). Common materials used for support substrates include glass, GaN, GaAs, InP, Ga2CF, AI2O3, silicon, silicon carbide, gallium nitride (GaN), gallium arsenide (GaAs), and sapphire, depending on specific applications. An opposite side of the substrate 20 may be thinned, thereupon the thickness of the substrate material is reduced (not shown).

[0054] It is noted that although the RDL represents an important component in semiconductor packaging designs, in some scenarios it may be omitted (not shown). Designs without RDL involve for example 3D integration with TSVs (where TSVs may be connected to integrated circuits’ active layers of the stacked dies / chips bypassing RDLs), or direct chip-on-wafer (CoW) or wafer-on-wafer (WoW) bonding technologies.

[0055] The process continues at Fig. 1(c) with formation of etched features 31 in the substrate 20. Etching step is preceded with applying photoresist and mask using (photo)lithography techniques (not shown). Any alternative patterning technique may be utilized. Features 31 are etched into the substrate 20 preferably using dry etching techniques. Dry etching is preferred over a wet etching method, since the latter does not allow achieving good anisotropy in fabrication.

[0056] Dry etching methods and equipment utilized for formation of etched features 31 include, but are not limited to plasma etching, also referred to as plasma enhanced chemical reaction, reactive ion etching (RIE), including deep reactive ion etching (DRIE), and physical sputtering, also referred to as plasma sputtering. Dry etching is typically performed in a dedicated equipment comprising a vacuum reaction chamber, into which a selected etching gas is supplied using a shower head or related appliance. This gas is subjected to a strong electric field, generated with two opposite electrodes. Electric field ionizes the gas molecules resulting in formation of reactive (plasma) species, such as ions, atoms, and / or radicals.

[0057] In plasma etching, the substrate is attacked by radicals and the substrate material is converted into volatile compounds. The procedure is highly material-selective, but proceeds at relatively “high” pressure (about 1 Torr), which may lead to more isotropic etching (when material is etched uniformly in all directions). On the other hand, physical methods (plasma sputtering) are based on generation of ions in electrical filed, which collide with the substrate resulting in removal of the substrate material. The process proceeds at low pressure (< 10m Torr) and provides for more directional (anisotropic) etching.

[0058] RIE techniques combine the above described mechanisms and use both radicals for chemical reaction and ions for surface bombardment. Reactive ion etching proceeds at low pressure (< 10 mTorr) and can be adapted for fabrication of anisotropic nanofeatures. RIE techniques are hence particularly suitable for the purposes of the present invention.

[0059] The method disclosed in conjunction with Fig. 1 preferably utilizes fluorine -based plasma, i.e. the plasma generated from fluorine-containing gas. Fluorine - containing gases are less toxic compared to chlorine -based and bromine -based counterparts, and provide for higher etch rates. The gases utilized in the present invention for generation of the fluorine-based plasma, include, but are not limited to: sulfur hexafluoride (SFe), nitrogen trifluoride (NF3), and fluorocarbon gases, such as carbon tetrafluoride (CF4), hexafluoroethane (C2F6), hexafluorobutadiene (C4F6), trifluoromethane (CHF3), or any combination thereof. In preferred embodiment, the SFe plasma was utilized.

[0060] Fluorine-containing gas dissociates in the plasma to form reactive species. In RIE methods, fluorine containing gas generates both fluorine radicals and ions, where radicals, as highly reactive species, effectively break chemical bonds of the substrate material, and hence selectively remove material during plasma etching, in particular, during plasma etching of silicon. On the other hand, fluorine ions, being directed perpendicularly towards the substrate surface, collide with said surface resulting in highly directional etching (anisotropic etching), which is essential in creating vertical sidewalls and high aspect ratio features in microfabrication.

[0061] Reactive fluorine species exhibit chemical selectivity toward the etch mask, allowing the etching process to proceed selectively at the unmasked substrate regions. That the etched features 31 are formed on unmasked regions is shown on Fig. 2, where the mask layer of designated with reference numeral 23.

[0062] Etching process continues until the etch stop layer 11 is reached (Fig. 1 (c)). In an embodiment, each etched feature 31 is configured to extend vertically through the substrate 20 to form an opening having sidewall(s) 32 and a bottom 33. In an embodiment, the etched features 31 are configured as via holes (through-substrate holes) (see Fig. 1(c)). In such an event the bottom 33 of the etched TSV is formed with the etch stop layer 11. Additionally or alternatively, the etched features may be provided as deep trenches etched into the substrate but not reaching the ESL 11 (not shown). Etched features 31 may preserve essentially the same profile across the etched region, or the etched profiles may vary in terms of at least dimension and shape. The example of Fig. 1(c) shows that two features 31 have a tapered profile, but the feature on the right is slightly narrower than the feature on the left, i.e. the width of the profile on the right has decreased. The etches features 31 may be provided with any one of tapered, vertical, or reentrant sidewall profiles, or a combination thereof. On the other hand, the depth of the etched features 31 is preferably defined by the ESL 11, i.e. all features 31 across the etched region have the same depth. In an embodiment, the etched features 31 are high aspect ratio (HAR) features.

[0063] When the etched feature has reached the ESL 11 , the method continues at Fig. 1 (d), with exposing the ESL to the fluorine-based plasma. When the ESL is made of yttrium oxide (Y2O3), according to the embodiment, exposing yttrium oxide to fluorine reactive species contained in the fluorine-based etching plasma results in fluorination of yttrium oxide with formation a thin fluorinated layer or film 15 (Fig. 2(b)). In embodiments the fluorinated film 15 is composed of yttrium oxyfluoride (YOF) and / or yttrium fluoride (YF3).

[0064] Fluorination of yttrium oxide is described in more detail with reference to Fig. 2. Overall, Fig. 2 schematically illustrates the events occurring at step (c) of the method depicted on Fig. 1. Fig. 2(a) shows that reactive species 14, herewith, fluorine reactive species such as fluorine radicals and / or fluorine ions, generated by a plasma source 51 are directed towards the exposed etch stop layer 11, which forms the bottom 33 of the etched feature 31. After exposure to said fluorine reactive species contained in the fluorine-based etching plasma (in described setup, the SFe plasma was utilized, according to the preferred embodiment), the Y2O3 film (ESL 11) surface undergoes fluorination to form a fluorinated yttria layer / film 15. The fluorinated film 15 formed on the surface of as-deposited Y2O3 (i.e. on the surface of ESL 11) is typically composed of yttrium oxyfluoride (YOF). TEM analysis of the Y2O3 ESL 11 after surface irradiation by fluorine-based plasma has demonstrated that the fluorinated film 15 contains multiple phases of YOF.

[0065] Upon further exposure to the fluorine-based plasma, the YOF surface layers may further be converted to YF3.

[0066] Fluorinated film 15 composed of YOF and / or YF3 has a thickness within a range of about 0.01 nm to about 50 nm. In an embodiment, after exposure to the fluorinebased plasma, the Y2O3 film (ESL 11) surface is fluorinated to form a fluorinated film 15 having an approximate average thickness of 0.1-40 nm. Fluorinated yttrium oxide exhibits better resistance to the etching gases, hence improving the ability of the ESL to maintain its integrity during longer etching processes and / or etching under higher substrate biases. Fortifying the ESL 11 with the fluorinated film 15, in fluorine-based plasma etching, contributes to maintaining the uniformity of etched features 31 and prevents their collapse or damage during fabrication. Moreover, the fluorinated surface layer 15 has been shown to accumulate less contamination particles, which arise during the etching process.

[0067] In an embodiment, the process continues, at Fig. 1 (d), with removal of the etch stop layer 11. The ESL 11 is selectively removed from the bottom of the etched features 31 configured as via-holes to establish a contact between the through- substrate via and the conductive landing pad 13. Contact point between the etched feature 31 and the landing pad 13 is shown on Fig. 1(d) with a dashed circle. Depending on design requirements and intended electrical connections within the semiconductor device, the TSV may be connected with any suitable contact layer or structure beneath it. In some approaches, such as via-first or via-middle integration flows (see description below), TSVs may be electrically connected to active circuitry layers.

[0068] The ESL is typically removed by wet etching. Exemplary procedure for selective ESL removal may involve immersion of the substrate in a solution of buffered hydrofluoric acid (BHF) provided as a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F), followed with rinsing with deionized water and drying.

[0069] With reference back to Fig. 1, once the ESL is selectively etched at the bottoms of the etched features 31 (step d), the method continues deposition of insulation and barrier layers over the etched feature surface (i.e. over the sidewalls 32 and the bottom 33 void of ESL), followed with insulation bottom opening and deposition of a conductive seed layer, such as copper or platinum (not shown). Insulation layer may be composed of silicon oxide or silicon nitride, for example, while the barrier layer may be composed of metals (e.g. titanium or tantalum) or their nitrides. Each of these layers may be deposited using PVD, CVD or ALD methods. Overall, deposition of insulation and barrier layer, and deposition of the seed layer may follow conventional procedures omitted from the present description.

[0070] In some approaches used to incorporate through-substrate vias in semiconductor manufacturing, removal of the ESL (Fig. 1 (d)) may be omitted from the method (not shown). This is possible if the semiconductor design allows for the ESL to remain as an insulating layer between the TSV conductive material thereof) and adjacent conductive layers or structures beneath. Fig. 1 (e) illustrates filling the etched feature 31 (provided with protective- and seed layers described hereinabove) with a conductive material 41 to produce a conductive component, such as a through-substrate via (TSV). Typically, copper is used as a filling material, due to its excellent electrical conductivity, relatively low cost and compatibility with existing semiconductor processing technologies. Still, utilization of other suitable conductive materials for filling TSVs, such as for example, gold, silver, nickel, tungsten, carbon nanotubes, or conductive polymers, is not excluded.

[0071] When copper is used as a conductive material 41, the filling step is typically accomplished using electroplating, during which the substrate with a pre-applied seed layer is submerged in an electrolyte solution, and an electrical current is applied. Metal ions (e.g. copper ions) in the electrolyte solution are reduced and deposited onto the seed layer, gradually filling the etched feature 31 from the bottom up. Filling step (Fig. 1(e)) is followed with a planarization process (not shown) aiming at removal of an excess copper and achieving a smooth, planar surface. While the most common method for planarization includes chemical mechanical planarization (CMP), any other suitable methods, such as for example electropolishing, laser ablation, or ion beam planarization, are not excluded.

[0072] A substrate structure 10 for use with a semiconductor device is thus formed.

[0073] It is noted that the method depicted on Fig. 1 illustrates a TSV integration flow, according to a so called via-last integration approach adopted in the fabrication of integrated circuits in semiconductor manufacturing. The last-via approach involves the integration of TSV modules after (or during) the fabrication of multiple layers of metal interconnects, also referred to as metallization layers, used to connect semiconductor components (transistors, diodes, resistors, capacitors, etc.) of the circuitry layers and to form a complete circuit in a back-end-of-line (BEOL) process. However, the method of Fig. 1 can be adapted for any one of via- first and via-middle integration flows. Via-first approach involves formation of TSV modules before active or operational circuitry of the semiconductor device is fabricated (FEOL, Front-end of the line) on a substrate / wafer to be connected to said active circuitry layers thereafter. Via-middle approach, in turn, involves formation of TSVs after the active circuitry is fabricated on the substrate, but before fabrication of metallization layers (BEOL).

[0074] Typical process of manufacturing a semiconductor device thus involves integration of the TSV-integrated substrate wafer with other semiconductor components, such as transistors, diodes, resistors, and capacitors. This integration can for example include chip stacking or the formation of RDLs (if required and not yet formed), followed by final interconnection and packaging (not shown). The process of finalizing a semiconductor device largely depends on the specific package design and related technology, can varies depending on the components used in manufacturing, the integration techniques employed, and the desired performance characteristics of the device. For these reasons, the finalization stages are omitted from the present disclosure.

[0075] The invention further pertains to a method of producing high aspect ratio (HAR) features in a substrate, the method comprising: obtaining a substrate 20; forming an etch stop layer (ESL) 11 over a substrate surface; forming HAR features 31 in the substrate 20 with a fluorine-based plasma until the ESL 11 is reached; and exposing the ESL 11 to the fluorine-based plasma. In an embodiment, the ESL 11 comprises or consists of yttrium oxide (Y2O3).

[0076] Overall, the method of producing HAR features in the substrate generally follows the procedure according to Fig. 1 (c-d) and Fig. 2, and related embodiments. In the method, the fluorine-based plasma can thus be generated from a fluorine-based gas selected from the group consisting of: sulfur hexafluoride (SFe), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), hexafluorobutadiene (C Fe), nitrogen trifluoride (NF3), trifluoromethane (CHF3), and any combination thereof. In preferred embodiment, the SFe plasma was utilized.

[0077] In embodiments, formation of HAR features 31 using fluorine-based plasma is conducted using dry etching techniques selected from any one of: plasma etching, reactive ion etching (RIE), and plasma sputtering, and described herein above.

[0078] In an embodiment, yttrium oxide of the ESL 11 reacts with fluorine reactive species 14 contained in the fluorine-based etching plasma and undergoes fluorination with formation, on the ESL surface, of a fluorinated film 15 composed of yttrium oxy fluoride (YOF) and / or yttrium fluoride (YF3). In an embodiment, the HAR feature 31 is provided as an opening configured to extend vertically through the substrate 20 and having a bottom 33 formed with the etch stop layer 11 and a sidewall 32. In such an event, the fluorinated filml5 is formed at the bottom of the high aspect ratio feature 31.

[0079] The invention further pertains to a substrate structure 10 for use in semiconductor devices. The substrate structure 10 comprises: a substrate body 20, an etch stop layer (ESL) 11 formed over a surface of the substrate body, and at least one feature 31 etched in the substrate by fluorine-based plasma. The ESL 11 preferably comprises or consists of yttrium oxide. The etched feature(s) 31 is / are configured as opening(s) extending vertically through the substrate 20 and having a bottom 33 formed with the etch stop layer 11 and a sidewall 32. In an embodiment, said at least one etched feature 31 is a high aspect ratio (HAR) feature.

[0080] In an embodiment, the substrate structure 10 comprises a fluorinated film 15 composed of yttrium oxyfluoride (YOF) and / or of yttrium fluoride (YF3) formed at the bottom of said etched HAR feature 31 upon exposure of the ESL layer to the fluorine-based plasma. The fluorinated film 15 forms as a product of fluorination reaction between yttrium oxide of the ESL 11 and the fluorine-based plasma (reactive species 14 thereon).

[0081] In an embodiment, the substrate structure comprises the HAR features 31 filled with the conductive material 41, such as for example copper. Said HAR features 31 filled with the conductive material advantageously form conductive components, such a through-substrate vias (provided that the etched HAR feature 31 is through-substrate hole). In an embodiment, in said substrate structure 10, the ESL layer 11 is selectively removed from the bottoms of the etched HAR features 31 (before the features 31 are filled with the conductive material 41).

[0082] In an embodiment, the substrate structure 10 is produced using a method described with regard to Fig. 1 (a-e) and related embodiments.

[0083] The invention further pertains to a semiconductor device comprising a substrate structure 10 according to some previous embodiments, and / or produced using a method described hereinabove. The semiconductor device advantageously comprises a substrate-through via or vias formed with high aspect ratio features 31 etched in the substrate 20 of the substrate structure 10, said etched HAR features 31 being filled with a conductive material 41.

[0084] The semiconductor device further comprises a number of active (e.g. transistors, diodes) and passive (e.g. resistors, capacitors) components. Advanced semiconductor devices, such as 3D integrated circuits and / or System-on-Package (SiP) devices include stacked dies interconnected with TSVs, and multiple layers of metal interconnects. In embodiments, the semiconductor device can thus be configured as any one of: a memory device, an image sensor, a 3D integrated circuit, a System-in-Package (SiP) device, and a System-on-Chip (SoC) device. It shall be appreciated by those skilled in the art that with the advancement of technology the basic ideas of the present invention may be implemented and combined in various ways. The invention and its embodiments are thus not limited to the examples described hereinabove, instead they may generally vary within the scope of the claims.

Claims

Claims1. A method of manufacturing a semiconductor device, the method comprising:- obtaining a substrate (20),- forming an etch stop layer (ESL) (11) over a substrate surface, wherein the etch stop layer comprises or consists of yttrium oxide,- forming etched features (31) in the substrate with a fluorine-based plasma until the etch stop layer (11) is reached, and- when the etched feature has reached the ESL (11), exposing the etch stop layer (11) to the fluorine-based plasma, wherein the etched features (31) are high aspect ratio features (HAR), and wherein, a fluorinated film (15) is formed on the ESL (11) surface, when fluorine reactive species (14) contained in the fluorine-based etching plasma react with yttrium oxide of the etch stop layer (11), said fluorinated film (15) being composed of yttrium oxyfluoride (YOF) and / or yttrium fluoride (YF3).

2. The method of claim 1, wherein the etch stop layer (11) is formed on the substrate (20) using any one of Atomic Layer Deposition (ALD), Chemical Vapour Deposition (CVD), or Physical Vapour Deposition.

3. The method of claim 1, wherein the fluorine-based plasma is generated from a fluorine-based gas selected from the group consisting of: sulfur hexafluoride (SFe), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), hexafluorobutadiene (C Fe), nitrogen trifluoride (NF3), trifluoromethane (CHF3), and any combination thereof.

4. The method of any preceding claim, wherein formation of etched features (31) with the fluorine-based plasma is conducted using dry etching techniques, selected from any one of: plasma etching, reactive ion etching (RIE), and plasma sputtering.

5. The method of claim 1, wherein the etched feature (31) is an opening configured to extend vertically through the substrate (20) and having a bottom (33) formed with the etch stop layer (11) and a sidewall (32).

6. The method of claim 1, wherein the thickness of the fluorinated film (15) formed on the surface of the ESL (11) is within a range of about 0.01 nm to about 50 nm.

7. The method of any preceding claim, wherein the substrate (20) comprises or consists of an element semiconductor, a compound semiconductor, an alloy semiconductor, a doped semiconductor, or any combination thereof.

8. The method of any preceding claim, wherein the substrate (20) is selected from the group consisting of: glass, gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), gallium oxide (Ga2Ch), aluminium oxide (AI2O3), silicon (Si), polycrystalline silicon (poly-Si), silicon dioxide (SiCh), silicon carbide (SiC), silicon-on-insulator (SOI), a doped silicon, a silicon alloy, a doped silicon alloy, and combination thereof.

9. The method of claim 1, further comprising removal of the etch stop layer (11).

10. The method of any one of claims 5 or 6, comprising selective removal of the etch stop layer (11) from the bottom (33) of the etched feature (31).

11. The method of any preceding claim, further comprising filling the etched feature (31) with a conductive material (41) to produce a conductive component, such as a through-substrate via.

12. A method of producing high aspect ratio features in a substrate, comprising:- obtaining a substrate (20),- forming an etch stop layer (ESL) (11) over a substrate surface, wherein the etch stop layer comprises or consists of yttrium oxide,- forming high aspect ratio features (31) in the substrate with a fluorinebased plasma until the etch stop layer (11) is reached, and- when the etched feature has reached the ESL (11), exposing the etch stop layer (11) to the fluorine-based plasma, wherein, a fluorinated film (15) is formed on the ESL (11) surface, when fluorine reactive species (14) contained in the fluorine-based etching plasma react with yttrium oxide of the etch stop layer (11), said fluorinatedfilm (15) being composed of yttrium oxyfluoride (YOF) and / or yttrium fluoride (YF3).

13. The method of claim 12, wherein the fluorine-based plasma is generated from a fluorine-based gas selected from the group consisting of: sulfur hexafluoride (SFe), carbon tetrafluoride (CF4), hexafluoroethane (C2F6), hexafluorobutadiene (C4F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), and any combination thereof.

14. The method of any one of claims 12 or 13, wherein formation of high aspect ratio features (31) with the fluorine-based plasma is conducted using dry etching techniques, selected from any one of: plasma etching, reactive ion etching (RIE), and plasma sputtering.

15. The method of any preceding claim 12-14, wherein the high aspect ratio feature (31) is an opening configured to extend vertically through the substrate (20) and having a bottom (33) formed with the etch stop layer (11) and a sidewall (32), and wherein the fluorinated film (15) is formed at the bottom of the high aspect ratio feature (31).

16. A substrate structure (10) for use in semiconductor devices, comprising: a substrate body (20), an etch stop layer (11) formed over a surface of the substrate body and comprising or consisting of yttrium oxide, and at least one high aspect ratio feature (31) etched in the substrate with fluorine-based plasma, said at least one high aspect ratio feature (31) being configured as an opening extending vertically through the substrate (20) and having a bottom (33) formed with the etch stop layer (11) and a sidewall (32), wherein the substrate structure comprises a film (15) of yttrium oxy fluoride (YOF) and / or yttrium fluoride (YF3) at the bottom of the high aspect ratio feature, said film formed upon fluorination of yttrium oxide of the etch stop layer (11) with fluorine-based plasma.

17. A semiconductor device comprising a substrate structure (10) as defined in claim 16, said device comprising a substrate-through via or vias formed with high aspect ratio features (31) provided in said substrate structure and filled with a conductive material (41).

18. The semiconductor device of claim 17, configured as a memory device, an image sensor, a 3D integrated circuit, a System-in-Package (SiP) device, and a System-on-Chip (SoC) device.

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