Method for providing metal contacts on a two-dimensional material layer structure and corresponding electronic device

Abstract

The disclosed invention provides a method for forming metal contacts on a two-dimensional material layer structure such as graphene, which comprises (i) providing a laminate comprising an inorganic dielectric layer (920) on a two-dimensional material layer structure (910) overlying a substrate (900), (ii) wet-etching, within each of a plurality of regions, a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two-dimensional material layer structure and form a corresponding group of wells (915) in the dielectric layer, and (iii) performing metallisation by depositing one or more metals (925') and forming a plurality of contact pads (925), wherein each contact pad (925) is in electrical communication with the two-dimensional material layer structure (910) through a group of metal vias (925a) filling a corresponding group of wells. Also provided are electronic devices which may be obtained by the method, such as Hall sensors and field effect transistors.

Description

[0001] Methods for the provision of metal contacts on a two-dimensional material layer structure

[0002] The present invention relates to methods for the provision of metal contacts on a two-dimensional material layer structure. The present invention also relates to an electronic device comprising metal contacts on a two-dimensional material layer structure, which device may be obtained by the methods. More particularly, metal for the contacts is deposited in wells in a dielectric layer provided on a surface of the two-dimensional material layer structure, the metal contacting the surface of the two-dimensional material layer structure (i.e. providing “top” contacts).

[0003] Two-dimensional (2D) materials, in particular graphene, and their electronic devices are currently the focus of intense research and development worldwide. 2D materials have been shown to have extraordinary properties, both in theory and in practice which has led to a deluge of products incorporating such materials which include coatings, batteries and sensors to name but a few. Graphene is arguably the most prominent, though transition metal dichalcogenides (TMDs) such as M0S2 and heterostructures of 2D materials are often also the focus of developments, and these are all being investigated for a range of potential applications. Most notable is the use of 2D materials such as graphene in electronic devices and their constituent components which includes transistors, diodes, LEDs, photovoltaic cells, optical modulators, photodetectors, Hall-effect sensors, current sensors, biosensors, gas sensors and the like.

[0004] Due to the exceptionally thin nature of two-dimensional materials, and their often minimal interaction with the underlying substrate / wafer generally being based on weak van der Waals interactions, the inventors have found that such materials are particularly susceptible to delamination. Such a problem can arise during manufacture and the deposition of various layers on and over two-dimensional materials. This problem is also especially pronounced under subsequent solution-based processing and other environments and occasions where the two-dimensional material is re-exposed to liquids and solutions (e.g. during wet photolithography patterning). Such processing is necessary for patterning the two-dimensional material (at least for wafer scale mass manufacture of devices) as well as contact deposition.

[0005] As identified in a review article by Zheng et al. in Cell Reports Physical Science 2021 , 2, 100298 “Ohmic Contact Engineering for Two-Dimensional Materials”, one of the major areas of semiconductor device research is the development of transparent or ohmic contacts between semiconductors and metal electrodes for the efficient injection of charge carriers into the conduction channel, particularly conduction channels formed from 2D materials. The review presents variety of engineering strategies for contacting 2D materials. One such technique includes the formation of an “edge” contact to the 2D material. The one-dimensional (1 D) edge contact is said to enable stronger orbital overlap at the 2D / metal interface due to the existence of dangling bonds at the edge. The Applicant has previously developed a method, as described in US 2022 / 0178872, by which wrinkles in a graphene layer structure are plasma-etched to create / expose edges of the graphene, and metal is then deposited in the plasma-etched portion to contact the edges.

[0006] The Applicant has also developed a range of methods and products which may include edge contacts to graphene, details of which may be found in WO 2022 / 129606, WO 2022 / 129570, WO 2023 / 067309, WO 2023 / 237561 . The methods and products include a graphene layer structure capped (or co- patterned) with one or more layers of dielectric material, with metal contacts being provided in contact with only the edge of the graphene layer structure. The dielectric material provides protection for the graphene layer structure.

[0007] US 2021 / 0043830 discloses a method for providing edge contacts to low dimensional materials such as graphene.

[0008] Edge contacts are therefore desirable in theory as a solution to the problem of improving (reducing) contact resistance. However, despite these developments in the art, the present inventors have found that there are problems with providing a consistent and reliable edge contact, particularly across multiple contacts in a device and / or an array of devices, due to the very small contact “area” being susceptible to damage during processing and patterning. Any damage during these steps therefore has a greater effect on the electronic properties of the interface due to the small size.

[0009] An alternative method developed by the Applicant which includes a polymer coating to protect a graphene layer structure, as described in WO 2021 / 008939, involves contacting the polymer coating with a conductive metal-containing solution, wherein the polymer coating is soluble in the solvent to provide “top” contacts by a fast and low-cost processing method. However, polymer coatings are not particularly suitable for providing robust protection for two-dimensional materials in electronic devices and / or are unsuitable for subsequent device manufacture and thus less desirable for many applications. arXiv:1802.02197v1 [cond-mat.mes-hall] “Via Method for Lithography Free Contact and Preservation of 2D Materials” discloses a technique for contacting 2D materials, in which metal via contacts are integrated into flakes of insulating hexagonal boron nitride, and then placed (i.e. transferred) onto the desired conducting 2D layer, avoiding direct lithographic patterning onto the 2D conductor.

[0010] Nature Electronics 2019, 2, 187 “Transferred via contacts as a platform for ideal two-dimensional transistors” similarly discloses transferred via contacts, made from metal embedded in insulating hexagonal boron nitride and dry transferred onto 2D semiconductors. However, transfer methods are not desirable at least because they are unsuitable for accurate mass manufacture of devices at wafer scale (i.e. for producing an array of devices on a common underlying substrate). As such, improved methods for forming contacts that are suitable for commercial production are still needed in the art.

[0011] US 2013 / 146847 relates to semiconductor structures and methods of manufacture and, more particularly, to a graphene field effect transistor (FET). The method includes: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.

[0012] US 2023 / 069273 discloses a FET, and a method for manufacturing such FET. The FET includes a substrate carrying a gate electrode, a gate dielectric layer, and a channel layer sequentially stacked on the substrate. An insulating layer, an etching stop layer, and a protective layer are stacked sequentially on the channel layer. Source and drain electrodes are also formed. A material of the channel layer includes a 2D material. The FET defines two through holes extending through the insulating layer, the etching stop layer, and the protection layer and the channel layer is exposed, the two through holes carry the source and drain electrodes to form a top or direct contact with the channel layer.

[0013] US 8445320 discloses a semiconductor device including a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

[0014] The present invention aims to overcome, or at least reduce, the aforementioned problems in the prior art, so as to improve the reliability of device manufacture and the required metal contacts into robust electronic devices, or to at least provide a commercially viable alternative thereto.

[0015] Thus, a first aspect of the present invention provides a method for the provision of metal contacts on a two-dimensional material layer structure, the method comprising:

[0016] (i) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm; (ii) depositing a first resist on and across the inorganic dielectric layer and patterning the first resist to expose a plurality of portions of the dielectric layer;

[0017] (iii) wet-etching the plurality of portions of the dielectric layer to expose a corresponding plurality of surface portions of the two-dimensional material layer structure and form a plurality of wells in the dielectric layer;

[0018] (iv) performing a first metallisation step by depositing a first metal on and across the exposed plurality of surface portions of the two-dimensional material layer structure and the patterned first resist and then removing the patterned first resist by lift-off to form metal plugs substantially filling the wells of the dielectric layer; and

[0019] (v) performing a second metallisation step by depositing a second metal and forming a plurality of metal contact pads, each contact pad in contact with one or more of the metal plugs.

[0020] A second aspect of the present invention provides an electronic device comprising: a substrate having a patterned two-dimensional material layer structure thereon, the two- dimensional material layer structure having edges; an inorganic dielectric layer co-patterned with the two-dimensional material layer structure, wherein the dielectric layer has a thickness from an upper surface to the two-dimensional material layer structure of less than 80 nm; a passivation layer protecting at least the edges of the patterned two-dimensional material layer structure; and a plurality of metal plugs substantially filling wells in the dielectric layer, wherein each plug extends from a surface portion of the two-dimensional material layer structure to one of a plurality of metal contact pads provided on the dielectric layer or the passivation layer; wherein each well has a cross-sectional area co-planar with the substrate of less than 2,500 pm2and has a maximum width of less than 50 pm.

[0021] A third aspect of the present invention provides a method for the provision of metal contacts on a two- dimensional material layer structure, the method comprising:

[0022] (i) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm;

[0023] (ii) wet-etching, within each of a plurality of regions of the laminate structure, a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two- dimensional material layer structure and form a corresponding group of wells in the dielectric layer, wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm;

[0024] (iii) performing one or more metallisation steps by depositing one or more metals and forming a plurality of contact pads, wherein each contact pad is in electrical communication with the two- dimensional material layer structure through a group of metal vias filling one of the corresponding group of wells.

[0025] A fourth aspect of the present invention provides an electronic device comprising: a substrate having a patterned two-dimensional material layer structure thereon, the two- dimensional material layer structure having edges; an inorganic dielectric layer co-patterned with the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm; and a plurality of contact pads, each contact pad comprising a group of metal vias filling wells in the dielectric layer; wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm.

[0026] The present disclosure will now be described further. In the following passages, different aspects / embodiments of the disclosure are defined in more detail. Each aspect / embodiment so defined may be combined with any other aspect / embodiment or aspects / embodiments unless clearly indicated to the contrary. In particular, any feature indicated as being preferred or advantageous may be combined with any other feature or features indicated as being preferred or advantageous.

[0027] It is intended that the features disclosed in relation to the methods may be combined with those disclosed in relation to the electronic device (and the array described herein) and vice versa. In particular, the method of the first aspect is one suitable for manufacturing the electronic device of the second aspect, and the third aspect is one suitable for manufacturing the electronic device of the fourth aspect. More particularly, the first and third aspects provide alternative methods which, in embodiments, can afford essentially the same product. Accordingly, the electronic device is obtainable by the methods disclosed herein.

[0028] The present invention relates to methods for the provision of metal contacts on a two-dimensional material layer structure. Specifically, the method provides “top” contacts, in which these metal contacts are deposited on the surface of the two-dimensional material layer structure and do not contact any edges of the two-dimensional material layer structure.

[0029] Two-dimensional materials per se are well-known, the most preferred for the present invention being graphene. Two-dimensional materials include mono-elemental two-dimensional materials such as graphene, silicene, phosphorene (black phosphorus), borophene (all of which may be doped or undoped) as well as hetero-elemental two-dimensional materials such as transition metal dichalcogenides (TMDs), for example M0S2, WS2 and MoSe2 (a monolayer being known in the art to refer to a layer of MX2 stoichiometry). The device therefore comprises a semiconducting / semimetallic two-dimensional material, preferably graphene, phosphorene, or a TMD due to the unique electronic properties of such materials being desirable for electronic devices, particularly for at least the uppermost layer of the layer structure which provides the surface on which the metal contacts are deposited. For many devices such as sensors, undoped (e.g. pristine or unintentionally doped) two- dimensional material is preferred for device manufacture.

[0030] A two-dimensional material layer (which may be referred to herein as a two-dimensional material layer structure, for example a graphene layer structure consisting of graphene) preferably has from 1 to 10 monolayers of two-dimensional material. Preferably the two-dimensional material layer is comprised of a single monolayer. A preferred multilayer structure would have 2 or 3 monolayers. In some embodiments, all of the monolayers are of the same two-dimensional material (e.g. bilayer graphene), though in some preferred embodiments, the multilayer structure may be a heterostructure. By way of example only, the two-dimensional material layer structure may be a TMD on graphene.

[0031] A monolayer of graphene has a known thickness of about 0.34 nm, that of monolayer phosphorene is about 0.85 nm, and that of a monolayer of TMD can be in the region of about 0.6 to about 0.7 nm. As described in greater detail herein, the method is resilient to delamination of such thin materials from the surface of the substrate during manufacture. Any reference herein to graphene may be understood to extend to two-dimensional materials, unless the context clearly indicates otherwise. Graphene is the most preferred embodiment.

[0032] The method comprises a step (i) of providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure.

[0033] The two-dimensional material layer structure may be patterned as discussed further herein. Patterning is a well-known technique in the art of microfabrication and semiconductor manufacturing (i.e. semiconductor device fabrication). A patterned two-dimensional material layer structure has a shape with one or more edges, typically multiple straight edges defining a polygon. The patterned two-dimensional material layer structure typically is a “solid” or “filled” shape with only outer edges, through some embodiments may adopt more complex patterns whereby the layer structure has holes or the like, such as a “ring” shape. Suitable shapes for the intended device application are well-known to those skilled in the art.

[0034] In some preferred embodiments, the two-dimensional material layer structure is provided on and across the substrate (e.g. an entire wafer) without having been patterned before step (ii). It is generally preferred that step (i) of providing the laminate comprises forming the two-dimensional material layer structure directly on and across the substrate, especially by CVD, and the two- dimensional material subsequently patterned. The preparation of sufficiently large area graphene with high uniformity has been major problem in the art which has hindered the uptake of graphene in commercial processes and ultimately electronic devices. The standard in the art is to manufacture graphene by CVD on copper foils or other catalytic metal substrates. A significant proportion of research and development has since focussed on the need to optimise the process by which graphene is transferred from such substrates to those of interest for electronic devices (i.e. non-metallic substrates, for example semiconductors such as silicon and insulators such as sapphire).

[0035] However, the inventors found that graphene grown on copper is inevitably contaminated, if not with copper, at least with the additional materials which are essential to effect the transfer. These include transfer polymers such as PMMA, metal etchants and solvents to remove the polymer. Polymer residues are however never fully removed and graphene provided by such methods cannot be devoid of transfer polymers and / or copper, which is achieved by direct CVD-grown material. Additionally, the physical manipulation of the graphene during transfer leads to defects in the atomically thin material. Unintentional doping, particularly from the catalytic metal substrates together with the etching solutions also results in the production of material which is not sufficiently consistent from sample to sample. This is required for commercial production of electronic devices such that the method of manufacture described herein is more consistent from wafer to wafer and device to device with graphene grown directly on the substrate by CVD.

[0036] The physical transfer of two-dimensional materials can introduce numerous defects which negatively impacts the physical and electronic properties. As such, a person skilled in the art can readily ascertain whether a graphene layer structure, and by extension a device, is one comprising a CVD- grown graphene layer structure that has been grown directly using conventional techniques in the art such as AFM and energy dispersive X-ray (EDX) spectroscopy.

[0037] Forming may be considered synonymous with synthesising, depositing, producing and growing. CVD refers generally to a range of chemical vapour deposition techniques, each of which involve deposition to produce thin film materials such as two-dimensional crystalline materials like graphene, optionally under vacuum / reduced pressure. Volatile precursors, those in the gas phase or suspended in a gas, are decomposed to liberate the necessary species to form the desired material, carbon in the case of graphene. CVD as described herein is intended to refer to thermal CVD such that the formation of graphene from the decomposition of a carbon-containing precursor is the result of the thermal decomposition of said carbon-containing precursor. The description herein for the CVD of graphene may be modified accordingly to produce other two-dimensional materials.

[0038] Preferably, the temperature of the growth surface during CVD is from 700°C to 1 ,350°C, preferably from 800°C to 1 ,250°C, more preferably from 1000°C to 1 ,250°C. The inventors have found that such temperatures are particularly effective for providing graphene growth directly on the materials described herein by CVD. Lower temperatures may be used for CVD growth of other two-dimensional materials. For example, the temperature of the growth surface for TMD growth may be less than 500°C, such as from 100°C to 400°C. Preferably, the CVD reaction chamber used in the method disclosed herein is a cold-walled reaction chamber wherein a heater coupled to the substrate is the only source of heat to the chamber.

[0039] As will be appreciated by those skilled in the art, the temperature setting input to some CVD reactors (i.e. set temperature) will generally be greater than the actual wafer temperature (such as with MOCVD reactors available from Aixtron®). The set temperature may be 100°C (or more) greater than the wafer temperature, for example from 1 ,300°C to 1 ,400°C. The wafer temperature may be measured using conventional techniques, for example using an optical probe. Other apparatuses may have a temperature feedback control whereby the reactor achieves the same wafer temperature as the input temperature (such as with high rotation rate MOCVD reactors available from Veeco®).

[0040] In a particularly preferred embodiment, the CVD reaction chamber comprises a close-coupled showerhead having a plurality, or an array, of precursor entry points. Such CVD apparatus comprising a close-coupled showerhead may be known for use in MOCVD processes. Accordingly, the method may alternatively be said to be performed using an MOCVD reactor comprising a close-coupled showerhead. In either case, the showerhead is preferably configured to provide a minimum separation of less than 100 mm, more preferably less than 25 mm, even more preferably less than 10 mm, between the surface of the substrate and the plurality of precursor entry points. As will be appreciated, by a constant separation it is meant that the minimum separation between the surface of the substrate and each precursor entry point is substantially the same. The minimum separation refers to the smallest separation between a precursor entry point and the substrate surface. Accordingly, such an embodiment involves a “vertical” arrangement whereby the plane containing the precursor entry points is substantially parallel to the plane of the exposed substrate surface (i.e. the growth surface).

[0041] The precursor entry points into the reaction chamber are preferably cooled. The inlets, or when used, the showerhead, are preferably actively cooled by an external coolant, for example water, so as to maintain a relatively cool temperature of the precursor entry points such that the temperature of the precursor as it passes through the plurality of precursor entry points and into the reaction chamber is less than 100°C, preferably less than 50°C. For the avoidance of doubt, the addition of precursor does not constitute heating the chamber or cooling the inlets, since the heating and cooling are responsible for establishing a temperature gradient in the chamber.

[0042] Preferably, a combination of a sufficiently small separation between the substrate surface and the plurality of precursor entry points and the cooling of the precursor entry points, coupled with the heating of the substrate to with a decomposition range of the precursor, generates a sufficiently steep thermal gradient extending from the substrate surface to the precursor entry points to allow graphene formation on the substrate surface. As disclosed in WO 2017 / 029470, very steep thermal gradients may be used to facilitate the formation of high-quality and uniform two-dimensional material layers directly on non-metallic substrates, preferably across the entire surface of the substrate. The substrate may have a diameter of at least 5 cm (2 inches), at least 15 cm (6 inches) or at least 30 cm (12 inches). Particularly suitable apparatus for the method described herein include an Aixtron® Close-Coupled Showerhead® reactor and a Veeco® TurboDisk reactor.

[0043] Consequently, in a particularly preferred embodiment wherein the method of the present invention involves using a method as disclosed in WO 2017 / 029470, forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a close-coupled reaction chamber, the close- coupled reaction chamber having a plurality of cooled inlets arranged so that, in use, the inlets are distributed across the growth surface of the substrate and have constant separation from the substrate; cooling the inlets to less than 100°C; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the close-coupled reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor, to provide a thermal gradient between the growth surface and inlets that is sufficiently steep to allow the formation of graphene from carbon released from the decomposed precursor; wherein the constant separation is less than 100 mm, preferably less than 25 mm, even more preferably less than 10 mm.

[0044] In another particularly preferred embodiment wherein the method involves using a method as disclosed in WO 2019 / 138231 , forming the graphene layer structure by CVD comprises: providing the substrate on a heated susceptor in a reaction chamber, the reaction chamber having a plurality of inlets arranged so that, in use, the inlets are distributed across the growth surface and have constant separation from the substrate; rotating the heated susceptor at a rotation rate of at least 600 rpm, preferably up to 3000 rpm; introducing a carbon-containing precursor in a gas phase and / or suspended in a gas through the inlets and into the reaction chamber; and heating the susceptor to achieve a growth surface temperature of at least 50°C in excess of a decomposition temperature of the precursor; wherein the constant separation is at least 12 cm, preferably up to 20 cm.

[0045] The most common carbon-containing precursor in the art for graphene growth is methane (CH4). The inventors have found that it is preferable that the carbon-containing precursor used to form graphene is an organic compound, that is, a chemical compound, or molecule, that contains a carbon-hydrogen covalent bond, which comprises two or more carbon atoms. The carbon-containing precursor is preferably a C3-C10 organic compound consisting of carbon and hydrogen and, optionally, oxygen, nitrogen, fluorine, chlorine and / or bromine, even more preferably a C6-C9 organic compound. In a preferred embodiment, the precursor does not comprise a heteroatom, such that the precursor consists of carbon and hydrogen. In other words, preferably the carbon-containing precursor is a hydrocarbon, preferably an alkane. It is also preferable that the organic compound comprise at least two methyl groups (-CH3). Particularly preferred organic compounds for use as carbon-containing precursors, and methods of forming graphene therefrom by CVD, are described in GB 2604377.

[0046] Suitable transition metal-containing and chalcogen-containing precursors for use in the formation of a TMD layer structure are well-known. Examples of transition metal precursors (which may be organometallic precursors) include zero valent metal precursors such as metal hexacarbonyls (e.g. Mo(CO)e and W(CO)e) and metallocene complexes. Examples of chalcogen precursors include dialkyls, such as dimethyl, diethyl, di-isopropyl and di-tertbutyl - sulfide, selenide and telluride. Such precursors are sufficiently volatile to be provided in a gas phase or suspended in a gas phase for use in an MOCVD reactor. TMDs may also be formed by CVD using transition metal oxides and pure chalcogen, though these methods are less preferred when forming a heterostructure on graphene due to the higher temperatures required which risk damaging the graphene during growth.

[0047] Two-dimensional materials produced directly on the substrate are generally of much higher quality with fewer defects. As a result, there is significantly less interaction with the substrate, this essentially being only weak van der Waals interactions, especially for graphene on the substrate surface. Consequently, the inventors have found that there is a significant risk of delamination for two- dimensional materials produced by such a method, and the additional processing steps of the present invention which help to mitigate the delamination risk provide a synergistic benefit when combined with directly CVD-grown two-dimensional materials.

[0048] At least when formed directly on the substrate, it is preferred that the non-metallic surface upon which the two-dimensional material layer structure is provided is silicon (Si), silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiC>2), sapphire (AI2O3), aluminium gallium oxide (AGO), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), yttria-stabilised hafnia (YSH), yttria-stabilised zirconia (YSZ), magnesium aluminate (MgAhO^, yttrium orthoaluminate (YAIO3), strontium titanate (SrTiOs), cerium oxide (Ce2O3), scandium oxide (SC2O3), scandium aluminium oxide, scandium gallium oxide, erbium oxide (Er2Os), magnesium difluoride (MgF2), calcium difluoride (CaF2), strontium difluoride (SrF2), barium difluoride (BaF2), scandium trifluoride (ScFs), germanium (Ge), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN) and / or a lll / V semiconductor such as aluminium nitride (AIN) and gallium nitride (GaN). Preferably, the non-metallic growth surface is silicon nitride, silicon dioxide, sapphire, aluminium nitride, YSZ, scandium oxide, scandium aluminium oxide, scandium gallium oxide, germanium, h-BN and / or calcium difluoride. More preferably, the non-metallic surface is sapphire or a rare-earth oxide (e.g. yttria-stabilised zirconia, scandium oxide, scandium aluminium oxide or scandium gallium oxide). In some embodiments, the growth surface may have a specific crystallographic orientation, with <111> cubic (e.g. for rare earth oxides such as YSZ or SC2O3, or CaF2) or <1-102> hexagonal (i.e. r-plane, such as for sapphire) being preferred.

[0049] In some embodiments, the substrate may consist of one such material. In some preferred embodiments, the substrate comprises, or consists of, a first layer which provides the non-metallic surface and a “substrate support” layer, sapphire being a preferred example (such embodiments being particularly suitable for insulative substrates, i.e. typically the oxides, nitrides and fluorides described). In other preferred embodiments, the substrate support layer comprises silicon. A silicon support layer, includes a “pure” silicon wafer (essentially consisting of silicon, doped or undoped) or what may be referred to as a CMOS wafer which includes additional associated circuitry. First layers comprising or consisting of rare earth oxides are particularly preferably provided on a silicon substrate support. Scandium oxide, for example, is particularly preferred. A substrate may also comprise one or more layers, regions or channels (for example, embedded waveguide materials such as silicon nitride suitable for electro-optic modulators and photodetectors).

[0050] The thickness of the substrate support layer is generally much thicker than the thickness of the first layer thereon. Typically, the substrate support layer has a thickness of 250 pm to 1 .5 mm, for example from 400 pm to 1 mm. On the other hand, the thickness of the first layer of such a substrate is substantially thinner and may be formed on the substrate support by epitaxy such as molecular beam epitaxy (MBE) or high temperature sputtering. Preferably, the thickness is at least 2 nm, preferably at least 5 nm and / or less than 500 nm, preferably less than 100 nm. Suitable ranges for the thickness of the first layer are preferably 5 nm to 100 nm, preferably 10 to 50 nm. In some embodiments, very thin layers are preferred and the thickness of the layer may preferably be from 2 nm to 10 nm.

[0051] The following description focuses on the first and second aspects, though it will be appreciated that the third and fourth aspects share numerous common features such that the descriptions of these features may apply equally to the third and fourth aspects.

[0052] The laminate structure comprises an inorganic dielectric layer on and across the two-dimensional material layer structure. As described in greater detail herein, the dielectric layer and the two- dimensional material layer structure of the provided laminate may be (co-) patterned before wetetching and metal deposition (see Figures 1 and 2, for example), though in some preferred embodiments of the first aspect, both layers of the laminate are provided across the underlying substrate without having been patterned (e.g. an as-grown laminate) before wet-etching and metal deposition (see Figure 3, for example).

[0053] The dielectric layer and / or passivation layer (where present) may be formed by any conventional means, for example physical vapour deposition techniques such as molecular beam epitaxy (MBE), sputtering, thermal evaporation, e-beam evaporation, or ALD. Any typical dielectric material may be used for these layers, including those described herein for the non-metallic surface of the substrate, in particular metal oxides in order to allow for an efficient wet-etch as described herein. For example, suitable dielectric metal oxides include aluminium oxide, hafnium oxide, silicon oxide, magnesium oxide, magnesium aluminate, zinc oxide, gallium oxide, titanium oxide, strontium titanate, lanthanum aluminate, lithium niobate, yttrium oxide, yttria-stabilise zirconia (YSZ), zirconium oxide and yttrium aluminium garnet (YAG). Aluminium oxide and hafnium oxide are particularly preferred and common “high-k” dielectric metal oxides which are preferred to a least be included in the dielectric layer.

[0054] In preferred embodiments, the dielectric layer has a multi-layer structure, and comprises a sub-layer of a transition metal oxide selected from the group consisting of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide, and combinations thereof, preferably molybdenum oxide, and a sub-layer of dielectric material such as those listed above (e.g. aluminium oxide and / or hafnium oxide) which may be a thin layer (e.g. from 2 nm to 20 nm). Such transition metal oxides may be selected for their high work function, their proximity to the two-dimensional material layer structure having a doping effect which can be used to control the final charge carrier density, and therefore the electronic properties, of a device.

[0055] The passivation layer is not intended to be used to influence the electronic properties but provide protective encapsulation by covering at least the edges of the two-dimensional material layer structure once patterned. This layer may preferably consist of a single material such as aluminium oxide and / or hafnium oxide.

[0056] The thickness of a first sub-layer of the dielectric layer when formed from the transition metal oxide directly on the two-dimensional material layer structure is preferably less than 10 nm (e.g. less than 5 nm or less than 3 nm, for example from 0.1 nm to 5 nm). The desired nominal thickness can be achieved through use of a Quartz Crystal Microbalance (QCM) during formation, particularly of molybdenum oxide, which provides the skilled person with an in-situ measurement of the amount of material deposited when carrying out the method. The thickness of the layer is therefore a mean average thickness of the layer. The thickness may then equally be readily determined by those skilled in the art using conventional techniques, for example AFM. The inventors have found that a transition metal oxide layer 5 nm to 10 nm thick may be preferred. As described in WO 2024 / 153479, the use of a transition metal oxide such as molybdenum oxide, which has increased solubility relative to other metal oxides (e.g. aluminium and / or hafnium oxide), can facilitate the wet-etch. This therefore reduces the time required for the etching process and the risk of damaging the two-dimensional material layer structure. Similarly, milder etchants may be used. Accordingly, a thicker transition metal oxide layer can be preferred where deposited as the first sub-layer, though this is limited by the need to control the extent of doping, particularly for sensors.

[0057] Alternatively, a first sub-layer may provide a “barrier layer” upon which a second sub-layer formed from the transition metal oxide is formed physically separating the transition metal oxide from the two- dimensional material layer structure. The barrier layer preferably has a thickness of at least 3 nm in order to ensure that a fully coalesced and conformal layer is provided for this reason. In such embodiments, it is preferred that the barrier layer is thin, i.e. up to 15 nm, or even preferably up to 10 nm (such as from 5 nm to 10 nm). The presence of a barrier layer (e.g. aluminium oxide or hafnium oxide) permits a thicker transition metal oxide layer to be deposited, such as greater than 5 nm, whilst having an equivalent doping effect on the two-dimensional material layer structure (e.g. from 5 nm to 40 nm, preferably from 10 nm to 30 nm). This advantageously allows the transition metal oxide layer to be deposited with greater process control. Where the barrier layer is too thick, the field effect from the doping layer is diminished. The barrier also aids with consistent doping across the whole area of the two-dimensional material layer structure (which is in turn essential for the mass manufacture of devices with consistent properties from device to device). The ratio of the barrier thickness to transition metal oxide may be from 1 :1 to 1 :10, preferably from 1 :3 to 1 :5.

[0058] The total thickness of the dielectric layer, as measured from an upper surface thereof to the two- dimensional material layer structure, is less than 80 nm, preferably from 10 to 65 nm.

[0059] The method further comprises a step (ii) of depositing a first resist on and across the inorganic dielectric layer and patterning the first resist to expose a plurality of portions of the dielectric layer and a step (iii) of wet-etching the plurality of portions of the dielectric layerto expose a corresponding plurality of surface portions of the two-dimensional material layer structure and form a plurality of wells in the dielectric layer.

[0060] Such steps can be performed using standard photolithography techniques in the art. For example, a first resist is coated on and across the dielectric layer. A photoresist (known simply as a resist) is a light-sensitive material. For example, PMMA (polymethylmethacrylate) is a known industry standard whereby the allyl monomer is spin coated across the surface and polymerised is desired portions by exposure to light sufficient to initiate the polymerisation (typically UV light). The unpolymerised material is then removed, such as by washing with a solvent. A negative photoresist is particularly preferred as described herein. These steps provide at least one patterned region of resist and exposes the remaining areas to provide at least one region which does not have resist thereon. Protected therefore serves to refer to the regions upon which the resist is present and allows the subsequent etching elsewhere, and it will be appreciated that the resist is resistant to etching thereby protecting the underlying layers. Unprotected regions have no resist on the surface of the dielectric layer.

[0061] The method comprises forming an array of unprotected regions, each corresponding to region in which metal plugs are subsequently to be formed (which may be before patterning of the two- dimensional material and device shaping). Where an array of unprotected regions are patterned on the laminate layer structure, this typically affords a single continuous protected region separating the various unprotected regions.

[0062] After having patterned the first resist to provide the protected and unprotected regions, wet-etching removes the dielectric material in the unprotected regions and exposes the corresponding portions of the surface of the underlying two-dimensional material layer structure, thereby creating wells (or holes) in the dielectric layer. Any conventional wet etchant may be used, such as an aqueous acid solution (e.g. comprising phosphoric acid or hydrofluoric acid though many variations and buffered solutions are known). Etching may be performed at an increased temperature, such as to from 30°C to 80°C. By one example, 100% phosphoric acid may be used at a temperature of about 50°C.

[0063] In a preferred embodiment for device manufacture, each well has a cross-sectional area co-planar with the substrate of less than 2,500 pm2, and each well and has a maximum width of less than 50 pm, and more preferably an area of less than 900 pm2and a maximum width of less than 30 pm. The inventors have found that the dimensions of the well must be controlled so to mitigate the risk of delamination when etching an inorganic dielectric layer, which is more problematic to remove from the surface of graphene without concomitant delamination of the underlying two-dimensional material than other materials (e.g. organic polymers). Otherwise, without wishing to be bound by theory, it is believed that with wells that are too large, there is a greater chance of exposing a defect site in the two-dimensional material which is believed to be more likely to be damaged under the etching conditions required for removing inorganic dielectric layers. This can then lead to delamination of essentially the entire two-dimensional material within the well. Similarly, as described above, the inventors have found that the thickness of the dielectric layer (equivalent to the depth of the well) should be less than 80 nm. At greater thicknesses and larger well areas, longer etch times can be necessary to ensure that all of the exposed inorganic dielectric layer has been removed to expose the entire surface of the underlying two-dimensional material (due to natural non-uniformities in etch rate in different portions of the well). As such, it is believed that this risks delamination by extending the length of time in which the two-dimensional material is exposed to wet etchant. Optimal etch conditions, including for example etch time and temperature, may depend on the shape and dimensions of the well to be formed.

[0064] As used herein, the term “maximum width” refers to a maximum diameter (i.e. a width) of a circle that may fit into the shape of the well. As such, the term provides a parameter which ensures that the size of the well is not too large across two orthogonal directions (i.e. in the plane of the two-dimensional material) so as to unduly expose the two-dimensional material which the inventors have found can lead to delamination. In other words, this ensures that for a maximum width of 50 pm, any point of the exposed two-dimensional material is less than 25 pm from any part of the patterned dielectric layer (equal to the radius of the maximum sized circle). The inventors have found that a first orthogonal axis (i.e. a length) may be larger than 50 pm provided that the total area does not exceed 2,500 pm2(equivalent to 50 pm square) such that a second orthogonal axis must be suitably smaller than 50 pm. As will be appreciated, the shape of the wells need not be particularly limited if they meet these requirements. Preferably the maximum width of each well is at least 5 pm and / or up to 30 pm. Each well may adopt a shape with curved edges (e.g. a circle) or may be any simple polygon with straight edges. Preferably the shape of each well is a quadrilateral, preferably, an isosceles trapezoid, a rectangle or a square. Preferably the cross-sectional area of each well is from 100 to 500 pm2, particularly for each well in a group as described herein.

[0065] In some embodiments, the shape of each well is a comb comprising a plurality of linked teeth, wherein each tooth is preferably an isosceles trapezoid, a rectangle or a square. As will be appreciated, a comb will have a generally rectangular spine with, ideally evenly, spaced teeth. The teeth of the comb may be provided along one or both long edges of the spine. Preferably each tooth is spaced at least 2 pm from any other tooth, preferably at least 5 pm.

[0066] In other preferred embodiments, a plurality of, ideally evenly, spaced wells are provided in separate contact regions of the laminate (i.e. as a group of wells). As described herein, a first metal substantially fills the wells in that the metal coats substantially all of the exposed surface of the two- dimensional material layer structure, and a second metal is deposited thereon to form contact pads. One contact pad may contact a corresponding group of the metal plugs providing a single point of contact to the device. As such, whilst these wells may be formed prior to patterning the underlying two-dimensional material into a device shape, groups of wells may be formed together in predetermined contact regions. Such a group may be viewed as the teeth of a comb without the spine. These groups are typically toward but not at the edge of the patterned two-dimensional material (for example, two short sides of a rectangle for a transistor or electro-optic modulator, or each arm of a cross for a Hall sensor).

[0067] Preferably each well is spaced at least 2 pm from any other well and / or any edge of the two- dimensional material layer structure, preferably at least 5 pm. Wells in a group may have a regular spacing of from 2 pm to 20 pm, such as up to 10 pm. This ensures there is sufficient dielectric material between wells and the edges of the two-dimensional material layer structure to avoid delamination of the two-dimensional material layer structure. A group of wells may have 3 or more wells, for example 5 or more. There is no specific upper limit, though up to 50 is typically sufficient, or even up to 25. Each contact pad is then formed in contact with the group of wells and such an arrangement with a group of wells for a device is particularly advantageous since the inventors have found that, if one of the wells were to fail through delamination, a sufficiently effective contact in the contact region of the device may still be made with the second metal to the other metal plug(s) in the group.

[0068] By way of example, square wells in a group may each have a width and length of from 2 pm to 25 pm, such as from 5 pm to 20 pm, and rectangular wells in a group may each have a width of from 2 pm to 20 pm, such as from 3 to 10 pm, and a length of greater than 50 pm, such as from 100 pm to 300 pm.

[0069] Preferably each well has a substantially constant cross-sectional area co-planar with the substrate. That is, each well preferably has the same shape as the other wells.

[0070] The method further comprises a step (iv) of performing a first metallisation step by depositing a first metal on and across the patterned photoresist and the exposed plurality of surface portions of the two-dimensional material layer structure which forms metal plugs that substantially fill the wells of the dielectric layer. The wet-etching patterning and subsequent first metallisation step uses the same photoresist which is advantageous for a more effective metal lift-off process due to the undercut. By using a negative photoresist, for example, for the wet-etching and patterning step (iii), there is typically a degree of undercut in the photoresist. As will be appreciated, the undercut in the resist can lead to the area of the metal plug being marginally smaller than the area of the well, though this is typically filled by the second metal in the second metallisation step. One key advantage of the method of the first aspect is that the same photoresist is used for the wet-etching and first metallisation steps, since this reduces any possible exposure of the underlying two-dimensional material to solvents or further photoresist before the first metal is deposited on the surface ensuring a good ohmic contact can be achieved. Avoiding exposure to resist during deposition and curing is especially important. This is particularly relevant and noticeable for two-dimensional materials directly grown on the substrate which have therefore avoided the more significant contamination which occurs during transfer processes. As such, the method comprises removing the patterned first resist by lift-off to form the metal plugs (i.e. by leaving behind the first metal which substantially fills the wells and removing all other metal which was deposited on the resist).

[0071] The method further comprises a step (v) of performing a second metallisation step by depositing a second metal and forming a plurality of metal contact pads, each contact pad in contact with one or more of the metal plugs. Each metal plug therefore extends from a surface portion of the two- dimensional material layer structure to only one of the plurality of metal contact pads. Such a step may again be performed using photolithography techniques, with a second photoresist being used to provide the pattern for the contact pad after washing away (stripping) the first photoresist. The contact pad will be provided on the dielectric layer and / or the passivation layer (when present) and may preferably extend onto the adjacent substrate forming tracks (i.e. metal wiring on the surface of the substrate). Accordingly, it is preferred that the laminate is patterned to provide device shapes before step (v) exposing the adjacent substrate between each device portion. It is advantageous to be able to probe and / or wire bond the contact pad in an area without an underlying portion of the two- dimensional material layer structure (i.e. on the substrate) to avoid damage to the sensitive layers of the device.

[0072] As will be appreciated, by appropriate patterning of the first resist, where the first metallisation step is performed after co-patterning, the first metal may be used to form tracks on the exposed substrate (or passivation layer where present). The contact pad may be deposited to connect the metal plug(s) with the preformed track(s).

[0073] A device may then be packaged by conventional steps such as dicing the substrate, die bonding, and wire bonding to the tracks, followed by encapsulation.

[0074] Typically, the electrical contacts are formed of metal, such as chromium, titanium, aluminium, nickel and / or gold and may be formed by conventional techniques in the art, including physical vapour deposition techniques such as e-beam deposition. In a preferred embodiment, the first metal is a first stack of chromium and gold, wherein the chromium of the first stack is deposited before the gold of the first stack, and the second metal is a second stack of titanium and gold, wherein the titanium of the second stack is deposited before the gold of the second stack. The inventors have found that this combination is particularly suitable for providing both a good ohmic contact to the surface of a two- dimensional material such as graphene, and for providing a mechanically robust contact pad which adheres well to the adjacent substrate such as sapphire, which is beneficial for subsequent packaging steps like wire bonding.

[0075] Generally, for the production of the electronic device, the method of the first aspect further comprises co-patterning the two-dimensional material layer structure and the dielectric layer. Preferably, the method does not comprise patterning the two-dimensional material layer structure before steps (ii) and (iii) of depositing and patterning a resist and then wet-etching a plurality of portions of the dielectric layer. This is generally preferred as forming the metal plugs beforehand ensures that no edges of the two-dimensional material layer structure can be exposed to the photolithography chemicals in the plug formation. Where in some embodiments, the two-dimensional material layer structure is patterned before step (ii), this is generally co-patterned with the dielectric layer. That is, the dielectric layer is co-patterned in the sense that the dielectric layer has the same shape as the underlying two-dimensional material layer structure and thus share a continuous outer edge defining said shape whereby their edges align above one another. This may be referred to as a co-patterned stack. In other words, step (i) of providing a laminate structure may comprise forming a layer of dielectric material on and across the two-dimensional material layer structure and co-patterning the layer of dielectric material and two-dimensional material layer structure thereby exposing a first portion of the adjacent growth surface of the substrate. Co-patterning may use photolithography, and the dielectric layer serves to protect the two-dimensional material from surface contamination during patterning. The method may comprise forming a passivation layer on and across the co-patterned stack and the adjacent substrate thereby encapsulating the edges of the stack, before formation of the contacts (i.e. steps (ii) to (v)). This again advantageously minimises any exposure of the two- dimensional material to photolithography chemicals. In such embodiments, a total thickness of the dielectric layer and the passivation layer is less than 80 nm, and it will be appreciated that layers described herein as being formed on the dielectric layer will instead be formed on the passivation layer.

[0076] Any conventional etching process may be used for the co-patterning. Preferably, the unprotected region is etched to remove the unprotected region of the laminate (equivalent to that already described in respect of the well formation). Preferably, the unprotected regions of the laminate are etched and removed by reactive ion etching (REI) which is a known type of dry-etching. Such etching may be sufficient to remove the underlying two-dimensional material layer structure in the unprotected regions. It may also be preferred to plasma etch to remove any remaining residue of two-dimensional material (such as carbon fragments of graphene). Preferably, the plasma etching is oxygen plasma etching.

[0077] Whether before or after well formation, it may be that only one unprotected region is formed during the patterning step since the step of etching as described herein then results in the formation of a continuous outer edge surface of the underlying layers for each electronic device (i.e. the formation of an array of “filled” “2D shapes” each with an outer edge such as a rectangle). However, in some embodiments, each co-patterned stack may have an uncovered portion therein providing an inner and outer edge to the underlying layers after etching (i.e. the formation of a ring, preferably a circular ring, i.e. annular). Suitable patterns and geometries for devices are known to those skilled in the art. Common shapes for a Hall sensor include crosses with four contact regions provided toward the end of each arm of the cross, though other geometries include rectangles (including squares), circles, clover leaves, and hall-bars (which may have more than four arms). These may have C2 or C4 rotational symmetry (whereby the rotational axis is that orthogonal to the surface). The electronic device may be a diode, a transistor, a sensor or an optoelectronic, with preferred examples including hall sensors and field effect transistors. However, many other devices will benefit from the structure of the present device (e.g. RF devices and inductors) where contact resistance is a problem.

[0078] Preferably the two-dimensional material layer structure and the dielectric layer are first co-patterned between the first and second metallisation steps (iv) and (v). Similarly, in preferred embodiments the method further comprises forming a passivation layer between the first and second metallisation steps (iv) and (v) to protect the two-dimensional material layer structure, and etching portions of the passivation layer to expose each metal plug. By forming a passivation layer at this stage, the passivation layer may fill any small gaps between the metal plugs and their wells. Advantageously, depositing a passivation layer at this stage on and across the patterned stack and metal plugs, and the adjacent exposed substrate encapsulates the edges of the stack, which means that the edges are never exposed to photoresist for patterning.

[0079] In order to avoid excessive material and processing time, it is preferred that only one passivation layer is deposited during manufacture of the contacts, preferably directly after having co-patterned the two- dimensional material layer structure and dielectric layer, though multiple layers may be formed as described. Where multiple passivation layers are formed in different steps, each layer may be referred to as a first or second passivation layer, and so on. In either case, the passivation layer needs to be etched, either with the dielectric layer to form the well(s) and / or in regions over the metal plugs to expose the plugs for contacting with the second metal of the contact pad. The passivation layer may also be etched from regions of the substrate to allow the metal to be deposited on the substrate to provide tracks. The passivation layer is however still retained adjacent the patterned stack to protect the edges.

[0080] In some embodiments, the method may comprise forming a passivation layer after the second metallisation step (v) to protect the two-dimensional material layer structure, and etching portions of the passivation layer to expose portions of each contact pad. Where a passivation layer has already been formed during the process of contact formation, any subsequent passivation layer will not directly contact and protect the edges of the two-dimensional material layer structure, but may otherwise serve to coat and encapsulate the layers providing a further barrier to air and moisture to protect the device from atmospheric contamination over device lifetime (and any further downstream processing for device formation). The further passivation layer may be etched to expose a region of the contact pad for probing and / or wire bonding. Such a passivation layer deposited after formation of the contact pad may alternatively be referred to as a coating layer which typically encapsulates the entire device.

[0081] The following description focuses on the third and fourth aspects, though it will be appreciated that the third and fourth aspects share numerous common features such that the descriptions of these features may apply equally to the first and second aspects.

[0082] Key differences between the method of the third aspect when compared to the first aspect include the third aspect requiring formation of a plurality of a group of wells, each well having the desirably low area and maximum width which the inventors have found mitigates damage and delamination to the two-dimensional material layer structure. Additionally, the contact pad is in electrical communication with the two-dimensional material layer structure though a group of metal vias, thus mitigating the risk that any one via fails to form an effective contact due to any damage or delamination that may have occurred. Such a combination of features provides a simpler method which still improves the reliability of device manufacture with a robust final device.

[0083] On the other hand, the method of the first aspect requires a two-step metallisation process since this was found in some respects to reduce exposure of the two-dimensional material layer structure to contamination during processing. The method and product of the third and fourth aspects may, and preferably, includes only a single metallisation step to form both the metal plugs and the contact pad, and thus the method forms a contact pad which may be described as one comprising metal vias. It will therefore be appreciated that the final structure of the electrical contact may be essentially the same as that formed in embodiments of the first and second aspects.

[0084] In accordance with embodiments of the first aspect, the method of the third aspect generally comprises co-patterning the two-dimensional material layer structure and the dielectric layer to form one or more co-patterned stacks. The co-patterning therefore exposes the substrate surface adjacent the stacks. Similarly, the method may preferably comprise forming a passivation layer on and across the co-patterned stack and the adjacent substrate thereby encapsulating the edges of the stack, before formation of the contacts (i.e. step (iii), whether one or more metallisation steps are used). Where multiple metallisation steps are used, co-patterning and passivation layer deposition may take place between these steps in accordance the first aspect.

[0085] As described herein, each co-patterned stack may preferably be patterned to have a hall cross shape comprising at least four arms. Each arm of a hall cross then provides a region for forming a contact pad. As will be appreciated, each co-patterned stack may be patterned to any other shape that is desired for the intended final device application.

[0086] Preferably, the step of co-patterning is performed between steps (i) and (ii) of providing the laminate structure and wet-etching to form wells, though in other embodiments may be performed during step (iii) between the first and any further metallisation step. Preferably, the method further comprises a step of forming a passivation layer after the step of co-patterning and before step (ii) to protect the edges of the two-dimensional material layer structure, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm. As will be appreciated, step (ii) then comprises wetetching a group of portions of the dielectric layer and the passivation layer to expose a corresponding group of surface portions of the two-dimensional material layer structure and form a corresponding group of wells in the dielectric layer and passivation layer.

[0087] Consequently, one preferred embodiment comprises:

[0088] (I) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure; (II) co-patterning the two-dimensional material layer structure and the dielectric layer to form one or more co-patterned stacks, and thereby exposing the substrate adjacent thereto;

[0089] (III) forming a passivation layer on and across the one or more co-patterned stacks and the adjacent substrate thereby encapsulating the edges of the stack, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm;

[0090] (IV) depositing a first resist on and across the passivation layer and patterning the first resist to expose, within each of a plurality of regions of each co-patterned stack, a group of portions of the passivation layer;

[0091] (V) wet-etching each group of portions of the passivation layer and corresponding underlying portions of the dielectric layer to expose a corresponding group of surface portions of the two- dimensional material layer structure and form a corresponding group of wells in the passivation and dielectric layers, wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm;

[0092] (VI) performing one or more metallisation steps by depositing one or more metals and forming a plurality of contact pads, wherein each contact pad is in electrical communication with the two- dimensional material layer structure through a group of metal vias filling one of the corresponding group of wells.

[0093] The method of the third aspect comprises wet-etching, within each of a plurality of regions of the laminate structure, a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two-dimensional material layer structure. The wet-etching to expose the two- dimensional material layer structure forms a corresponding group of wells in the dielectric layer. That is, the method involves forming multiple groups of wells for each co-patterned stack (i.e. each device), wherein each group is provided in a region suitable for providing a contact to the two-dimensional material layer structure in an electronic device. As described herein, this may be performed before copatterning to provide the shape of the device, but can also be performed before co-patterning. Generally, each device comprises at least two contacts, though devices may have more (e.g. a hall sensor with a hall cross shape may have four contact regions).

[0094] Each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm. As described further herein, the inventors have found such dimensions to be particularly suitable for mitigating the risk of delamination and / or damage to the underlying two-dimensional material layer structure. Preferably, each group of wells comprises at least 3 wells, preferably at least 5 wells, and / or up to 50 wells, preferably up to 25 wells. As described herein, each well is preferably spaced at least 2 pm from any other well and / or any edge of the two- dimensional material layer structure, preferably at least 5 pm.

[0095] Preferably, the maximum width of each well is from 5 to 25 pm. In particular, the maximum width being at least 5 pm, more preferably at least 10 pm, is preferred since with dimensions which are too small, the inventors have found that insufficient development can occur, particularly where there is a large aspect ratio between the “length” and “width”. As such, it can also be preferred that the aspect ratio of the length and width of each well is less than 10:1 (that is, with the length defined as the longer side, an aspect ratio of 1 :1 is the minimum providing equal length and width), more preferably less than 5:1 . It is similarly preferred that the cross-sectional area of each well is from 100 to 500 pm2.

[0096] The inventors have also found that a maximum width of at least 5 pm is preferred since below 5 pm, the inventors have observed that there is an increased risk in cracking of the dielectric layer, with the cracks typically originating from the relatively sharp edges of the wells. Cracking of the dielectric layer can unduly compromise the integrity of the device and therefore device performance and lifetime which is desirable to avoid.

[0097] Typically, it may be preferred that each group of wells has a linear arrangement. By a linear arrangement, it is meant that the group of wells are arranged symmetrically so that the group has C2 rotational symmetry (whereby the rotational axis is that orthogonal to the surface) and / or a mirror plane of symmetry (whereby the mirror plane is one orthogonal to the surface). For example, a group of wells may be provided in one or more rows of wells. Each group of wells, and therefore each region of the co-patterned stack, is typically provided proximal to an edge thereof (such that the “channel” of two-dimensional material therebetween provides for the device function).

[0098] The method further comprises performing one or more metallisation steps by depositing one or more metals. That is, each metallisation step may comprise depositing multiple metals (such as titanium followed by gold) with each step distinguished by patterning the metal layer deposited by the preceding step. The method ultimately comprises forming a plurality of contact pads by patterning the metal layer(s) deposited by the metallisation step(s). A key feature of the third and fourth aspects is that each contact pad is in electrical communication with the two-dimensional material layer structure through a group of metal vias filling one of the corresponding group of wells. That is, each contact pad in each region of the co-patterned stack comprises a group of metal vias.

[0099] Co-patterning between steps (i) and (ii) is essential for contact pad formation by a one-step metallisation process where the contact pad extends onto the adjacent substrate (or passivation layer) which is generally preferred. Step (iii) therefore preferably comprises performing a metallisation step by depositing one or more metals to form a metal layer on and across the dielectric layer of the co-patterned stacks and each group of exposed surface portions of the two-dimensional material layer structure, and the adjacent substrate and / or passivation layer. The metal layer may then be patterned to form the contact pads, for example, by dry-etching. In some preferred embodiments, step (iii) comprises a single metallisation step which comprises depositing a layer of titanium or chromium, and then a layer of gold. Where a one-step metallisation is desired for the manufacturing simplicity, co-patterning before step (ii) is essential because use of a resist to define the desired shape of the contact pad on the copatterned stack, without prior formation of the metal vias, would contaminate the exposed surface of the two-dimensional material layer structure. Advantageously, it is believed that the smaller well size, which ensures delamination is not an issue when etching, assists in reducing the risk of damage or contamination during resist stripping following co-patterning.

[0100] In some embodiments, the method may comprise deposition of multiple passivation layers at each stage as described herein. In such embodiments, the first passivation layer deposited before step (iii) will directly protect the edges of the two-dimensional material layer structure. The second passivation layer deposited after step (v) (which may be regarded as a coating or encapsulation layer) is deposited on and across the contact pads and the first passivation layer. The second passivation layer may then be etched to expose portions of each contact pad. The additional coating also generally helps to ensure the two-dimensional material layer structure is protected from atmospheric contamination (e.g. from oxygen and water) which is desirable for device stability and improved lifetime, particularly for sensors.

[0101] Figures

[0102] The present invention will now be described further with reference to the following exemplary non-limiting Figures, in which:

[0103] Figure 1 is a plan view illustrating a method for the provision of metal contacts as described herein.

[0104] Figure 2 is a plan view illustrating an alternative method for the provision of metal contacts starting with an intermediate of the method illustrated in Figure 1.

[0105] Figure 3 is a plan view illustrating an alternative method for the provision of metal contacts which provides the intermediate as used as a starting point in Figure 2.

[0106] Figure 4 is a cross-sectional view of an electronic device as described herein, such as that obtained by the method illustrated in Figure 2.

[0107] Figure 5A is a plan view schematic design of a group of wells for an electronic device.

[0108] Figure 5B is a plan view schematic design of a plurality of the groups of wells shown in Figure 5A arranged for an electronic device. Figure 5C is a plan view schematic design of an electronic device comprising the arrangement of groups of wells shown in Figure 5B.

[0109] Figure 6A is a plan view schematic design of a well having a comb shape.

[0110] Figure 6B is a plan view schematic design of a plurality of the wells shown in Figure 6A arranged for an electronic device.

[0111] Figure 7 illustrates the maximum width of a well.

[0112] Figure 8 is a plan view illustrating a method for the provision of metal contacts as described herein.

[0113] Figure 9 is a plan view illustrating the method shown in Figure 8, but which further comprises forming a passivation layer.

[0114] Figure 10 is a cross-sectional view of an electronic device as described herein, such as that obtained by the method illustrated in Figure 9.

[0115] Figure 11 is an optical image of a well formed by a comparative method.

[0116] Figure 12 is an optical image of multiple groups of wells having various cross-sectional areas I maximum widths.

[0117] Figure 13 is an optical image of a laminate structure comprising a plurality of groups of wells in regions intended for contacts for devices.

[0118] Figure 1 illustrates a method for the provision of metal contacts on a two-dimensional material layer structure. There is provided a laminate structure comprising a substrate 100 having a two-dimensional material layer structure 110 thereon and across (e.g. a graphene monolayer). An inorganic dielectric layer 120 is provided on and across the two-dimensional material layer structure 110, which may have a thickness of about 10 nm. As described herein, multi-layer dielectric layers are preferred and may be used to influence the charge carrier concentration of the two-dimensional material 110. Preferably, the two-dimensional material 110 was grown directly on the substrate 100 by CVD.

[0119] In a first step 200 of the method, the stack of the two-dimensional material layer structure 110 and the inorganic dielectric layer 120 is patterned by photolithography to provide a co-patterned stack 105 on the substrate 100, preferably wherein the etching of the layers is performed with reactive ion etching and / or plasma etching. The patterning therefore exposes the adjacent growth surface of the substrate 100. The co-patterned stack has a hall cross shape suitable for a hall sensor, comprising four arms having C4 rotational symmetry. As will be appreciated, an array of such co-patterned stacks may be prepared simultaneously on a common substrate for the “wafer scale” mass manufacture of electronic devices.

[0120] In a second step 205, wells 115 in the dielectric layer 120 are formed by photolithography using a (first) photoresist 140 and a wet-etching process to expose a surface of the two-dimensional material layer structure 110 (it will be appreciated that other photoresists may have been used in the preceding patterning step). The wells 115 are designed to have a maximum width of less than 50 pm and a cross-sectional area of less than 2,500 pm2to mitigate the risk of delamination of the two-dimensional material layer structure 110. As shown in Figure 1 , four wells 115 are provided, each aligned in an area toward the end of each of the arms of the underlying co-patterned stack 105. Each well of the present embodiment has a substantially constant cross-sectional area in the same isosceles trapezoidal shape. The first photoresist 140 is retained and in a third step 210, a first metal is deposited on and across the wafer, i.e. on and across the first photoresist 140 and substantially filling each well 115 in the form of metal plugs 125. A lift-off step removes the underlying first photoresist 140 and any of the first metal deposited thereon leaving the metal plugs 125.

[0121] In a fourth step 215, a second metal is deposited to form contact pads 130, each contact pad 130 being in contact with one of the underlying metal plugs 125. Such a step may again use photolithography and a resist and lift-off process to provide the desired pattern / d esign of the contact pads 130. Each contact pad extends on the adjacent surface of the substrate 100 which may then form tracks for circuitry (not shown).

[0122] In an alternative embodiment (not shown), before the second step 205, a passivation layer may be formed on and across the co-patterned stack 105 and the adjacent exposed substrate 100. The second, third and fourth steps (205, 210, 215) may then follow to form wells in the combination of the dielectric layer 120 and passivation layer, then form plugs and contact pads. The final contact pads 130 may then extend onto the adjacent surface of the passivation layer which is on the substrate 100 to form tracks for circuitry.

[0123] Figure 2 is a plan view illustrating an alternative method for the provision of metal contacts on a two- dimensional material layer structure, the method starting with the intermediate produced following the first metallisation and lift-off step 210 as shown in Figure 1 .

[0124] In a first step 220, a passivation layer 135 is deposited on and across the wafer (illustrated in Figure 2 as partially transparent to show the underlying layers with the reference numerals also identifying such layers). In a second step 225, the passivation layer 135 is patterned by photolithography to expose each of the metal plugs 125, as well as portions of the substrate 100 proximate to the end of each arm of the co-patterned stack 105. The passivation layer 135 serves to encapsulate the edges of the copatterned stack 105 and protects the edges from contamination with photoresist during step 215 of depositing the second metal to form contact pads 130 (which may otherwise be equivalent to the final step in Figure 1). A cross-section across the line A-A of the final device is shown in Figure 4.

[0125] Figure 3 is a plan view illustrating an alternative preferred method for the provision of metal contacts, the method in Figure 3 produces the intermediate as used as a starting point in Figure 2 for forming contact pads 130. Alternatively, contact pads may be formed by the method in Figure 1 without the passivation layer 135.

[0126] The method shown in Figure 3 starts with the same laminate structure as illustrated in Figure 1 . However, using photolithography, a first photoresist 140 is patterned on the laminate structure in a first step 300, the photoresist 140 exposing portions of the dielectric layer 120 in the shape of the desired wells 115. In a second step, a wet-etch exposes the underlying two-dimensional material layer structure 110, forming the wells 115 in the dielectric layer 120 (equivalent to step 205 in Figure 1).

[0127] In a third step 310, a first metal 125’ is deposited on and across the first photoresist 140 and substantially filling each well 115. A lift-off step 315 removes the underlying first photoresist 140 and any of the first metal deposited thereon leaving the metal plugs 125 (equivalent to step 210 in Figure 1).

[0128] In a fourth step 320, a second photoresist 145 is patterned onto the wafer in the shape of the intended device, the hall cross as shown in Figure 1 in the present method, with the shape being aligned with the underlying metal plugs 125 arranged so that each metal plug is at least 2 pm from the edge of the device shape. In a fifth step 325, the stack of the two-dimensional material layer structure 110 and the inorganic dielectric layer 120 is etched to provide a co-patterned stack 105 on the substrate 100. By performing the patterning of the stack 105 after the formation of the metal plugs 125, the edges of the stack 105 are not exposed to the photolithography chemicals used for metal plug 125 formation.

[0129] An exemplary method in accordance with Figure 3 is provided in Example 1 below.

[0130] Figure 4 is a cross-sectional view of the device produced by the method shown in Figure 2, across the line A-A. Figure 4 illustrates that the substrate 100 may be formed of a substrate support layer 100b, such as silicon, and an epitaxially grown non-metallic upper layer 100a thereon, such as silicon oxide or scandium oxide, providing a growth surface upon which the two-dimensional material layer structure 110 may be directly formed. The two-dimensional material layer structure 110 is co- patterned with the dielectric layer 120 such that their edges align. Metal plugs 125 fill the wells 115 in the dielectric layer contacting the surface of the two-dimensional material layer structure 110 in each well 115, with each well 115 and associated metal plug 125 being a distance 150 of at least 2 pm from the edge of the stack 105. The passivation layer 135 is provided on and across the dielectric layer 120 and extends onto the adjacent surface of the upper layer 100a encapsulating the edges of the stack 105. The contact pads 130 each contact one metal plug, and further extends on and over the passivation layer on the adjacent surface of the upper layer 100a forming tracks.

[0131] Figure 5A is a plan view schematic design of a group of wells 400 for an electronic device. The schematic is shown on a grid of points spaced 5 pm apart for scale. The group of wells 400 consists of 9 individual square wells 405, each having a width and length of about 20 pm (and therefore each well 405 has an area of about 400 pm2). Each well 405 is also regularly spaced 410 from another well 405 by about 10 pm. Many variations will be apparent to those skilled in the art. Figure 5B is a plan view schematic design of a plurality of the groups of wells 400 shown in Figure 5A arranged for an electronic device, such as a hall sensor with four groups of wells 400 arranged in a position suitable for contacting four arms of a hall cross. Figure 5C is a plan view schematic design of such an exemplary hall sensor comprising the arrangement of groups of wells 400 shown in Figure 5B, together with a design of a co-patterned stack 420 in the form of a hall cross. Contact pads 415 are provided, each contact pad 415 contacting each well 405 in each group of wells 400.

[0132] Figure 6A is a plan view schematic design of a well 505 having a comb shape. The schematic is shown on a grid of points spaced 5 pm apart for scale. The exemplary well 505 comprises 13 teeth 515, connected to one side of a rectangular spine 520. Each tooth 515 has a square shape, with a width and length of about 10 pm, whereby each tooth 515 is spaced apart from another tooth by a distance 510 of about 10 pm. The spine 520 therefore has a total length of about 250 pm, and has a width of about 4 pm. Consequently, the maximum width of well 515 is about 10 pm, the well 515 having an area of about 2,300 pm2. Figure 6B is a plan view schematic design of a plurality of the wells shown in Figure 6A arranged for an electronic device. Similar to Figure 5B, each of the four wells 515 is arranged in a position suitable for contacting the four arms of a hall cross for a hall sensor.

[0133] Figure 7 illustrates the maximum width 610 of an isosceles trapezoidal well 600. The maximum width 610 of the well 600 is equal to the diameter of the maximum sized circle 605 that may fit into the shape of the well 600 (i.e. 50 pm). The use of a circle ensures that at least one dimension is not too large so as to avoid the risk of delamination during wet-etching of the inorganic dielectric layer. In other words, any point on the two-dimensional material layer structure exposed by the well 600 is less than half of the diameter of such a circle (i.e. 25 pm) from the dielectric layer. Figure 8 illustrates a method for the provision of metal contacts on a two-dimensional material layer structure. There is provided a laminate structure comprising a substrate 700 having a two-dimensional material layer structure 710 thereon and across (e.g. a graphene monolayer). An inorganic dielectric layer 720 is provided on and across the two-dimensional material layer structure 710, which may have a thickness of about 10 nm. As described herein, multi-layer dielectric layers are preferred and may be used to influence the charge carrier concentration of the two-dimensional material 710. Preferably, the two-dimensional material 710 was grown directly on the substrate 700 by CVD.

[0134] In a first step 800 of the method, the stack of the two-dimensional material layer structure 710 and the inorganic dielectric layer 720 is patterned by photolithography to provide a co-patterned stack 705 on the substrate 700, preferably wherein the etching of the layers is performed with reactive ion etching and / or plasma etching. The patterning therefore exposes the adjacent growth surface of the substrate 700. The co-patterned stack has a hall cross shape suitable for a hall sensor, comprising four arms having C4 rotational symmetry. As will be appreciated, an array of such co-patterned stacks may be prepared simultaneously on a common substrate for the “wafer scale” mass manufacture of electronic devices.

[0135] In a second step 805, four groups of wells 715 in the dielectric layer 720, each group comprising 5 wells in a region that is proximal to the end of the arms (750a, 750b) of the underlying hall cross at least 2 pm from the edge, are formed by photolithography using a (first) photoresist 740 and a wetetching process to expose a surface of the two-dimensional material layer structure 710 (it will be appreciated that other photoresists may have been used in the preceding patterning step). The group of wells 715 are designed so that each well has a maximum width of less than 30 pm and a cross- sectional area of less than 900 pm2to mitigate the risk of delamination of the two-dimensional material layer structure 710 whilst providing dimensions suitable for multiple contacts to the two- dimensional material layer structure 710 at each arm. Each well of each group in the present embodiment has a substantially constant cross-sectional area in the same square shape, with each group having a linear arrangement. The first photoresist 740 is then stripped in the third step 810 to expose the co-patterned stack 705 before depositing one or more metals in a fourth step 815 on and across the co-patterned stack 705, the exposed portions of the two-dimensional material layer structure 710 filling each group of wells 715, and the exposed substrate 700 adjacent the stack 705, thereby forming a metal layer 725’ (for example, a layer of titanium and gold).

[0136] In a fifth step 820, the metal layer 725’ is patterned by dry-etching to form four contact pads 725 (it will be appreciated that a (further) photoresist may be used to define the pattern for the contact pads). Alternatively, wet-etching, or a combination or wet and dry-etching, may be used to pattern the metal layer 725’. The etching may be selected based on the composition of the metal layer 725’. Every one of the contact pads 725 individually comprise five metal vias which fill the wells of each of the associated group of wells 715 thereby contacting the two-dimensional material layer structure 710. In the event that delamination or damage occurs within any given well of a group 715, such as during the wet-etching step 805, the plurality of wells associated with each group 715 ensures sufficient electrical connectivity providing a robust manufacturing process. As shown in Figure 8, each contact pad further comprises a portion on the adjacent substrate which may be used for probing and / or wire bonding without risking damage to the underlying layers.

[0137] Figure 9 illustrates a modification of the method shown in Figure 8. There is provided a laminate structure comprising a substrate 900, a two-dimensional material layer structure 910 thereon and across, and an inorganic dielectric layer 920 thereon and across. In a first step 1000, the stack is patterned by photolithography to provide a co-patterned stack 905 on the substrate 900, having a hall cross shape with four arms (950a, 950b).

[0138] The method shown in Figure 9 further comprises a second step 1005 of depositing a passivation layer 935 on and across the exposed substrate 900 and co-patterned stack 905 (with the passivation layer 935 illustrated as partially transparent to show the underlying layers with the reference numerals also identifying such layers). The passivation layer 935 therefore coats and protects the edges of the stack 905 during further processing, in particular from resist deposition and curing (patterning) but also from other wet chemistries such as resist strippers and deionised water rinses which follow. The passivation layer 935 also reduces the exposure to the atmosphere during the photo processing.

[0139] The remaining steps are otherwise equivalent to those in Figure 8. In a third step 1010, four groups of wells 915 are formed in the combination of the dielectric layer 920 and passivation layer 935 by wetetching through a patterned resist 940 which is then stripped in a fourth step 1015. Thereafter, in a fifth step 1020, one or metals are deposited on and across the passivation layer 935 and the exposed portions of the two-dimensional material layer structure 910 filling each group of wells 915 to form a metal layer 925’. In a sixth step 1025, the metal layer 925’ is patterned by dry-etching to form four contact pads 925 (and / or by wet-etching depending on the composition of the metal layer 925’). As shown in Figure 9, each contact pad further comprises a portion on the adjacent passivation layer which may be used for probing and / or wire bonding without risking damage to the underlying layers.

[0140] A cross-section across the line B-B of the final device is shown in Figure 10. This cross-section illustrates the group of wells 915 and the metal vias 925a of one contact pad 925 proximate the edge of one arm of the hall cross.

[0141] Similar to the device shown in Figure 4, the substrate 900 may be formed of a substrate support layer 900b, such as silicon, and an epitaxially grown non-metallic upper layer 900a thereon, such as silicon oxide or scandium oxide, providing a growth surface upon which the two-dimensional material layer structure 910 may be directly formed. Alternatively, the substrate may consist of a single material, such as sapphire. The two-dimensional material layer structure 910 is co-patterned with the dielectric layer 920 such that their edges align. In embodiments, the dielectric layer may comprise multiple layers, such as one or more layers of aluminium oxide and molybdenum oxide. The passivation layer 935 is provided on and across the dielectric layer 920 and extends onto the adjacent surface of the upper layer 900a encapsulating the edges of the stack 905. The contact pad 925 comprises 5 metal vias 925a which contact the surface of the two-dimensional material layer structure 910, and the contact pad 925 further extends on the passivation layer to form a track beyond the perimeter of the hall cross.

[0142] Figures 11 to 13 are optical images of wells of various dimensions, having all been formed by the same manufacturing process. Graphene is first deposited on and across a substrate, followed by a layer of molybdenum oxide and a layer of aluminium oxide. A photoresist is then coated thereon across the substrate and patterned to provide the various well shapes. The laminate is then wet- etched in order to etch the metal oxide exposed by the patterned photoresist. Finally, the photoresist is stripped and the laminate rinsed with deionised water. The wells are then inspected by optical imagery.

[0143] Figure 11 is an optical image of a well 1100 formed by a comparative method. The well 1100 has a substantially rectangular shape which has a length of 265 pm and a width of 50 pm (and thus a cross sectional area of 13,205 pm2). Figure 11 demonstrates that not all of the metal oxide is successfully removed (visible as the brightest features scattered across the well 1100) and that therefore the large well size would require excessive development and risk damage to the underlying graphene.

[0144] Figure 12 is an optical image of multiple groups of wells having various cross-sectional areas I maximum widths. The top two and bottom two rows, 7 and 3 well in length respectively, each comprise wells 1105 of approximately 50 pm by 50 pm square (2,500 pm2). The third and fourth rows each comprise 7 wells 1110 of approximately 20 pm by 20 pm square (400 pm2). The fifth and sixth rows each comprise 7 wells 1115 of approximately 10 pm by 10 pm square (100 pm2). Like Figure 11 , Figure 12 demonstrates that wells 1105 of 50 pm by 50 pm risk damage to the graphene, as seen in imperfections 1120 in the image in some of the wells 1105. However, with the reduced dimensions, no damage is observed, and all metal oxide has been successfully etched away.

[0145] Figure 13 is an optical image of a laminate structure comprising a plurality of groups of wells (1125, 1130) in regions intended for contacts for devices. Each group of wells (1125, 1130) comprises three rectangular wells in a linear arrangement. The top and bottom groups of wells 1125 on the left half of the image have dimensions of approximately 86 pm by 4 pm, and having a 3 pm gap therebetween, and the top and bottom groups of wells 1130 on the right half of the image have dimensions of approximately 86 pm by 6 pm, and having a 3 pm gap therebetween. Figure 13 demonstrates that wells 1125 having a maximum width less than 5 pm and a large aspect ratio risks the formation of cracks 1135, which cracks 1135 originate from some of the edges of the 4 pm wide wells 1125 on the left hand side. Without wishing to be bound by theory, it is believed that the annealing steps during photolithography and etch processing resulting in the release of film stress, which results in cracking from the sharper edges of wells.

[0146] Tables 1 to 3 below provide simplified exemplary schemes for embodiments of the methods described herein. Table 1 illustrates example embodiments 1 to 4 which each relate to a two-step metallisation process in which co-patterning of the two-dimensional material layer structure and dielectric layer takes places between the metallisation steps. Example embodiments 3 and 4 comprise forming a passivation layer directly after co-patterning. Figure 3 may represent embodiments 1 to 4.

[0147] Table 2 illustrates example embodiments 5 to 9 which each relate to a two-step metallisation process in which co-patterning of the two-dimensional material layer structure and dielectric layer takes places before the metallisation steps. Example embodiments 8 and 9 comprise forming a passivation layer directly after co-patterning. Figure 1 may represent embodiment 5. Figure 2 may represent embodiment 6.

[0148] Table 3 illustrates example embodiments 10 and 11 which each relate to a single metallisation process in which co-patterning of the two-dimensional material layer structure and dielectric layer takes places before the metallisation step. Example embodiment 11 comprises forming a passivation layer directly after co-patterning.

[0149] In some aspects, embodiments 3, 4, 8 and 9 are most preferred since these embodiments are those which the inventors have found minimise contamination of the two-dimensional material layer structure. These embodiments comprise forming a passivation layer directly after co-patterning thereby protecting the two-dimensional material layer structure edges from contamination. Embodiments 8 and 9 are generally simpler with fewer process steps. Nevertheless, embodiments 1 , 2, and 5-7, like 3, 4, 8 and 9, still benefit principally from protecting the surface of the two-dimensional material layer structure where the contacts are to be formed by using the same resist for dielectric etching and metal lift-off. Embodiments 1 and 2, for example, offer benefits over embodiment 5 in that there are fewer process steps where the edges may be exposed to resist and / or metal deposition and stripping / lift-off and / or metal patterning. However, these minor drawbacks in embodiment 5 may be addressed by the passivation layer in embodiments 6 and 7.

[0150] In other aspects, embodiments 10 and 11 , in particular embodiment 11 , are most preferred since these broadly minimise any contamination, yet provide a significantly simpler one step metallisation reducing the complexity of the overall production which is essential for mass production of electronic devices. These embodiments avoid the more problematic issue of avoiding depositing resist in contact with the surface of the two-dimensional material layer structure, whilst embodiment 11 further protects the edge. Without wishing to be bound by theory, it is believed that the deposition and curing process during resist development is more problematic for contamination, whereas the stripping and lift-off steps which dissolve the resist are less damaging in terms of polymer contamination.

[0151] Nevertheless, such steps also present their own problems in migration of polymer residues, and in terms of influencing the electronic properties of the two-dimensional material layer structure (e.g. extent and / or uniformity of doping). These in turn can also still impact device stability over time.

[0152]

[0153]

[0154]

[0155] Examples

[0156] A monolayer of graphene is grown across the entirety of a 2 inch (2.5 cm) diameter sapphire wafer using MOCVD. This is followed by the deposition of a 3 nm layer of molybdenum oxide onto the graphene using thermal evaporation at a rate of 0.5 A / s at a base pressure of ~1x10"® mbar. The wafer is transferred under a nitrogen environment into an ALD chamber and 10 nm of aluminium oxide is deposited at a temperature of 165°C and a base pressure of 100 mTorr (133 mbar).

[0157] A round of photolithography is used to create an array of 10 pm x 10 pm contact apertures separated by 5 pm to create an array of contact apertures across the wafer in suitable positions for the contacts of an array of Hall crosses. The photoresist used is nLOF2020, which is spun at 4000 rpm, baked at 110°C, exposed at 66 mJ / cm2and developed in MF319 for 2 minutes. A wet chemical etch is subsequently performed using 100% phosphoric acid at 50°C for 40 seconds to etch the aluminium oxide and molybdenum oxide layers in the resist apertures down to the graphene layer, whilst leaving the graphene layer intact.

[0158] Using the same resist mask, a metallisation and lift off process is performed to create metal plugs in the contact apertures. This is performed by blanket coating the wafer with a 10 nm layer of electron beam evaporated chromium at a rate of 2 A / s, followed by 50 nm of electron beam evaporated gold at 2 A / s. Lift-off of the nLOF2020 resist layer is then performed by 40 minutes immersion in SVC-14 solvent held at 80°C. This leaves an array of metallised contact plugs across the wafer to act as top contacts to the graphene Hall crosses to be patterned.

[0159] A second round of photolithography is performed to co-pattern suitable shaped Hall crosses in the stack of aluminium oxide / molybdenum oxide / graphene layers around the contact plugs. This is done using S1813 resist, which is spun at 4000 rpm, baked at 115°C, exposed at 150 mJ / cm2and developed in AZ developer for 1 minute. AZ developer is used at 1 :2 weight ratio with deionised water. An inductively coupled plasma reactive ion etching (ICP-RIE) dry etch is then performed using the S1813 resist mask to define the array of Hall cross outlines using 20 seem BCh gases at 100 W RF power and 1000 W ICP power for 27 seconds. The resist mask is then stripped in MICROPOSIT™ remover 1165 at 80°C with 3 minutes of O2 plasma ashing before and after the solvent strip.

[0160] A third round of photolithography is then performed to provide a contact pads which each cover one or a group of the metal plugs (depending on the metal plug patterning employed) to form a continuous contact which contains a bond pad tracked off the side of the Hall cross to allow stable wire bonding / probing onto the sapphire substrate. This is done using LOR7B resist, which is spun at 2500 rpm and baked at 160°C, followed by S1813 resist, which is spun at 4000 rpm and baked at 115°C. The resist is exposed at 150 mJ / cm2and developed in MF319 for 1 minute. A metallisation and lift off process is performed by blanket coating the wafer with a 10 nm layer of electron beam evaporated titanium at a rate of 1 A / s, followed by 200 nm of electron beam evaporated gold at 2 A / s. Lift-off of the resist layer is then performed by 40 minutes immersion in SVC-14 solvent held at 80°C.

[0161] As used herein, the singular form of “a”, “an” and “the” include plural references unless the context clearly dictates otherwise. The use of the term “comprising” is intended to be interpreted as including such features but not excluding other features and is also intended to include the option of the features necessarily being limited to those described. In other words, the term also includes the limitations of “consisting essentially of’ (intended to mean that specific further components can be present provided they do not materially affect the essential characteristic of the described feature) and “consisting of’ (intended to mean that no other feature may be included such that if the components were expressed as percentages by their proportions, these would add up to 100%, whilst accounting for any unavoidable impurities), unless the context clearly dictates otherwise.

[0162] It will be understood that, although the terms "first", "second", etc. may be used herein to describe, for example, various elements, layers and / or portions, the elements, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, layer or portion from another, or a further, element, layer or portion. It will be understood that the term “on” is intended to mean “directly on” such that there are no intervening layers between one material being said to be “on” another material. Spatially relative terms, such as “under”, "below", "beneath", "lower", “over”, "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device as described herein is turned over, elements described as "under” or “below" other elements or features would then be oriented “over” or "above" the other elements or features. Thus, the example term "under" can encompass both an orientation of over and under. The device may be otherwise oriented and the spatially relative descriptors used herein interpreted accordingly.

[0163] Numerical lower and upper limits of features described herein may preferably be combined to provide a closed range.

[0164] The foregoing detailed description has been provided by way of explanation and illustration, and is not intended to limit the scope of the appended claims. Many variations of the presently preferred embodiments illustrated herein will be apparent to one of ordinary skill in the art, and remain within the scope of the appended claims and their equivalents.

[0165] For the avoidance of doubt, the entire contents of all documents acknowledged herein are incorporated herein by reference. The present invention will now be described further with reference to the following numbered embodiments:

[0166] 1 . A method for the provision of metal contacts on a two-dimensional material layer structure, the method comprising:

[0167] (i) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm;

[0168] (ii) depositing a first resist on and across the inorganic dielectric layer and patterning the first resist to expose a plurality of portions of the dielectric layer;

[0169] (iii) wet-etching the plurality of portions of the dielectric layer to expose a corresponding plurality of surface portions of the two-dimensional material layer structure and form a plurality of wells in the dielectric layer;

[0170] (iv) performing a first metallisation step by depositing a first metal on and across the exposed plurality of surface portions of the two-dimensional material layer structure and the patterned first resist and then removing the patterned first resist by lift-off to form metal plugs substantially filling the wells of the dielectric layer; and

[0171] (v) performing a second metallisation step by depositing a second metal and forming a plurality of metal contact pads, each contact pad in contact with one or more of the metal plugs.

[0172] 2. The method according to embodiment 1 , wherein each well formed in step (iii) has a cross- sectional area co-planar with the substrate of less than 2,500 pm2and has a maximum width of less than 50 pm, preferably wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm.

[0173] 3. The method according to embodiment 1 or embodiment 2, wherein the two-dimensional material layer structure comprises or consists of a graphene layer structure, preferably a graphene monolayer.

[0174] 4. The method according to any preceding embodiment, wherein step (i) of providing a laminate structure comprises forming the two-dimensional material layer structure directly on and across the substrate by CVD.

[0175] 5. The method according to any preceding embodiment, wherein the thickness of the dielectric layer is from 10 to 65 nm.

[0176] 6. The method according to any preceding embodiment, wherein the dielectric layer comprises a layer of aluminium oxide. 7. The method according to any preceding embodiment, wherein the dielectric layer comprises a layer of a transition metal oxide selected from the group consisting of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide, and combinations thereof, preferably molybdenum oxide.

[0177] 8. The method according to any preceding embodiment, wherein the first and / or second metals comprise gold.

[0178] 9. The method according to embodiment 8, wherein the first metal is a first stack of chromium and gold, wherein the chromium of the first stack is deposited before the gold of the first stack, and wherein the second metal is a second stack of titanium and gold, wherein the titanium of the second stack is deposited before the gold of the second stack.

[0179] 10. The method according to any preceding embodiment, wherein the cross-sectional area of each well is from 100 to 500 pm2.

[0180] 11 . The method according to any preceding embodiment, wherein each well has a substantially constant cross-sectional area co-planarwith the substrate.

[0181] 12. The method according to any preceding embodiment, wherein the maximum width of each well is from 5 to 30 pm.

[0182] 13. The method according to any preceding embodiment, wherein each well is a quadrilateral, preferably, an isosceles trapezoid, a rectangle or a square.

[0183] 14. The method according to any one of embodiments 1 to 12, wherein each well is a comb comprising a plurality of linked teeth, wherein each tooth is preferably an isosceles trapezoid, a rectangle or a square.

[0184] 15. The method according to embodiment 14, wherein each tooth is spaced at least 2 pm from any other tooth, preferably at least 5 pm.

[0185] 16. The method according to any preceding embodiment, wherein each well is spaced at least 2 pm from any other well and / or any edge of the two-dimensional material layer structure, preferably at least 5 pm.

[0186] 17. The method according to any preceding embodiment, wherein the method does not comprise patterning the two-dimensional material layer structure before step (iii) of wet-etching a plurality of portions of the dielectric layer. 18. The method according to any preceding embodiment, wherein the method further comprises a step of co-patterning the two-dimensional material layer structure and the dielectric layer between the first and second metallisation steps (iv) and (v).

[0187] 19. The method according to any preceding embodiment, wherein the method further comprises a step of forming a passivation layer after the second metallisation step (v) to protect the two- dimensional material layer structure, and etching portions of the passivation layer to expose portions of each contact pad.

[0188] 20. The method according to any preceding embodiment, preferably embodiment 18, wherein the method further comprises a step of forming a passivation layer between the first and second metallisation steps (iv) and (v) to protect the two-dimensional material layer structure, and etching portions of the passivation layer to expose each metal plug before the second metallisation step.

[0189] 21. The method according to any one of embodiments 1 to 16, wherein the method comprises a step of co-patterning the two-dimensional material layer structure and the dielectric layer to form one or more co-patterned stacks, wherein the step of co-patterning is performed between steps (i) and (ii) of providing a laminate structure and depositing a first resist.

[0190] 22. The method according to embodiment 21 , wherein the method further comprises forming a passivation layer between the step of co-patterning and step (ii) to protect the two-dimensional material layer structure, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm, wherein step (ii) comprises depositing a first resist on and across the passivation layer and patterning the first resist to expose a plurality of portions of the passivation layer, and wherein step (iii) comprises wet-etching the plurality of portions of the passivation layer and corresponding underlying portions of the dielectric layer to expose a corresponding plurality of surface portions of the two-dimensional material layer structure and form a plurality of wells in the passivation and dielectric layers.

[0191] 23. The method according to embodiment 21 , wherein the method further comprises forming a passivation layer between the first and second metallisation steps (iv) and (v) to protect the two- dimensional material layer structure, and etching portions of the passivation layer to expose each metal plug before the second metallisation step.

[0192] 24. The method according to any preceding embodiment, wherein the dielectric layer and / or passivation layer are formed by ALD. 25. The method according to any preceding embodiment, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided is selected from the group consisting of yttria-stabilised zirconia (YSZ), CaF2, AIN, sapphire, or a rare-earth oxide, preferably YSZ, sapphire, or a rare-earth oxide.

[0193] 26. The method according to any preceding embodiment, wherein a crystallographic orientation of the growth surface is <1-102> (i.e. r-plane for hexagonal materials) or <111> (for cubic materials).

[0194] 27. The method according to any preceding embodiment, wherein the method further comprises, between the first and second metallisation steps (iv) and (v), a step of depositing a second resist on and across the inorganic dielectric layer (or, where present, the passivation layer) and patterning the second resist to expose the metal plugs, wherein step (v) comprises performing a second metallisation step by depositing a second metal on and across the exposed metal plugs and the patterned second resist and then removing the patterned second resist by lift-off to form metal contact pads, each contact pad in contact with one or more of the metal plugs.

[0195] 28. The method according to any one of embodiments 1 to 26, wherein step (v) comprises performing a second metallisation step by depositing a second metal on and across the inorganic dielectric layer (or, where present, the passivation layer) and the metal plugs and forming a plurality of metal contact pads by patterning the second metal (e.g. by dry-etching), each contact pad in contact with one or more of the metal plugs.

[0196] 29. A method for the provision of metal contacts on a two-dimensional material layer structure, the method comprising:

[0197] (i) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure, wherein the dielectric layer has a thickness from an upper surface to the two- dimensional material layer structure of less than 80 nm;

[0198] (ii) wet-etching a plurality of portions of the dielectric layer to expose a corresponding plurality of surface portions of the two-dimensional material layer structure and form a plurality of wells in the dielectric layer;

[0199] (iii) performing a first metallisation step to deposit a first metal on the exposed plurality of surface portions of the two-dimensional material layer structure and to form metal plugs substantially filling the wells of the dielectric layer; and

[0200] (iv) performing a second metallisation step to deposit a second metal and form a plurality of metal contact pads, each contact pad in contact with one or more of the metal plugs; wherein each well formed in step (ii) has a cross-sectional area co-planar with the substrate of less than 2,500 pm2and has a maximum width of less than 50 pm. The method of embodiment 29 may, like embodiment 1 , equally be combined with the further features described herein, such as those features set out in embodiments 2 to 28.

[0201] 30. An electronic device comprising: a substrate having a patterned two-dimensional material layer structure thereon, the two- dimensional material layer structure having edges; an inorganic dielectric layer co-patterned with the two-dimensional material layer structure, wherein the dielectric layer has a thickness from an upper surface to the two-dimensional material layer structure of less than 80 nm; a passivation layer protecting at least the edges of the patterned two-dimensional material layer structure; and a plurality of metal plugs substantially filling wells in the dielectric layer, wherein each plug extends from a surface portion of the two-dimensional material layer structure to one of a plurality of metal contact pads provided on the dielectric layer or the passivation layer; wherein each well has a cross-sectional area co-planar with the substrate of less than 2,500 pm2and has a maximum width of less than 50 pm.

[0202] 31 . The electronic device according to embodiment 30, wherein the electronic device is obtained by the method of any one of embodiments 1 to 29.

[0203] 32. The electronic device according to embodiment 30 or embodiment 31 , wherein the electronic device is a diode, a transistor, a sensor or an optoelectronic, preferably a hall sensor, a field effect transistor, an electro-optic modulator or a photodetector.

[0204] 33. The electronic device according to any one of embodiments 30 to 32, wherein each contact pad is in contact with two or more of the metal plugs.

[0205] 34. The electronic device according to any one of embodiments 30 to 33, wherein the two- dimensional material layer structure comprises or consists of a graphene layer structure, preferably a graphene monolayer.

[0206] 35. The electronic device according to any one of embodiments 30 to 34, wherein the thickness of the dielectric layer is from 10 to 65 nm.

[0207] 36. The electronic device according to any one of embodiments 30 to 35, wherein the dielectric layer comprises a layer of aluminium oxide.

[0208] 37. The electronic device according to any one of embodiments 30 to 36, wherein the dielectric layer comprises a layer of a transition metal oxide selected from the group consisting of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide, and combinations thereof, preferably molybdenum oxide.

[0209] 38. The electronic device according to any one of embodiments 30 to 37, wherein each metal plug and / or contact pad comprises gold.

[0210] 39. The electronic device according to any one of embodiments 30 to 38, wherein each metal plug is a first stack of chromium and gold, wherein the chromium of the first stack is deposited on the surface portion of the two-dimensional material layer structure and the gold of the first stack deposited thereon, and wherein each metal contact pad is a second stack of titanium and gold, wherein the titanium of the second stack is deposited on at least one metal plug, and the gold of the second stack is deposited thereon.

[0211] 40. The electronic device according to any one of embodiments 30 to 39, wherein the cross- sectional area of each well is from 100 to 500 pm2.

[0212] 41 . The electronic device according to any one of embodiments 30 to 40, wherein each well has a substantially constant cross-sectional area co-planar with the substrate.

[0213] 42. The electronic device according to any one of embodiments 30 to 41 , wherein the maximum width of each well is from 5 to 30 pm.

[0214] 43. The electronic device according to any one of embodiments 30 to 42, wherein each well is a quadrilateral, preferably, an isosceles trapezoid, a rectangle or a square.

[0215] 44. The electronic device according to any one of embodiments 30 to 42, wherein each well is a comb comprising a plurality of linked teeth, wherein each tooth is preferably an isosceles trapezoid, a rectangle or a square.

[0216] 45. The electronic device according to embodiment 44, wherein each tooth is spaced at least 2 pm from any other tooth, preferably at least 5 pm.

[0217] 46. The electronic device according to any one of embodiments 30 to 45, wherein each well is spaced at least 2 pm from any other well, preferably at least 5 pm.

[0218] 47. The electronic device according to any one of embodiments 30 to 46, wherein each well is spaced at least 2 pm from any edge of the two-dimensional material layer structure, preferably at least 5 pm. 48. The electronic device according to any one of embodiments 30 to 47, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided is selected from the group consisting of yttria-stabilised zirconia (YSZ), CaF2, AIN, sapphire, or a rare- earth oxide, preferably YSZ, sapphire, or a rare-earth oxide.

[0219] 49. The electronic device according to any one of embodiments 30 to 48, wherein a crystallographic orientation of the growth surface is <1-102> or <111 >.

[0220] 50. A method for the provision of metal contacts on a two-dimensional material layer structure, the method comprising:

[0221] (i) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm;

[0222] (ii) wet-etching, within each of a plurality of regions of the laminate structure, a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two- dimensional material layer structure and form a corresponding group of wells in the dielectric layer, wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm;

[0223] (iii) performing one or more metallisation steps by depositing one or more metals and forming a plurality of contact pads, wherein each contact pad is in electrical communication with the two- dimensional material layer structure through a group of metal vias filling one of the corresponding group of wells.

[0224] 51 . The method according to embodiment 50, wherein the method further comprises a step of copatterning the two-dimensional material layer structure and the dielectric layer to form one or more copatterned stacks, and thereby exposing the substrate adjacent thereto, wherein the step of copatterning is performed between steps (i) and (ii), or during step (iii) between the first and any further metallisation step, preferably between steps (i) and (ii).

[0225] Consequently, where co-patterning is performed between steps (i) and (ii), step (ii) of wet-etching may instead be described as wet-etching, within each of a plurality of regions of each co-patterned stack, a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two-dimensional material layer structure and form a corresponding group of wells in the dielectric layer. Where co-patterning is performed during step (iii), it will also be appreciated that step (ii) may be described as wet-etching, within each of a plurality of regions of each intended co-patterned stack to be formed during step (iii), a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two-dimensional material layer structure and form a corresponding group of wells in the dielectric layer. 52. The method according to embodiment 51 , wherein each co-patterned stack has a hall cross shape comprising at least four arms, wherein each arm provides a region for forming a contact pad.

[0226] 53. The method according to embodiment 51 or embodiment 52, wherein the method further comprises a step of forming a passivation layer after forming the plurality of contact pads to protect the edges of the two-dimensional material layer structure, and etching portions of the passivation layer to expose portions of each contact pad.

[0227] 54. The method according to embodiment 51 or embodiment 52, wherein the method further comprises a step of forming a passivation layer after the step of co-patterning and before step (ii) to protect the edges of the two-dimensional material layer structure, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm, and wherein step (ii) comprises wetetching a group of portions of the dielectric layer and the passivation layer to expose a corresponding group of surface portions of the two-dimensional material layer structure and form a corresponding group of wells in the dielectric layer and passivation layer.

[0228] That is, in such an embodiment, the step of co-patterning is performed between steps (i) and (ii).

[0229] 55. The method according to any one of embodiments 51 to 54, wherein the step of co-patterning is performed between steps (i) and (ii), and step (iii) comprises performing a metallisation step by depositing one or more metals to form a metal layer on and across the dielectric layer of the copatterned stacks (or, where present, the passivation layer) and each group of exposed surface portions of the two-dimensional material layer structure.

[0230] 56. The method according to any one of embodiments 51 to 54, wherein the step of co-patterning is performed between steps (i) and (ii), and step (iii) comprises performing a first metallisation step by depositing a first metal on and across each group of exposed surface portions of the two-dimensional material layer structure and the patterned first resist and then removing the patterned first resist by liftoff to form metal plugs substantially filling the wells of the dielectric layer.

[0231] As will be appreciated, the patterned first resist is that which is used in the wet-etching step.

[0232] 57. The method according to any one of embodiments 51 to 54, wherein the step of co-patterning is performed during step (iii) between the first and a further metallisation step, and step (iii) comprises performing a first metallisation step by depositing a first metal on and across each group of exposed surface portions of the two-dimensional material layer structure and the patterned first resist and then removing the patterned first resist by lift-off to form metal plugs substantially filling the wells of the dielectric layer. 58. The method according to embodiment 56 or embodiment 57, wherein step (iii) further comprises performing a second metallisation step by depositing a second metal on and across the exposed metal plugs and the patterned second resist and then removing the patterned second resist by lift-off to form the plurality of contact pads.

[0233] 59. The method according to embodiment 58, wherein step (iii) further comprises performing a second metallisation step by depositing a second metal on and across the inorganic dielectric layer (or, where present, the passivation layer) and the metal plugs and forming the plurality of contact pads by patterning the second metal (e.g. by dry-etching).

[0234] As will be appreciated, the metal plugs form the metal vias of the contact pad.

[0235] 60. The method according to any one of embodiments 50 to 59, wherein the two-dimensional material layer structure comprises or consists of a graphene layer structure, preferably a graphene monolayer.

[0236] 61 . The method according to any one of embodiments 50 to 60, wherein step (i) of providing a laminate structure comprises forming the two-dimensional material layer structure directly on and across the substrate by CVD.

[0237] 62. The method according to any one of embodiments 50 to 61 , wherein the thickness of the dielectric layer is from 10 to 65 nm.

[0238] 63. The method according to any one of embodiments 50 to 62, wherein the dielectric layer comprises a layer of aluminium oxide.

[0239] 64. The method according to any one of embodiments 50 to 63, wherein the dielectric layer comprises a layer of a transition metal oxide selected from the group consisting of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide, and combinations thereof, preferably molybdenum oxide.

[0240] 65. The method according to any one of embodiments 50 to 64, wherein the metallisation step (iii) comprises depositing titanium followed by gold.

[0241] 66. The method according to any one of embodiments 50 to 65, wherein each group of wells comprises at least 3 wells, preferably at least 5 wells, and / or up to 50 wells, preferably up to 25 wells.

[0242] 67. The method according to any one of embodiments 50 to 66, wherein the maximum width of each well is from 5 to 25 pm. 68. The method according to any one of embodiments 50 to 67, wherein the cross-sectional area of each well is from 100 to 500 pm2.

[0243] 69. The method according to any one of embodiments 50 to 68, wherein each well has a substantially constant cross-sectional area co-planar with the substrate.

[0244] 70. The method according to any one of embodiments 50 to 69, wherein each well has a circular or quadrilateral cross-section, preferably, an isosceles trapezoid, a rectangle or a square crosssection.

[0245] 71 . The method according to any one of embodiments 50 to 70, wherein each well is spaced at least 2 pm from any other well and / or any edge of the two-dimensional material layer structure, preferably at least 5 pm.

[0246] 72. The method according to any one of embodiments 50 to 71 , wherein each group of wells has a linear arrangement.

[0247] 73. The method according to any one of embodiments 50 to 72, wherein depositing one or more metals forms a metal layer and the metal layer is patterned by dry-etching to form the plurality of contact pads.

[0248] 74. The method according to any one of embodiments 50 to 73, wherein the dielectric layer and / or passivation layer are formed by ALD.

[0249] 75. The method according to any one of embodiments 50 to 74, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided is selected from the group consisting of yttria-stabilised zirconia (YSZ), CaF2, AIN, sapphire, silicon oxide, silicon nitride, or a rare-earth oxide, preferably sapphire, silicon oxide, silicon nitride, or a rare- earth oxide.

[0250] 76. The method according to any one of embodiments 50 to 75, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided has a crystallographic orientation of <1-102> or <111>.

[0251] 77. An electronic device comprising: a substrate having a patterned two-dimensional material layer structure thereon, the two- dimensional material layer structure having edges; an inorganic dielectric layer co-patterned with the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm; and a plurality of contact pads, each contact pad comprising a group of metal vias filling wells in the dielectric layer; wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm.

[0252] 78. The electronic device according to embodiment 77, wherein the electronic device is obtained by the method of any one of embodiments 50 to 76.

[0253] 79. The electronic device according to embodiment 77 or embodiment 78, further comprising a passivation layer protecting at least the edges of the patterned two-dimensional material layer structure.

[0254] 80. The electronic device according to embodiment 79, wherein the passivation layer is provided on and across the substrate, the inorganic dielectric layer, and the plurality of contact pads, and wherein portions of the passivation layer are etched thereby exposing portions of each contact pad. In such an embodiment, each contact pad is provided on the inorganic dielectric layer (and optionally the substrate as described herein), with each contact pad comprising vias which fill wells in the dielectric layer.

[0255] 81 . The electronic device according to embodiment 79, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm, wherein the passivation layer is provided on and across the substrate, and the inorganic dielectric layer. In such an embodiment, each group of metal vias of the contacts pads fill wells in the passivation and dielectric layers. Each contact pad is provided on the passivation layer and optionally the substrate as described herein, if the passivation layer has been etched to expose the substrate, though this may not be necessary.

[0256] 82. The electronic device according to any one of embodiments 77 to 81 , wherein the electronic device is a diode, a transistor, a sensor or an optoelectronic, preferably a hall sensor, a field effect transistor, an electro-optic modulator or a photodetector.

[0257] 83. The electronic device according to any one of embodiments 77 to 82, wherein the maximum width of each well is from 5 to 25 pm.

[0258] 84. The electronic device according to any one of embodiments 77 to 83, wherein the cross- sectional area of each well is from 100 to 500 pm2. 85. The electronic device according to any one of embodiments 77 to 84, wherein the patterned two-dimensional material layer structure comprises or consists of a patterned graphene layer structure, preferably a patterned graphene monolayer.

[0259] 86. The electronic device according to any one of embodiments 77 to 85, wherein the thickness of the dielectric layer is from 10 to 65 nm.

[0260] 87. The electronic device according to any one of embodiments 77 to 86, wherein the dielectric layer comprises a layer of aluminium oxide.

[0261] 88. The electronic device according to any one of embodiments 77 to 87, wherein the dielectric layer comprises a layer of a transition metal oxide selected from the group consisting of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide, and combinations thereof, preferably molybdenum oxide.

[0262] 89. The electronic device according to any one of embodiments 77 to 88, wherein each contact pad is formed of a layer of titanium and a layer of gold thereon (i.e. Ti / Au).

[0263] 90. The electronic device according to any one of embodiments 77 to 89, wherein the inorganic dielectric layer and the two-dimensional material layer structure are co-patterned having a hall cross shape comprising at least four arms, each arm comprising one of the contact pads.

[0264] 91 . The electronic device according to any one of embodiments 77 to 90, wherein each group of wells comprises at least 3 wells, preferably at least 5 wells, and / or up to 50 wells, preferably up to 25 wells.

[0265] 92. The electronic device according to any one of embodiments 77 to 91 , wherein the maximum width of each well is from 5 to 25 pm.

[0266] 93. The electronic device according to any one of embodiments 77 to 92, wherein the cross- sectional area of each well is from 100 to 500 pm2.

[0267] 94. The electronic device according to any one of embodiments 77 to 93, wherein each well has a substantially constant cross-sectional area co-planar with the substrate.

[0268] 95. The electronic device according to any one of embodiments 77 to 94, wherein each well has a circular or quadrilateral cross-section, preferably, an isosceles trapezoid, a rectangle or a square cross-section. 96. The electronic device according to any one of embodiments 77 to 95, wherein each well is spaced at least 2 pm from any other well and / or any edge of the two-dimensional material layer structure, preferably at least 5 pm. 97. The electronic device according to any one of embodiments 77 to 96, wherein each group of wells has a linear arrangement.

[0269] 98. The electronic device according to any one of embodiments 77 to 97, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided is selected from the group consisting of yttria-stabilised zirconia (YSZ), CaF2, AIN, sapphire, silicon oxide, silicon nitride, or a rare-earth oxide, preferably sapphire, silicon oxide, silicon nitride, or a rare- earth oxide.

[0270] 99. The electronic device according to any one of embodiments 77 to 98, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided has a crystallographic orientation of <1-102> or <111>.

[0271] 100. An array of electronic devices sharing a common substrate, wherein each electronic device is in accordance with any one of embodiments 30 to 49 or 77 to 99.

Claims

Claims:1 . A method for the provision of metal contacts on a two-dimensional material layer structure, the method comprising:(i) providing a laminate structure comprising a substrate having a two-dimensional material layer structure thereon, and an inorganic dielectric layer on and across the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm;(ii) wet-etching, within each of a plurality of regions of the laminate structure, a group of portions of the dielectric layer to expose a corresponding group of surface portions of the two- dimensional material layer structure and form a corresponding group of wells in the dielectric layer, wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm;(Hi) performing one or more metallisation steps by depositing one or more metals and forming a plurality of contact pads, wherein each contact pad is in electrical communication with the two- dimensional material layer structure through a group of metal vias filling one of the corresponding group of wells.

2. The method according to claim 1 , wherein the method further comprises a step of copatterning the two-dimensional material layer structure and the dielectric layer to form one or more copatterned stacks, and thereby exposing the substrate adjacent thereto, wherein the step of copatterning is performed between steps (i) and (ii), or during step (iii) between the first and any further metallisation step, preferably between steps (i) and (ii).

3. The method according to claim 2, wherein the step of co-patterning is performed between steps (i) and (ii), and step (iii) comprises performing a metallisation step by depositing one or more metals to form a metal layer on and across the dielectric layer of the co-patterned stacks and each group of exposed surface portions of the two-dimensional material layer structure, preferably wherein the one or more metals are titanium followed by gold.

4. The method according to claim 2 or claim 3, wherein the method further comprises a step of forming a passivation layer after the step of co-patterning and before step (ii) to protect the edges of the two-dimensional material layer structure, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm, and wherein step (ii) comprises wet-etching a group of portions of the dielectric layer and the passivation layer to expose a corresponding group of surface portions of the two-dimensional material layer structure and form a corresponding group of wells in the dielectric layer and passivation layer.

5. The method according to any one of claims 2 to 4, wherein each co-patterned stack has a hall cross shape comprising at least four arms, wherein each arm provides a region for forming a contact pad.

6. The method according to any preceding claim, wherein step (i) of providing a laminate structure comprises forming the two-dimensional material layer structure directly on and across the substrate by CVD.

7. The method according to any preceding claim, wherein the thickness of the dielectric layer is from 10 to 65 nm.

8. The method according to any preceding claim, wherein the dielectric layer comprises a layer of aluminium oxide and / or a layer of a transition metal oxide selected from the group consisting of vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and nickel oxide, and combinations thereof, preferably molybdenum oxide.

9. The method according to any preceding claim, wherein each group of wells comprises at least 3 wells, preferably at least 5 wells, and / or up to 50 wells, preferably up to 25 wells.

10. The method according to any preceding claim, wherein the maximum width of each well is from 5 to 25 pm.11 . The method according to any preceding claim, wherein the cross-sectional area of each well is from 100 to 500 pm2.

12. The method according to any preceding claim, wherein each well has a substantially constant cross-sectional area co-planar with the substrate.

13. The method according to any preceding claim, wherein each well is spaced at least 2 pm from any other well and / or any edge of the two-dimensional material layer structure, preferably at least 5 pm.

14. The method according to any preceding claim, wherein each group of wells has a linear arrangement.

15. The method according to any preceding claim, wherein depositing one or more metals forms a metal layer and the metal layer is patterned by dry-etching to form the plurality of contact pads.

16. The method according to any preceding claim, wherein the dielectric layer and / or passivation layer are formed by ALD.

17. The method according to any preceding claim, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided is selected from the group consisting of yttria-stabilised zirconia (YSZ), CaF2, AIN, sapphire, silicon oxide, silicon nitride, or a rare-earth oxide, preferably sapphire, silicon oxide, silicon nitride, or a rare-earth oxide.

18. The method according to any preceding claim, wherein a crystalline growth surface of the substrate upon which the two-dimensional material layer structure is provided has a crystallographic orientation of <1 -102> or <1 1 1 >.

19. An electronic device comprising: a substrate having a patterned two-dimensional material layer structure thereon, the two- dimensional material layer structure having edges; an inorganic dielectric layer co-patterned with the two-dimensional material layer structure, wherein the dielectric layer has a thickness of less than 80 nm; and a plurality of contact pads, each contact pad comprising a group of metal vias filling wells in the dielectric layer; wherein each well has a cross-sectional area co-planar with the substrate of less than 900 pm2and has a maximum width of less than 30 pm.

20. The electronic device according to claim 19, further comprising a passivation layer protecting at least the edges of the patterned two-dimensional material layer structure.21 . The electronic device according to claim 20, wherein the passivation layer is provided on and across the substrate, the inorganic dielectric layer, and the plurality of contact pads, and wherein portions of the passivation layer are etched thereby exposing portions of each contact pad.

22. The electronic device according to claim 20, wherein a total thickness of the dielectric layer and the passivation layer is less than 80 nm, wherein the passivation layer is provided on and across the substrate, and the inorganic dielectric layer, and wherein each contact pad is provided on the passivation layer.

23. The electronic device according to any one of claims 19 to 22, wherein the electronic device is a diode, a transistor, a sensor or an optoelectronic.

24. The electronic device according to any one of claims 19 to 23, wherein the maximum width of each well is from 5 to 25 gm, and / or wherein the cross-sectional area of each well is from 100 to 500 gm2.

25. An array of electronic devices sharing a common substrate, wherein each electronic device is in accordance with any one of claims 19 to 24.

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