Method for manufacturing electronic chip card module circuits with colored contact pads and circuits produced by the method

Abstract

The invention relates to a circuit, for example of the printed circuit type, for the production of a module intended to be integrated in a chip card. This module has an area of electrical contact pads - or connectors (3) - for the connection and communication of the chip with a reading / writing system. In order to give them a colour different from that of the gold or silver plating usually used, these electrical contact areas (3) are at least partially covered with a surface layer (14) comprising a compound of the type XpOqNrCs, in which X can be Hf, Ta, Zr, Nb, Mo, Cr, V, Ti or Sc, in which p, q > 0, and r > 0 and / or s > 0. The invention also relates to a method for manufacturing such a circuit.

Description

Technical Field

[0001] This invention relates to the field of circuits with connector contacts or conductive traces. Existing technology

[0002] The application examples of the circuits according to the present invention described herein are taken from the field of chip cards, but these examples can be easily transferred to other circuit applications. It is noteworthy that the present invention is particularly advantageous in all cases where conductive traces are visible on the finished product used by consumers. For example, for SD cards...

[0003] The colored contacts on the connectors of memory cards or USB memory sticks can also provide additional aesthetic value.

[0004] The chip card has an electronic module with electrical contact pads or connector areas for connection and communication between at least one electronic chip and a read / write system attached to the module.

[0005] Specifically, a chip card typically consists of a relatively rigid support that forms the main part of the card. For example, the rigid support is made of plastic, and a separately manufactured electronic module is integrated within it. This electronic module has a typically flexible printed circuit that houses an electronic chip (integrated circuit) and connection or connector devices / devices, such as contacts formed by conductive metal traces flush with the surface of the support.

[0006] Chip cards have multiple uses: credit cards, mobile phone SIM cards, travel cards, ID cards, etc.

[0007] In addition to ensuring good conductivity between the contacts and the connector of the reader / writer, chip card manufacturers now want the contact color to match the card color. For this purpose, contacts are typically coated with gold for a gold-plated finish, or with silver or palladium for a silver-plated finish.

[0008] To obtain a wider range of colors, the method described in document US6259035B1 can be used. This method relies on using solutions based on gold, palladium, or silver to achieve a broader range of colors. However, this type of method cannot obtain certain colors, particularly black or near-black.

[0009] One object of the present invention is to provide a circuit having colored contacts or conductive traces, particularly having black or near-black color on at least a portion of the surface of the contacts or conductive traces, while still maintaining electrical and mechanical properties particularly suitable for establishing electrical connections. Invention Summary

[0010] Therefore, a method for manufacturing circuits, particularly for manufacturing chip card modules, is proposed, comprising the following steps:

[0011] A dielectric substrate is provided, on which a sheet of conductive material is disposed.

[0012] At least one layer of conductive material is deposited on a conductive material sheet, the conductive material layer forming a surface layer covering at least one region of the surface of at least one conductive trace formed in the conductive material sheet.

[0013] In this method, the formation of the surface layer includes a physical vapor deposition step originating from at least one metal target, wherein the composition involves at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium, and scandium; and at least one gas comprising argon, nitrogen, and oxygen. Optionally, the gas includes argon, nitrogen, and oxygen.

[0014] Specifically, through this type of physical vapor deposition, the inventors have been able to obtain surface layers that not only have colors close to or even very deep black, but also possess conductivity and robustness, thereby meeting the specifications particularly required in the chip card field, and more specifically for use in chip cards for banking applications. Other colors for surface layers can also be obtained through this type of physical vapor deposition.

[0015] This method includes one or more other features from the following optional features, which are considered independently of each other or in combination with one or more other features:

[0016] The surface layer is composed of compounds of the type XpOqNrCs, where X is contained in the elements consisting of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, where p and q are strictly positive numbers, and at least one of r and s is a number greater than or equal to zero.

[0017] A surface layer is deposited on a bonding layer, which itself is formed by physical vapor deposition in an atmosphere containing argon working gas, wherein at least one metal target is used, and the composition involves at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium, and scandium.

[0018] It includes the step of laser etching a surface layer and a bonding layer located between at least two conductive traces to break the conductive traces;

[0019] The bonding layer and surface layer are deposited on the conductive mesh (that is, the conductive mesh used in the context of lead frame technology), which is formed in the conductive material sheet during the step of transferring the mesh to the dielectric substrate;

[0020] A surface layer is selectively deposited on at least one region of the surface of at least one conductive trace, during which the surface layer, pre-deposited on a support, is transferred to a sheet of conductive material using a laser; and

[0021] The method includes a step of creating a mask before forming the surface layer, so as to selectively deposit the surface layer only on certain areas of the conductive material sheet.

[0022] According to another aspect, a circuit specifically designed for manufacturing chip card modules is proposed. For example, this circuit is manufactured using the method described above.

[0023] The circuit includes:

[0024] Dielectric substrate, and conductive material sheet placed on the dielectric substrate.

[0025] At least one conductive material layer is disposed directly or indirectly on a conductive material sheet, the conductive material layer forming a surface layer covering at least one region of a surface of at least one conductive trace formed in the conductive material sheet.

[0026] In this circuit, the surface layer comprises a compound of the type XpOqNrCs, wherein X is contained in the elements consisting of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, and wherein p and q are strictly positive numbers, and at least one of r and s is a number greater than or equal to 0.

[0027] This stoichiometry of the layer allows for the production of colored and conductive coatings. The roughness of the layer also contributes to giving it a more or less striking appearance (especially black) and a more or less matte finish.

[0028] In addition, the circuit may have one or more of the following optional features, which are considered independently of each other or in combination with one or more other features:

[0029] The surface layer comprises, by weight, at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium, by weight, at 30% to 65% of nitrogen, by weight, at 15% to 55% of oxygen and at 0% to 6% of carbon.

[0030] It includes a bonding layer located beneath the surface layer, the bonding layer comprising at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium, and scandium; and

[0031] It includes a bonding layer with a thickness between 10 and 1000 nanometers; for example, if the bonding layer mainly comprises titanium, the thickness of the bonding layer is close to 700 nanometers; however, the bonding layer may optionally have a smaller thickness, for example, between 10 and 200 nanometers or even between 10 and 100 nanometers; and the surface layer has a thickness between 100 and 2000 nanometers, for example, between 300 and 400 nanometers. Attached Figure Description

[0032] Other features, objects, and advantages of the invention mentioned above will become apparent upon reading the following detailed description and referring to the accompanying drawings, which are given by way of non-limiting example, and in which:

[0033] Figure 1 A chip card illustrating an example of a module according to the present invention is shown in perspective view;

[0034] Figure 2 Schematic and partial cross-section shown Figure 1 An example portion of the connector for the chip card module shown;

[0035] Figure 3 Schematic illustration for use Figure 1 A top view of a portion of the circuitry of the chip card module connector shown.

[0036] Figure 4 Various steps of several examples of embodiments of the method according to the invention are illustrated schematically.

[0037] Detailed description

[0038] like Figure 1 As shown, in one example of a circuit application according to the invention, the chip card 1 has a module 2 with a connector 3. The module 2 is typically manufactured as a separate element that is inserted into a cavity formed by the body of the chip card 1. This element typically has a flexible dielectric substrate 4 made of materials such as PET, epoxy glass, or polyimide (see...). Figure 2 A connector 3, which is then used to connect an electronic chip (not shown), is fabricated on this component.

[0039] Figure 3 An example of a portion of a circuit 5 having two connectors 3 is shown. Each connector 3 includes a contact area 8 formed by conductive traces 6. In the example shown, eight electrical contacts 7 are formed by conductive traces 6 on one side (single-sided circuit). Optionally, if the connector corresponds to a double-sided circuit, additional traces and / or contacts may be produced on the other side.

[0040] More specifically, such as Figure 2As shown in the figure, connector 3 (i.e., a module that is essentially without electronic chips) has a multilayer structure formed by dielectric substrate 4, adhesive layer 9, conductive material sheet 10, first intermediate layer 11, optional second intermediate layer 12, optional bonding layer 13, and finally surface layer 14.

[0041] The dielectric substrate 4 is formed from an epoxy resin glass strip with a thickness of, for example, 110 micrometers. The conductive material sheet 10 is formed from a copper or copper alloy sheet with a thickness of, for example, 35 micrometers. The first intermediate layer 11 is formed, for example, an electrodeposited nickel layer with a thickness of 1,000 to 7,000 nanometers. The second intermediate layer 12 is formed, for example, an electrodeposited palladium or gold layer with a thickness of 1 to 300 nanometers. More generally, the first and second intermediate layers 11 and 12 are formed by electrodeposition, and may include, for example, at least one metal selected from the list of metals such as palladium, copper, aluminum, iron, gold, and nickel.

[0042] The bonding layer 13 is essentially composed of a metal layer comprising at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium, and scandium. This layer is formed by vapor deposition. The surface layer 14 is primarily composed of an XpOqNrCs type compound, where X is contained in an element composed of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti, and Sc, wherein p and q are strictly positive, and at least one of r and s is a number greater than or equal to zero. This surface layer is also formed by vapor deposition of 30% to 65% by weight of one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium, and scandium, 0% to 40% by weight of nitrogen, 15% to 55% by weight of oxygen, and 0% to 6% by weight of carbon. The bonding layer 13 has a thickness of, for example, between 10 and 1000 nanometers, and the surface layer 14 has a thickness of, for example, between 100 and 1000 nanometers.

[0043] Figure 4 The steps of several examples of an embodiment of the method for manufacturing connector 3 according to the present invention are illustrated schematically. These steps include:

[0044] Step 100: Providing the conductive material sheet 10;

[0045] Step 200 includes:

[0046] A substrate 4 is provided, which is made of, for example, epoxy glass, PET or polyimide.

[0047] A layer of adhesive 9 is applied to one side of substrate 4.

[0048] Perforations are made in the substrate 4 to which the adhesive layer 9 is applied, to form a connection well 15 and an optional cavity through the substrate 4 and the adhesive layer 9, which is then used to house an electronic chip.

[0049] A conductive material sheet 10 is laminated onto a substrate 4 covered with an adhesive layer 9, and at least partially covers the connection well 15 and the cavity, and optionally crosslinks with the adhesive layer 9.

[0050] Photolithography step 300 is used to form conductive traces 6 and / or contacts 7 in the conductive material sheet 10;

[0051] Step 400, which involves depositing a first intermediate layer 11 and an optional second intermediate layer 12 by means of, for example, electrodeposition;

[0052] Step 500: Physical vapor deposition of optional bonding layer 13 and surface layer 14;

[0053] Step 600, laser etching is performed on the area 16 located between the contacts 7 (see...). Figure 3 The steps of bonding layer 13 and surface layer 14 on the substrate are performed to expose the substrate in these regions 16 to disconnect the conductive traces 6 and the contacts 7 from each other. For this step, the laser has a spot diameter of, for example, 12 micrometers to 35 micrometers, a power of 1 watt to 15 watts, and a spacing of 0 micrometers to 60 micrometers between each beam impact;

[0054] One or more steps 700 of transferring chips (e.g., one electronic chip per connector 3) separate the connectors 3, etc., from the circuits 5 obtained at the end of the previous steps, and perform the production of module 2 and / or complete the chip card 1 having such module 2.

[0055] Alternatively, according to another embodiment of the method, it includes steps identical or similar to steps 100 to 500. However, between steps 400 and 500, step 800 is performed, which includes depositing a photosensitive resin film on electrodeposited layers 11 and 12. This resin is exposed to radiation designed to penetrate the mask and then developed to expose the conductive traces 6 and the contacts 7 and to protect the area located between the conductive traces 6 and the contacts 7. Thus, during step 500 of the physical vapor deposition of the optional bonding layers 13 and surface layers 14, these layers are deposited only in the areas intended to conduct electricity (conductive traces 6 and contacts 7). Of course, the resin protecting the area 16 located between the conductive traces 6 and the contacts 7 during step 500 of the physical vapor deposition of the bonding layers 13 and surface layers 14 is subsequently removed during step 900. For example, for this step, the solution used for removal may be acidic or alkaline, the temperature may be between 15 degrees Celsius and 50 degrees Celsius, and the pressure may be between 1 bar and 5 bar.

[0056] Alternatively, according to another embodiment of the method, in step 300B, the conductive material sheet 10 provided in step 100 is cut out to form conductive traces 6 and / or contacts 7 in the conductive sheet. In other words, step 300B makes it possible to manufacture the lead frame. Next, in step 500, an optional bonding layer 13 and a surface layer 14 are generated on the lead frame by physical vapor deposition. Then, step 200B is performed, which includes providing a substrate 4 made of, for example, epoxy glass, PET, or polyimide, applying an adhesive layer 9 to one side of the substrate 4, perforating the substrate 4 with the adhesive layer 9 to form a connection well 15 and an optional cavity through the substrate 4 and the adhesive layer 9, the cavity being used to accommodate an electronic chip, laminating the lead frame onto the substrate 4 coated with the adhesive layer 9, at least partially covering the connection well 15 and the cavity, and optionally crosslinking it with the adhesive layer 9. The resulting structure can then undergo one or more of the steps 700 described above. In this case, step 600 is not necessary, because as in the first embodiment described above, the optional bonding layer 13 and surface layer 14 are deposited only on the lead frame and not on the substrate 4. The lead frame can initially be cut by a punch / die piercing tool so that the conductive traces 6 and the contacts 7 are properly isolated from each other.

[0057] According to another embodiment of the method, steps 100 to 400 described above are performed. In parallel, step 500C1 is performed. Step 500C1 involves, for example, physical vapor deposition of a bonding layer 13 on a support made of PET on one hand, and physical vapor deposition of a surface layer 14 on the support made of PET on the other hand. Next, a selective laser transfer step 500C2 is performed, transferring the selective bonding layer 13 on the PET carrier, and then the surface layer 14 on the PET carrier, to the area intended to be covered by the conductive layer 14, that is, to the conductive traces 6 and the contacts 7. For this step 500C2, the laser has a spot diameter of 12 to 35 micrometers, a power of 1 to 15 watts, and a spacing between two beam impacts of 0 to 60 micrometers. One or more steps 700 as described above can then be performed to manufacture the manufacturing module 2 and / or complete a chip card 1 having such a module 2.

[0058] The physical vapor deposition of surface layer 14 is performed using a magnetron sputtering apparatus employing, for example, direct current, pulsed direct current, or radio frequency current, with a power of 100 watts to 700,000 watts and a current density of 10 amperes to 200 amperes per square meter. The deposition occurs on surfaces with a current density of 1 to 10⁻¹⁰. -3 It takes place in a vacuum with residual pressure between millibars.

[0059] Alternatively, this physical vapor deposition of the surface layer 14 can also be performed using thermal evaporation or cathodic arc physical vapor deposition (CAPVD) techniques.

[0060] Physical vapor deposition of surface layer 14 uses argon as the working gas at a flow rate of 100 to 600 standard cubic centimeters per minute (SCCM), with 10 to 150 standard cubic centimeters of nitrogen, 1 to 100 standard cubic centimeters of oxygen, and 1 to 20 standard cubic centimeters of acetylene per minute (if carbon deposition mode uses gases, this involves the deposition of surface layer 14 to obtain, for example, black or near-black color - acetylene is not always necessary for other colors).

[0061] The physical vapor deposition of the surface layer 14, whether performed directly on the conductive traces 6 and contacts 7, or on the support before transfer to the conductive traces 6 and contacts 7, can also be performed using reactive physical vapor deposition with an argon gas flow rate of 40 to 70 standard cubic centimeters per minute. To obtain a black or near-black surface layer 14, carbon can be added either by sputtering a graphite target at an argon gas flow rate of 100 to 600 standard cubic centimeters per minute, or by using an acetylene gas plasma at a flow rate of 1 to 20 standard cubic centimeters per minute. Furthermore, during this sputtering process, the plasma is formed from a gas mixture of nitrogen and oxygen.

[0062] The conductive trace 6 or the contact 7 and its surface layer 14, all of these embodiments advantageously have a contact resistance of less than 500 milliohms and are highly resistant to salt spray corrosion tests, such as those required for chip cards used in banking applications.

[0063] According to an alternative embodiment of the above method, colored patterns, such as logos (by means of a surface layer and an optional adhesive layer), can be generated on a yellow background (gold underlayer) or a gray background (palladium, silver, or nickel underlayer) by using a photosensitive resin mask. Such patterns can be generated for the purpose of graphic personalization or protection against copying.

[0064] Example:

[0065] Example 1: Black Deposition

[0066] The surface layer 14 of XpOqNrCs was deposited by reactive physical vapor deposition (see above). This deposition was performed using a sputtering apparatus with a power of, for example, 4 kW. The deposition was carried out on a titanium bonding layer 13 of approximately 700 nm (which itself sits on a copper substrate coated with nickel and gold). The surface layer 14 is approximately 300 to 400 nm in size. The deposition of the surface layer 14 was performed using argon as the working gas and in an environment containing dinitrogen, dioxygen, and carbon. The deposition was carried out in an environment with a temperature close to 10... -2 The process is carried out in a vacuum with a residual pressure of millibar.

[0067] Measurements performed by energy-dispersive X-ray spectroscopy (EDX) could not distinguish the composition of the surface layer from that of the bonding layer 13, yielding the following respective weight concentrations: titanium: 61.8%; oxygen: 17.5%; nitrogen: 16.7%; carbon: 4.0%.

[0068] According to standard ISO 9227, the contact resistance obtained before and after the 24-hour salt spray test is less than 500 milliohms.

[0069] The surface layer 14 obtained by this embodiment has a colorimetric index L* of less than 40 in the CIELAB color space introduced by the IEC (International Commission on Illumination). Similarly, the indices a* and b* in this color space are close to zero and less than 5 in absolute value.

[0070] Example 2: Green or blue sediment

[0071] The surface layer 14 of XpOqNrCs was deposited by PVD (physical vapor deposition). This deposition was performed, for example, using a 20 kW sputtering apparatus (magnetron type). This deposition was carried out without a titanium bonding layer 13. Therefore, the surface layer 14 is directly located on a copper substrate covered with nickel and then gold. The surface layer 14 has a thickness of approximately 50 to 100 nanometers. The deposition of the surface layer 14 was performed using argon as the working gas in the presence of dinitrogen and dioxygen. The deposition was carried out at a temperature close to 4.10 nm. -3 The process is carried out in a vacuum with a residual pressure of millibars (mbar).

[0072] Measurements performed using energy-dispersive spectroscopy yielded the following respective weight concentrations:

[0073] a) Green: Titanium: 62%; Oxygen: 38%; Nitrogen: present in trace amounts.

[0074] b) Blue: Titanium: 51%; Oxygen: 49%; Nitrogen: present in trace amounts.

[0075] In all these cases, the obtained contact resistance is less than 500 milliohms.

Claims

1. Circuits with electrical contacts, particularly used in the production of chip card modules, including: A dielectric substrate (4) having a conductive material sheet (10) disposed on the dielectric substrate (4), At least one layer of conductive material (14) is disposed directly or indirectly on the conductive material sheet (10), the conductive material layer (14) forming a surface layer covering at least one region of the surface of at least one conductive trace (6), the conductive trace (6) being formed in the conductive material sheet (10) and configured to form an electrical contact. The surface layer (14) is characterized in that it comprises an XpOqNrCs type compound, wherein X is contained in the elements consisting of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, wherein p and q are strictly positive numbers, and at least one of r and s is a number greater than or equal to zero.

2. The circuit according to claim 1, wherein the surface layer (14) comprises 30% to 65% by weight of at least one metal included in the list consisting of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti or Sc, 0% to 40% by weight of nitrogen, 15% to 55% by weight of oxygen and 0% to 6% by weight of carbon.

3. The circuit according to claim 1 or 2, comprising a bonding layer (13) located below the surface layer (14), the bonding layer (13) comprising at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium.

4. The circuit according to claim 3, comprising a bonding layer (13) and a surface layer (14), wherein the thickness of the bonding layer (13) is between 10 and 1000 nanometers; and the thickness of the surface layer (14) is between 100 and 2000 nanometers.

5. The circuit according to any one of claims 1 to 4, wherein X = Ti.

6. A chip card, comprising a card body and a module (2), the module (2) being inserted into a cavity formed in the card body, the module (2) comprising a connector (3), the connector (3) comprising a circuit according to any one of the preceding claims.

7. A manufacturing method specifically designed for manufacturing the circuit according to any one of claims 1 to 5, the method comprising the following steps: A dielectric substrate (4) is provided, and a conductive material sheet (10) is disposed on the dielectric substrate (4). At least one layer of conductive material (14) is deposited on a conductive material sheet (10), the conductive material (14) forming a surface layer (14) covering at least one region of the surface of at least one conductive trace (6), the conductive trace (6) being formed in the conductive material sheet (10) and configured to form an electrical contact. The surface layer (14) is characterized in that the formation of the surface layer (14) includes a physical vapor deposition step originating from at least one metal target, wherein the composition of the metal target involves at least one metal selected from the following elements: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium, and in an atmosphere of a gas including at least one of the following elements: argon, nitrogen and oxygen.

8. The method according to claim 7, wherein, The surface layer (14) comprises a compound of the type XpOqNrCs, wherein X is contained in the elements consisting of Hf, Ta, Zr, Nb, Mo, Cr, V, Ti and Sc, and wherein p and q are strictly positive numbers, and at least one of r and s is a number greater than or equal to zero.

9. The method according to claim 7 or 8, wherein, The surface layer (14) is deposited on the bonding layer (13), which itself is formed by physical vapor deposition in an atmosphere containing argon working gas, wherein at least one metal target is used, the composition of which contains at least one of the following metals: chromium, hafnium, tantalum, zirconium, niobium, molybdenum, vanadium, titanium and scandium.

10. The method of claim 9, further comprising the step of laser etching the surface layer (14) and the bonding layer (13) located between at least two of the conductive traces (6) to disconnect the conductive traces (6).

11. The method according to claim 9, wherein during the step prior to transferring the lead frame to the dielectric substrate (4), the bonding layer (13) and the surface layer (14) are deposited on the lead frame formed in the conductive material sheet (10).

12. The method according to any one of claims 7 to 9, wherein the surface layer (14) is selectively deposited in at least one region of the surface of at least one of the conductive traces (6), wherein the surface layer (14) pre-deposited on the support is transferred to the conductive material sheet (10) by means of a laser.

13. The method according to any one of claims 7 to 12, comprising the step (800) of fabricating a mask prior to forming the surface layer (14) to selectively deposit the surface layer (14) only in certain areas of the conductive material sheet (10).

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