Semiconductor package, semiconductor device, and method for manufacturing semiconductor package

Abstract

The present invention miniaturizes a WLCSP while improving test efficiency during manufacture of the WLCSP.　This semiconductor package is provided with a semiconductor substrate, a pixel region, a guard ring, and redistribution wiring. In the semiconductor package, the pixel region is formed on a front surface of the semiconductor substrate. The guard ring is formed around the pixel region. The redistribution wiring is wired on a rear surface of the semiconductor substrate with respect to the front surface. A terminal part of the redistribution wiring is positioned outside the guard ring.

Description

Semiconductor Package, Semiconductor Device, and Method of Manufacturing Semiconductor Package

[0001] This technology relates to a semiconductor package. More specifically, it relates to a semiconductor package with a chip size, a semiconductor device, and a method of manufacturing a semiconductor package.

[0002] Conventionally, because high-density mounting is possible, WLCSPs (Wafer Level-Chip Size Packages) that perform rewiring and electrode formation by a wafer-level process have been used. For example, a method of manufacturing a WLCSP that forms pads and solder bumps on the back surface where rewiring is performed has been proposed (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2010-192867

[0004] In the above conventional technology, by forming pads on a wafer, it is intended to perform tests on a plurality of WLCSPs collectively at the wafer level. However, in the above manufacturing method, since the pads are on the back surface, when forming a WLCSP including an image sensor, it is not possible to perform tests collectively in a state where light is incident on the surface with respect to the back surface. If pads are added to the surface of the WLCSP, tests can be performed collectively even in that state, but the area of the WLCSP increases by the area of the pads. Thus, in the above manufacturing method, it is difficult to miniaturize the WLCSP while improving test efficiency.

[0005] This technology was created in view of such a situation, and an object thereof is to miniaturize a WLCSP while improving test efficiency during manufacturing in a WLCSP.

[0006] This technology was made to solve the above problems, and a first aspect thereof is a semiconductor package including a semiconductor substrate, a pixel region formed on the surface of the semiconductor substrate, a guard ring formed around the pixel region, and a rewiring wired on the back surface of the semiconductor substrate with respect to the surface and having a terminal portion located outside the guard ring. This brings about an effect that test efficiency during manufacturing is improved and the semiconductor package becomes small.

[0007] Furthermore, in this first aspect, the surface of the semiconductor substrate may correspond to the surface of the semiconductor package. This has the effect of enabling miniaturization of WLCSPs including image sensors that do not have a light-transmitting substrate.

[0008] Furthermore, in this first aspect, an insulating film covering at least a portion of the side surface of the semiconductor substrate may be further provided. This has the effect of improving reliability.

[0009] Furthermore, in this first aspect, the semiconductor substrate may further include through vias formed on the back surface along the outer periphery, and the rewiring may include a first rewiring routed to the lead-out routing portion from the through via to the end portion and a second rewiring routed to a location not corresponding to the lead-out routing portion. This results in the rewiring being routed to the test pad during the wafer-level process.

[0010] Furthermore, in this first aspect, at least a portion of the first rewiring may be thinner than the second rewiring. This has the effect of reducing the parasitic capacitance of the lead-out wiring section.

[0011] Furthermore, in this first aspect, the semiconductor substrate is further provided with a solder mask covering the back surface and first and second insulating layers, wherein the first rewiring is formed between the first insulating layer and the solder mask, and the second rewiring is formed between the second insulating layer and the solder mask, and at least a portion of the first insulating layer may be thicker than the second insulating layer. This has the effect of reducing parasitic capacitance in the lead-out wiring portion.

[0012] Furthermore, in this first aspect, the first rewiring may be further provided with a fuse circuit inserted into it. This reduces the parasitic capacitance of the lead-out wiring section.

[0013] Furthermore, in this first aspect, a predetermined number of test pads may be provided, the pixel region may be rectangular when viewed from a direction perpendicular to the semiconductor substrate, and the test pads may be arranged along at least a portion of the four sides of the pixel region. This provides the effect of enabling testing after dicing.

[0014] Furthermore, in this first aspect, the semiconductor substrate may be a laminated substrate formed by stacking multiple semiconductor substrates. This results in a reduction in the circuit size and area per substrate.

[0015] Furthermore, in this first aspect, the shape of at least a portion of the edge face of the semiconductor substrate, when viewed from a direction perpendicular to the surface of the semiconductor substrate, may be tapered. This has the effect of suppressing chipping and flare during transport.

[0016] Furthermore, the first side surface may be further provided with a low-temperature oxide film that covers the tapered portion of the end face. This provides protection for the tapered portion.

[0017] Furthermore, in this first aspect, the tapered shape may be formed along the crystal orientation of the semiconductor substrate material. This results in the tapered shape being obtained by anisotropic wet etching.

[0018] Furthermore, in this first aspect, the tapered shape may be formed along an orientation different from the crystal orientation of the semiconductor substrate material. This results in the tapered shape being obtained by blade dicing.

[0019] Furthermore, the first side surface may be further provided with resin filled in the tapered portion of the end face. This provides the effect of mitigating impact.

[0020] Furthermore, a second aspect of this technology is a semiconductor device comprising a semiconductor substrate, a pixel region formed on the surface of the semiconductor substrate, a guard ring formed around the pixel region, a rewiring that is wired on the back surface of the semiconductor substrate with its ends located outside the guard ring, and a mounting substrate to which the semiconductor package is connected. This improves the testing efficiency during manufacturing and results in a smaller semiconductor device.

[0021] Furthermore, in this second aspect, the semiconductor substrate may be further provided with an underfill covering the back surface and sides. This has the effect of improving reliability.

[0022] Furthermore, in this second aspect, the semiconductor substrate may further comprise a first underfill covering the back surface and a second underfill covering the side surface of the semiconductor substrate, and the materials of the first and second underfills may be different. This results in improved reliability.

[0023] Furthermore, a third aspect of this technology is a semiconductor package manufacturing method comprising a wafer manufacturing procedure for creating a wafer in which test pads are placed in the scribe region of the chip region and the scribe region; a test procedure for testing the devices in the chip region using the test pads; and a dicing procedure for cutting the wafer along the scribe region. This results in improved testing efficiency during manufacturing and the ability to obtain a smaller semiconductor package.

[0024] Furthermore, in this third aspect, the process may further include a tapering procedure for at least a portion of the end face of the semiconductor package cut from the wafer by the dicing procedure described above. This results in the creation of a tapered shape.

[0025] Furthermore, in this third aspect, the shape of the side surface of the test pad, when viewed from a predetermined direction parallel to the surface of the wafer, is tapered, and the chip region may include a part of the side surface of the test pad. This results in a simplification of the manufacturing method.

[0026] This is a diagram illustrating the manufacturing method up to laser dicing in the first embodiment of this technology. This is a diagram illustrating blade dicing in the first embodiment of this technology. This is a flowchart illustrating an example of a manufacturing method for WLCSP in the first embodiment of this technology. This is an example of a top view of a wafer in the first embodiment of this technology. This is an example of a bottom view of a wafer in the first embodiment of this technology. This is an example of a cross-sectional view of a wafer in the first embodiment of this technology. These are examples of top and bottom views of a WLCSP in the first embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in the first embodiment of this technology. This is an example of a cross-sectional view of a semiconductor device in the first embodiment of this technology. This is a diagram illustrating an example of a manufacturing method after dicing in the first modified example of the first embodiment of this technology. This is a diagram illustrating another example of a manufacturing method after dicing in the first modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in the first modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a semiconductor device in the second modified example of the first embodiment of this technology. This is an example of a bottom view of a WLCSP in the third modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a wafer in a third modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in a third modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in a fourth modified example of the first embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in a fifth modified example of the first embodiment of this technology. This is an example of a top view and cross-sectional view of a WLCSP in a sixth modified example of the first embodiment of this technology. This is an example of an enlarged view of the cross section of a WLCSP in a seventh modified example of the first embodiment of this technology. This is an example of a top view and cross-sectional view of a WLCSP in a second embodiment of this technology. This is a diagram illustrating an example of a tapering method in the second embodiment of this technology. This is a diagram illustrating another example of a tapering method in the second embodiment of this technology. This is a diagram illustrating a transport method in a second comparative example and the first embodiment. This is a diagram illustrating a transport method in a second embodiment of this technology. This is a cross-sectional view showing an example of a taper angle in the second embodiment of this technology.This is a diagram illustrating an example of dicing in the first modification of the second embodiment of this technology. This is a diagram illustrating another example of a tapering method in the second modification of the second embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in the second modification of the second embodiment of this technology. This is an example of a cross-sectional view of a WLCSP in the third modification of the second embodiment of this technology. This is an example of a top view and cross-sectional view of a WLCSP in the fourth modification of the second embodiment of this technology. This is an example of a cross-sectional view and perspective view of a collet in the fourth modification of the second embodiment of this technology. This is a diagram illustrating an example of a manufacturing method in the fifth modification of the second embodiment of this technology. This is a diagram illustrating an example of a manufacturing method using a high-viscosity resin in the fifth modification of the second embodiment of this technology. This is a diagram illustrating another example of a manufacturing method using a high-viscosity resin in the fifth modification of the second embodiment of this technology. This is an example of a plan view and perspective view of a squeegee mask in the fifth modification of the second embodiment of this technology. This is a block diagram illustrating an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit.

[0027] The following describes the embodiments for implementing this technology (hereinafter referred to as "embodiments"). The description will proceed in the following order: 1. First embodiment (example of placing test pads in the scribe area) 2. Second embodiment (example of placing test pads in the scribe area and tapering the edge of the semiconductor substrate) 3. Application example to a mobile device

[0028] <1. First Embodiment> [Method for Manufacturing WLCSP] The method for manufacturing WLCSP in the first embodiment will be described with reference to Figures 1 and 2.

[0029] First, a wafer 100 is created as illustrated in Figure 1a. Pixel regions 111 are formed on one of the two sides of the wafer 100, and this light-receiving side will hereafter be referred to as the "top surface" or "front surface." When viewed from above, the wafer 100 is divided into multiple chip regions and scribe regions for separating these chip regions. The pixel regions 111 are then arranged for each chip region. Each chip region becomes a WLCSP through dicing, which will be described later. Various devices that function as image sensors are arranged in each WLCSP, for example.

[0030] Furthermore, below, a predetermined axis parallel to the surface of the wafer 100 will be referred to as the "X-axis," and an axis perpendicular to that surface will be referred to as the "Z-axis." An axis perpendicular to the X-axis and Z-axis will be referred to as the "Y-axis."

[0031] In the figure, a, b, and c show cross-sectional views of the wafer 100 as seen from the Y-axis direction. In the figure, coordinates X1 to X4 on the X-axis in a correspond to the chip region, and coordinates X4 to X5 correspond to the scribe region. Coordinates X2 to X3 correspond to the pixel region 111. A predetermined number of test pads 121 are formed in the scribe region.

[0032] Next, as illustrated in figure b, the probes 310 are in contact with each of the test pads 121, and with light incident on the surface, multiple WLCSPs are tested simultaneously.

[0033] Next, as illustrated in figure c, the laser is focused onto the scribe area and laser dicing is performed.

[0034] Next, as illustrated in Figure 2, the wafer 100 is cut along the scribe region by the blade 320, and the wafer 100 is separated into multiple semiconductor chips. Each semiconductor chip is used as a WLCSP 110. In the figure, the blade 320 is inserted on the front side of the wafer 100, but it can also be inserted on the back side.

[0035] Figure 3 is a flowchart showing an example of a manufacturing method for WLCSP110 in the first embodiment of this technology. A wafer 100 with test pads 121 placed in the scribe area is created (step S901). Next, the device in the chip area is tested using the test pads 121 (step S902). Then, for example, the wafer 100 is cut along the scribe area by laser dicing, followed by blade dicing (step S903). Note that the flowchart is just an example, and dicing may be either laser dicing or blade dicing, or laser dicing may be performed after blade dicing.

[0036] Here, as a first comparative example, we assume a configuration in which a test pad 121 is provided on the back surface of the wafer 100, as described in Patent Document 1. In this first comparative example, since there is no test pad 121 on the surface, it is not possible to test multiple WLCSPs at once with light incident on the surface, as illustrated in Figure 1b. If a test pad 121 is added to the surface side of the chip area, it is possible to perform simultaneous testing in that state as well, but the area of ​​the WLCSP will increase by the amount of the added test pad 121.

[0037] In contrast, in the first embodiment, since the test pads 121 are placed on the surface of the wafer 100, tests can be performed all at once while light is incident on the surface. This improves test efficiency.

[0038] Furthermore, since the test pads 121 are located in the scribe area, the area of ​​the WLCSP 110 can be reduced and miniaturized compared to the case where the test pads 121 are located in the chip area.

[0039] WLCSP110 is an example of a semiconductor package described in the claims.

[0040] [Example of wafer configuration] Next, the details of wafer 100 will be described with reference to Figures 4 to 6.

[0041] Figure 4 is an example of a top view of the wafer 100 in the first embodiment of the present technology. As illustrated in the figure, the wafer 100 is divided into a plurality of rectangular chip regions and scribe regions for separating them. For example, the rectangular region surrounded by the XY coordinates (X1, Y1), (X1, Y4), (X4, Y1), and (X4, Y4) in the figure corresponds to the chip region. A pixel region 111 is provided within the chip region, and a plurality of pixels (not shown) are arranged.

[0042] Each of the chip regions is divided by a linear scribe region. A predetermined number of test pads 121 are arranged within this scribe region. For example, the test pads 121 are arranged along each of the four sides of the chip region.

[0043] Figure 5 is an example of a bottom view of the wafer 100 in the first embodiment of the present technology. On the bottom surface (in other words, the back surface) of the wafer 100, a plurality of back pads 112 are arranged in the chip region. These pads are used for connection to a mounting substrate (not shown). Instead of the back pads 112, solder balls may be formed.

[0044] Also, as described above, the test pads 121 are arranged on the surface of the scribe region. On the back surface, through vias 122 are arranged directly below the test pads 121. The region surrounded by the dashed-dotted line in the figure indicates the region directly below the test pads 121.

[0045] In the chip region, through vias 113 are arranged in addition to the back pads 112. These through vias 113 are connected to the through vias 122 in the scribe region by redistribution lines 114. Also, the through vias 113 are connected to the back pads 112 by the redistribution lines 114. These redistribution lines 114 are wired in the RDL (ReDistribution Layer) layer 133.

[0046] Figure 6 is an example of a cross-sectional view of the wafer 100 in the first embodiment of the present technology. This figure shows a cross-sectional view when the wafer 100 is cut along the line segment A - A' in FIGS. 4 and 5.

[0047] A test pad 121 is placed in the scribe region on the surface of the semiconductor substrate 130 (such as a silicon substrate) that constitutes the wafer 100. On the back surface of the semiconductor substrate 130, a through via 122 is formed directly beneath the test pad 121.

[0048] Pixel regions 111 are formed in the chip region of the surface of the semiconductor substrate 130. A predetermined number of back-side pads 112 and a predetermined number of through-vias 113 are arranged in the chip region of the back surface of the semiconductor substrate 130. In addition, rewiring 114 is routed on the back surface of the semiconductor substrate 130, and this rewiring 114 connects the through-vias 113 and 122 to the back-side pads 112.

[0049] In the configuration illustrated in the figure, the test pad 121 is electrically connected to various devices within the chip area via through-vias 122, rerouting 114, and through-vias 113. The back pad 112 is also electrically connected to devices within the chip area via rerouting 114 and through-vias 113.

[0050] [Example of WLCSP Configuration] Next, the details of the WLCSP 110 will be described with reference to Figures 7 and 8.

[0051] Figure 7 shows an example of a top view and a bottom view of the WLCSP110 in the first embodiment of the present technology. In the figure, a is an example of a top view of the WLCSP110, and b is an example of a bottom view of the WLCSP110.

[0052] As illustrated in figure a, a pixel region 111 is formed on the upper surface (front surface) of the WLCSP 110.

[0053] As illustrated in figure b, an RDL layer 133 is formed on the lower surface (back surface) of the WLCSP 110. A predetermined number of back surface pads 112 and a predetermined number of through vias 113 are arranged on the RDL layer 133, and these are connected by rewiring 114. The arrangement on the lower surface of the WLCSP 110 is called LGA (Land Grid Array), but it is not limited to this configuration and may also be BGA (Ball Grid Array).

[0054] Figure 8 is an example of a cross-sectional view of the WLCSP 110 in the first embodiment of this technology. The figure shows a cross-sectional view obtained when the WLCSP 110 is cut along the line segments A-A' in Figure 7.

[0055] The semiconductor substrate 130 constituting the WLCSP110 has a laminated structure in which a light-receiving substrate 130-1 and a circuit board 130-2 are stacked. These substrates are connected by a Cu-Cu connector 115. Pixels and the like are arranged on the light-receiving substrate 130-1, and various devices such as an ADC (Analog to Digital Converter) are arranged on the circuit board 130-2.

[0056] Furthermore, the WLCSP110 has a glassless structure in which no glass is mounted on top of the semiconductor substrate 130. Therefore, the surface of the semiconductor substrate 130 becomes the surface of the WLCSP110.

[0057] Furthermore, a pixel region 111 is formed on the surface of the semiconductor substrate 130. In addition, a device layer 131 is formed on top of the semiconductor substrate 130. This device layer 131 includes various devices that function as an image sensor and a predetermined number of guard rings 116. These guard rings 116 are formed around the pixel region 111 when viewed from the Z-axis direction.

[0058] Furthermore, an RDL layer 133 with rewiring 114 is formed on the back surface of the semiconductor substrate 130. In the figure, for example, the right side of coordinate X31 corresponds to the rewiring 114, and the left side corresponds to the back surface pad 112.

[0059] Furthermore, the RDL layer 133 is covered with a solder mask 134, and an insulating layer 132 is formed on the upper surface of the RDL layer 133. For example, a silicon oxynitride (SiON) film is used as the insulating layer 132.

[0060] Furthermore, the end of the rewiring 114 is located outside the guard ring 116. In the figure, coordinate X32 is the X coordinate of the outer circumference of the guard ring 116, and coordinate X4 is the X coordinate of the end of the rewiring 114.

[0061] As mentioned above, in the wafer-level process, a test pad 121 (not shown) was placed in the scribe region, and a rewiring 114 was connected to that pad. However, during dicing, the scribe region was cut, causing the rewiring 114 to be interrupted outside the guard ring 116, with that point becoming the end of the wire.

[0062] Although the semiconductor substrate 130 is shown as having a two-layer stacked structure, the semiconductor substrate 130 may be a single-layer substrate instead of a two-layer substrate.

[0063] Figure 9 is an example of a cross-sectional view of a semiconductor device 200 in the first embodiment of this technology. The WLCSP 110 is mounted on a mounting substrate 210. The device including these is referred to as the semiconductor device 200.

[0064] During mounting, the lands 211 of the mounting substrate 210 are connected to the back pads 112 of the WLCSP 110 by solder 212. Then, underfill 213 is filled between the back surface of the semiconductor substrate 130 of the WLCSP 110 and the mounting substrate 210. The main components of the underfill 213 include epoxy resin, urethane resin, and fused silica.

[0065] In this figure, the back surface of the semiconductor substrate 130 is covered with underfill 213, but its sides are not covered.

[0066] Thus, in the first embodiment of this technology, the test pad 121 is placed in the scribe region on the surface of the wafer 100, thereby improving the efficiency of the test. Furthermore, the WLCSP 110 can be miniaturized compared to the case where the test pad 121 is placed in the chip region. In addition, by dicing the wafer 100, a WLCSP 110 is manufactured in which the end portion of the redistribution 114 is located outside the guard ring.

[0067] [First Modification] In the first embodiment described above, the substrate and rewiring 114 were exposed on the side surface of the semiconductor substrate 130, but it is preferable to cover them with an insulating film to prevent corrosion. The WLCSP 110 in this first modification of the first embodiment differs from the first embodiment in that the side surface of the semiconductor substrate 130 is covered with an insulating film.

[0068] Figure 10 shows an example of a manufacturing method after dicing in a first modification of the first embodiment of the present technology. As illustrated in figure a, after blade dicing is performed, as illustrated in figure b, the side surface of the semiconductor substrate 130 is covered with an insulating film 117. This prevents corrosion of rewiring 114 and other components and improves the reliability after individual piece formation.

[0069] Furthermore, after performing blade dicing as illustrated in Figure 11a, the scribed region can be filled with insulating material that will become the insulating film 117, as illustrated in Figure 11b. In this case, as illustrated in Figure 11c, blade dicing is further performed with a blade 320-1 that is thinner than blade 320, so that some insulating material remains on the side surface. This forms the insulating film 117, as illustrated in Figure 11d.

[0070] Furthermore, although the insulating film 117 covers the entire side surface in Figures 10 and 11, the configuration is not limited to this.

[0071] As illustrated in Figure 12, the insulating film 117 can also cover only a portion of the side surface, including the end portion of the rewiring 114.

[0072] Furthermore, the insulating film 117 can be made from materials such as silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride (SiCN), or silicon dioxide (SiO2). ２ Examples include silicon oxynitride (SiON).

[0073] In addition to these, BTA (Benzotriazole) such as 1,2,3-benzotriazole can also be applied to the sides. When the material of the rewiring 114 is copper (Cu), a Cu-BTA complex is formed according to the following formula, ensuring insulation and becoming an insulating film 117.

[0074]

[0075] As described above, according to the first modification of the first embodiment of this technology, at least a portion of the side surface of the semiconductor substrate 130 is covered with an insulating film 117, thereby preventing corrosion of rewiring 114 and other components and improving reliability.

[0076] [Second Modification] In the first embodiment described above, underfill 213 was filled between the back surface of the semiconductor substrate 130 and the mounting substrate 210 during mounting. It is preferable that the underfill 213 also covers the sides of the semiconductor substrate 130. The semiconductor device 200 in this second modification of the first embodiment differs from the first embodiment in that the underfill 213 also covers the sides of the semiconductor substrate 130.

[0077] Figure 13 is an example of a cross-sectional view of a semiconductor device 200 in a second modification of the first embodiment of the present technology.

[0078] As illustrated in figure a, the semiconductor device 200 of the second modification of the first embodiment of this technology differs from the first embodiment in that, when the underfill 213 is filled, the side surface of the semiconductor substrate 130 is covered by the underfill 213. This prevents corrosion and improves reliability.

[0079] Furthermore, as illustrated in figure b, the sides of the semiconductor substrate 130 can also be covered with an underfill 214 made of a different material than the underfill 213 that covers the back surface of the semiconductor substrate 130.

[0080] In this case, the underfill 214 preferably has light-shielding properties from the viewpoint of suppressing flare. When shielding from the visible region, carbon black, titanium black, etc., are used as the material for the underfill 214. When shielding from the infrared region, lanthanum hexaboride (LaB6) or tungsten cesium oxide (CWO), etc., are used as the material for the underfill 214.

[0081] Underfill 213 is an example of the first underfill described in the claims, and underfill 214 is an example of the second underfill described in the claims.

[0082] Thus, according to the second modification of the first embodiment of this technology, the sides of the semiconductor substrate 130 are covered with underfill 213 and 214, thereby preventing corrosion, improving reliability, and suppressing flare.

[0083] [Third Modification] In the first embodiment described above, rewiring 114 was formed on the back surface of the WLCSP 110. However, it is preferable to reduce the parasitic capacitance of the lead-out wiring portion of this rewiring 114, which was led out to the test pad 121. The WLCSP 110 in this third modification of the first embodiment differs from the first embodiment in that the rewiring of the lead-out wiring portion is made thinner.

[0084] Figure 14 is an example of a bottom view of the WLCSP 110 in a third modified example of the first embodiment of the present technology. In the figure, the portion from the through via 113 formed along the outer circumference to the end of the rewiring 114 corresponds to the aforementioned lead-out wiring portion. The portion of the rewiring 114 formed in the lead-out wiring portion is designated as rewiring 114-1. The portion of the rewiring 114 formed in a location that does not correspond to the lead-out wiring portion is designated as rewiring 114-2.

[0085] In the figure, the color of rewiring 114-1 is lighter than that of rewiring 114-2, but this is to clearly indicate the location of the lead-out wiring, and the materials are the same. However, when viewed from a direction parallel to the surface of the semiconductor substrate 130 (X-axis direction or Y-axis direction), rewiring 114-1 is thinner than rewiring 114-2.

[0086] Rewiring 114-1 is an example of the first rewiring described in the claims, and rewiring 114-2 is an example of the second rewiring described in the claims.

[0087] Figure 15 is an example of a cross-sectional view of wafer 100 in a third modification of the first embodiment of the present technology. In wafer 100, the portion from through vias (not shown) near the outer edge of the chip region to through vias 122 in the scribe region corresponds to the lead-out wiring portion. Viewed from the Y-axis direction, the rerouting 114-1 of the lead-out wiring portion is thinner than the other reroutings 114-2. That is, the size (in other words, thickness) of the rerouting 114-1 in the Z-axis direction is dZ. １ dZ is the size of the rewiring 114-2 in the Z-axis direction. ２ It is smaller than that.

[0088] Figure 16 is an example of a cross-sectional view of WLCSP110 in a third modified example of the first embodiment of the present technology. As illustrated in figure a, when viewed from the Y-axis direction, the rewiring 114-1 of the lead wiring section is thinner than the other rewiring 114-2.

[0089] Furthermore, as illustrated in figure b, the portion of the rewiring 114-1 from a predetermined position in the lead-out wiring section to the end may be thinner than the rest of the wiring. In this case, a step will be created at the point where the thickness changes.

[0090] As illustrated in figures a and b, by making at least a portion of the rewiring 114-1 of the lead-out wiring section thinner than the rewiring 114-2, the parasitic capacitance of the lead-out wiring section can be reduced.

[0091] Furthermore, the first and second modifications of the first embodiment can also be applied to the third modification of the first embodiment.

[0092] Thus, according to the third modification of the first embodiment of this technology, at least a portion of the rewiring 114-1 of the lead-out wiring section is thinner than the other rewiring 114-2, making it possible to reduce the parasitic capacitance of the lead-out wiring section.

[0093] [Fourth Modification] In the first embodiment described above, an insulating layer 132 was formed on the upper surface of the rewiring 114, but it is preferable to reduce the parasitic capacitance of the lead-out wiring portion. The WLCSP 110 in this fourth modification of the first embodiment differs from the first embodiment in that the insulating layer of the lead-out wiring portion is made thicker.

[0094] Figure 17 is an example of a cross-sectional view of the WLCSP110 in a fourth modified example of the first embodiment of the present technology.

[0095] As illustrated in Figure a, the insulating layer 132 formed on the lead wiring portion is designated as insulating layer 132-1, and the rest is designated as insulating layer 132-2. The rewiring 114-1 on the lead wiring portion is formed between insulating layer 132-1 and the solder mask 134, while the other rewiring 114-2 is formed between insulating layer 132-2 and the solder mask 134.

[0096] In the fourth modification, the thickness of the rewirings 114-1 and 114-2 is assumed to be the same. On the other hand, the insulating layer 132-1 of the lead-out wiring section is thicker than the insulating layer 132-2. That is, the size (in other words, thickness) of the insulating layer 132-1 in the Z-axis direction is dZ. ３ dZ is the size of the insulating layer 132-2 in the Z-axis direction. ４ Larger.

[0097] Furthermore, as illustrated in figure b, the portion of the insulating layer 132-1 from a predetermined position in the lead wiring section to the end portion may be thicker than the rest of the layer. In this case, a step will be created at the position where the thickness changes.

[0098] As illustrated in figures a and b, by making at least a portion of the insulating layer 132-1 of the lead wiring section thicker than the insulating layer 132-2, the parasitic capacitance of the lead wiring section can be reduced.

[0099] Note that insulating layer 132-1 is an example of the first insulating layer described in the claims, and insulating layer 132-2 is an example of the second insulating layer described in the claims.

[0100] Furthermore, the first, second, and third modifications of the first embodiment can be applied to the fourth modification of the first embodiment.

[0101] Thus, according to the fourth modification of the first embodiment of this technology, at least a portion of the insulating layer 132-1 of the lead wiring portion is thicker than the insulating layer 132-2, which reduces the parasitic capacitance of the lead wiring portion.

[0102] [Fifth Modification] In the first embodiment described above, rewiring 114 was formed on the back surface of the WLCSP 110, but it is preferable to reduce the parasitic capacitance of the lead-out wiring portion. The WLCSP 110 in this fifth modification of the first embodiment differs from the first embodiment in that a part of the rewiring 114 is disconnected by a fuse circuit.

[0103] Figure 18 is an example of a cross-sectional view of the WLCSP 110 in a fifth modification of the first embodiment of the present technology. The WLCSP 110 in this fifth modification of the first embodiment differs from the first embodiment in that a fuse circuit 135 is inserted into the rewiring 114-1 of the lead-out wiring section. The position of this fuse circuit 135 is preferably inside the guard ring 116. In the fifth modification, the thickness of the rewirings 114-1 and 114-2 is assumed to be the same.

[0104] In the manufacturing process of WLCSP110, at the end of testing of the device exemplified in Figure 1b, an overvoltage sufficient to cause the fuse circuit 135 to operate is applied to the fuse circuit 135. When an overvoltage is applied, the fuse circuit 135 interrupts (in other words, fuses off) the circuit outside the fuse circuit 135 of the rewiring 114-1. This fuse cut reduces the parasitic capacitance of the lead-out wiring.

[0105] Furthermore, the first, second, third, and fourth modifications of the first embodiment can be applied to the fifth modification of the first embodiment.

[0106] Thus, according to the fifth modification of the first embodiment of this technology, since a fuse circuit 135 is inserted into the rewiring 114-1 of the lead wiring section, the parasitic capacitance of the lead wiring section can be reduced by fuse cutting.

[0107] [Sixth Modification] In the first embodiment described above, all test pads 121 around the pixel region 111 were removed during dicing, but it is also possible to leave some of the test pads 121. The WLCSP 110 in this sixth modification of the first embodiment differs from the first embodiment in that additional test pads 121 are arranged.

[0108] Figure 19 shows an example of a top view and a cross-sectional view of the WLCSP 110 in a sixth modification of the first embodiment of the present technology. In the figure, a shows an example of a top view of the WLCSP 110, and b shows an example of a cross-sectional view of the WLCSP 110 when cut along the line segment A-A' in the figure a.

[0109] In the sixth modification of the first embodiment, in the WLCSP 110, each of the test pads 121 arranged along three of the four sides of the rectangular pixel region 111 as viewed from the Z-axis direction is removed by dicing. As a result, as illustrated in figures a and b, a test pad 121 arranged along one of the four sides remains after dicing. By using this test pad 121, testing can be performed even after dicing.

[0110] It is also possible to leave test pads 121 arranged along two or three of the four sides.

[0111] Furthermore, the first, second, third, fourth, and fifth modifications of the first embodiment can be applied to the sixth modification of the first embodiment.

[0112] Thus, according to the sixth modification of the first embodiment of this technology, the WLCSP 110 is equipped with test pads 121 arranged along a portion of the four sides of the pixel region 111, so that testing can be performed even after dicing using the test pads 121.

[0113] [Seventh Modification] In the first embodiment described above, the WLCSP 110 had two layers, a light-receiving substrate 130-1 and a circuit board 130-2, stacked on top of each other. However, it is also possible to stack three or more layers. The WLCSP 110 in this seventh modification of the first embodiment differs from the first embodiment in that it has three layers stacked on top of each other.

[0114] Figure 20 is an example of an enlarged cross-sectional view of the WLCSP 110 in the seventh modification of the first embodiment of the present technology. As illustrated in the figure, the WLCSP 110 in the seventh modification of the first embodiment differs from the first embodiment in that, in addition to the light-receiving substrate 130-1 and the circuit board 130-2, it further comprises a circuit board 130-3 laminated on them. Various devices constituting the image sensor are distributed and arranged on the light-receiving substrate 130-1, the circuit board 130-2, and the circuit board 130-3. By laminating three layers as illustrated in the figure, the circuit size per substrate can be reduced and the area can be narrowed.

[0115] Furthermore, it is possible to stack four or more layers. Also, the first, second, third, fourth, fifth, and sixth modifications of the first embodiment can be applied to the seventh modification of the first embodiment.

[0116] Thus, according to the seventh modification of the first embodiment of this technology, since three layers, a light-receiving substrate 130-1, a circuit board 130-2, and a circuit board 130-3, are stacked, the circuit size per substrate can be reduced compared to the case where two layers are stacked.

[0117] <2. Second Embodiment> In the first embodiment described above, the wafer 100 was diced by placing a test pad 121 in the scribe region. However, in this manufacturing method, the test pad 121 is removed, so the surface of the WLCSP 110 becomes almost entirely the pixel region 111. When transporting this WLCSP 110, if a pyramidal collet is used, there is a risk that the corners of the semiconductor substrate 130 will chip upon contact (in other words, chipping will occur). The WLCSP 110 in this second embodiment differs from the first embodiment in that the shape of the end face of the semiconductor substrate 130 is tapered in order to suppress chipping.

[0118] Figure 21 shows an example of a top view and a cross-sectional view of the WLCSP110 in a second embodiment of the present technology. In the figure, a is an example of a top view of the WLCSP110, and b is an example of a cross-sectional view obtained by cutting along the line segment A-A' of a in the figure.

[0119] As illustrated in figure b, the end face of the WLCSP110 is tapered. More specifically, the end face is inclined with respect to the front and back surfaces so that the cross-sectional area of ​​the semiconductor substrate 130 gradually narrows from a predetermined coordinate (X4, Z2) toward the front surface coordinate (X32, Z1), and the shape of this inclined portion corresponds to the tapered shape. The portion from coordinate (X4, Z2) to the back surface coordinate (X4, Z3) is a plane without a taper and perpendicular to the back surface, similar to the first embodiment.

[0120] Furthermore, while the line segment A-A' crosses a portion of the end face when viewed from above, the entire end face, not just this portion, is tapered when viewed from above.

[0121] Furthermore, as illustrated in figure b, the tapered portion is preferably on the outside of the guard ring 116. In the figure, X32 corresponds to the X coordinate of the outer circumference of the guard ring 116.

[0122] Furthermore, as illustrated in figure c, the entire edge shape of the semiconductor substrate 130 can be tapered when viewed from the X-axis or Y-axis direction. In this case, the area from the coordinates on the back surface (X4, Z3) to the coordinates on the front surface (X32, Z1) becomes an inclined surface.

[0123] Figure 22 is a diagram illustrating an example of a tapering method in a second embodiment of the present technology. After laser dicing as shown in c in Figure 1, dicing with a blade 320 is performed as illustrated in a in Figure 22. As a result, the wafer 100 is separated into a plurality of WLCSPs 110.

[0124] Then, dicing is performed using a V-shaped blade 321, as illustrated in figure b. This results in a tapered end face, as illustrated in figure c.

[0125] Alternatively, as illustrated in Figure 23a, after the wafer 100 is separated into multiple WLCSPs 110, dicing is performed with a blade 322 that is thinner than the blade 320 and tilted, as illustrated in Figure 23b. This method also yields a tapered end face, as illustrated in Figure 23c.

[0126] Here, as a second comparative example, we consider a configuration in which the test pad 121 is not provided in the scribe region, as described in Patent Document 1, and the test pad 121 remains on the surface of the WLCSP 110 even after dicing.

[0127] Figure 24 is a diagram illustrating the transport methods in the second comparative example and the first embodiment. In the figure, a shows the transport method of the WLCSP110 in the second comparative example, and b shows the transport method in the first embodiment.

[0128] In the second comparative example, a collet 330 with a flat bottom surface is used. A projection 332 is formed on the bottom surface of this collet 330 at a position corresponding to the test pad 121. When transporting the WLCSP 110, the collet 330's drive system drives the collet 330 to bring the projection 332 into contact with the test pad 121 on its surface and draws air out through the intake port 331. As a result, the WLCSP 110 is attracted to the collet 330 and can be transported.

[0129] On the other hand, in the first embodiment, since the test pad 121 is removed by dicing, the chip yield is higher than in the second comparative example, and manufacturing costs can be reduced. However, the surface of the WLCSP 110 consists almost entirely of the pixel area 111. If the collet 330 shown as a in the figure is used on this WLCSP 110, the protrusion 332 may come into contact with the pixel, potentially damaging it.

[0130] To prevent damage to the pixels, a pyramidal collet 340 can be used, as illustrated in figure b. However, in this case, chipping may occur when the collet 340 contacts the corners of the cut surface, potentially leading to the inclusion of silicon debris and dust. The arrow in figure b indicates the location where chipping occurs.

[0131] In contrast, as illustrated in Figure 25, the second embodiment has a tapered end face. This allows the collet 340 to come into contact with the tapered surface, thereby suppressing chipping. In Figure 24, the intake port 341 was located in the center of the bottom surface of the collet 340, but as illustrated in Figure 25, it is preferable to provide the intake port 341 closer to the contact point with the tapered surface.

[0132] Another secondary effect of tapering is the suppression of flare.

[0133] Figure 26 is a cross-sectional view showing an example of a taper angle in a second embodiment of this technology. The taper angle is defined as the angle between the tapered surface and the front (or back) surface of the semiconductor substrate 130. From the viewpoint of suppressing flare, a taper angle of 45° or more is preferable.

[0134] For example, as illustrated in figure a, if the taper angle is less than 45° (e.g., 30°), stray light reflected from the tapered surface escapes upward, which may cause flare.

[0135] On the other hand, as illustrated in figure b, when the taper angle is 45°, stray light can be directed horizontally. Also, as illustrated in figure c, when the taper angle is greater than 45° (e.g., 60°), stray light can be directed downwards. By directing stray light horizontally or downwards, flare can be suppressed.

[0136] As indicated by the white arrow at point b in the figure, curved surfaces may occur at the boundary between the tapered surface and the horizontal or vertical surface, and strictly speaking, not all of the tapered surface is necessarily a slope. Even if a part of the tapered surface is curved, if the majority is a slope, the angle between that slope and the back surface can be considered as the taper angle.

[0137] Furthermore, each of the first to seventh modifications of the first embodiment can be applied to the second embodiment.

[0138] Thus, according to the second embodiment of this technology, the shape of the end face of the semiconductor substrate 130 is tapered, which suppresses chipping during transport. Furthermore, by setting the taper angle to 45° or more, flare can be suppressed.

[0139] [First Modification] In the second embodiment described above, tapering was performed using a V-shaped blade 321 or the like, but it is preferable to simplify the manufacturing process. The wafer 100 in this first modification of the second embodiment differs from the second embodiment in that a part of the side surface of the test pad 121 is included in the chip region.

[0140] Figure 27 is a diagram illustrating an example of dicing in a first modification of the second embodiment of the present technology.

[0141] As illustrated in Figure a, in the first modification of the second embodiment, a portion of the side surface of the test pad 121 is included in the chip region. When the test pad 121 is formed by etching or the like, the shape of its side surface becomes tapered. If the X coordinate of the bottom surface of the test pad 121 that is closest to the chip region is taken as X41, then X41 is set as the coordinate of the boundary between the chip region and the scribe region.

[0142] By dicing a chip region that includes a portion of the side surface of the test pad 121, the end face of the semiconductor substrate 130 can be tapered, as illustrated in figure b. Unlike the second embodiment, there is no need to perform tapering using a V-shaped blade 321 or the like, thus simplifying the manufacturing process.

[0143] Furthermore, each of the first to seventh modifications of the first embodiment can be applied to the first modification of the second embodiment.

[0144] Thus, according to the first modification of the second embodiment of this technology, a portion of the side surface of the test pad 121 is included in the chip area, which simplifies the manufacturing process.

[0145] [Second Modification] In the second embodiment described above, tapering was performed using a V-shaped blade 321 or the like, but the manufacturing method is not limited to this. The manufacturing method in this second modification of the second embodiment differs from the second embodiment in that tapering is performed by anisotropic wet etching.

[0146] Figure 28 is a diagram illustrating another example of a tapering method in a second modification of the second embodiment of the present technology.

[0147] As illustrated in figure a, dicing is performed by the blade 320, and the wafer 100 is separated into multiple WLCSPs 110.

[0148] Then, as illustrated in figure b, a resist mask 350 is formed on each of the WLCSP 110, and tapering is performed by anisotropic wet etching. Then, as illustrated in figure c, the resist mask 350 is removed. By anisotropic wet etching, the tapered shape is formed along the crystal orientation of the semiconductor substrate 130 material. Note that if tapering is performed with a blade as in the second embodiment, the tapered shape can be formed along an orientation different from the crystal orientation.

[0149] Figure 29 is an example of a cross-sectional view of the WLCSP110 in a second modified example of the second embodiment of the present technology.

[0150] As illustrated in figure a, the end face is processed to become a bevel by anisotropic wet etching.

[0151] In anisotropic wet etching, as illustrated in figure b, a portion of the end face may be machined into a curved surface when viewed from the X-axis or Y-axis direction. In this case, the curved surface is treated as a tapered surface.

[0152] Furthermore, in anisotropic wet etching, the end face may be machined into an arc shape, as exemplified by c in the figure. In this case, the curved surface from near the center of the arc to the top surface is treated as a tapered surface.

[0153] Furthermore, each of the first to seventh modifications of the first embodiment can be applied to the second modification of the second embodiment.

[0154] Thus, according to the second modification of the second embodiment of this technology, tapering is performed by anisotropic wet etching, eliminating the need for blade processing.

[0155] [Third Modification] In the second embodiment described above, the silicon was exposed in the tapered portion, but it is preferable to protect that portion. The WLCSP110 in this third modification of the second embodiment differs from the second embodiment in that the tapered portion is covered with an LTO (Low Temperature Oxide) film.

[0156] Figure 30 is an example of a cross-sectional view of the WLCSP 110 in a third modification of the second embodiment of the present technology. The WLCSP 110 in this third modification of the second embodiment differs from the second embodiment in that the tapered portion is covered with an LTO film 118. This protects the tapered portion from damage when the collet makes contact.

[0157] Furthermore, the third modification of the second embodiment can be applied to the first to seventh modifications of the first embodiment and the first and second modifications of the second embodiment, respectively.

[0158] Thus, according to the third modification of the second embodiment of this technology, the tapered portion is covered with an LTO film, thereby protecting that portion from damage.

[0159] [Fourth Modification] In the second embodiment described above, the entire end face of the semiconductor substrate 130 was tapered when viewed from above, but it is preferable to reduce the number of contact points of the collet. The WLCSP 110 in this fourth modification of the second embodiment differs from the second embodiment in that, when viewed from above, a part of the shape of the end face of the semiconductor substrate 130 is tapered.

[0160] Figure 31 shows an example of a top view and a cross-sectional view of the WLCSP110 in a fourth modification of the second embodiment of the present technology. In the figure, a is an example of a top view of the WLCSP110. In the figure, b shows a cross-sectional view obtained by cutting along the line segment A-A' of a in the figure, and c shows a cross-sectional view obtained by cutting along the line segment B-B' of a in the figure.

[0161] In the fourth modification of the second embodiment, a portion of the end face of the semiconductor substrate 130 is tapered when viewed from above. For example, line segment A-A' in the figure crosses the tapered portion as illustrated in figure b. Line segment B-B' in the figure crosses a vertical end face without a tapered shape as illustrated in figure c.

[0162] Figure 32 shows an example of a cross-sectional view and a perspective view of a collet 340 in a fourth modification of the second embodiment of the present technology. In the figure, a is a cross-sectional view of the collet 340, and b is a perspective view of the collet 340 viewed from a downward oblique direction.

[0163] As illustrated in Figures a and b, the pyramidal collet 340 is provided with multiple protrusions 342. The end face of the semiconductor substrate 130 is tapered only in the portion corresponding to the protrusions 342. In addition, an intake port 341 is positioned near the protrusions 342 on the bottom surface of the collet 340. In Figure b, there are eight protrusions 342, but the number is not limited to this number.

[0164] As described above, since only a portion of the end face of the semiconductor substrate 130, that is, the portion corresponding to the projection 342 of the collet 340, is tapered, the contact area with the collet 340 can be reduced compared to the second embodiment.

[0165] Furthermore, the fourth modification of the second embodiment can be applied to the first to seventh modifications of the first embodiment, as well as the first, second, and third modifications of the second embodiment, respectively.

[0166] Thus, according to the fourth modification of the second embodiment of this technology, since a part of the end face is tapered when viewed from above, the contact area with the collet 340 can be reduced.

[0167] [Fifth Modification] In the second embodiment described above, the silicone was exposed in the tapered portion, but it is preferable to protect that portion. The WLCSP110 in this fifth modification of the second embodiment differs from the second embodiment in that the tapered portion is filled with resin.

[0168] Figure 33 is a diagram illustrating an example of a manufacturing method in a fifth modification of the second embodiment of the present technology. As illustrated in figure a, the wafer 100 is half-cut by a V-shaped blade 321 in an area slightly wider than the scribe area.

[0169] Then, as illustrated in figure b, resin 360 is filled into the tapered portion and the scribe region by a dispenser (not shown). Then, as illustrated in figure c, the wafer 100 is cut along the scribe region by a blade 320. This results in a WLCSP 110 with resin 360 filled into the tapered portion. This resin 360 can mitigate the impact when the collet makes contact.

[0170] Furthermore, step a in the same figure can also be performed by wet etching.

[0171] Furthermore, as illustrated in Figures 34 and 35, a high-viscosity resin 361 can also be filled in. This allows the resin 361 to be ejected upwards, thereby improving the impact mitigation effect. It also increases the design flexibility of the collet.

[0172] Figures a, b, and c in Figure 34 are the same as those in Figures a, b, and c in Figure 33, except that the resin 361 has high viscosity.

[0173] In Figure 35, after the half-cut shown in a, resin 361 is applied via a squeegee mask 370, as illustrated in b. Then, as illustrated in c, the wafer 100 is cut along the scribe area by a blade 320.

[0174] Figure 36 shows an example of a plan view and a perspective view of a squeegee mask 370 in a fifth modification of the second embodiment of the present technology. In the figure, a shows a plan view of the squeegee mask 370, and b shows a perspective view of the squeegee mask 370. As illustrated in figure a, the squeegee mask 370 is provided with an opening 371 in the area to which the resin 361 is to be applied.

[0175] Furthermore, the fifth modification of the second embodiment can be applied to the first to seventh modifications of the first embodiment and the first, second, third, and fourth modifications of the second embodiment, respectively.

[0176] Thus, according to the fifth modification of the second embodiment of this technology, since the tapered portion is filled with resin, the impact when the collet makes contact can be mitigated.

[0177] <3. Examples of Application to Mobile Devices> The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0178] Figure 37 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0179] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 37, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0180] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0181] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0182] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0183] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0184] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0185] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0186] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0187] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0188] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 37, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0189] Figure 38 shows an example of the installation position of the imaging unit 12031.

[0190] In Figure 38, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0191] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0192] Figure 38 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0193] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0194] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0195] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0196] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0197] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein can be applied to, for example, the imaging unit 12031 of the configuration described above. Specifically, the WLCSP 110 in Figure 2 can be applied to the imaging unit 12031. By applying the technology described herein to the imaging unit 12031, the cost of the imaging unit 12031 can be reduced and it can be miniaturized.

[0198] The embodiments described above are merely examples of how to realize this technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of this technology that bear the same name. However, this technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the technology.

[0199] The effects described herein are merely illustrative and not limited to those described herein, and other effects may also occur.

[0200] Furthermore, this technology can also take the following configurations: (1) A semiconductor package comprising: a semiconductor substrate; a pixel region formed on the surface of the semiconductor substrate; a guard ring formed around the pixel region; and rewiring wired on the back surface of the semiconductor substrate relative to the surface, with its end portion located outside the guard ring. (2) The semiconductor package according to (1), wherein the surface of the semiconductor substrate is the surface of the semiconductor package. (3) The semiconductor package according to (1) or (2), further comprising an insulating film covering at least a portion of the side surface of the semiconductor substrate. (4) The semiconductor package according to any one of (1) to (3), further comprising through vias formed on the back surface along the outer circumference of the semiconductor substrate, wherein the rewiring includes a first rewiring wired to a lead-out wiring portion from the through via to the end portion and a second rewiring wired to a location not corresponding to the lead-out wiring portion. (5) The semiconductor package according to (4), wherein at least a portion of the first rewiring is thinner than the second rewiring. (6) The semiconductor package according to (4) or (5), further comprising a solder mask covering the back surface of the semiconductor substrate, and first and second insulating layers, wherein the first rewiring is formed between the first insulating layer and the solder mask, and the second rewiring is formed between the second insulating layer and the solder mask, and at least a portion of the first insulating layer is thicker than the second insulating layer. (7) The semiconductor package according to any one of (4) to (6), further comprising a fuse circuit inserted into the first rewiring. (8) The semiconductor package according to any one of (1) to (7), further comprising a predetermined number of test pads, wherein the pixel region is rectangular when viewed from a direction perpendicular to the semiconductor substrate, and the test pads are arranged along at least a portion of the four sides of the pixel region. (9) The semiconductor package according to any one of (1) to (8), wherein the semiconductor substrate is a laminated substrate formed by stacking a plurality of semiconductor substrates. (10) The semiconductor package according to any one of (1) to (9), wherein the shape of at least a part of the end face of the semiconductor substrate, when viewed from a direction perpendicular to the surface of the semiconductor substrate, is tapered.(11) The semiconductor package according to (10), further comprising a low-temperature oxide film covering the tapered portion of the end face. (12) The semiconductor package according to (10) or (11), wherein the tapered shape is formed along the crystal orientation of the semiconductor substrate material. (13) The semiconductor package according to (10) or (11), wherein the tapered shape is formed along an orientation different from the crystal orientation of the semiconductor substrate material. (14) The semiconductor package according to any one of (10) to (13), further comprising a resin filled in the tapered portion of the end face. (15) A semiconductor device comprising a semiconductor substrate, a pixel region formed on the surface of the semiconductor substrate, a guard ring formed around the pixel region, a rewiring that is wired on the back surface of the semiconductor substrate relative to the surface and whose end portion is located outside the guard ring, and a mounting substrate to which the semiconductor package is connected. (16) The semiconductor device according to (15), further comprising an underfill covering the back surface and side surface of the semiconductor substrate. (17) The semiconductor device according to (15), further comprising a first underfill covering the back surface of the semiconductor substrate and a second underfill covering the side surface of the semiconductor substrate, wherein the materials of the first and second underfills are different. (18) A method for manufacturing a semiconductor package, comprising: a wafer manufacturing procedure for creating a wafer in which a test pad is placed in the scribe region of a chip region and a scribe region; a test procedure for testing a device in the chip region using the test pad; and a dicing procedure for cutting the wafer along the scribe region. (19) The method for manufacturing a semiconductor package according to (18), further comprising a processing procedure for tapering at least a portion of the end face of the semiconductor package cut from the wafer by the dicing procedure. (20) The method for manufacturing a semiconductor package according to (18), wherein the shape of the side surface of the test pad, when viewed from a predetermined direction parallel to the surface of the wafer, is tapered, and the chip region includes a portion of the side surface of the test pad.

[0201] 100 Wafer 110 WLCSP 111 Pixel area 112 Backside pad 113, 122 Through-hole via 114, 114-1, 114-2 Rerouting 115 Cu-Cu connection 116 Guard ring 117 Insulating film 118 LTO film 121 Test pad 130 Semiconductor substrate 130-1 Photodetector substrate 130-2, 130-3 Circuit board 131 Device layer 132, 132-1, 132-2 Insulating layer 133 RDL layer 134 Solder mask 135 Fuse circuit 200 Semiconductor device 210 Mounting board 211 Land 212 Solder 213, 214 Underfill 310 Probe 320, 320-1, 321, 322 Blade 330, 340 Collet 331, 341 Inlet 332, 342 Projection 350 Resist mask 360, 361 Resin 370 Squeegee mask 371 Opening 12031 Imaging unit

Claims

1. A semiconductor package comprising: a semiconductor substrate; a pixel region formed on the surface of the semiconductor substrate; a guard ring formed around the pixel region; and rewiring wired on the back surface of the semiconductor substrate relative to the surface, with its end portion located outside the guard ring.

2. The semiconductor package according to claim 1, wherein the surface of the semiconductor substrate corresponds to the surface of the semiconductor package.

3. The semiconductor package according to claim 1, further comprising an insulating film that covers at least a portion of the side surface of the semiconductor substrate.

4. The semiconductor package according to claim 1, further comprising through vias formed on the back surface along the outer periphery of the semiconductor substrate, wherein the rewiring includes a first rewiring routed to a lead-out routing portion from the through via to the end portion and a second rewiring routed to a location not corresponding to the lead-out routing portion.

5. The semiconductor package according to claim 4, wherein at least a portion of the first rewiring is thinner than the second rewiring.

6. The semiconductor package according to claim 4, further comprising a solder mask covering the back surface of the semiconductor substrate, and first and second insulating layers, wherein the first rewiring is formed between the first insulating layer and the solder mask, the second rewiring is formed between the second insulating layer and the solder mask, and at least a portion of the first insulating layer is thicker than the second insulating layer.

7. The semiconductor package according to claim 4, further comprising a fuse circuit inserted into the first rewiring.

8. The semiconductor package according to claim 1, further comprising a predetermined number of test pads, wherein the pixel region is rectangular when viewed from a direction perpendicular to the semiconductor substrate, and the test pads are arranged along at least a portion of the four sides of the pixel region.

9. The semiconductor package according to claim 1, wherein the semiconductor substrate is a laminated substrate obtained by stacking a plurality of semiconductor substrates.

10. The semiconductor package according to claim 1, wherein at least a portion of the shape of the end face of the semiconductor substrate, when viewed from a direction perpendicular to the surface of the semiconductor substrate, is tapered.

11. The semiconductor package according to claim 10, further comprising a low-temperature oxide film covering the tapered portion of the end face.

12. The semiconductor package according to claim 10, wherein the tapered shape is formed along the crystal orientation of the semiconductor substrate material.

13. The semiconductor package according to claim 10, wherein the tapered shape is formed along an orientation different from the crystal orientation of the semiconductor substrate material.

14. The semiconductor package according to claim 10, further comprising a resin filled in the tapered portion of the end face.

15. A semiconductor device comprising: a semiconductor substrate; a pixel region formed on the surface of the semiconductor substrate; a guard ring formed around the pixel region; a rewiring that is wired on the back surface of the semiconductor substrate relative to the surface and whose end portion is located outside the guard ring; and a mounting substrate to which the semiconductor package is connected.

16. The semiconductor device according to claim 15, further comprising an underfill covering the back surface and side surfaces of the semiconductor substrate.

17. The semiconductor device according to claim 15, further comprising a first underfill covering the back surface of the semiconductor substrate and a second underfill covering the side surface of the semiconductor substrate, wherein the materials of the first and second underfills are different.

18. A method for manufacturing a semiconductor package, comprising: a wafer manufacturing procedure for creating a wafer in which a test pad is placed in the scribe region of a chip region and a scribe region; a test procedure for testing a device in the chip region using the test pad; and a dicing procedure for cutting the wafer along the scribe region.

19. The method for manufacturing a semiconductor package according to claim 18, further comprising a processing step of tapering at least a portion of the end face of the semiconductor package cut from the wafer by the dicing step.

20. The method for manufacturing a semiconductor package according to claim 18, wherein the shape of the side surface of the test pad, when viewed from a predetermined direction parallel to the surface of the wafer, is tapered, and the chip region includes a part of the side surface of the test pad.

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