Chemical mechanical planarization method in semiconductor manufacturing process and apparatus thereof

Abstract

According to one embodiment of the present invention, provided, as the technical gist of the present invention, are: a chemical mechanical planarization method in a semiconductor manufacturing process, for controlling the distribution of charged particles within a slurry by applying an electric field to the surface of a wafer by using an electrophoresis phenomenon during a chemical mechanical planarization (CMP) process; and a chemical mechanical planarization apparatus in a semiconductor manufacturing process, comprising: CMP equipment for performing a CMP process for planarizing the surface of a wafer; and an electric field application control unit for applying an electric field to the surface of a wafer during the CMP process.

Description

Chemical mechanical planarization method and apparatus in semiconductor manufacturing process

[0001] The present invention relates to a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process, and more particularly to a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process that controls the planarization and etching rate of a wafer surface using an electrophoretic phenomenon.

[0002] The national research and development projects that supported this invention are as follows.

[0003] Project ID 1711183984

[0004] Project Number 2023M3H3A1059080

[0005] Ministry of Science and ICT

[0006] Project Management (Specialized) Agency Name: National Research Foundation of Korea

[0007] Research Project Name: Original Technology Development Project

[0008] Research Project Title: Establishment of Quantum Device Manufacturing Infrastructure Based on General-Purpose Equipment

[0009] Project Implementing Organization Name: Korea Institute of Nanotechnology

[0010] Research Period: August 7, 2020 – December 31, 2025

[0011] Semiconductor chips used in quantum technology require a very high level of accuracy and reliability. In particular, in fields such as quantum computing or quantum communication, the surface flatness of semiconductor chips has a significant impact on signal transmission speed and energy loss.

[0012] At this stage, the Chemical Mechanical Planarization (CMP) process is an essential step in semiconductor chip manufacturing, playing a role in removing non-uniform interlayer surfaces and flattening them in multilayer semiconductor devices.

[0013] In particular, unlike general semiconductor devices, quantum devices possess fine patterns and structures, requiring a higher level of CMP process to minimize surface non-uniformity. Furthermore, if the surface of the metal wiring layer used in quantum devices is uneven, the flow of current becomes unstable during signal transmission.

[0014] The key to the CMP process required for quantum technology chips is reducing problems such as dishing and erosion. Disshing is a phenomenon where the metal wiring layer is excessively polished, causing pitting, while erosion is a phenomenon where dielectric materials other than the target material are unintentionally etched, degrading surface uniformity.

[0015] FIG. 1(a) is a schematic diagram showing the profile of a semiconductor device prior to a conventional CMP process, FIG. 1(b) is a schematic diagram showing the surface after an ideal CMP process, and FIG. 1(c) is a schematic diagram showing dishing and corrosion phenomena occurring during the CMP process.

[0016] These dishing and etching phenomena can interfere with the fine structure of quantum devices and the accuracy of signal transmission. Furthermore, unlike general semiconductor devices, the CMP process in quantum technology requires more precise planarization, making the control of the initial topography and the management of the chemical composition of the slurry critical.

[0017] As such, since highly precise planarization is required for semiconductor devices used in quantum technology, dishing caused by excessive polishing of the metal layer during the CMP process can be a significant problem. When dishing occurs, the thickness of the metal wiring becomes non-uniform, distorting the signal transmission path and potentially leading to performance degradation of the quantum device.

[0018] Furthermore, erosion, in which the insulating layer rather than the target material is excessively etched, compromises surface uniformity and destabilizes the electrical properties of quantum devices. This increases energy loss during signal transmission and can impair the accuracy of high-performance quantum computing systems.

[0019] Furthermore, if the initial topography is uneven, sufficient surface uniformity may not be ensured even after the CMP process. In particular, fine structures in quantum technology devices are sensitive to such non-uniformity.

[0020] In addition, oxidation or contamination issues may occur during the wafer transfer process in the CMP process, which can affect electrical characteristics that are particularly important in quantum devices and lead to a degradation of process quality.

[0021] Therefore, in semiconductor manufacturing processes, improving the CMP process to maintain low dishing and low corrosion, and resolving issues of oxidation or contamination between processes, can be considered important problems to be solved.

[0022] The present invention aims to provide a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process for achieving planarization by improving the CMP process in the semiconductor manufacturing process to minimize dishing and erosion problems, and by controlling the distribution of charged particles in the slurry by applying an electric field to the wafer surface using the electrophoretic phenomenon.

[0023] In addition, the purpose is to provide a chemical mechanical planarization method and an apparatus for a semiconductor manufacturing process to solve oxidation and contamination problems that may occur during the continuous execution of the CMP process and the plating process.

[0024] According to one embodiment of the present invention, the technical gist of the chemical mechanical planarization method in a semiconductor manufacturing process is a method for controlling the distribution of charged particles in a slurry by applying an electric field to the wafer surface using an electrophoretic phenomenon during the Chemical Mechanical Planarization (CMP) process.

[0025] In addition, the present invention provides another technical feature of a chemical mechanical planarization device in a semiconductor manufacturing process, comprising a CMP device for performing a CMP process to planarize a wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

[0026] In addition, it is desirable to apply the electric field perpendicularly to the wafer surface to change the distribution of ions in the slurry according to the potential difference between the metal and the insulator, thereby controlling the local etching rate of the metal surface.

[0027] In addition, by applying the electric field, ions with negative or positive charges within the slurry can be concentrated on the metal surface, thereby lowering the etching rate of the metal.

[0028] In addition, a plating process may be performed after the above CMP process, and if the uniformity of the wafer surface after the CMP and plating processes is measured and falls below a standard, additional plating and CMP processes may be repeated. Furthermore, the above plating process may include at least one of an electrolytic plating process or an electroless plating process.

[0029] In addition, if the height difference (h0-h1) of the wafer surface after the plating process and CMP process is measured to be below the standard, the plating process can be stopped and the CMP process can be performed when the α coefficient (wup / woriginal, ratio of surface width before and after plating) is 0.99 or less.

[0030] In addition, an electric field can be formed by applying a voltage to prevent current from flowing on the wafer surface, thereby controlling the movement of charged particles within the slurry and controlling the etching rate of the wafer surface.

[0031] In addition, the etching rate of the wafer surface can be controlled by applying current to the wafer surface through a conductive substrate to form a potential difference and creating an electric field.

[0032] In addition, negatively charged ions in the slurry can be concentrated on the metal surface by electrophoresis, which can reduce the etching rate of the metal.

[0033] In addition, the chemical mechanical planarization method in the above semiconductor process can perform the CMP process in an inert gas atmosphere.

[0034] In addition, it includes a standby step in which the electric field is not applied, and the electric field application step and the standby step may be repeated periodically.

[0035] In addition, the distribution of the electric field can be controlled to have symmetrical non-uniformity with respect to the center of the wafer surface.

[0036] In addition, the etching rate can be controlled by applying a differential electric field to regions with high and low metal area density.

[0037] In addition, an electroless plating process can be additionally performed on a specific area of ​​the wafer surface.

[0038] In addition, mechanical polishing can be performed on the wafer surface after the above electroless plating process.

[0039] In addition, quantum superconducting materials used in semiconductor devices for quantum technology may be any one or more of Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

[0040] According to an embodiment of the present invention, the etching rate of a wafer surface can be locally controlled by controlling the distribution of charged particles in a slurry by applying an electric field or current. Through this, excessive dishing or erosion phenomena in the CMP process can be minimized, and uniform planarization of the surface can be achieved.

[0041] In addition, charged particles (cations, anions) present in the slurry can be concentrated on specific parts of the wafer surface by controlling them with an electric field or current. This allows for controlling the etching rate of metals and insulators, enabling selective planarization of only the desired areas.

[0042] In addition, oxidation of the wafer surface can be prevented by performing the process in an inert gas atmosphere or introducing an insulator. This prevents the degradation of electrical properties caused by the oxidation of the metal wiring layer, thereby improving process quality.

[0043] In addition, by controlling the application cycle to periodically apply and control the electric field, unnecessary etching during the CMP process can be prevented and efficient material removal is possible. Furthermore, if the uniformity of the wafer surface is measured to be below a standard, the number of repetitions for the CMP and plating processes can be reduced to increase productivity.

[0044] In addition, the electric field in a specific area can be locally concentrated through a conductor plate including an insulator or a current application method. This allows for the effective flattening of complex patterns or height differences in specific areas.

[0045] In addition, by controlling the symmetry and intensity of the electric field distribution, differential electric fields can be applied to regions with high and low metal area density. This allows for controlling the local etching rate while maintaining uniformity across the entire wafer surface.

[0046] Thus, according to one embodiment of the present invention, by improving the CMP process to minimize dishing and erosion problems and improving the flatness of the wafer surface, high-quality quantum devices can be manufactured.

[0047] In addition, it is possible to resolve oxidation and contamination issues that may occur during the continuous operation of CMP and plating processes, and to improve productivity through an automated transfer system between processes and precise process control.

[0048] This enables the manufacture of high-quality quantum devices, providing excellent performance in high-precision applications such as quantum computers and quantum communication.

[0049] FIG. 1(a) is a schematic diagram showing the profile of a semiconductor device prior to a conventional CMP process, FIG. 1(b) is a schematic diagram showing the surface after an ideal CMP process, and FIG. 1(c) is a schematic diagram showing dishing and corrosion phenomena occurring during the CMP process.

[0050] FIG. 2 is a schematic diagram illustrating the principle of the electrophoretic phenomenon according to an embodiment of the present invention.

[0051] FIG. 3 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention.

[0052] Figure 4 is a schematic diagram of a process according to an embodiment of Figure 3.

[0053] FIG. 5 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention.

[0054] Figure 6 is a schematic diagram of a process according to an embodiment of Figure 5.

[0055] FIG. 7 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention.

[0056] FIG. 8 is a schematic diagram showing the profile of a semiconductor device according to an embodiment of the present invention.

[0057] FIG. 9 is a schematic diagram of the main parts of a chemical mechanical planarization device in a semiconductor manufacturing process according to an embodiment of the present invention.

[0058] FIG. 10 is a schematic diagram showing various embodiments of applying an electric field to a wafer in a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to one embodiment of the present invention.

[0059] The present invention relates to a chemical mechanical planarization method and apparatus in a semiconductor manufacturing process for improving the CMP process in a semiconductor manufacturing process to minimize dishing and erosion problems, achieve high planarization, and solve oxidation and contamination problems that may occur during the continuous execution of the CMP process and the plating process.

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. FIG. 2 is a schematic diagram explaining the principle of the electrophoretic phenomenon according to one embodiment of the present invention, FIG. 3 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to one embodiment of the present invention, FIG. 4 is a schematic diagram of a process according to the embodiment of FIG. 3, FIG. 5 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention, FIG. 6 is a schematic diagram of a process according to the embodiment of FIG. 5, FIG. 7 is a block diagram of a chemical mechanical planarization method in a semiconductor manufacturing process according to another embodiment of the present invention, FIG. 9 is a schematic diagram of a main part of a chemical mechanical planarization device in a semiconductor manufacturing process according to one embodiment of the present invention, and FIG. 10 is a schematic diagram showing various embodiments of applying an electric field to a wafer in a chemical mechanical planarization device in a semiconductor manufacturing process according to one embodiment of the present invention.

[0061] As illustrated in FIGS. 2 to 7, the chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention controls the distribution of charged particles in a slurry by applying an electric field to the wafer surface using the electrophoretic phenomenon during the CMP (Chemical Mechanical Planarization) process.

[0062] In addition, as illustrated in FIGS. 2 to 7, a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to an embodiment of the present invention comprises, in an apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process, a CMP apparatus for performing a CMP process for planarizing a wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

[0063] Accordingly, the present invention can minimize dishing and corrosion phenomena in the CMP process and achieve uniform planarization of the wafer surface. In addition, oxidation and contamination that may occur during the process can be prevented through the repetition of electric field application and standby steps, electrolytic / electroless plating processes, and the supply of inert gas. This enables the high-quality manufacturing of quantum devices and provides excellent performance in application fields such as quantum computers and quantum communication, including high-speed signal transmission and reduced energy loss.

[0064] According to an embodiment of the present invention, the distribution of charged particles in a slurry can be controlled by applying an electric field to the wafer surface using the electrophoretic phenomenon during a Chemical Mechanical Planarization (CMP) process. This involves controlling the distribution of charged particles in the slurry and controlling the etching rate by applying an electric field to the wafer surface. In other words, a high level of planarization required for quantum devices can be achieved by applying an electric field to the wafer surface.

[0065] Chemical Mechanical Planarization (CMP) is used in semiconductor manufacturing processes to planarize multilayer wafers. It is a method in which a polishing pad contacts a slurry (an abrasive containing fine particles) to polish the wafer surface. During this process, charged particles (such as cations and anions) within the slurry move in response to an electric field, a phenomenon known as electrophoresis. When an electric field is applied to the wafer surface, the charged particles within the slurry move, allowing the polishing speed of specific areas to be increased or decreased. By utilizing this phenomenon, the etching rate for specific areas of the wafer can be controlled to achieve a uniform surface.

[0066] For example, if there is a large difference in height between the area where the metal layer needs to be planarized and the insulating layer, an electric field can be applied to induce intensive etching of the metal layer. This minimizes problems commonly occurring in CMP processes, such as dishing and erosion.

[0067] FIG. 2 is a schematic diagram explaining the principle of the electrophoretic phenomenon according to an embodiment of the present invention, showing a process of controlling the distribution of charged particles in a slurry by applying an electric field during the chemical mechanical planarization (CMP) process in a semiconductor manufacturing process. That is, it explains a method of controlling the etching rate of a wafer surface using the electrophoretic phenomenon to effectively perform planarization in the CMP process.

[0068] As described, an electric field is formed on the wafer surface, and this electric field induces the movement of charged particles within the slurry. To generate the electric field, a voltage is applied between the wafer surface and the structure located beneath it. With a potential difference of approximately 1 V, the electric field applied to the wafer surface is calculated to be about 10,000 V / m. This electric field serves to induce the movement of charged particles within the slurry. In other words, the strength of the electric field is 10,000 V / m, and this value was calculated based on a potential difference with a height difference of 100 µm from the wafer surface. With an electric field strength of 10,000 V / m and a distance of 10^ -4 Since it is m (100㎛), the potential difference is calculated as 1V.

[0069] In addition, particles with positive (+) and negative (-) charges are mixed within the slurry. In the diagram, there are positively charged particles (+) indicated in red and negatively charged particles (-) indicated in blue. Under the influence of the electric field, positively charged particles move toward the (-) electrode, and negatively charged particles move toward the (+) electrode. This movement of particles changes the distribution of charged particles within the slurry, thereby controlling the etching rate at a specific location.

[0070] In addition, the drawing shows that an electric field is applied in a vertical direction. An electric field is generated vertically between the surface of the wafer and the electrode underneath, and this electric field plays an important role in controlling the local etching rate of the wafer surface. Furthermore, the potential difference provides the energy required for the etching and polishing processes of the wafer surface, and if the potential difference increases or decreases, the movement of charged particles can be accelerated or slowed down.

[0071] In this way, positive and negative charged particles in the slurry are distributed on the wafer surface by the electric field, thereby controlling the etching rate. As positive charged particles move toward the (-) electrode and negative charged particles move toward the (+) electrode, the concentration and distribution of charged particles in the slurry affect the wafer surface.

[0072] A local potential difference is formed on the surface of the wafer due to an electric field, which controls the etching rate of each region. This is used as a method to control the degree of etching and planarization in specific areas of the wafer surface, and problems such as dishing and erosion can be resolved by controlling the local etching rate.

[0073] In addition, if the entire distribution is formed to be uniform or have a specific pattern, the etching rate on the wafer surface is controlled accordingly. This allows for the reduction of non-uniformity on the wafer surface and the optimization of the degree of planarization.

[0074] In addition, according to one embodiment of the present invention, the electric field is applied perpendicularly to the wafer surface to change the distribution of ions in the slurry according to the potential difference between the metal and the insulator, thereby controlling the local etching rate of the metal surface.

[0075] An electric field applied perpendicularly to the wafer surface generates a potential difference between the metal and the insulator. This potential difference induces the movement of charged particles within the slurry, thereby controlling the polishing speed on the surface. The potential difference between the metal layer and the insulating layer induces specific ions to specific regions, thereby increasing or decreasing the polishing speed of those areas. This allows for precise control of the surface height.

[0076] For example, if polishing of the metal surface is required more than that of the insulator, the potential difference is increased to concentrate charged particles in the slurry onto the metal surface. This increases the etching rate of the metal surface and lowers the etching rate of the insulator, thereby enabling more effective planarization.

[0077] In addition, according to an embodiment of the present invention, the etching rate of the metal is lowered by concentrating positively or negatively charged ions within the slurry on the metal surface through the application of an electric field.

[0078] In the CMP process, the concentration of negatively or positively charged ions in the slurry significantly affects the surface etching rate. When an electric field is applied, specific ions can be concentrated on the metal surface of the wafer, thereby controlling the etching rate of the metal layer. This has the effect of preventing surface dishing and reducing excessive etching.

[0079] For example, when polishing a copper (Cu) metal layer, if positively charged ions are concentrated in the slurry, chemical reactions on the metal surface are suppressed, and the etching rate is lowered. This allows for control so that the metal layer is not excessively etched away.

[0080] In addition, according to an embodiment of the present invention, a plating process is performed after a CMP process, and then the uniformity of the wafer surface is measured, and if it is below a standard, additional plating and CMP processes are repeated.

[0081] If surface flattening is not sufficiently achieved due to problems such as dishing or aerosol in the CMP process, the difference in height on the wafer surface is filled through a plating process, and the final surface flatness of the wafer is improved through a repetitive process of performing the CMP process again.

[0082] This has the effect of improving the signal transmission efficiency and electrical characteristics of semiconductor devices. For example, if the metal wiring layer is unevenly etched after the CMP process, this method involves realigning the wafer surface through additional plating and then uniformly polishing it through CMP again.

[0083] In addition, according to an embodiment of the present invention, the plating process includes at least one of electrolytic plating or electroless plating.

[0084] Electroplating is a process that uses an electric current to deposit metal ions onto a wafer surface, offering the advantage of rapidly depositing thick metal layers. In contrast, electroless plating is a process in which metal ions are reduced and deposited on the surface through chemical reactions without an electric current, enabling uniform plating. The appropriate method between these two can be selected to proceed with plating based on the flatness of the wafer surface.

[0085] For example, electroplating is used when rapidly increasing the thickness of a metal wiring layer, while electroless plating is used when a uniform plating layer is required.

[0086] In addition, according to an embodiment of the present invention, when the height difference (h0-h1) of the wafer surface after the CMP process and the plating process is measured to be below a reference, the plating process is stopped and the CMP process is performed when the α coefficient (wup / woriginal) is 0.99 or less.

[0087] The α coefficient represents the ratio of the surface width before and after plating. If this ratio is 0.99 or less, it indicates that surface planarization is complete and no further plating is required. At this point, the plating process is stopped and switched to the CMP process to increase process efficiency. This minimizes surface dishing and erosion and optimizes the flatness of the wafer surface during the repetitive process.

[0088] In addition, according to an embodiment of the present invention, an electric field is formed by applying voltage so that current does not flow, and thereby the movement of charged particles in the slurry is controlled.

[0089] By applying voltage instead of current, only an electric field is formed to control the movement of charged particles within the slurry. Since this method does not directly affect the surface with current, electrical damage can be prevented during the etching process. Additionally, this allows for the control of the etching rate in specific regions (see Fig. 10(a), (b), and (C)).

[0090] In addition, according to an embodiment of the present invention, a potential is formed by applying current to the wafer surface through a conductive substrate, thereby creating an electric field. By directly applying current to the wafer surface using a conductive substrate, a potential on the surface can be formed and an electric field can be created. This is effective for locally controlling the etching rate of a specific region by controlling the electric field (see FIG. 10(d)).

[0091] In addition, according to an embodiment of the present invention, negatively charged ions in the slurry can be concentrated on the metal surface by the electrophoretic phenomenon, thereby reducing the etching rate of the metal.

[0092] In the CMP process, the type and distribution of charged particles within the slurry significantly influence the surface etching rate. By applying an electric field to control the concentration of negatively charged ions within the slurry on the metal surface, excessive etching of the metal layer is prevented. This method is effective in minimizing dishing by preventing excessive polishing of the metal layer. Consequently, it is possible to prevent unnecessary etching while maintaining a uniform metal layer.

[0093] For example, if an electric field is applied to an area where the metal surface is exposed to concentrate negatively charged ions in the slurry, the chemical reaction on the metal surface is suppressed, and the etching rate is lowered.

[0094] In addition, according to one embodiment of the present invention, the CMP process is performed in an inert gas atmosphere to prevent oxidation of the wafer surface. Negative effects, such as oxidation of the wafer surface, may occur. To prevent this, performing the process in an inert gas atmosphere (e.g., argon, helium, nitrogen) blocks contact with oxygen, thereby preventing oxidation and contamination of the metal layer. This maintains the planar state of the wafer surface and stabilizes the electrical properties of the surface. For example, using argon gas in the CMP process of a copper (Cu) plating layer suppresses oxide formation during the process, enabling higher quality planarization.

[0095] In addition, according to one embodiment of the present invention, a standby step in which an electric field is not applied is included, and the electric field application and standby steps are repeated periodically. Repeating the electric field application and standby steps periodically is more effective in achieving uniform planarization of the surface than continuously applying an electric field to the wafer surface during the CMP process. While the electric field is not applied, particles in the slurry move freely and can control the overall distribution. Through such periodic electric field application, uniform polishing is possible overall without being concentrated only in specific areas.

[0096] For example, by applying an electric field for a certain period of time to concentrate charged particles in a specific area of ​​the surface and then moving to an atmospheric phase to naturally redistribute the particle distribution, the planarization process is performed more uniformly.

[0097] In addition, the electric field distribution is controlled to have symmetric non-uniformity with respect to the center of the wafer surface. Symmetric non-uniformity in the electric field distribution significantly affects the efficiency of the CMP process depending on the surface characteristics. By adjusting the electric field distribution symmetrically with respect to the center of the wafer surface, uniform etching across the entire surface is enabled. This prevents localized over-etching or under-etching.

[0098] For example, the influence of the electric field is efficiently controlled by distributing the electric field strength differently according to a specific pattern on the wafer surface.

[0099] In addition, according to one embodiment of the present invention, the etching rate is controlled by differentially applying an electric field distribution to regions with high and low metal area density. In the CMP process, the etching rate varies depending on the metal area density; to control this, differential electric fields are applied to regions with high and low metal area density. The electric field distribution is controlled so that the etching rate is low in regions with high metal area density, while conversely, the etching rate is high in regions with low area density, thereby enabling uniform planarization.

[0100] For example, an electric field is applied to an area with high metal area density to concentrate charged particles within the slurry, thereby increasing the etching rate in that area, and the electric field is weakened in an area with low metal area density to lower the etching rate, thereby creating a uniform surface.

[0101] In addition, according to one embodiment of the present invention, an electroless plating process is additionally performed on a specific area of ​​the wafer surface. If non-uniformity remains even after the CMP process, an electroless plating process is performed on the corresponding portion to control the height difference of the surface. Electroless plating can deposit metal ions on the surface by chemical reaction without an electric current, allowing for the uniform addition of metal only to specific areas.

[0102] For example, a metal layer is deposited via electroless plating only in specific areas where the metal layer is not flat, and then a CMP process is performed again to create an overall uniform surface.

[0103] In addition, according to one embodiment of the present invention, mechanical polishing is performed on the wafer surface after the electroless plating process. After adjusting the height of a specific area through electroless plating, the plating layer is flattened through mechanical polishing. Although electroless plating is effective in resolving local non-uniformity, it is accurate to finish the final flattening of the surface after plating with mechanical polishing. That is, after depositing metal only on a specific area of ​​the wafer surface through electroless plating, polishing is performed to match the height of that area with the surroundings.

[0104] In addition, the quantum superconducting material used in the semiconductor device for quantum technology according to the embodiment of the present invention may be composed of various metals or superconducting materials.

[0105] Specifically, any one or more of Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors may be used.

[0106] Semiconductor devices used in quantum computing and quantum communication require very high electrical characteristics and stability. To this end, superconducting materials such as Nb (niobium), Sn (tin), and Al (aluminum) are used; these materials possess low resistance and fast signal transmission characteristics. Special care is required when handling these materials during the CMP process, and device performance can be optimized through uniform and precise planarization.

[0107] For example, Nb3Sn is a material with high conductivity and superconducting properties that can be used for wiring in quantum devices. In this case, the efficiency of the device is enhanced by planarizing the surface of the material using a CMP process and maintaining a uniform thickness. Quantum technology devices utilize superconducting materials that possess high conductivity and stability by nature. This claim mentions various metals, alloys, and compound superconductors, each of which can be selected depending on the characteristics of the quantum device. These materials exhibit superconducting properties at very low temperatures and are essential for the rapid and accurate transmission of information in quantum computing and quantum communication.

[0108] For example, YBCO (Yttrium Barium Copper Oxide) is a superconductor with a high critical temperature suitable for signal transmission in quantum devices, and the selection of the slurry and the electric field application conditions are important when planarizing the surface of the material using the CMP process.

[0109] A chemical mechanical planarization device in a semiconductor manufacturing process according to an embodiment of the present invention is a device for performing chemical mechanical planarization, and includes a CMP equipment for performing a CMP process and an electric field application control unit for applying an electric field to a wafer surface.

[0110] According to an embodiment of the present invention, it serves to control the distribution of charged particles and the etching rate of the wafer surface by applying an electric field during the CMP process. By concentrating the electric field on a specific area of ​​the wafer surface through an electric field application control unit, it enhances the uniformity of etching and minimizes dishing and corrosion. Unlike conventional CMP equipment, this device provides higher precision in wafer surface planarization by adding a control unit capable of performing electric field application.

[0111] For example, the local etching rate can be controlled by applying an electric field to a wafer surface with a specific pattern so that charged particles of the slurry are concentrated in the metal region.

[0112] In addition, the electric field application control unit according to an embodiment of the present invention applies an electric field perpendicularly to the wafer surface to form a potential difference between the metal and the insulator. Through this, the distribution of ions in the slurry is controlled.

[0113] By applying a vertical electric field during the CMP process, the distribution of charged particles within the slurry can be controlled, thereby allowing for the adjustment of the etching rate on the wafer surface. In particular, since the etching rate changes depending on the potential difference between the metal and the insulator, surface uniformity can be improved by appropriately adjusting this.

[0114] For example, by applying an electric field perpendicularly to the wafer surface, etching occurs less on the insulating surface and more on the metal surface, making uniform planarization possible.

[0115] According to an embodiment of the present invention, the etching rate of a metal is reduced by concentrating ions with negative or positive charges on the wafer surface through the application of an electric field. By concentrating ions with negative or positive charges within the slurry on the metal surface, etching caused by chemical reactions is suppressed. This prevents excessive removal of the metal surface and allows for the maintenance of stable etching. This method is effective in suppressing dishing phenomena of metal wiring in the CMP process.

[0116] For example, by applying an electric field, positively charged ions in the slurry are concentrated on the metal surface to suppress metal etching and create uniform metal wiring.

[0117] In addition, according to an embodiment of the present invention, a plating process is performed on the wafer surface after a CMP process, and a measuring unit is included to measure the uniformity of the wafer surface after the CMP and plating processes and perform additional plating and CMP processes if it is below a standard. The uniformity of the wafer surface is enhanced by alternately performing the CMP process and the plating process. By measuring the surface uniformity after the process, it is determined whether additional processes are required, and if necessary, additional plating and CMP can be performed to achieve a desired surface flatness. This process is particularly important for quantum devices that require a high degree of planarization.

[0118] For example, after CMP, a measuring device is used to measure the height difference of the surface, and if it is below a standard, the height is corrected through an additional plating process, and then the final CMP is performed.

[0119] In addition, according to an embodiment of the present invention, at least one of an electroplating device or an electroless plating device is included for a plating process. Electroplating involves depositing metal ions onto a wafer surface using an electric current, while electroless plating involves depositing metal through a chemical reaction. A suitable method among the two can be selected and used, or the plating can be performed by combining the two processes. Through this, the metal thickness on the wafer surface is made uniform and planarization is performed.

[0120] For example, electroplating is performed on electrically conductive areas, while electroless plating is performed on complex structures or non-conductive areas to make the surface uniform.

[0121] In addition, the electric field application control unit according to an embodiment of the present invention forms an electric field by applying a voltage so that current does not flow on the wafer surface. Through this, the movement of charged particles in the slurry is controlled to control the etching rate.

[0122] An electric field is formed by applying a voltage that prevents current from flowing, thereby controlling the movement of charged particles within the slurry. This method allows for effective control of surface etching while minimizing contamination or damage caused by the current. For example, a uniform etching rate is maintained by applying a voltage to the wafer surface to prevent charged particles within the slurry from concentrating at specific locations.

[0123] In addition, according to one embodiment of the present invention, the electric field application control unit applies current to the wafer surface through a conductive substrate to form a potential, and performs the role of controlling the etching rate of the wafer surface by locally creating an electric field.

[0124] By directly applying current to the wafer surface through a conductive substrate, a potential difference is formed, creating a local electric field. This local electric field controls the movement of ions within the slurry, enabling the adjustment of the etching rate. This allows for the suppression or promotion of etching in specific areas and enables uniform planarization of the wafer surface during the CMP process. By generating a local potential difference, the etching rate can be finely controlled to suit various surface patterns.

[0125] For example, if a local electric field is formed by applying an electric current to the metal surface of a specific area, ions in the slurry are concentrated in that area, causing the local etching rate to increase or decrease.

[0126] In addition, the electric field application control unit according to an embodiment of the present invention controls negatively charged ions within the slurry to concentrate on the metal surface by means of an electrophoretic phenomenon. By utilizing the electrophoretic phenomenon, the negatively charged ions within the slurry are controlled to concentrate on the metal surface. This allows for lowering or controlling the etching rate of the metal surface. Electrophoresis refers to the phenomenon in which charged particles move due to an electric field, and this is utilized to concentrate ions within the slurry at a specific location. As a result, excessive etching of the metal surface can be prevented, and uniform polishing is enabled.

[0127] For example, when an electric field is applied during the CMP process, negatively charged ions in the slurry move to the metal surface, lowering the etching rate of the surface, thereby reducing dishing phenomena.

[0128] In addition, it includes an inert gas supply unit capable of performing the CMP process in an inert gas atmosphere to prevent oxidation of the wafer surface during the CMP process.

[0129] A device for supplying inert gas is required to prevent wafer surface oxidation during the CMP process. Inert gas can consist of compounds with low chemical reactivity, such as He, Ar, and N2; performing the process in such an atmosphere prevents surface oxidation and contamination. In particular, this oxidation prevention technology is essential for maintaining surface quality in processes requiring high precision, such as those for quantum semiconductor devices.

[0130] For example, oxidation of the wafer surface during the process is minimized by injecting an anti-oxidation gas into the CMP equipment through an inert gas supply unit.

[0131] In addition, according to an embodiment of the present invention, the inert gas comprises at least one of He, Ar, Ne, Kr, and N2. The inert gas used in the CMP process is used to prevent oxidation of the wafer surface and to provide a clean environment. By using at least one of He, Ar, Ne, Kr, and N2 to maintain the atmosphere inside the equipment, the metal layer is prevented from being oxidized or contaminated during CMP. When selecting and using such an inert gas, an appropriate atmosphere can be created according to the characteristics of each gas and the wafer material.

[0132] For example, N2 gas is used to maintain an N2 atmosphere inside the CMP equipment to prevent oxidation of the metal surface.

[0133] In addition, according to an embodiment of the present invention, the electric field application control unit controls the distribution of the electric field to have symmetrical non-uniformity with respect to the center of the wafer surface. When applying an electric field to the wafer surface, the distribution is adjusted to be symmetrically non-uniform with respect to the center of the wafer surface. This symmetrical electric field distribution helps achieve uniform etching during the wafer planarization process and reduces defects that may occur due to non-uniform etching. This non-uniform electric field distribution is used to avoid etching concentrated only in specific areas while maintaining a uniform electric field distribution. For example, metal wiring of a specific pattern is etched more precisely by applying the electric field differently across the edges and the center of the wafer surface.

[0134] In addition, according to an embodiment of the present invention, the electric field application control unit controls the etching rate by applying a differential electric field to regions with high and low metal area density on the wafer surface. The etching rate is controlled by applying a different electric field according to the area density of the metal formed on the wafer surface. By applying different electric fields to regions with high and low metal area, respectively, the uniformity of the etching can be maintained and excessive polishing of specific areas can be prevented. Through this, the entire surface can be uniformly flattened, and the uniformity of the wiring thickness can be improved. For example, a low electric field is applied to regions with high metal area density and a high electric field is applied to regions with low metal area density to achieve overall uniform etching.

[0135] In addition, according to an embodiment of the present invention, the electric field application control unit controls the etching rate of the wafer surface by periodically repeating an electric field application step and a standby step in which the electric field is not applied. That is, rather than continuously applying the electric field, the etching rate is controlled by periodically repeating the electric field application and standby steps. Through this, the etching rate of a specific area of ​​the wafer surface can be finely adjusted, and excessive etching or contamination can be prevented. Since the movement of charged particles stops or slows down during the standby step, the etching speed and uniformity during the electric field application step can be effectively controlled.

[0136] For example, if an electric field is applied for a specific period and then a certain waiting period is passed, a uniform etching rate can be maintained across the entire surface.

[0137] In addition, according to an embodiment of the present invention, the electric field application control unit controls the strength and direction of the electric field to change over time, thereby controlling the etching rate of a specific area on the wafer surface. The etching rate of the wafer surface is controlled through a function that allows the strength and direction of the electric field to be adjusted over time. This method prevents uneven etching from occurring on the wafer surface by periodically adjusting the magnitude and direction of the electric field. When intensive etching is required in a specific area, the strength of the electric field can be increased or the direction can be concentrated on that specific part; conversely, when the etching rate is to be reduced, the electric field can be weakened. Through this, it is possible to respond sensitively to local shape changes on the wafer surface and achieve desired planarization. For example, when the edges of the wafer surface need to be etched further, the strength of the electric field is increased and the direction is adjusted to concentrate the etching effect on that part.

[0138] In addition, according to an embodiment of the present invention, the electric field application control unit performs the role of finely adjusting the distribution of the electric field and the direction of the current to locally control the etching rate of the wafer surface. Detailed description and effect: The distribution of the electric field is locally adjusted to finely tune the etching rate for a specific area of ​​the wafer. In addition, by finely adjusting the direction of the current, the movement of charged particles within the slurry can be precisely controlled. This control enables fine planarization, such as increasing or decreasing the etching rate of a specific area, and supports uniform etching of the wafer surface. For example, if the wafer pattern is complex, the direction and intensity of the current are finely adjusted to perform etching suitable for the complex pattern.

[0139] In addition, quantum superconducting materials used in semiconductor devices for quantum technology may be composed of one or more of the following materials: Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

[0140] Superconducting materials required for semiconductor devices in quantum technology need properties that enable high electrical conductivity, low resistance, and rapid signal transmission. The proposed materials possess these characteristics and enable the efficient operation of quantum devices. In particular, the use of such superconductors in quantum computing and communications plays a crucial role in improving device performance by minimizing energy loss and accelerating signal transmission. For example, Nb3Sn exhibits a high critical current, and high-temperature superconductors such as YBCO are suitable for wiring in quantum computers requiring high-speed operation.

[0141] In addition, according to one embodiment of the present invention, a protective film can be formed on the wafer surface after plating and CMP processes to prevent oxidation remaining on the wafer surface after the CMP process. A protective film is formed to prevent the metal wiring on the wafer surface from reacting with oxygen in the air and oxidizing after the CMP process is completed. The protective film is generally composed of an anti-oxidation material and blocks the metal layer from coming into contact with moisture or oxygen in the air. This allows the electrical characteristics and surface condition of the metal wiring on the wafer surface to be maintained stably. For example, a protective film such as SiO2 or Si3N4 is deposited on the metal surface to prevent oxidation.

[0142] In addition, according to one embodiment of the present invention, the electric field application control unit can finely adjust the distribution of the electric field and the direction of the current to locally control the etching rate of the wafer surface. By finely adjusting the distribution of the electric field and the direction of the current, the etching rate of a specific area is finely controlled. Through this, uniform planarization of the wafer surface can be maintained, and selective etching can be induced only in the necessary parts. For example, the strength and direction of the electric field are adjusted so that etching suitable for each part can be performed even when the specific pattern structure or pad size of the wafer varies. In addition, when fine polishing is required on a specific part of the wafer, the direction of the current is concentrated on that part and the strength of the electric field is adjusted to precisely control the etching rate.

[0143] In addition, according to one embodiment of the present invention, the electric field application control unit controls the strength and direction of the electric field to change over time, thereby allowing the etching rate of a specific area on the wafer surface to be controlled. This is a method of controlling the etching rate by controlling the strength and direction of the electric field that change over time. This is useful when one wants to change or control the etching rate of a specific part of the wafer surface. If the electric field is changed over time, the speed or pattern of etching changes, and this can be utilized to intensively control the etching of a specific part. For example, if one wants to increase the etching rate in the center of the wafer, the electric field can be intensively applied to that part at regular time intervals.

[0144] In addition, according to one embodiment of the present invention, the electric field application control unit can control the etching rate of the wafer surface by periodically repeating the electric field application step and the standby step of not applying the electric field. Periodically repeating the electric field application and standby steps is a method that can precisely control the etching rate of the wafer surface.

[0145] When an electric field is continuously applied, excessive etching may occur in specific areas, so the etching rate of the wafer surface is adjusted by controlling the application-wait cycle. This method has the advantage of controlling local height differences on the surface and preventing damage caused by excessive etching or polishing.

[0146] For example, to prevent the wafer surface from being excessively etched during the CMP process, the surface etching rate is controlled by periodically cutting off the electric field to switch to a standby phase and repeating the process of reapplying it.

[0147] Hereinafter, other embodiments of the present invention will be described in detail.

[0148] A chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention comprises, in a chemical mechanical planarization method in a semiconductor manufacturing process, a step of measuring the initial topography of a wafer surface to measure the non-uniformity of the wafer surface; a step of performing a plating process when the height difference (h0-h1) of the wafer surface is below a certain standard; a step of performing a CMP process to planarize the wafer surface; and a step of re-measuring the uniformity of the wafer surface after the plating process and the CMP process to determine whether an additional plating process and an additional CMP process are required, and repeating the CMP process and the plating process at least once.

[0149] During the above CMP process, a process is performed to control the distribution of charged particles in the slurry by applying an electric field to the wafer surface using the electrophoretic phenomenon. That is, the electrophoretic process may be performed one or more times in each process as needed, such as in the initial process, intermediate process, or reprocess, or each process individually.

[0150] FIGS. 3, FIGS. 5, and FIGS. 7 illustrate the application of an electric field at least once during each CMP process to utilize the electrophoretic phenomenon. FIG. 3 shows the process of applying an electric field (current) at least once during the CMP process. FIG. 5 shows the additional plating process performed after applying an electric field (current) at least once during the CMP process. FIG. 7 shows the additional plating process performed after applying an electric field (current) at least once during the CMP process, followed by an additional CMP process.

[0151] Each process may be performed one or more times as needed, and depending on the wafer surface condition, the electric field application process may be performed during one or more CMP processes, namely the initial CMP process, intermediate CMP process, and re-CMP process.

[0152] An apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process according to an embodiment of the present invention comprises: a CMP apparatus (200) formed on one side of a device forming apparatus (100) for performing a CMP process for planarizing a wafer surface, and a plating apparatus (300) formed on one side of the CMP apparatus (200) for performing a plating process for plating a wafer surface, a measuring unit (600) for measuring an initial topography of a wafer surface provided by the device forming apparatus (100) to detect non-uniformity, a control unit (700) for detecting a height difference (h0-h1) of the wafer surface measured by the measuring unit (600) and controlling the CMP apparatus (200) and the plating apparatus (300), and a transfer system for transferring a wafer from each of the device forming apparatus (100), the CMP apparatus (200), and the plating apparatus (300).

[0153] In a chemical mechanical planarization device for such a semiconductor manufacturing process, according to one embodiment of the present invention, the role of an electric field application control unit may be added to the configuration of the control unit. That is, according to one embodiment of the present invention, it may include a CMP device, a control unit including the function of an electric field application control unit, a plating device, a measuring unit, and a transfer system.

[0154] As described above, the electric field application control unit applies an electric field to the wafer surface during the CMP process to control the distribution of charged particles in the slurry and control the etching rate. In addition, it optimizes the flatness of the surface by controlling the strength, direction, application, and standby cycle of the electric field.

[0155] The present invention relates to a method and apparatus for repeatedly performing plating and CMP processes in a semiconductor manufacturing process, measuring non-uniformity on a wafer surface, and performing additional plating and CMP processes if necessary.

[0156] In addition, the CMP process of the present invention measures the initial topology of the wafer and, when the height difference of the wafer surface is below a certain standard, performs a plating process and then flattens the surface through a CMP process. Subsequently, uniformity is evaluated through re-measurement, and the process is repeated if necessary.

[0157] In addition, the present invention provides an apparatus for performing a process in an inert gas atmosphere to prevent oxidation during wafer transfer.

[0158] In a chemical mechanical planarization method for a semiconductor manufacturing process according to one embodiment of the present invention, first, the initial topography of the wafer surface is measured to measure the non-uniformity of the wafer surface.

[0159] A wafer according to one embodiment of the present invention comprises one or more semiconductor devices, wherein a semiconductor device is formed on a substrate by a semiconductor process, a dielectric layer (10) is formed, a barrier layer (20) is formed on top of it, and a wiring metal layer (Cu) is formed on top of it, and then, in order to form a metal wiring (40), the upper part of the wiring metal layer and the barrier layer (20), etc., are planarized through a CMP (Chemical Mechanical Planarization) process to complete the metal wiring (40).

[0160] If necessary, the wafer in the present invention may also include a structure in which such semiconductor devices and metal wiring (40) are stacked in multiple layers. In this case, the CMP process serves to remove non-uniform surfaces between layers and flatten them in the semiconductor device with a multi-layer structure.

[0161] In the silicon semiconductor process, materials such as Ta, TaN, TiN, Ti, W, WN, Ru, Co, CoSi2, Ni, and NiSi can be used as the barrier layer (20).

[0162] According to one embodiment of the present invention, the semiconductor device is for quantum technology, and the material forming the main effective layer is made of a quantum superconducting material.

[0163] According to one embodiment of the present invention, the quantum superconducting material used in the semiconductor device for quantum technology is Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO(YBa2Cu3O 7-x ), BSCCO(Bi2Sr2Ca2Cu3O 10 ), Iron Pnictides (e.g., Ba 1-x K x Fe2As2), LBCO (La 2-x Ba x CuO4), Iron Chalcogenides (e.g., FeSe), TBCCOTl2Ba2Ca2Cu3O 10), Hg-1223 (HgBa2Ca2Cu3O 8+x It is a material that is a mixture of one or more of the following: ), Iron-Based Superconductors (LaFeAsO, BaFe2As2, SmFeAsORb3C60).

[0164] The initial topography of the wafer surface is measured to determine the non-uniformity of the wafer surface. That is, by precisely measuring the height difference, roughness, etc., of the wafer surface, non-uniform areas can be identified, and this is performed by the measuring unit (600) according to an embodiment of the present invention.

[0165] The measuring unit (600) for measuring the topography of the wafer surface can measure the topography by measuring the change in reflectance or distance of the wafer surface using a laser or light. In addition, it can measure the height difference and pattern change of the surface by detecting the change in capacitance between the wafer surface and the sensor, and in particular, can precisely measure the change in thickness of the plating layer.

[0166] Here, the wafer surface has a barrier layer (20) formed on the dielectric layer (10) and a metal wiring layer (30) formed by a plating process, and the height of the metal wiring layer (30) can be varied in accordance with the pattern or shape of the semiconductor device.

[0167] Meanwhile, a preliminary CMP process may be performed before measuring the non-uniformity of the wafer surface. This allows the subsequent plating process or CMP process to proceed more smoothly.

[0168] In cases where the initial state of the wafer surface is too non-uniform, where planarization is difficult to complete with the main CMP process alone, or where there are wafers with large height differences, uneven pressure may be applied during the polishing process, which may result in uneven planarization. In such cases, the initial non-uniformity is removed to some extent through a preliminary CMP process, thereby enabling more precise planarization in the subsequent main CMP process.

[0169] In one embodiment of the present invention, the vertical cross-sectional shape is shown to be formed in a square pattern, and the metal wiring layer (30) is also formed with different heights along the square pattern, and the measurement of the initial topography in the present invention is to detect the surface of the metal wiring layer (30) with different heights.

[0170] FIG. 8 is an example diagram showing variables related to the initial topography after the initial plating process is completed, showing a state in which a barrier layer (20) is formed on top of a dielectric layer (SiO2) (10) and a metal wiring layer (30) is formed on top of it by the plating process.

[0171] As shown in FIG. 8, as the plating process proceeds, the lower width of the wafer surface (w original Compared to the width of the barrier layer pattern before plating, the upper width of the wafer surface (w) up After plating, the width of the plating pattern can be formed narrower. As the plating process is completed, a change in topology can be achieved as shown in Fig. 6(b).

[0172] The coefficient α is w up / w original It represents the upper width of the wafer surface (w up Width of the plating pattern after plating) and the width of the bottom of the wafer surface (w original It represents the ratio of the width of the barrier layer pattern before plating.

[0173] In the surface topology, the variables related to height are h0, h1, h2, and h3, each representing the height of a different layer or region. For example, h0 represents the maximum height of the plating pattern when the initial plating process is completed from a predetermined baseline, h1 represents the minimum height of the plating pattern formed by the initial plating process, h2 represents the height to the barrier layer (20), and h3 represents the height to the exposed metal wiring (40) after the barrier layer (20) is removed.

[0174] Then, when the measurement of the initial topography is completed, and the height difference (h0-h1) of the wafer surface is below a certain standard—that is, when the initial plating process is completed—a preliminary CMP process is performed. When the difference between the maximum height (h0) of the plating pattern and the minimum height (h1) of the plating pattern formed by the initial plating process becomes below a certain standard, a re-plating process is performed.

[0175] That is, when the height difference of the pattern is large, planarization is first performed by a preliminary CMP process, and then, when the height difference of the pattern is below a certain standard, a redeling process is performed to minimize dishing and corrosion. In one embodiment of the present invention, the redeling process is performed when the height difference is below a certain standard, which is 10㎛ or less. If the height difference is greater than 10㎛, the plated metal layer may be formed unevenly.

[0176] In one embodiment of the present invention, the plating process may include at least one of electrolytic plating and electroless plating. That is, depending on the initial topography, only electrolytic plating may be performed, only electroless plating may be performed, both electrolytic plating and electroless plating may be performed, or each may be repeated multiple times.

[0177] When removing the metal wiring layer (30) during the CMP process, some of the metal wiring layer (30) may be excessively removed (disshing and etching) from the wafer surface, resulting in thickness non-uniformity. To solve this problem, a plating process is required, and through plating, the metal layer is reconstructed on the wafer surface to maintain surface uniformity. Due to this need, the present invention performs a plating process during the CMP process and introduces electrolytic plating and electroless plating processes to selectively deposit metal on the wafer surface, thereby resolving surface non-uniformity.

[0178] Generally, electroplating is a method of depositing metal ions onto a wafer surface using an electric current, which has the advantage of allowing for the uniform deposition of a metal layer (metal wiring layer) and high-speed plating. In one embodiment of the present invention, when there is a large height difference on the wafer surface, electroplating can fill in the surface blockage points and deposit a metal layer uniformly. In the case of electroplating, if a metal wiring layer (30) remains, plating is mainly performed on the upper surface thereof.

[0179] Furthermore, electroless plating is a method of depositing metal onto a wafer surface through chemical reactions without using electric current. Since metal ions are reduced to the wafer surface to form a metal layer, it allows for plating even on surfaces with no electrical conductivity or complex structures, enables uniform plating thickness, and allows for selective plating on specific areas.

[0180] The plating material according to one embodiment of the present invention may use one or more of metal materials with excellent electrical conductivity, such as Cu, Al, Au, Ag, Ni, Cr, Zn, Sn, etc.

[0181] In addition, depending on the shape or structure of the device and the initial topography, the plating process may be selectively applied to specific areas of the wafer surface. That is, considering the non-uniformity of the wafer surface or if there is a higher likelihood of dishing and corrosion occurring in a specific area, the plating process may be performed only on that area. In this case, electroless plating may be appropriately used. When performing electrolytic plating, other areas are masked, and plating is performed only on the exposed area.

[0182] Additionally, the electroless plating process can be performed in a specific area of ​​the wafer surface before and / or after the CMP process, in an area where the height of the wafer surface is below a certain value (h3).

[0183] In other words, during the CMP process, non-uniformity on the wafer surface is not removed in some areas, or areas that are polished more than expected occur. To resolve this, the process proceeds by using electroless plating to deposit metal on specific areas requiring plating and then planarizing them.

[0184] The height h3 of the wafer surface before and / or after the CMP process represents the height to the exposed metal wiring (40) after the barrier layer (20) is removed, and metal is deposited on the lower part of the wafer surface through electroless plating, and metal is selectively deposited on non-uniform parts, complex structures, or non-electrically conductive areas.

[0185] In addition, an electroless plating process may be performed depending on the non-uniformity of the wafer surface. That is, if non-uniformity remains on the wafer surface even after the CMP process, an additional electroless plating process can be performed to compensate for it. This method aims to make the wafer surface more uniform by selectively applying electroless plating when complete planarization is not achieved through the CMP process, redelivery process, or even the CMP process. Through electroless plating, metal is deposited on lower parts of the wafer surface, and metal is selectively deposited on non-uniform areas, complex structures, or regions lacking electrical conductivity.

[0186] This process involves re-measuring the surface after the CMP process and performing additional electroless plating if the wafer surface non-uniformity exceeds a certain standard. Since this process does not require electric current, it can be effectively performed even in complex structures or non-conductive regions. Subsequently, the CMP process is performed again to finally planarize the surface. This minimizes wafer surface non-uniformity and maximizes the performance of quantum devices.

[0187] In addition, according to one embodiment of the present invention, the plating thickness can be automatically adjusted by detecting non-uniformity on the wafer surface during the plating process.

[0188] If the plating process is not properly performed during the semiconductor device manufacturing process, non-uniformity remains on the wafer surface, causing signal transmission and device performance issues. Therefore, the condition of the wafer surface is monitored in real time during plating to ensure that the plating thickness is accurately adjusted only to the necessary parts, thereby preventing unnecessary plating and optimizing the planarization of the wafer surface.

[0189] This non-uniformity detection is performed by using the measurement unit (optical sensor or laser scanning equipment) (600) described above to measure the height difference on the wafer surface, and the control unit (700) transmits this data to the plating equipment (300), etc., to cause a change in the plating process conditions.

[0190] As one of these methods for automatically adjusting the plating thickness, during the plating process, electroplating may perform a reverse current process during a pulse forward current process, or repeat the pulse reverse current process and the pulse forward current process.

[0191] Electroplating utilizes electric current to rapidly deposit metal ions onto a wafer surface, which is advantageous for forming a metal layer of uniform thickness. The constant current process deposits metal ions onto the wafer surface while maintaining a constant current. In this process, the plating thickness can be precisely controlled based on the current intensity and duration. However, if this process is used exclusively, the uniformity of the plating layer may be degraded due to non-uniformity in metal ion concentration or localized differences in current density on the wafer surface.

[0192] To this end, in one embodiment of the present invention, a current is flowed in the opposite direction to the constant current to temporarily remove some metal from the wafer surface, and this process serves to remove defects in the metal layer and improve the uniformity of the plating layer.

[0193] In other words, localized non-uniformity may occur on the wafer surface during the plating process, and the non-uniform parts of the surface can be flattened by temporarily removing the metal using a reverse current.

[0194] In one embodiment of the present invention, a constant current process and a reverse current process are performed alternately. While the constant current process is advantageous for rapidly and uniformly depositing metal, if local non-uniformity occurs, a reverse current is provided to temporarily remove the metal layer and eliminate the non-uniformity. In this case, the metal layer is deposited more precisely, surface defects are reduced, and a high-quality metal layer can be formed.

[0195] In other words, since using only a constant current process on wafers with complex patterns can lead to excessive metal deposition in specific areas, a reverse current process was introduced to solve this problem and enable uniform plating.

[0196] In addition, as the plating process proceeds, the lower width of the wafer surface (w original Compared to the width of the barrier layer pattern before plating, the upper width of the wafer surface (w) up After plating, the width of the plating pattern can be formed narrower. As the plating process is completed, a change in topology can be achieved as shown in Fig. 8(b).

[0197] α coefficient (w up / w original , upper width of the wafer surface (w up Width of the plating pattern after plating) and the width of the bottom of the wafer surface (w original When the ratio of the width of the barrier layer pattern before plating is 0.99 or less, the redecorating can be stopped and the CMP process can be performed. An α coefficient closer to 1 indicates that the plating layer maintains the shape of the original pattern well, and when it is 0.99 or less, it indicates that the plating has reached an appropriate level, and accordingly, the plating process is stopped and the CMP process is performed.

[0198] That is, as shown in Fig. 8, plating is performed on the upper part of the pattern, and when the width of the pattern before and after plating is compared to 0.99 or less, the re-plating can be stopped and the CMP process can be performed. If the α factor is greater than 0.99 but the re-plating is not stopped, there is a high possibility that the plating layer will become too thick or be formed non-uniformly.

[0199] As such, the α factor serves as an important criterion for controlling the plating and CMP processes, and when the α factor reaches 0.99, it indicates that the plating process is complete. By stopping the plating process and performing the CMP process based on this value, the overall process efficiency and quality are ensured.

[0200] In addition, if the α coefficient is measured in real time, the plating process can be automatically stopped and switched to the CMP process when the α coefficient becomes 0.99 or lower during the plating process. This enables the automation of the process and prevents unnecessary plating processes. In one embodiment of the present invention, this function can be controlled by the control unit (700). That is, by utilizing the α coefficient, the end time of the plating process and the start time of the CMP process can be clearly set, thereby maximizing process efficiency.

[0201] Then, once the redecorating process is completed, a CMP process is performed to flatten the wafer surface. The CMP process, used in semiconductor device manufacturing, applies chemical reactions and mechanical polishing simultaneously to uniformly flatten the surface of the semiconductor device, thereby ensuring the stable execution of subsequent processes. In particular, the CMP process plays a role in removing interlayer non-uniformity and creating a flat surface in multilayer semiconductor devices.

[0202] Generally, a wafer is fixed on a polishing pad and the surface is scraped away with a slurry to eliminate surface non-uniformity of the wafer, and the slurry causes a chemical reaction that selectively removes specific substances on the wafer surface, while the abrasive acts to mechanically scrape the wafer surface.

[0203] In one embodiment of the present invention, since the slurry is used to remove layers such as oxides, metals, and insulating films, abrasive particles such as silica (SiO2) or alumina (Al2O3) may be used, or an alkaline slurry may be used when removing oxide films. A suitable slurry is selected to perform the CMP process. The insulating film on the surface of the wafer is removed to flatten it, or after forming the metal wiring layer (30), the wiring layer is flattened to allow subsequent processes to proceed smoothly, or each layer in a multilayer semiconductor device is flattened to reduce alignment errors.

[0204] Then, the uniformity of the wafer surface is re-measured after the plating and CMP processes to determine whether additional plating and CMP processes are required. If additional plating or CMP processes are required, the CMP and plating processes are repeated one or more times. The condition of the surface is checked after each process, and the process is repeated as necessary.

[0205] The re-measurement of the uniformity of the wafer surface is performed in a measurement unit (600) using an optical sensor, etc., similar to the initial topography measurement.

[0206] In other words, after the CMP process is completed, the surface uniformity is re-measured if necessary to determine whether additional plating or CMP is required. If necessary, additional plating and additional CMP are performed to finally complete the surface planarization. The redelivery and additional plating processes prevent the possibility of dishing and corrosion.

[0207] The CMP process and plating process according to one embodiment of the present invention may be performed in an inert gas atmosphere to prevent oxidation of the wafer surface. As the inert gas, any one of He, Ar, Ne, Kr, and N2, or a mixture of two or more of these may be used.

[0208] During the CMP process or plating process, the wafer surface may oxidize. If oxidation occurs during the process of forming the metal wiring layer (30), the electrical conductivity of the metal may decrease and problems may arise in signal transmission. In particular, in the case of quantum semiconductor devices, this can be fatal to the performance of the device.

[0209] In one embodiment of the present invention, an inert gas is supplied by an inert gas supply unit (500) during the CMP process and plating process to block contact with oxygen and prevent the metal layer from oxidizing.

[0210] In one embodiment of the present invention, the pressure inside the CMP equipment (200) and plating equipment (300) can be set to be about 5 to 200 mbar higher than atmospheric pressure. This prevents external air or contaminants from entering the equipment, while maintaining a high concentration of inert gas to prevent oxidation of the wafer surface and maintain a clean state of the surface.

[0211] According to one embodiment of the present invention, the control unit (700) controls the pressure through a pressure sensor and a check valve, and monitors it in real time to maintain a state 5 to 200 mbar higher than atmospheric pressure, and in conjunction with the inert gas supply unit (500), maintains a constant pressure and atmosphere inside the equipment. That is, as the inert gas is continuously supplied, the pressure inside the CMP equipment (200) and the plating equipment (300) is maintained at a constant level.

[0212] In addition, a cleaning process may be included to remove residual impurities on the wafer surface after the above CMP process. After the CMP process is completed, residual impurities (polishing residue and chemical byproducts) may remain on the wafer surface, which are cleaned with ultrapure water or a chemical cleaning agent and dried.

[0213] In addition, if additional plating and CMP processes are not required after the above plating and CMP processes, an additional protective film may be formed to protect the wafer surface.

[0214] If additional plating or CMP processes are not required, a mechanical polishing process may be additionally performed to remove unnecessary residues or rough areas. According to one embodiment of the present invention, mechanical polishing methods such as buffing or lapping are used.

[0215] In addition, in one embodiment of the present invention, oxide (SiO2) or nitride (Si3N4), etc., may be used to protect the wafer surface and prevent the plated metal layer from being corroded by oxygen, moisture, etc. in the air.

[0216] FIG. 3 is a chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention, wherein one or more processes of applying an electric field are performed during the CMP process; FIG. 5 is wherein an additional plating process is performed after applying an electric field during the CMP process; and FIG. 7 is wherein an additional plating process is performed after applying an electric field during the CMP process, and an additional CMP process is performed. Between each process, a cleaning process and a drying process are performed.

[0217] FIG. 4 shows a schematic diagram of a process according to an embodiment of FIG. 3. FIG. 4(a) shows a wafer (device) in which a barrier layer (20) is formed on a dielectric layer (10) and a metal wiring layer (30) is formed on the upper part by an initial plating process. FIG. 4(b) shows a portion of the metal wiring layer (30) polished by performing a CMP process. FIG. 4(c) shows the initial topography of the wafer surface and the non-uniformity of the wafer surface being measured, and the height difference of the wafer surface being determined to be below a certain standard, so a re-plating process is performed. FIG. 4(d) and (e) show the re-plating process being stopped and the CMP process being performed according to the α coefficient. After the plating process and the CMP process, the uniformity of the wafer surface is re-measured, and since additional plating and CMP processes are not required, the CMP process is completed. In the embodiment of FIG. 4, an electric field may be applied during each CMP process for an electrophoretic phenomenon.

[0218] FIG. 5 illustrates a chemical mechanical planarization method in a semiconductor manufacturing process according to an embodiment of the present invention, wherein an electroplating process is performed after applying an electric field (current) one or more times during the CMP process. Additionally, planarization of the wafer surface can be achieved by performing the CMP process once more, followed by an additional electroless plating process and the CMP process. Between each process, a cleaning process and a drying process are performed.

[0219] FIG. 6 shows a schematic diagram of a process according to an embodiment of FIG. 5. FIG. 6(a) shows a wafer (device) in which a barrier layer (20) is formed on a dielectric layer (10) and a metal wiring layer (30) is formed on the upper part by an initial plating process. FIG. 6(b) shows a portion of the metal wiring layer (30) being polished by performing a CMP process. FIG. 6(c) shows the initial topography of the wafer surface being measured and the non-uniformity of the wafer surface being measured, and the height difference of the wafer surface being determined to be below a certain standard, so a re-plating process is performed. FIG. 6(d) shows the re-plating process being stopped according to the α coefficient and the CMP process being performed. After the plating process and the CMP process, the uniformity of the wafer surface is re-measured, and additional plating and CMP processes are required, so electroless plating is additionally performed in FIG. 6(e). After that, the CMP process is performed in FIG. 6(f) to achieve surface planarization. Afterwards, if the uniformity of the wafer surface is re-measured and additional plating and CMP processes are required, additional electroless plating may be performed. In the embodiment of FIG. 6, an electric field may be applied during each CMP process to induce electrophoretic phenomena.

[0220] By doing so, an electric field can be applied during the CMP process or a plating process can be introduced to minimize dishing and corrosion problems and achieve high planarization of the wafer surface.

[0221] Figure 7 shows that after applying an electric field (current) one or more times during the CMP process, an additional plating process is performed, and an additional CMP process is performed. Between each process, a cleaning process and a drying process may be performed.

[0222] Hereinafter, a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to an embodiment of the present invention will be described. Parts that are duplicated from previous descriptions will be omitted.

[0223] FIG. 9 shows a chemical mechanical planarization device in a semiconductor manufacturing process according to an embodiment of the present invention, which is a device for performing chemical mechanical planarization, and includes a CMP equipment (200) for performing a CMP process and an electric field application control unit (720) for applying an electric field to a wafer surface.

[0224] According to one embodiment of the present invention, an apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process comprises: a CMP apparatus (200) formed on one side of a device forming apparatus (100) for performing a CMP process for planarizing a wafer surface; a plating apparatus (300) formed on one side of the CMP apparatus (200) for performing a plating process for plating a wafer surface; a measuring unit (600) for detecting non-uniformity by measuring the initial topography of the wafer surface provided by the device forming apparatus (100); a control unit (700) for controlling the CMP apparatus (200) and the plating apparatus (300) by detecting a height difference (h0-h1) of the wafer surface measured by the measuring unit (600); and a transfer system for transferring a wafer from each of the device forming apparatus (100), the CMP apparatus (200), and the plating apparatus (300).

[0225] According to an embodiment of the present invention, the distribution of charged particles is controlled by applying an electric field during the CMP process, and the etching rate of the wafer surface is controlled. By concentrating the electric field on a specific area of ​​the wafer surface through the electric field application control unit (720), the uniformity of the etching is increased, and dishing and corrosion are minimized. Unlike conventional CMP equipment, this device provides higher precision in the planarization of the wafer surface by adding a control unit (700) that includes an electric field application control unit (720) capable of performing electric field application.

[0226] A wafer manufactured in a device forming equipment (100) is transferred to a CMP equipment (200) and a plating equipment (300) so that each process is performed. The device forming equipment (100) according to one embodiment of the present invention performs the process in a vacuum state and may be a PVD or an e-Bean Evaporator, etc.

[0227] The above CMP equipment (200) is formed on one side of the device forming equipment (100) and flattens the wafer surface by physically polishing the wafer surface using a polishing pad and a slurry and creating a uniform surface through a chemical reaction.

[0228] The plating equipment (300) deposits a metal wiring layer (30) on the wafer surface after a CMP process and may include one or more of an electrolytic plating equipment (300) and an electroless plating equipment (300).

[0229] The above measuring unit (600) measures the topography of the wafer surface and can be used to measure the height difference of the wafer surface to check the flatness after the CMP process or to measure the thickness of the metal wiring layer (30) before and after plating. That is, it can be used to measure the initial topography or to re-measure after the CMP process, thereby determining whether an additional CMP process is required.

[0230] The control unit (700) controls the CMP equipment (200) and the plating equipment (300) and can automatically adjust the process based on data measured by the measurement unit (600). The control unit (700) determines whether to proceed with the CMP process and the plating process based on the height difference (h0-h1) of the wafer surface. That is, the control unit (700) controls the process so that the plating process is performed when the height difference of the wafer surface is below a certain standard, or performs an additional CMP process if necessary. In addition, the operation of the CMP equipment (200) and the plating equipment (300) can be automatically controlled based on data measured in real time.

[0231] The above transfer system (e.g., a robot arm) is intended to smoothly transfer a wafer between device forming equipment (100), CMP equipment (200), and plating equipment (300), and moves the wafer in a vacuum state to prevent contamination or oxidation that may occur during the process.

[0232] In other words, it safely transports the wafer under vacuum conditions, facilitates the connection between device formation, CMP, and plating processes, and prevents the wafer surface from oxidizing between processes.

[0233] In a semiconductor manufacturing process according to one embodiment of the present invention, a chemical mechanical planarization device is provided with a wafer in a vacuum state from a device forming device (100), and includes a CMP device (200), a plating device (300), a measuring unit (600), a control unit (700), and a transfer system. The initial topography of the wafer is measured to identify non-uniformity, and a CMP process is performed to remove the non-uniformity of the wafer. After the CMP process, a metal is plated on the wafer surface, and after plating, the surface is measured to determine whether an additional CMP process or plating process is required. The control unit (700) checks whether an additional CMP process or plating process is required. The transfer system ensures that the wafer is safely transferred without contamination between all these processes.

[0234] Meanwhile, the CMP equipment (200) for the CMP process and the plating equipment (300) for the plating process may include one or more partitions (400) between the device forming equipment (100), the CMP equipment (200), and the plating equipment (300) for maintaining a vacuum state of the device forming equipment (100) and maintaining an inert gas atmosphere of the CMP equipment (200) and the plating equipment (300).

[0235] A partition (400) is installed between the device forming equipment, the CMP equipment (200), and the plating equipment (300) to maintain the process atmosphere while the wafer moves between each process, thereby protecting the wafer from vacuum breakdown, oxidation, contamination, etc., that may occur when the wafer moves between equipment.

[0236] According to one embodiment of the present invention, the partition wall (400) is opened while the wafer is being transported and is closed while each process is in progress. For example, the partition wall (400) is formed such that it opens by a sensor when the wafer arrives at the transport zone and closes when the transport is completed. It may be formed of a chemically stable metal or a highly durable synthetic material. For example, it may be formed of tempered glass or stainless steel. Additionally, a load lock in the vacuum equipment may perform this role.

[0237] In the process according to one embodiment of the present invention, an electric field is applied to the wafer surface by an electric field application control unit (720) during the CMP process to induce movement of charged particles in the slurry and to control the local etching rate of the metal surface. Then, the electric field application and standby steps are repeated periodically to prevent excessive etching and achieve uniform planarization, and the uniformity of the wafer surface is evaluated after the CMP process. If it is below a standard, plating and an additional CMP process are performed to ensure uniformity. In addition, electroplating and electroless plating are selectively performed to maintain a uniform etching rate on the wafer surface. An inert gas is supplied to prevent oxidation of the wafer surface during the CMP process or the plating process.

[0238] FIG. 10 is a schematic diagram showing various embodiments of applying an electric field to a wafer in a chemical mechanical planarization apparatus in a semiconductor manufacturing process according to an embodiment of the present invention, illustrating various electric field application methods for planarizing the wafer surface using a slurry and an electric field in a semiconductor CMP process.

[0239] FIG. 10(a) includes a conductive substrate (conductor plate), a wafer (substrate), an insulator, a slurry, a platen (polishing pad), a voltage source (electric field application control unit), and a control unit. The conductor plate is positioned on top of the wafer and forms an electric field through the wafer and the insulator. An electric field is applied by forming a potential difference between the conductor plate and the platen through the voltage source, and this electric field induces the movement of charged particles present in the slurry. In this method, the distribution and movement of charged particles within the slurry can be controlled by applying a vertical electric field to the wafer surface. This allows for uniform control of the etching rate of the wafer surface and achieves the desired planarization. Additionally, the influence of impurities such as oxidation can be minimized through the supply of an inert gas.

[0240] There is an inert gas supply unit, which uses an inert gas (e.g., argon, helium) to prevent oxidation of the wafer during the CMP process and stabilizes the behavior of charged particles in the slurry when an electric field is applied, thereby enabling uniform etching.

[0241] FIG. 10(b) includes a conductive plate, a wafer (substrate), an insulator, a slurry, a platen, a voltage source (electric field application control unit), and a control unit, and generates an electric field on the wafer surface by applying voltage through the conductive plate. At this time, the electric field is designed to uniformly distribute charged particles within the slurry. The distribution of charged particles within the slurry is uniformly controlled to flatten the wafer surface. This enables precise flattening by minimizing minute height differences on the wafer surface.

[0242] FIG. 10(c) includes a conductor plate (including a portion of an insulator), a wafer (substrate), a slurry, a platen, a voltage source (electric field application control unit), and a control unit. A portion of the conductor plate is composed of an insulator, thereby controlling the electric field so that it can be concentrated only in a specific area. By making a portion of the conductor plate an insulator, the concentration of the electric field is controlled. Through this, the etching rate of the wafer surface can be controlled more finely, and local planarization can be performed by concentrating the electric field in a specific area.

[0243] FIG. 10(d) includes a conductive plate, a wafer (substrate), an insulator, a slurry, a platen, a current source (electric field application control unit), and a control unit. Charged particles within the slurry are controlled by directly applying current to the wafer through the conductive plate. An electric potential is formed by allowing current to flow through the current source, thereby controlling the movement of ions within the slurry. Planarization is performed by applying current rather than voltage. As a result, the formation of an electric field in a specific region is locally possible, and the etching rate of the wafer surface can be finely controlled. This allows for more accurate planarization.

[0244] These methods control the distribution of charged particles in a slurry by applying an electric field or flowing a current to the wafer surface, thereby controlling the etching rate of the wafer surface to perform planarization. Each method can be applied depending on process conditions, and effects such as uniform surface planarization, oxidation prevention, and precise etching rate control can be achieved.

[0245] As described above, the various methods from (a) to (d) achieve wafer surface planarization through the application of an electric field and control the etching rate by controlling the ion distribution and the movement of charged particles within the slurry during the process. Through this, high-level wafer planarization, oxidation prevention, and uniform process conditions can be secured during the semiconductor manufacturing process.

[0246] In this way, the electric field application control unit according to an embodiment of the present invention performs the role of applying an electric field to the wafer surface during the CMP process, thereby controlling the etching rate of the wafer surface by controlling the movement and distribution of charged particles in the slurry.

[0247] As described above, the electric field application control unit controls the distribution of charged particles in the slurry by applying an electric field to the wafer surface to form a potential difference between the metal and the insulator. This electric field affects the surface etching rate and enables a uniform planarization process by controlling it.

[0248] In addition, the electric field application control unit finely adjusts the strength and direction of the electric field to control the local etching rate of the wafer surface. For example, surface planarization can be induced by applying a stronger electric field to a specific area to increase or decrease the etching rate of that area.

[0249] In addition, the etching rate is locally controlled by changing the local distribution of charged particles in the slurry by forming a potential at a specific location on the wafer surface. This allows the etching rate to be uniformly adjusted across regions with different metal pattern densities.

[0250] In addition, the electric field application control unit precisely controls the etching rate by periodically repeating the steps of applying the electric field and waiting. This prevents local non-uniformity from occurring during the planarization process.

[0251] In addition, the electric field is finely controlled by adjusting the voltage so that no current flows on the wafer surface when the electric field is applied, or by forming a potential by locally applying current through a conductive substrate. Through such control, the movement and reaction of ions within the slurry are controlled to optimize the etching rate.

[0252] In addition, the electric field application control unit ensures uniformity of the electric field across the entire wafer surface and can apply the electric field differentially to regions with high and low metal area density. This function compensates for regional etching non-uniformity and improves the final planarization level.

[0253] As such, the electric field application control unit is intended to utilize the electrophoretic phenomenon during the entire CMP process and plays an important role in enabling the realization of an optimal etching rate along with uniform surface planarization by precisely controlling the electric field strength, direction, and application time.

[0254] As described above, according to an embodiment of the present invention, the etching rate of a wafer surface can be locally controlled by controlling the distribution of charged particles in a slurry by applying an electric field or current. Through this, excessive dishing or erosion phenomena in the CMP process can be minimized, and uniform planarization of the surface can be achieved.

[0255] In addition, charged particles (cations, anions) present in the slurry can be concentrated on specific parts of the wafer surface by controlling them with an electric field or current. This allows for controlling the etching rate of metals and insulators, enabling selective planarization of only the desired areas.

[0256] In addition, oxidation of the wafer surface can be prevented by performing the process in an inert gas atmosphere or introducing an insulator. This prevents the degradation of electrical properties caused by the oxidation of the metal wiring layer, thereby improving process quality.

[0257] In addition, by controlling the application cycle to periodically apply and control the electric field, unnecessary etching during the CMP process can be prevented and efficient material removal is possible. Furthermore, if the uniformity of the wafer surface is measured to be below a standard, the number of repetitions for the CMP and plating processes can be reduced to increase productivity.

[0258] In addition, the electric field in a specific area can be locally concentrated through a conductor plate including an insulator or a current application method. This allows for the effective flattening of complex patterns or height differences in specific areas.

[0259] In addition, by controlling the symmetry and intensity of the electric field distribution, differential electric fields can be applied to regions with high and low metal area density. This allows for controlling the local etching rate while maintaining uniformity across the entire wafer surface.

[0260] Thus, according to one embodiment of the present invention, by improving the CMP process to minimize dishing and erosion problems and improving the flatness of the wafer surface, high-quality quantum devices can be manufactured.

[0261] In addition, it is possible to resolve oxidation and contamination issues that may occur during the continuous operation of CMP and plating processes, and to improve productivity through an automated transfer system between processes and precise process control.

[0262] This enables the manufacture of high-quality quantum devices, providing excellent performance in high-precision applications such as quantum computers and quantum communication.

Claims

1. In a chemical mechanical planarization method in a semiconductor manufacturing process, A chemical mechanical planarization method in a semiconductor manufacturing process that controls the distribution of charged particles in a slurry by applying an electric field to the wafer surface using the electrophoretic phenomenon during the CMP (Chemical Mechanical Planarization) process.

2. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 1, wherein the electric field is applied perpendicularly to the wafer surface to change the distribution of ions in the slurry according to the potential difference between the metal and the insulator, thereby controlling the local etching rate of the metal surface.

3. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 2, wherein negatively or positively charged ions within a slurry are concentrated on a metal surface through the application of the electric field to lower the etching rate of the metal.

4. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 2, wherein a plating process is performed after the CMP process, and the uniformity of the wafer surface is measured after the CMP process and the plating process, and if it is below a standard, additional plating and CMP processes are repeated.

5. In paragraph 4, the plating process comprises at least one of an electrolytic plating process or an electroless plating process, in a chemical mechanical planarization method in a semiconductor process.

6. A chemical mechanical planarization method in a semiconductor process according to claim 4, wherein when the height difference (h0-h1) of the wafer surface after the plating process and CMP process is measured to be below a reference, the plating process is stopped and the CMP process is performed when the α coefficient (wup / woriginal, ratio of surface width before and after plating) is 0.99 or less.

7. A chemical mechanical planarization method in a semiconductor process according to claim 1, wherein a voltage is applied to form an electric field so as not to allow current to flow on the wafer surface, and thereby the movement of charged particles within the slurry is controlled to control the etching rate of the wafer surface.

8. A chemical mechanical planarization method in a semiconductor process according to claim 1, wherein an electric current is applied to the wafer surface through a conductive substrate to form a potential difference and an electric field is formed to control the etching rate of the wafer surface.

9. A chemical mechanical planarization method in a semiconductor process according to claim 1, wherein negatively charged ions in a slurry are concentrated on a metal surface by an electrophoretic phenomenon to reduce the etching rate of the metal.

10. In claim 1, the chemical mechanical planarization method in the semiconductor process is, Chemical mechanical planarization method in a semiconductor process in which a CMP process is performed in an inert gas atmosphere.

11. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 1, comprising a standby step in which the electric field is not applied, wherein the electric field application step and the standby step are repeated periodically.

12. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 1, wherein the distribution of the electric field is controlled to have symmetric non-uniformity with respect to the center of the wafer surface.

13. A chemical mechanical planarization method in a semiconductor manufacturing process according to claim 1, wherein the etching rate is controlled by applying a differential electric field to regions with high and low metal area density.

14. A chemical mechanical planarization method in a semiconductor process according to claim 1, wherein an electroless plating process is additionally performed on a specific area of ​​the wafer surface.

15. A chemical mechanical planarization method in a semiconductor process, wherein mechanical polishing is performed on the wafer surface after the electroless plating process according to claim 14.

16. In paragraph 1, the quantum superconducting material used in semiconductor devices for quantum technology is, A chemical mechanical planarization method in a semiconductor manufacturing process comprising one or more of the following materials: Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

17. An apparatus for performing chemical mechanical planarization in a semiconductor manufacturing process, A chemical mechanical planarization device in a semiconductor manufacturing process comprising a CMP equipment for performing a CMP process for planarizing a wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

18. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process that controls the distribution of ions in a slurry by applying an electric field perpendicularly to the wafer surface to form a potential difference between a metal and an insulator.

19. A chemical mechanical planarization apparatus in a semiconductor manufacturing process that lowers the etching rate of a metal by concentrating ions with negative or positive charges on the wafer surface through the application of the electric field according to claim 18.

20. A chemical mechanical planarization apparatus in a semiconductor manufacturing process according to claim 17, comprising a measuring unit capable of performing a plating process on a wafer surface after a CMP process, measuring the uniformity of the wafer surface after the CMP process and the plating process, and performing additional plating and CMP processes if the uniformity is below a standard.

21. A chemical mechanical planarization apparatus in a semiconductor manufacturing process comprising at least one of an electrolytic plating apparatus or an electroless plating apparatus for the plating process according to claim 20.

22. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process that controls the etching rate by applying voltage to form an electric field so that current does not flow on the wafer surface, thereby controlling the movement of charged particles within the slurry.

23. In Clause 17, the electric field application control unit is, A chemical mechanical planarization apparatus in a semiconductor manufacturing process comprising controlling the etching rate of a wafer surface by applying an electric current to the wafer surface through a conductive substrate to form a potential and locally creating an electric field.

24. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process that controls negatively charged ions in a slurry to be concentrated on a metal surface by the phenomenon of electrophoresis.

25. A chemical mechanical planarization apparatus in a semiconductor manufacturing process according to claim 17, comprising an inert gas supply unit capable of performing a CMP process in an inert gas atmosphere to prevent oxidation of the wafer surface during the CMP process.

26. A chemical mechanical planarization apparatus in a semiconductor manufacturing process, wherein the inert gas in claim 25 comprises at least one of He, Ar, Ne, Kr, and N2.

27. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process that controls the distribution of an electric field to have symmetrical non-uniformity with respect to the center of the wafer surface.

28. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process capable of controlling the etching rate by applying a differential electric field to regions of high and low metal area density on a wafer surface.

29. In Clause 17, the electric field application control unit, A chemical mechanical planarization device in a semiconductor manufacturing process that controls the etching rate of a wafer surface by periodically repeating an electric field application step and a standby step without application.

30. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process that controls the strength and direction of the electric field to change over time, thereby controlling the etching rate of a specific area on the wafer surface.

31. In Clause 17, the electric field application control unit is, A chemical mechanical planarization device in a semiconductor manufacturing process capable of controlling the distribution of an electric field and the direction of current to locally control the etching rate of a wafer surface.

32. In paragraph 17, the quantum superconducting material used in semiconductor devices for quantum technology is, A chemical mechanical planarization device in a semiconductor manufacturing process that is a material comprising one or more of Nb, Sn, Al, Zn, Ta, Nb-Ti, Nb3Sn, V3Si, V3Ga, Nb3Ge, MgB2, YBCO, BSCCO, Iron Pnictides, LBCO, Iron Chalcogenides, TBCCO, Hg-1223, and Iron-Based Superconductors.

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