Display panel and electronic device comprising same

Abstract

This display panel comprises: a base layer including a first surface and a second surface opposite to the first surface; a first pixel circuit layer, which is disposed on the first surface of the base layer and includes a transistor and insulating layers; a second pixel circuit layer, which is disposed on the first surface of the base layer, is spaced apart from the first pixel circuit layer, and includes transistors and insulating layers; a first light-emitting diode, which is disposed on the first pixel circuit layer and is electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode, which is disposed on the second pixel circuit layer and is electrically connected to a transistor of the second pixel circuit layer; a first line electrically connected to the transistor of the first pixel circuit layer; a second line electrically connected to the transistor of the second pixel circuit layer; and a connection line electrically connecting the first line to the second line, wherein a first portion of the first line extends toward the connection line, and at least a part of the first portion is embedded in the connection line.

Description

Display panel and electronic device including the same

[0001] One or more embodiments relate to a display panel. One or more embodiments disclose a display panel, a manufacturing process of a display panel, and an electronic device including a display panel.

[0002] In general, as display panels that visually display electrical signals advance, various display panels with excellent characteristics such as thinness, lightness, and low power consumption, as well as electronic devices containing them, are being introduced. For example, research and development is actively underway on display panels of various structures, such as flexible display panels that can be folded or rolled into a roll shape, and stretchable display panels, as well as electronic devices containing them.

[0003] One or more embodiments disclose a display panel, such as a flexible display panel, an electronic device including the same, and a manufacturing process of the display panel.

[0004] Additional aspects will be presented in part in the following description, and will be made apparent in part from the description or by practicing the embodiments presented in this disclosure.

[0005] One embodiment of the present invention discloses a display panel comprising: a base layer including a first surface and a second surface opposite to the first surface; a first pixel circuit layer disposed on the first surface of the base layer and including transistors and insulating layers; a second pixel circuit layer disposed on the first surface of the base layer and spaced apart from the first pixel circuit layer and including transistors and insulating layers; a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; a first line electrically connected to the transistor of the first pixel circuit layer; a second line electrically connected to the transistor of the second pixel circuit layer; and a connecting line electrically connecting the first line and the second line, wherein a first portion of the first line extends toward the connecting line and at least a portion of the first portion is embedded within the connecting line.

[0006] The bottom surface and side surface of the first part of the first line can come into direct contact with the connecting line.

[0007] The insulating layers of each of the first pixel circuit layer and the second pixel circuit layer include an inorganic insulating stack comprising inorganic insulating layers and a first organic insulating layer on the inorganic insulating stack, and the first organic insulating layer of the first pixel circuit layer may overlap with the first portion of the first line.

[0008] The first organic insulating layer can be in direct contact with the upper surface of the first part of the first line.

[0009] A portion of the above base layer may come into direct contact with a portion of the side of the above inorganic insulation stack.

[0010] The above connection line includes a first portion that overlaps with the first organic insulating layer but does not overlap with the first portion of the first line, and a second portion located between the first organic insulating layer of the first pixel circuit layer and the first organic insulating layer of the second pixel circuit layer, and the first thickness of the first portion of the connection line may be greater than the second thickness of the second portion of the connection line.

[0011] The above connecting line further includes a third portion that overlaps with the first portion of the above connecting line, wherein the third thickness of the third portion of the above connecting line may be smaller than the first thickness.

[0012] The insulating layers of each of the first pixel circuit layer and the second pixel circuit layer further include a second organic insulating layer on the first organic insulating layer; and a third organic insulating layer interposed between the inorganic insulating stack and the first organic insulating layer and overlapping with the side of the inorganic insulating stack, and a portion of the first line may be disposed between the third organic insulating layer and the first organic insulating layer.

[0013] The width of the first organic insulating layer may be greater than the width of the inorganic insulating stack.

[0014] The first line comprises a first layer including a first metal and a second layer including a metal different from the first layer and located on the first layer, wherein the second layer includes a tip protruding laterally from a point where the side of the first layer and the bottom surface of the second layer meet, and the connecting line can come into direct contact with the side and bottom surfaces of the tip.

[0015] It further includes a protective layer on the first light-emitting diode and the second light-emitting diode, wherein the protective layer can be in direct contact with the connection line.

[0016] One embodiment of the present invention comprises: a base layer comprising two mutually spaced first regions and a second region between the two first regions; a first pixel circuit layer disposed in either of the two first regions of the base layer and comprising a transistor and an insulating layer; a second pixel circuit layer disposed in the other of the two first regions of the base layer, spaced apart from the first pixel circuit layer, and comprising a transistor and an insulating layer; a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; a first line electrically connected to the transistor of the first pixel circuit layer; a second line electrically connected to the transistor of the second pixel circuit layer; and a connecting line electrically connecting the first line and the second line, wherein the first line extends toward the connecting line and the first portion of the first line A display panel is disclosed in which the bottom surface and the side surface are in direct contact with the above-mentioned connection line.

[0017] The insulating layers of each of the first pixel circuit layer and the second pixel circuit layer include an inorganic insulating stack comprising inorganic insulating layers, and a first organic insulating layer on the inorganic insulating stack, wherein the first organic insulating layer may overlap with the first portion of the first line.

[0018] The above connecting line includes a first portion that overlaps with the first organic insulating layer but does not overlap with the first portion of the first line, and a second portion located in the second region, and the first thickness of the first portion of the connecting line may be greater than the second thickness of the second portion of the connecting line.

[0019] The above connecting line further includes a third portion that overlaps with the first portion of the above first line, and the third thickness of the third portion of the above connecting line may be smaller than the first thickness.

[0020] The insulating layers of each of the first pixel circuit layer and the second pixel circuit layer may further include a second organic insulating layer between the inorganic insulating stack and the first organic insulating layer, overlapping with the side of the inorganic insulating stack, and a portion of the first line may be disposed between the second organic insulating layer and the first organic insulating layer.

[0021] A portion of the above base layer may come into direct contact with a portion of the side of the above inorganic insulation stack.

[0022] The first organic insulating layer can be in direct contact with the upper surface of the first part of the first line.

[0023] The first line comprises a first layer comprising a first metal and a second layer on the first layer comprising a metal different from the first layer, wherein the second layer comprises a tip protruding laterally from a point where the side of the first layer and the bottom surface of the second layer meet, and the connecting line may come into direct contact with the side and bottom surfaces of the tip.

[0024] It further includes a protective layer on the first light-emitting diode and the second light-emitting diode, wherein the protective layer can be in direct contact with the connection line.

[0025] An electronic device comprising a display panel, wherein the display panel comprises a base layer comprising a first surface and a second surface opposite to the first surface; a first pixel circuit layer disposed on the first surface of the base layer and comprising transistors and insulating layers; a second pixel circuit layer disposed on the first surface of the base layer and spaced apart from the first pixel circuit layer and comprising transistors and insulating layers; a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; a first line electrically connected to the transistor of the first pixel circuit layer; a second line electrically connected to the transistor of the second pixel circuit layer; and a connecting line electrically connecting the first line and the second line, wherein a first portion of the first line extends toward the connecting line, and at least a portion of the first portion is embedded within the connecting line.

[0026] According to one or more embodiments, high-quality display panels and electronic devices can be provided. The effects described above are exemplary and the effects of the present invention are not limited to those described above.

[0027] FIG. 1 is a schematic perspective view of a display panel according to one or more embodiments.

[0028] FIGS. 2A and FIGS. 2B are perspective views showing the display panel of FIG. 1 extended in a first direction.

[0029] FIG. 2c is a perspective view showing the display panel of FIG. 1 extended in a second direction.

[0030] FIG. 2d is a perspective view showing the display panel of FIG. 1 extended in the first direction and the second direction.

[0031] FIG. 2e is a perspective view showing the display panel of FIG. 1 extended in a third direction.

[0032] FIG. 3 is a schematic plan view showing the display area of ​​a display panel according to one or more embodiments.

[0033] Figure 4 is a cross-sectional view showing the first region of Figure 3.

[0034] FIGS. 5a to 5c are equivalent circuit diagrams of pixels of a display panel according to one or more embodiments.

[0035] FIGS. 6a to 6e are cross-sectional views schematically showing light-emitting diodes of a display panel according to one or more embodiments.

[0036] FIG. 7 is a schematic plan view showing a portion of the display area of ​​a display panel according to one or more embodiments.

[0037] FIG. 8 is a plan view schematically showing a portion of the display area of ​​a display panel according to one or more embodiments.

[0038] FIG. 9 is a plan view showing a portion of a display panel according to one or more embodiments.

[0039] Figure 10 shows a cross-section of a display panel along the X-X' line of Figure 9.

[0040] FIG. 11a is an enlarged cross-sectional view of the XIA portion of FIG. 10.

[0041] FIG. 11b is a schematic perspective view of FIG. 11a.

[0042] FIGS. 12a and FIGS. 12b are cross-sectional views of a display panel along the line XII-XII' of FIGS. 9, respectively.

[0043] FIG. 13 is a cross-sectional view showing a part of a display panel according to one or more embodiments, which may correspond to a cross-section along the line X-X' of FIG. 9.

[0044] FIGS. 14a to 14h are cross-sectional views illustrating a process according to a method for manufacturing a display panel according to one or more embodiments.

[0045] FIG. 15 is a schematic perspective view of an embodiment of an electronic device including a display panel according to one or more embodiments.

[0046] FIG. 16 is a block diagram showing an electronic device including a display panel according to one or more embodiments.

[0047] FIGS. 17 and FIGS. 18 are perspective views showing an electronic device according to one or more embodiments, respectively.

[0048] According to one or more embodiments, a base layer; a first pixel circuit layer disposed on the base layer and comprising transistors and insulating layers; a second pixel circuit layer disposed on the base layer and spaced apart from the first pixel circuit layer and comprising transistors and insulating layers; a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; and a protective layer on the first light-emitting diode and the second light-emitting diode, wherein the insulating layers of each of the first pixel circuit layer and the second pixel circuit layer comprise an inorganic insulating stack comprising inorganic insulating layers, and a first organic insulating layer disposed on the inorganic insulating stack, wherein the first organic insulating layer of the first pixel circuit layer and the first organic insulating layer of the second pixel circuit layer are spaced apart from each other, and the first pixel circuit layer A display panel is disclosed in which the first organic insulating layer comprises first grooves arranged along the edges, wherein a portion of the protective layer is disposed in each of the first grooves.

[0049] According to one or more embodiments, the invention comprises a base layer including a first surface and a second surface opposite to the first surface; a first pixel circuit layer disposed on the first surface of the base layer and including transistors and insulating layers; a second pixel circuit layer disposed on the first surface of the base layer and spaced apart from the first pixel circuit layer and including transistors and insulating layers; a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; a protective layer on the first light-emitting diode and the second light-emitting diode; a first line electrically connected to the transistor of the first pixel circuit layer; a second line electrically connected to the transistor of the second pixel circuit layer; and a connecting line electrically connecting the first line and the second line, wherein each of the first pixel circuit layer and the second pixel circuit layer Insulating layers include a first organic insulating layer, wherein the first organic insulating layer of the first pixel circuit layer and the first organic insulating layer of the second pixel circuit layer are spaced apart from each other, and the first organic insulating layer of the first pixel circuit layer includes a first groove located at the edge of the first organic insulating layer, wherein the first groove includes a first portion having a first width and a second portion having a second width different from the first width, and a portion of the protective layer exists within the first groove, thereby disclosing a display panel.

[0050] In one or more embodiments, the electronic device comprises a display panel, wherein the display panel comprises a base layer, a first pixel circuit layer disposed on the base layer and comprising transistors and insulating layers, a second pixel circuit layer disposed on the base layer and spaced apart from the first pixel circuit layer and comprising transistors and insulating layers, a first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer, a second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer, and a protective layer on the first light-emitting diode and the second light-emitting diode, wherein the insulating layers of each of the first pixel circuit layer and the second pixel circuit layer comprise an inorganic insulating stack comprising inorganic insulating layers, and a first organic insulating layer disposed on the inorganic insulating stack, and the first organic insulating layer of the first pixel circuit layer and the first organic insulating layer of the second pixel circuit layer The first organic insulating layer of the first pixel circuit layer is spaced apart from each other and includes first grooves arranged along the edges, wherein a portion of the protective layer is in each of the first grooves.

[0051] Now, reference is made to the embodiments illustrated in the accompanying drawings, where the same reference numerals refer to the same elements throughout. In this regard, the embodiments may take other forms and should not be interpreted as being limited to the description provided herein. Accordingly, embodiments of the invention are described below only to explain aspects of the invention with reference to the drawings. The term "and / or" as used herein includes any combination of one or more of the related listed items. Throughout this specification, the expressions "at least one of a, b, or c" or "at least one of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all a, b, and c, or variations thereof.

[0052] As this specification allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the drawings and described in detail in the written description. The effects and features of the invention and the methods for achieving them will become more apparent through the embodiments described in detail with reference to the drawings. However, the invention is not limited to the following embodiments and may be implemented in various forms.

[0053] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In describing the embodiments with reference to the attached drawings, identical or corresponding components are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0054] In the following embodiments, terms such as "first," "second," etc. are not used in a restrictive sense and are used to distinguish one component from another.

[0055] As used herein, the singular forms (“a,” “an,” and “the”) are intended to include the plural forms unless the context clearly indicates otherwise.

[0056] You will better understand that the terms “comprising” and / or “comprising” as used in this specification specify the presence of the mentioned feature or element, and do not exclude the presence or addition of one or more other features or elements.

[0057] When a layer, region, or element is referred to as being "on" another layer, region, or element, it is better understood that this may be directly above the other layer, region, or element, but there may also be a layer, region, or element interposed between them.

[0058] Additionally, the size of elements in the drawings may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of elements in the drawings are depicted arbitrarily for convenience of explanation, and the present disclosure is not necessarily limited thereto.

[0059] If specific embodiments are implemented differently, specific process sequences may be performed differently from the order described herein. For example, two processes described consecutively may be performed substantially concurrently (e.g., simultaneously) or in an order opposite to the specified order.

[0060] When it is mentioned that layers, regions, or elements are connected to one another, it will be better understood that they may be directly connected to one another or indirectly connected through layers, regions, or elements. For example, when it is mentioned that layers, regions, or elements are electrically connected to one another, they may be directly electrically connected to one another or indirectly electrically connected through layers, regions, or elements.

[0061] Those skilled in the art will understand that, considering the whole of the invention, each suitable feature of the various embodiments of the invention may be combined or combined with one another, either partially or wholly, and may be technically linked and operated in various suitable ways, and that each embodiment may be implemented independently of one another or combined with one another in any suitable way unless otherwise specified or implied.

[0062] FIG. 1 is a schematic perspective view of a display panel (10) according to one or more embodiments. FIG. 2a and FIG. 2b are perspective views showing the display panel (10) of FIG. 1 extended in a first direction. FIG. 2c is a perspective view showing the display panel (10) of FIG. 1 extended in a second direction. FIG. 2d is a perspective view showing the display panel (10) of FIG. 1 extended in the first direction and the second direction. FIG. 2e is a perspective view showing the display panel (10) of FIG. 1 extended in a third direction.

[0063] Referring to FIG. 1, a display panel (10) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a plurality of pixels. The display panel (10) may provide a predetermined image using light emitted from a plurality of pixels. The non-display area (NDA) may be placed on the edge of the display area (DA) or on the outside of the display area (DA) around the periphery. The non-display area (NDA) may completely surround the display area (DA).

[0064] The display panel (10) may be extended or retracted in various directions. The display panel (10) may be extended in a first direction (e.g., x direction and / or -x direction) by an external force applied by an external object or a user. In one or more embodiments, the display area (DA) and / or non-display area (NDA) of the display panel (10) may be extended in a first direction (e.g., x direction and / or -x direction), as shown in FIG. 2a and FIG. 2b. For example, it may be extended along the x direction and -x direction as shown in FIG. 2a, or extended along the x direction while one side of the display panel (10) remains fixed, as shown in FIG. 2b.

[0065] The display panel (10) may be extended in a second direction (e.g., the y direction and / or the -y direction) by an external force applied by an external object or a user. In one or more embodiments, the display area (DA) and / or non-display area (NDA) of the display panel (10) may be extended in the y direction and the -y direction, as shown in FIG. 2c. In another embodiment, one side of the display panel (10) may be fixed while being extended in the y direction or the -y direction.

[0066] The display panel (10) can be extended in multiple directions, such as a first direction (e.g., x direction and / or -x direction) and a second direction (e.g., y direction and / or -y direction) by an external force applied by an external object or a part of a person's body. As shown in FIG. 2d, the display area (DA) and / or non-display area (NDA) of the display panel (10) can be extended in the ±x direction and ±y direction.

[0067] The display panel (10) may be extended in a third direction (e.g., the z direction or the -z direction) by an external force applied by an external object or a part of a person's body. In one or more embodiments, FIG. 2e illustrates that a part of the display panel (10), such as a part of the display area (DA), protrudes in the z direction. In another embodiment, a part of the display panel (10), such as a part of the display area (DA), may protrude along the z direction (or be sunken along the -z direction).

[0068] FIGS. 2a to 2e illustrate a display panel (10) extended in a first direction (e.g., ±x direction), a second direction (e.g., ±y direction), and / or a third direction (e.g., ±z direction), but the present invention is not limited thereto. In other embodiments, the display panel (10) may be deformed into various irregular shapes, such as having two or more axes, such as being bent or twisted.

[0069] FIG. 3 is a schematic plan view showing a display area (DA) of a display panel (10) according to one or more embodiments, and FIG. 4 is a cross-sectional view showing a first area of ​​FIG. 3.

[0070] Referring to FIG. 3, the display area (DA) may include first areas (11) and a second area (12) surrounding each of the first areas (11). The first areas (11) may be arranged repeatedly along a first direction (e.g., x-direction) and a second direction (e.g., y-direction).

[0071] The display area (DA) may include a first area (11) and a second area (12) with different elongation rates. For example, the display panel (10) may include a first area (11) with a relatively small elongation rate and a second area (12) with a relatively large elongation rate. In this specification, elongation rate is a numerical value representing the change in length (ΔL / L) by which the display panel (10) can be stretched without physical damage to the display panel (10) when an external force is applied to the display panel (10). Here, ΔL is the amount of change in length of the display panel (10), and L represents the initial length of the display panel (10). Accordingly, the elongation rate of each of the first area (11) and the second area (12) may represent the change in length of each of the first area (11) and the second area (12) when the same external force is applied to the first area (11) and the second area (12).

[0072] The fact that the elongation rate of the first region (11) is smaller than the elongation rate of the second region (12) indicates that the deformation of the first region (11) due to external force occurs relatively less. Therefore, the first region (11) can be called a low-deformation region and the second region (12) can be called a high-deformation region.

[0073] The first regions (11) may be spaced apart from each other (e.g., spaced apart) and arranged two-dimensionally in the display area (DA). The first region (11) may be an area where pixels are placed, and thus the first region (11) may be referred to as a pixel area or a light-emitting area. One or more pixels may be placed in each first region (11). The first region (11) may be provided with a pixel unit (PU) that is a set of pixels, and each pixel unit (PU) may include a red pixel (PXr), a green pixel (PXg), and a blue pixel (PXb).

[0074] The red pixel (PXr), green pixel (PXg), and blue pixel (PXb) may each include a first light-emitting diode (LED1), a second light-emitting diode (LED2), and a third light-emitting diode (LED3). Referring to FIG. 4, the first region (11) of the display panel (10) may include a pixel circuit (PC) disposed on a base layer (400), an inorganic insulating stack (IIL), an organic insulating layer (OIL), first to third light-emitting diodes (LED1, LED2, LED3) electrically connected to the pixel circuit (PC), and a protective layer (300). The elongation rate of the first region (11) may be relatively smaller than the elongation rate of the second region (12) due to the stacked structure of pixel circuits (PCs), inorganic insulating stack (IIL), organic insulating layer (OIL), and first to third light-emitting diodes (LED1, LED2, LED3) arranged in the first region (11).

[0075] The second region (12) may be located between adjacent first regions (11). As illustrated in FIG. 3, the second region (12) may have a shape that surrounds each first region (11). The second region (12) may be an area through which a connection line passes to connect a line electrically connected to each of the pixel circuits (PC, FIG. 4) placed in each of the two adjacent first regions (11).

[0076] FIGS. 5a to 5c are equivalent circuit diagrams of pixels of a display panel according to one or more embodiments.

[0077] Referring to FIG. 5a, a light-emitting diode (LED) corresponding to a pixel is electrically connected to a pixel circuit (PC), and the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel circuit (PC) may be electrically connected to signal lines and voltage lines. The signal lines may include a scan signal line (GWL) and a data line (DL), and the voltage lines may include a first voltage line (VDDL) and a second voltage line (VSSL).

[0078] The second transistor (T2) can be electrically connected to the scan signal line (GWL) and the data line (DL). The scan signal line (GWL) can provide a scan signal (GW) to the gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the scan signal (GW) input from the scan signal line (GWL).

[0079] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power supply voltage (VDD) supplied by the first voltage line (VDDL).

[0080] The first transistor (T1) is a driving transistor capable of controlling the driving current flowing through the light-emitting diode (LED). The first transistor (T1) can be connected to the first voltage line (VDDL) and the light-emitting diode (LED). The first transistor (T1) can control the driving current flowing from the first voltage line (VDDL) to the light-emitting diode (LED) in correspondence with the voltage value stored in the storage capacitor (Cst) connected to the first transistor (T1). The light-emitting diode (LED) can emit light having a predetermined brightness by the driving current. The first electrode of the light-emitting diode (LED) is electrically connected to the first transistor (T1), and the second electrode can be electrically connected to the second voltage line (VSSL) that supplies the second power supply voltage (VSS).

[0081] FIG. 5a illustrates a pixel circuit (PC) comprising two transistors and one storage capacitor, but in other embodiments, the pixel circuit (PC) may comprise three or more transistors.

[0082] Referring to FIG. 5b, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0083] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a scan signal line (GWL), a bypass control line (GBL), an initialization control line (GIL), and an emission control line (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a first voltage line (VDDL), and a second voltage line (VSSL).

[0084] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC).

[0085] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and receives a data signal (Dm) from the first electrode of the first transistor connected to the first node (N1) according to the switching operation of the second transistor (T2), and supplies a driving current to the light-emitting diode (LED).

[0086] The second transistor (T2) is a data write transistor and is electrically connected to the scan signal line (GWL) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0087] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) can be connected between the second electrode and the gate electrode of the first transistor (T1). The third transistor (T3) can be turned on according to the scan signal (GW) received through the scan signal line (GWL) to diode-connect the first transistor (T1).

[0088] The fourth transistor (T4) is the first initialization transistor and is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1), thereby initializing the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0089] The fifth transistor (T5) may be an operation control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light emission control line (EML) and are turned on concurrently (e.g., simultaneously) according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED). The first electrode of the light-emitting diode (LED) may be electrically connected to the first transistor (T1) through the sixth transistor (T6), and the second electrode may be electrically connected to the second voltage line (VSSL) that supplies the second power supply voltage (VSS).

[0090] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can initialize the first electrode of the light-emitting diode (LED) by transmitting the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED).

[0091] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0092] Referring to FIG. 5c, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0093] The pixel circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a scan signal line (GWL), a bypass control line (GBL), an initialization control line (GIL), and an emission control line (EML), and data lines (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a hold voltage line (VSL), a first voltage line (VDDL), and a second voltage line (VSSL).

[0094] The first voltage line (VDDL) can transmit a first power supply voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) that initializes the first electrode of the light-emitting diode (LED) to the pixel circuit (PC). The holding voltage line (VSL) can provide a holding voltage (VSUS) to the second electrode (CE2) of the second node (N2), for example, the storage capacitor (Cst), during the initialization period and the data writing period.

[0095] The first transistor (T1) can be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and can be electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and can receive a data signal (Dm) according to the switching operation of the second transistor (T2) and supply a driving current to the light-emitting diode (LED).

[0096] The second transistor (T2) is electrically connected to the scan signal line (GWL) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0097] The third transistor (T3) is electrically connected to the scan signal line (GWL) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the scan signal (GW) received through the scan signal line (GWL) and connects the first transistor (T1) to the diode, thereby compensating for the threshold voltage of the first transistor (T1).

[0098] The fourth transistor (T4) is electrically connected to the initialization control line (GIL) and the first initialization voltage line (VIL1), and is turned on according to the initialization control signal (GI) received through the initialization control line (GIL) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The initialization control signal (GI) may correspond to a scan signal of another pixel circuit placed in the previous row of the corresponding pixel circuit (PC).

[0099] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the light emission control line (EML) and are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting diode (LED). The first electrode of the light-emitting diode (LED) is electrically connected to the first transistor (T1) through the sixth transistor (T6), and the second electrode can be electrically connected to the second voltage line (VSSL) that supplies the second power supply voltage (VSS).

[0100] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the bypass control line (GBL), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting diode (LED) to initialize the first electrode of the light-emitting diode (LED).

[0101] The ninth transistor (T9) can be electrically connected to the bypass control line (GBL), the second electrode (CE2) of the storage capacitor (Cst), and the holding voltage line (VSL). The ninth transistor (T9) is turned on according to the bypass control signal (GB) received through the bypass control line (GBL), and can transmit a holding voltage (VSUS) to the second node (N2), such as the second electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0102] The eighth transistor (T8) and the ninth transistor (T9) may each be electrically connected to the second node (N2), for example, the second electrode (CE2) of the storage capacitor (Cst). In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on during the initialization period and the data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off during the light emission period.

[0103] The storage capacitor (Cst) includes a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0104] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the holding voltage line (VSL), and the first electrode of the light-emitting diode (LED). By storing and maintaining a voltage corresponding to the voltage difference between the first electrode of the light-emitting diode (LED) and the holding voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, the auxiliary capacitor (Ca) can prevent the problem of the black brightness rising when the sixth transistor (T6) is turned off.

[0105] FIGS. 6a and FIGS. 6e are cross-sectional views schematically showing a light-emitting diode of a display panel according to one or more embodiments.

[0106] Referring to FIG. 6a, the light-emitting diode (LED) may include an inorganic light-emitting diode containing an inorganic material. The light-emitting diode (LED) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may each be electrically connected to a first electrode pad (241) and a second electrode pad (242) disposed on the same layer. The second electrode pad (242) may be a part of the second voltage line (VSSL, FIG. 5a) or a conductive layer electrically connected to the second voltage line (VSSL, FIG. 5a).

[0107] In one or more embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from a semiconductor material having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, and / or Ba.

[0108] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having the compositional formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with an n-type dopant such as Si, Ge, and / or Sn.

[0109] The intermediate layer (233) is a region where electrons and holes recombine, and as electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including a semiconductor material having, for example, the composition formula InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well (MQW) structure. Additionally, the intermediate layer (233) may include a quantum wire structure and / or a quantum dot structure.

[0110] FIG. 6a illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, but the present invention is not limited thereto. In another embodiment, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0111] FIG. 6a illustrates that the first electrode pad (241) and the second electrode pad (242) are disposed on the same layer, but the present invention is not limited thereto. Referring to FIG. 6b, the first electrode pad (241) and the second electrode pad (242) may be disposed on different layers. For example, a bank layer (230) having an opening that overlaps with at least a portion of the first electrode pad (241) may be disposed on the first electrode pad (241), and the second electrode pad (242) may be disposed on the upper surface of the bank layer (230). The structure of the light-emitting diode (LED) shown in FIG. 6b is the same as previously described with reference to FIG. 6a.

[0112] In another embodiment, as shown in FIG. 6c, the second electrode pad (242) may be positioned on both sides centered on the first electrode pad (241) in a cross-sectional view. The bank layer (230) includes an opening that overlaps at least a portion of the first electrode pad (241), and the second electrode pad (242) may be positioned in the bank layer (230) around the first electrode pad (241). In one or more embodiments, the second electrode pad (242) may have a closed-loop shape that completely surrounds the opening of the bank layer (230) and / or the first electrode pad (241) in a planar view. The structure of the light-emitting diode (LED) shown in FIG. 6c is the same as previously described with reference to FIG. 6a.

[0113] FIGS. 6a to 6c illustrate the first electrode (235) and the second electrode (238) of a light-emitting diode (LED) facing in the same direction (e.g., downward direction, -z direction), but the present invention is not limited thereto. As shown in FIG. 6d, the first electrode (235) and the second electrode (238) of the light-emitting diode (LED) may face in opposite directions.

[0114] The bank layer (230) includes an opening that exposes at least a portion of the first electrode pad (241), and the thickness of the bank layer (230) may be substantially the same as the thickness of the light-emitting diode (LED). The opening of the bank layer (230) may be filled with a filling material (FM), and the second electrode pad (242) may be disposed on the upper surface of the bank layer (230) so as to be electrically connected (e.g., in contact) with the second electrode (238) of the light-emitting diode (LED). The filling material may be an organic material having insulating properties.

[0115] FIGS. 6a to 6d illustrate that the light-emitting diode (LED) includes an inorganic light-emitting diode containing an inorganic material, but the present invention is not limited thereto. Referring to FIG. 6e, the light-emitting diode (LED) may include an organic light-emitting diode (OLED) containing an organic material. For example, the light-emitting diode (LED) may include a first electrode pad (or first electrode, 241), an organic light-emitting layer (243) that overlaps with the first electrode pad (241) through an opening of a bank layer (230) disposed on the first electrode pad (241), and a second electrode pad (or second electrode, 242) on the organic light-emitting layer (243). The second electrode pad (242) may be shared among a single light-emitting diode (LED). In other words, the second electrode pad (242) of one light-emitting diode (LED) can be integrally connected with the second electrode pad (242) of another light-emitting diode (LED).

[0116] FIG. 7 is a schematic plan view showing a portion of a display area (DA) of a display panel (10) according to one or more embodiments. FIG. 7 shows conductive lines (L, hereinafter referred to as lines) electrically connected to pixel circuits (PCs) placed in the display area (DA). The pixel circuits (PCs) placed in each first area (11) shown in FIG. 7 may be electrically connected to light-emitting diodes corresponding to the pixels (PXr, PXg, PXb) described with reference to FIG. 3.

[0117] Referring to FIG. 7, a pixel circuit (PC) for driving the light-emitting diode of each pixel may be placed in a first area (11). In this regard, FIG. 7 illustrates three pixel circuits (PCs) placed in the first area (11). Each pixel circuit (PC) may include a transistor and a capacitor, as described above with reference to FIG. 5a to 5c.

[0118] The first region (11) may have a smaller elongation rate than the second region (12). Accordingly, when the display panel (10) is stretched, the first region (11) may undergo less deformation than the second region (12). The first region (11) may be referred to as a low-deformation region (or low-deformation part) as previously described. The first region (11) may be referred to as a pixel region or a light-emitting region as the area where light-emitting diodes are arranged.

[0119] The second region (12) surrounds the first region (11) and may have a greater elongation rate than the first region (11). The second region (12) may be an area where the main deformation occurs according to the expansion and contraction of the display device. Since the second region (12) is positioned between a plurality of first regions (11), it may be referred to as a connecting part that connects the first regions (11). The second region (12) may be referred to as a main deformation area (or a peripheral deformation part) or a high deformation area (or a high deformation part). The second region (12) may be referred to as a non-pixel area or a non-luminous area, as it is an area within the display region where a light-emitting diode is not positioned.

[0120] Lines (L) electrically connected to the pixel circuit (PC) may be placed in the display area (DA). In one or more embodiments, FIG. 7 illustrates lines (L) extended in a first direction (e.g., x direction or -x direction) and lines (L) extended in a second direction (e.g., y direction or -y direction) being electrically connected to the pixel circuit (PC). Each of the lines (L) may be electrically connected to the pixel circuit (PC) through a contact hole (not shown).

[0121] Any one line (L) placed in the first region (11) may be electrically connected to any one line (L) placed in the adjacent first region (11) via a connection line (WL). The aforementioned lines (L) may include voltage lines or signal lines. The lines (L) may include gate lines, data lines, and / or voltage lines that provide a gate signal to the gate electrode of a transistor. In one or more embodiments, lines (L) extended in the first direction of FIG. 7 (e.g., x direction or -x direction) may include gate lines (e.g., scan signal line (GWL), bypass control line (GBL), initialization control line (GIL), light emission control line (EML) and / or similar ones) and / or second voltage lines (VSSL) as previously described with reference to FIG. 5a through 5c. Lines (L) extended in a second direction (e.g., y direction or -y direction) may include the data line (DL), the first initial voltage line (VIL1), the second initial voltage line (VIL2), the holding voltage line (VSL), and / or the first voltage line (VDDL) described with reference to FIGS. 5a through 5c.

[0122] The connecting line (WL) placed in the second area (12) can be stretched better than the lines (L) placed in the first area (11). The elongation rate of each connecting line (WL) can be greater than the elongation rate of each line (L).

[0123] The lines (L) may each comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). In one or more embodiments, the lines (L) may each be a single layer or a plurality of layers comprising the aforementioned metals. In one or more embodiments, the lines (L) may each comprise a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0124] The connecting line (WL) may include liquid metal or a conductive composite material including a metal nanostructure, an elastic polymer, and / or an elastomer. Thus, when the display panel (10, FIG. 1) is stretched, high deformation may occur in the connecting line (WL) and the second region (12).

[0125] FIG. 8 is a schematic plan view showing a portion of the display area (DA) of a display panel (10) according to one or more embodiments.

[0126] The embodiment described with reference to FIG. 7 illustrates that the connecting line (WL) is a straight line in a plane, but the present invention is not limited thereto. As shown in FIG. 8, the connecting line (WL) may have a shape that is not a straight line in a plane. The display panel (10) according to one or more embodiments of FIG. 8 differs in the shape of the connecting line (WL) in a plane, while other configurations are identical to the embodiment described above with reference to FIG. 7. Hereinafter, identical descriptions will be omitted and the focus will be on the differences.

[0127] Referring to FIG. 8, each connecting line (WL) may have a serpentine shape in a plane. For example, each connecting line (WL) may have a wave shape with two or more inflection points. When the connecting line (WL) has a serpentine shape, deformation or damage to the connecting line (WL) can be effectively prevented when the second region (12) is stretched. FIG. 8 illustrates the connecting line (WL) having a gentle C-shape in a plane, but in other embodiments, the connecting line (WL) may have a wave shape such as having an S-shape in a plane.

[0128] FIG. 9 is a plan view showing a portion of a display panel according to one or more embodiments, and FIG. 10 shows a cross-section along the line X-X' of FIG. 9. FIG. 11a is an enlarged cross-sectional view showing a portion XIA of FIG. 10, and FIG. 11b is a perspective view schematically showing FIG. 11a.

[0129] Referring to FIG. 9, light-emitting diodes disposed in the first region (11), such as first to third light-emitting diodes (LED1, LED2, LED3, FIG. 9), can be electrically connected to pixel circuits (PC, FIG. 7) described with reference to FIG. 7. An inorganic insulating stack (IIL) and an organic insulating layer (OIL) are disposed in the first region (11). The first to third light-emitting diodes (LED1, LED2, LED3) can be disposed on the inorganic insulating stack (IIL) and the organic insulating layer (OIL).

[0130] Referring to FIG. 9, the display panel (10) may include a second region (12) located between the first regions (11), as previously described with reference to FIG. 7. Since the components of the display panel (10) are placed on a base layer (400) as shown in FIG. 10, the statement that the display panel (10) includes a first region (11) and a second region (12) corresponds to the base layer (400) including a first region (11) and a second region (12).

[0131] Referring to FIG. 10, the display panel (10) may include a pixel circuit layer (PCL) and a light-emitting diode (LED) on the pixel circuit layer (PCL) disposed in each of two adjacent first regions (11). The light-emitting diode (LED) disposed on each of the pixel circuit layers (PCL) shown in FIG. 10 may correspond to any one of the first to third light-emitting diodes (LED1, LED2, LED3) shown in FIG. 9.

[0132] Each pixel circuit layer (PCL) may include an inorganic insulating stack (IIL), a pixel circuit (PC), and an organic insulating layer (OIL). For convenience of explanation, one of the pixel circuit layers (PCLs) disposed in each of two adjacent first regions (11) is referred to as the first pixel circuit layer (PCL1), and the other as the second pixel circuit layer (PCL2).

[0133] The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may each be disposed on the base layer (400). The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may each be disposed on the first surface (e.g., the top surface) of the base layer (400).

[0134] The base layer (400) can absorb stress generated during the stretching of the display panel (10). The base layer (400) may include an elastomer. The base layer (400) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), and / or Ecoflex TM (Ecoflex TM It may include (which is a registered trademark of Smooth-On Inc.).

[0135] Each of the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may include an inorganic insulating stack (IIL), a pixel circuit (PC), and an organic insulating layer (OIL). The inorganic insulating stack (IIL) may include a buffer layer (111), a gate insulating layer (113), a first interlayer insulating layer (115), and a second interlayer insulating layer (117). The organic insulating layer (OIL) may include a first organic insulating layer (121) and a second organic insulating layer (123).

[0136] The inorganic insulating stack (IIL) and the organic insulating layer (OIL) may each have an isolated shape as shown in FIG. 9. The inorganic insulating stack (IIL) and the organic insulating layer (OIL) may each be placed in the first region (11). The second region (12), where the inorganic insulating stack (IIL) and the organic insulating layer (OIL) are not present, may be relatively prone to deformation.

[0137] The first region (11) may be defined as the region when an inorganic insulating stack (IIL) and an organic insulating layer (OIL) are projected along a direction perpendicular to the base layer (400). In one or more embodiments, when the width (Wi) of the inorganic insulating stack (IIL) is smaller than the width (Wo) of the organic insulating layer (OIL), the width of the organic insulating layer (OIL) may correspond to the width of the first region (11).

[0138] The first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) may be spaced apart from each other. The statement that the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) are spaced apart from each other may indicate that the inorganic insulating stack (IIL), pixel circuit (PC), and organic insulating layer (OIL) of the first pixel circuit layer (PCL1) are spaced apart from the inorganic insulating stack (IIL), pixel circuit (PC), and organic insulating layer (OIL) of the second pixel circuit layer (PCL2), respectively.

[0139] The inorganic insulating stack (IIL) may be placed in the first region (11) and may not be placed in the second region (12). The inorganic insulating stack (IIL) placed in each of the first regions (11) may be spaced apart from each other in a plane. For example, the buffer layer (111), gate insulating layer (113), first interlayer insulating layer (115), and second interlayer insulating layer (117) of the first pixel circuit layer (PCL1) may be separated and spaced apart from the buffer layer (111), gate insulating layer (113), first interlayer insulating layer (115), and second interlayer insulating layer (117) of the second pixel circuit layer (PCL2), respectively.

[0140] Likewise, the organic insulating layer (OIL) may be placed in the first region (11) and not in the second region (12). For example, the first organic insulating layer (121) and the second organic insulating layer (123) of the first pixel circuit layer (PCL1) may be separated and spaced apart from the first organic insulating layer (121) and the second organic insulating layer (123) of the second pixel circuit layer (PCL2), respectively.

[0141] As illustrated in FIG. 10, the buffer layer (111) is disposed on the base layer (400), and the pixel circuit (PC) may be disposed on the buffer layer (111). The buffer layer (111) may include an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0142] The thin-film transistor (TFT) of the pixel circuit (PC) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). FIG. 10 illustrates a top-gate type in which the gate electrode (GE) is placed on the semiconductor layer (Act) with the gate insulating layer (113) in between, but according to another embodiment, the thin-film transistor (TFT) may be a bottom-gate type.

[0143] The semiconductor layer (Act) may include polysilicon. Alternatively, the semiconductor layer (Act) may include amorphous silicon, an oxide semiconductor, and / or an organic semiconductor, etc. The gate electrode (GE) may include a metal thin film composed of a low-resistance metal material. The gate electrode (GE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the gate electrode (GE) may include a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0144] The gate insulating layer (113) between the semiconductor layer (Act) and the gate electrode (GE) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The gate insulating layer (113) may be a single layer or a multilayer containing the aforementioned materials.

[0145] The source electrode (SE) and the drain electrode (DE) may be located on the same layer, for example, the second interlayer insulating layer (117), and may contain the same material. The source electrode (SE) and the drain electrode (DE) may contain a metal thin film composed of a low-resistance metal material. The source electrode (SE) and the drain electrode (DE) may be connected to the source region and the drain region of the semiconductor layer (Act), respectively.

[0146] The source electrode (SE) and drain electrode (DE) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the source electrode (SE) and drain electrode (DE), like the gate electrode (GE), may be provided as a metal thin film formed as a triple layer of titanium (Ti) / aluminum (Al) / titanium (Ti) structure. The second interlayer insulating layer (117) may include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer including the above materials.

[0147] A storage capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2) that overlap with a first interlayer insulating layer (115) in between. The storage capacitor (Cst) may overlap with a thin-film transistor (TFT). In this regard, FIG. 10 illustrates that the gate electrode (GE) of the thin-film transistor (TFT) is the first electrode (CE1) of the storage capacitor (Cst). In another embodiment, the storage capacitor (Cst) may not overlap with the thin-film transistor (TFT). The storage capacitor (Cst) may be covered by a second interlayer insulating layer (117).

[0148] The first interlayer insulating layer (115) may be disposed between the gate insulating layer (113) and the second interlayer insulating layer (117). The first interlayer insulating layer (115) and the second interlayer insulating layer (117) may each include an inorganic insulating material such as silicon oxide, nitrogen oxide, silicon oxynitride, aluminum oxide, or titanium oxide, and may be a single layer or a multilayer containing the aforementioned materials.

[0149] The second electrode (CE2) of the storage capacitor (Cst) may include a conductive material and may be formed as a multilayer or single layer. The second electrode (CE2) may include a metal thin film composed of a low-resistance metal material. The second electrode (CE2) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the second electrode (CE2) may be provided with a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0150] The first organic insulating layer (121) may be disposed on the second interlayer insulating layer (117). The second organic insulating layer (123) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) and the second voltage line (VSSL) may be disposed on the first organic insulating layer (121). The connecting electrode (CM) may electrically connect the pixel circuit (PC) and the first electrode pad (241). The second voltage line (VSSL) may be electrically connected to the second electrode pad (242).

[0151] The connecting electrode (CM) and the second voltage line (VSSL) may include a metal thin film composed of a low-resistance metal material. The connecting electrode (CM) and the second voltage line (VSSL) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be formed as a multilayer or single layer including the above materials. For example, the connecting electrode (CM) and the second voltage line (VSSL) may be provided with a metal thin film formed as a triple layer of a titanium (Ti) / aluminum (Al) / titanium (Ti) structure.

[0152] The first electrode pad (241) and the second electrode pad (242) may be disposed on the second organic insulating layer (123). The first electrode pad (241) may be electrically connected to a thin-film transistor (TFT) through a connecting electrode (CM) between the first organic insulating layer (121) and the second organic insulating layer (123).

[0153] The light-emitting diode (LED) on the first electrode pad (241) and the second electrode pad (242) may be the same as the light-emitting diode (LED) described above with reference to FIG. 6a. In another embodiment, the light-emitting diode (LED) may have a structure as shown in FIG. 6b to 6e. One side of the light-emitting diode (LED) may be covered with a protective material layer (240) that includes an organic insulator or an inorganic insulator and an organic insulator.

[0154] In one or more embodiments, the organic insulating layer (OIL) may further include a third organic insulating layer (119) positioned to cover the side of the inorganic insulating stack (IIL). The third organic insulating layer (119) may have a closed-loop shape in a planar form to cover the side of the inorganic insulating stack (IIL). The third organic insulating layer (119) may surround and / or overlap the edge (side) of the inorganic insulating stack (IIL). In other words, the third organic insulating layer (119) may have a frame shape in a planar form.

[0155] The line (L) described with reference to FIG. 9 can be electrically connected to the pixel circuit (PC) of the pixel circuit layer (PCL). In this regard, FIG. 10 illustrates that among the lines (L) of FIG. 9, a line (hereinafter referred to as the first line, L1) placed in one of the first regions (11) is electrically connected to the pixel circuit (PC) of the first pixel circuit layer (PCL1), and a line (hereinafter referred to as the second line, L2) placed in another first region (11) is electrically connected to the second pixel circuit layer (PCL2).

[0156] The first and second lines (L1, L2) of FIG. 10 may be signal lines or voltage lines. For example, the first and second lines (L1, L2) may be the gate line, data line (DL), first voltage line (VDDL), second voltage line (VSSL), first initialization voltage line (VIL1), second initialization voltage line (VIL2), holding voltage line (VSL), first voltage line (VDDL), or second voltage line (VSSL) described with reference to FIG. 5a to 5c.

[0157] Each of the first line (L1) and the second line (L2) is disposed on the interlayer insulation layer (117) and may extend toward the connection line (WL). For example, the first line (L1) and the second line (L2) may each extend toward the connection line (WL) by passing over the upper surface of the corresponding third organic insulation layer (119). A portion of each of the first line (L1) and the second line (L2) may be located between the third organic insulation layer (119) and the first organic insulation layer (121).

[0158] The first connection point between the first line (L1) and the connection line (WL), and the second connection point between the second line (L2) and the connection line (WL) may be located between the inorganic insulation stack (IIL) of the first pixel circuit layer (PCL1) and the inorganic insulation stack (IIL) of the second pixel circuit layer (PCL2). The first connection point between the first line (L1) and the connection line (WL) is a direct contact area between the first line (L1) and the connection line (WL) and does not overlap with the inorganic insulation stack (IIL) of the first pixel circuit layer (PCL1). The second connection point between the second line (L2) and the connection line (WL) is a direct contact area between the second line (L2) and the connection line (WL) and does not overlap with the inorganic insulation stack (IIL) of the second pixel circuit layer (PCL2).

[0159] The first organic insulating layer (121) corresponding to the first pixel circuit layer (PCL1) extends past the side of the inorganic insulating stack (IIL) toward the first connection point of the first line (L1) and the connection line (WL). The first organic insulating layer (121) corresponding to the second pixel circuit layer (PCL2) may extend past the side of the inorganic insulating stack (IIL) toward the second connection point of the second line (L2) and the connection line (WL). In other words, the first connection point of the first line (L1) and the connection line (WL) may be covered by the first organic insulating layer (121) corresponding to the first pixel circuit layer (PCL1), and the second connection point of the second line (L2) and the connection line (WL) may be covered by the first organic insulating layer (121) corresponding to the second pixel circuit layer (PCL2).

[0160] At least a portion of each of the first line (L1) and the second line (L2) (hereinafter referred to as the first portion) can be embedded within the connection line (WL), thereby increasing the contact area with the connection line (WL). Referring to FIGS. 11a and 11b, the first portion (L1A) of the first line (L1) can be embedded within the connection line (WL). The width (W0) of the connection line (WL) can be greater than the width (W1) of the first portion (L1A) of the first line (L1).

[0161] The bottom surface (bs) of the first part (L1A) of the first line (L1) and the side bent with respect to the bottom surface (bs) may come into direct contact with the connecting line (WL). For example, the bottom surface (bs) of the first part of the first line (L1), the first side (ss1) facing the first organic insulating layer (121), the second side (ss2) opposite the first side (ss1) and facing the inorganic insulating stack (IIL), the third side (ss3) between the first side (ss1) and the second side (ss2), and the fourth side (ss4) opposite the third side (ss3) may come into direct contact with the connecting line (WL). The first organic insulating layer (121) may extend over the first part (L1A) of the first line (L1). The first organic insulating layer (121) can be in direct contact with the upper surface (ts, FIG. 11b) of the first part (L1A) of the first line (L1).

[0162] The first thickness (tw1) of the first part of the connection line (WL) that overlaps with the first organic insulating layer (121) but does not overlap with the first part (L1A) of the first line (L1) may be greater than the second thickness (tw2) of the second part of the connection line (WL) located in the second region (12). The second part of the connection line (WL) having the second thickness (tw2) corresponds to the part located between the first organic insulating layer (121) of the first pixel circuit layer (PCL1) and the first organic insulating layer (121) of the second pixel circuit layer (PCL2).

[0163] The third thickness (tw3) of the third portion of the connection line (WL) overlapping with the third organic insulating layer (119) may be greater than the aforementioned second thickness (tw2). The fourth thickness (tw4) of the fourth portion of the connection line (WL) overlapping with the first portion (L1A) of the first line (L1), e.g., the bottom surface (bs), may be smaller than the aforementioned first thickness (tw1) and / or third thickness (tw3).

[0164] A portion of the connecting line (WL), for example, a portion of the connecting line (WL) that overlaps with the first organic insulating layer (121) and / or the third organic insulating layer (119) in the first region (11), may protrude further toward the third direction (e.g., z-direction) than a portion of the connecting line (WL) located in the second region (12). In other words, the upper surface of the connecting line (WL) may have a step. In other words, the upper surface (WL_ta) of the portion of the connecting line (WL) located in the first region (11) may be stepped relative to the upper surface (WL_tb) of the portion of the connecting line (WL) located in the second region (12). Also

[0165] FIGS. 11a and FIGS. 11b illustrate a first line (L1) and a connecting line (WL), but the present invention is not limited thereto. The structure of the second line (L2) and the connecting line (WL) is substantially the same as the structure of FIGS. 11a and FIGS. 11b.

[0166] Referring again to FIG. 10, the connection line (WL) may be embedded within the base layer (400). The base layer (400) may include a first surface (e.g., top surface) facing the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2), and a second surface (e.g., bottom surface) opposite it. The base layer (400) may include a recess (or concave portion, 400RC) that is concave with respect to the first surface, and the connection line (WL) may exist within the recess (400RC). For example, the connection line (WL) may fill the recess (400RC). As the connection line (WL) has a structure embedded in the base layer (400), the base layer (400) can absorb stress that may be concentrated on the connection line (WL) during the stretching of the display panel (10).

[0167] The connecting line (WL) includes a lower surface facing the base layer (400) and an upper surface opposite the lower surface. The upper surface of the connecting line (WL) may have a step as previously described with reference to FIGS. 11a and 11b. The lower surface of the connecting line (WL) facing the base layer (400) may have a level between the upper and lower surfaces of the base layer (400). The lower surface of the connecting line (WL) may have a substantially flat surface.

[0168] The lower surface of the base layer (400) may include a substantially flat surface, but the upper surface of the base layer (400) may include a step. The thickness (t1) of the first portion of the base layer (400) overlapping the connection line (WL) may be smaller than the thickness (t2) of the second portion of the base layer (400) overlapping the inorganic insulation stack (IIL).

[0169] In one or more embodiments, the thickness (t3) of the third portion of the base layer (400) disposed between the inorganic insulating stack (IIL) and the connection line (WL) may be greater than the thickness (t2) of the second portion of the base layer (400). The third portion of the base layer (400) may be in direct contact with a portion of the side of the inorganic insulating stack (IIL). FIG. 10 illustrates the third portion of the base layer (400) being in contact with the side of the buffer layer (111) of the inorganic insulating stack (IIL), but the invention is not limited thereto. In another embodiment, the third portion of the base layer (400) may be in direct contact with the side of the buffer layer (111) and the gate insulating layer (113), etc., of the inorganic insulating stack (IIL).

[0170] FIG. 10 illustrates that both edges of the connection line (WL) overlap with the third organic insulating layer (119), but the present invention is not limited thereto. In another embodiment, the connection line (WL) may be extended toward the inorganic insulating stack (IIL) such that both edges of the connection line (WL) overlap with the inorganic insulating stack (IIL) of the first and second pixel circuit layers (PCL1, PCL2), respectively. In this case, the connection line (WL) may come into direct contact with the bottom surface of the inorganic insulating stack (IIL).

[0171] A light-emitting diode (LED) can be placed on a pixel circuit layer (PCL). For example, a light-emitting diode (LED) electrically connected to a pixel circuit (PC) of a first pixel circuit layer (PCL1) can be placed on the corresponding first pixel circuit layer (PCL1), and a light-emitting diode (LED) electrically connected to a pixel circuit (PC) of a second pixel circuit layer (PCL2) can be placed on the corresponding second pixel circuit layer (PCL2). One side of each light-emitting diode (LED) can be covered with a protective material layer (240). The protective material layer (240) may include an organic insulating material such as polyimide.

[0172] A protective layer (300) may be placed on the light-emitting diode (LED) and the connection line (WL). The protective layer (300) may cover the light-emitting diode (LED) and the connection line (WL).

[0173] The protective layer (300) can absorb stress that may be transmitted to the light-emitting diode (LED) and the connection line (WL) during the stretching of the display panel (10), and can flatten the upper surface of the display panel (10). The protective layer (300) may include an elastomer. For example, the protective layer (300) is thermoplastic polyurethane, silicone, thermoplastic rubbers, elastolefin, thermoplastic olefin, polyamide, polyether block amide, synthetic polyisoprene, polybutadiene, chloroprene rubber, butyl rubber, styrene-butadiene, epichlorohydrin rubber, polyacrylic rubber, silicone rubber, fluorosilicone rubber, fluoroelastomers, ethylene-vinyl acetate, PDMS (polydimethylsiloxane), and / or Ecoflex TM (Ecoflex TM It may include (which is a registered trademark of Smooth-On Inc.).

[0174] In one or more embodiments, the protective layer (300) may be in direct contact with a portion of the upper surface of the connection line (WL) and may be in direct contact with a portion of the upper surface of the base layer (400) (e.g., a portion of the upper surface of the base layer (400) located between the connection line (WL) and the connection line (WL) shown in FIG. 9 and / or a similar portion thereof). In one or more embodiments, if the material of the protective layer (300) and the material of the base layer (400) are the same, the bonding strength between the protective layer (300) and the base layer (400) can be increased, thereby maintaining the airtightness of the display panel (10) more effectively.

[0175] FIGS. 12a and FIGS. 12b are cross-sectional views along the line XII-XII' of FIGS. 9, respectively.

[0176] The bottom surface (bs) and side of the first part of the line (L) can come into direct contact with the connecting line (WL), and in this regard, FIG. 12a illustrates the bottom surface (bs), third side (ss3), and fourth side (ss4) of the first part of the line (L) coming into direct contact with the connecting line (WL).

[0177] In one or more embodiments, as illustrated in FIG. 12a, the line (L) may be a single layer comprising metal. In one or more embodiments, as illustrated in FIG. 12b, the line (L) may have a multilayer structure comprising different metals. For example, the line (L) may include a first layer (La), a second layer (Lb) disposed on the upper surface of the first layer (La), and a third layer (Lc) disposed on the lower surface of the first layer (La). The connecting line (WL) may be in direct contact with the side of each of the first layer (La), the second layer (Lb), and the third layer (Lc), and the bottom surface of the third layer (Lc). FIG. 12b illustrates the line (L) comprising three layers, but the invention is not limited thereto. As another embodiment, the line (L) may include a two-layer structure of a first layer (La) and a second layer (Lb) disposed on the upper surface of the first layer (La).

[0178] The first layer (La) may comprise a material with a different etching selectivity than the second layer (Lb) and / or the third layer (Lc). For example, the first layer (La) may comprise aluminum, and the second layer (Lb) and / or the third layer (Lc) may comprise titanium. The second layer (Lb) may comprise a tip (PT) protruding laterally from the point where the side of the first layer (La) meets the bottom surface of the second layer (Lb). Similarly, the third layer (Lc) may comprise a tip (PT) protruding laterally from the point where the side of the first layer (La) meets the top surface of the third layer (Lc). A connecting line (WL) may come into direct contact with the side and bottom surfaces of the tips (PT) of the second layer (Lb) and the third layer (Lc), respectively. Since the second layer (Lb) and / or the third layer (Lc) includes a tip (PT) as described above, the bonding force between the connecting line (WL) and the line (L) can be increased. The structure of the tip (PT) of the second layer (Lb) may correspond to a type of anchor structure, and thus the bonding force between the connecting line (WL) and the line (L) that surrounds and contacts the side of the line (L) can be further enhanced.

[0179] FIG. 13 is a cross-sectional view showing a part of a display panel according to one or more embodiments, which may correspond to a cross-section along the line X-X' of FIG. 9.

[0180] The organic insulating layer (OIL) of the display panel (10) according to the embodiment described with reference to FIG. 10 includes a third organic insulating layer (119) covering the side of the inorganic insulating stack (IIL), but the present invention is not limited thereto. The organic insulating layer (OIL) of the display panel (10) according to the embodiment of FIG. 13 does not include the third organic insulating layer (119, FIG. 10). Since the display panel (10) according to the embodiment of FIG. 13 has a structure substantially identical to the structure described with reference to FIG. 10, the differences will be described below.

[0181] Referring to FIG. 13, the first line (L1) may extend along the connection line (WL) while in contact with the side of the corresponding inorganic insulating stack (IIL), and the second line (L2) may extend along the connection line (WL) while in contact with the side of the corresponding inorganic insulating stack (IIL). The first organic insulating layer (121) of the first pixel circuit layer (PCL1) may have a width greater than the width of the inorganic insulating stack (IIL). The first organic insulating layer (121) may cover the first connection point of the first line (L1) and the connection line (WL). Likewise, the first organic insulating layer (121) of the second pixel circuit layer (PCL2) may have a width greater than the width of the inorganic insulating stack (IIL). The first organic insulating layer (121) may cover the second connection point of the second line (L2) and the connection line (WL).

[0182] As previously described with reference to FIGS. 11a and 11b, the connecting line (WL) may come into direct contact with the bottom surface and side surface of the first portion of each of the first and second lines (L1, L2). The upper surface of the connecting line (WL) may include a stepped structure as described with reference to FIGS. 11a and 11b.

[0183] FIG. 13 illustrates a connection line (WL) in contact with a portion of the bottom surface of the first portion of each of the first and second lines (L1, L2), but the present invention is not limited thereto. In another embodiment, the connection line (WL) may extend onto the bottom surface of the inorganic insulating stack (IIL) of each of the first and second pixel circuit layers (PCL1, PCL2) and may contact the entire bottom surface of the first portion of each of the first and second lines (L1, L2).

[0184] FIGS. 14a to 14h are cross-sectional views illustrating a process according to a method for manufacturing a display panel according to one or more embodiments.

[0185] Referring to FIG. 14a, a carrier layer (LL) can be prepared. In one or more embodiments, the carrier layer (LL) may include a substrate (100) and a resin layer (110) disposed on the substrate (100). The substrate (100) may be a rigid substrate. For example, the substrate (100) may be a transparent glass substrate with SiO2 as the main component, or a substrate comprising a polymer resin material such as reinforced plastic. The resin layer (110) may include a polymer resin. For example, the resin layer (110) may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate cellulose acetate propionate, and / or such materials. In one or more embodiments, the thickness of the resin layer (110) may be greater than the thickness of the substrate (100).

[0186] On the carrier layer (LL), parts of an inorganic insulating stack (IIL), a storage capacitor (Cst), and a thin-film transistor (TFT, FIG. 10) may be formed. For example, on the carrier layer (LL), a buffer layer (111), a semiconductor layer (Act), a gate insulating layer (113), a gate electrode (GE), a first interlayer insulating layer (115), a second electrode (CE2), and a second interlayer insulating layer (117) may be formed.

[0187] The inorganic insulating stack (IIL) may be placed only in the first region (11) and not in the second region (12). For example, a portion of the inorganic insulating stack (IIL) that overlaps with the second region (12) may be removed through an etching process.

[0188] Referring to FIG. 14b, a third organic insulating layer (119) can be formed on the second interlayer insulating layer (117). The third organic insulating layer (119) can cover the side of the inorganic insulating stack (IIL). A source electrode (SE) and a drain electrode (DE) can be formed on the second interlayer insulating layer (117).

[0189] A first line (L1) and a second line (L2) may be formed. The first line (L1) may be located on the corresponding second interlayer insulating layer (117) and may extend over the upper surface of the third organic insulating layer (119) and onto the upper surface of the resin layer (110). The second line (L2) may be located on the corresponding second interlayer insulating layer (117) and may extend over the upper surface of the third organic insulating layer (119) and onto the first surface of the resin layer (110) (e.g., the surface in contact with the buffer layer (111)).

[0190] A first organic insulating layer (121) may be formed on the pixel circuit (PC), and a connection electrode (CM) and a second voltage line (VSSL) may be formed on the first organic insulating layer (121). A second organic insulating layer (123) may be formed on the connection electrode (CM), and a first electrode pad (241) and a second electrode pad (242) may be formed on the second organic insulating layer (123). The source electrode (SE) and drain electrode (DE) of the thin-film transistor (TFT) may also be formed on the second interlayer insulating layer (117).

[0191] FIG. 14b illustrates a structure in which a third organic insulating layer (119) is formed, but the present invention is not limited thereto. In another embodiment, the third organic insulating layer (119) may not be formed as shown in FIG. 13, in which case the first line (L1) and the second line (L2) may each extend onto the first surface of the resin layer (110) while in direct contact with the side of the corresponding inorganic insulating stack (IIL).

[0192] Referring to FIG. 14c, a light-emitting diode (LED) can be formed on the first pixel circuit layer (PCL1) and the second pixel circuit layer (PCL2) described with reference to FIG. 14b, respectively. The light-emitting diode (LED) may be an inorganic light-emitting diode as described in FIG. 6a to 6d, or an organic light-emitting diode (OLED) as described in FIG. 6e.

[0193] Referring to FIG. 14d, a protective layer (300) can be formed on a light-emitting diode (LED). The protective layer (300) may include the same material as described with reference to FIG. 10. During the process, the protective layer (300) may come into direct contact with the resin layer (110). The protective layer (300) may be formed by depositing a material constituting the protective layer (300) (e.g., an elastomer) and then curing it. The curing process may utilize heat or light such as UV.

[0194] A carrier film (500) may be formed on the protective layer (300). In one or more embodiments, an adhesive layer may be further disposed between the protective layer (300) and the carrier film (500). The carrier film (500) can protect the protective layer (300) from scratches, dents, and / or similar damage that occur during the process. For example, the carrier film (500) may include an insulating material.

[0195] Referring to FIG. 14e, the substrate (100) can be removed from the resin layer (110) after the upper and lower sides of the structure according to the process of FIG. 14d are inverted. A laser can be irradiated on the other side of the substrate (100), which is opposite to the side of the substrate (100) in contact with the resin layer (110), to weaken the bonding force between the substrate (100) and the resin layer (110). Accordingly, the substrate (100) can be separated and removed from the resin layer (110). However, this is an example, and the method of removing the substrate (100) can be varied.

[0196] Referring to FIG. 14f, the resin layer (110) can be removed. The resin layer (110) can be removed through a dry etching process. As the resin layer (110) is removed, one side of the first pixel circuit layer (PCL1) and the second pixel circuit layer (PC2) (e.g., the side opposite the side facing the light-emitting diode (LED)) may be exposed. For example, one side of the inorganic insulating stack (IIL) of each of the first pixel circuit layer (PCL1) and the second pixel circuit layer (PC2) (e.g., the side opposite the side facing the first organic insulating layer (121)), one side of a portion of the first organic insulating layer (121) of each of the first pixel circuit layer (PCL1) and the second pixel circuit layer (PC2), and one side of a portion of each of the first line (L1) and the second line (L2) may be exposed.

[0197] When the resin layer (110) is removed, a portion of the first organic insulating layer (121) and a portion of the third organic insulating layer (119) are removed together. The resin layer (110), a portion of the first organic insulating layer (121), and a portion of the third organic insulating layer (119) can be removed by the same gas. As a portion of the first organic insulating layer (121) and a portion of the third organic insulating layer (119) are removed, the bottom surface (bs) and sides of the first portion (L1A, L2A) of each of the first and second lines (L1, L2) may be exposed to the outside. In this regard, FIG. 14f illustrates the bottom surface (bs), the first side (ss1), and the second side (ss2) of the first portion (L1A, L2A) of each of the first and second lines (L1, L2) being exposed.

[0198] The bottom surface (bs) of the first portion (L1A, L2A) of each of the first and second lines (L1, L2) and one surface of the inorganic insulating stack (IIL) may be located on the same plane. However, as a portion of the first organic insulating layer (121) and a portion of the third organic insulating layer (119) are removed, one surface of the portion of the first organic insulating layer (121) and one surface of the portion of the third organic insulating layer (119) are not located on the same plane as one surface of the inorganic insulating stack (IIL).

[0199] Referring to FIG. 14g, a connecting line (WL) can be formed. The connecting line (WL) can be in direct contact with the first part (L1A) of the first line (L1) and the first part (L2A) of the second line (L2) that are exposed to the outside. For example, the connecting line (WL) can be in direct contact with the bottom surface (bs) and the sides of the first parts (L1A, L2A) of the first and second lines (L1, L2), respectively.

[0200] The connecting line (WL) can be placed in a second area (12) between two adjacent first areas (11) and can extend from one of the two adjacent first areas (11) toward the other.

[0201] In one or more embodiments, the connecting line (WL) may comprise a liquid metal or a conductive composite material comprising a metal nanostructure, an elastic polymer, and / or an elastomer. The connecting line (WL) may be formed through a vacuum deposition process, a printing process, a coating, and / or a similar method.

[0202] Referring to FIG. 14h, a base layer (400) can be formed on a connection line (WL). The base layer (400) can be positioned to cover the connection line (WL). The base layer (400) may include the same material as described with reference to FIG. 10. The base layer (400) can support the components of the display panel (10, FIG. 10) and can absorb stress that may occur during the stretching of the display panel (10, FIG. 10).

[0203] The structure of FIG. 14h can be reversed as shown in FIG. 10, and a display panel (10) as shown in FIG. 10 can be formed by removing the carrier film (500). The carrier film (500, FIG. 14h) can be removed using a release tape.

[0204] FIG. 15 is a schematic perspective view of an embodiment of an electronic device (1) including a display panel according to one or more embodiments, and FIG. 16 is a block diagram of an electronic device (1) including a display panel (10) according to one or more embodiments.

[0205] Referring to FIG. 15, the electronic device (1) can be freely deformed in three dimensions and can provide a three-dimensional image surface through the display area (DA). The statement that the electronic device (1) can be freely deformed in three dimensions is distinguished from the operation of an electronic device having a rollable display panel, such as when only a part of the rolled-up display area is visible to the user, and then another part of the rolled-up display area is unfolded so that the entire display area is visible to the user (or when the entire unfolded display area is visible to the user, and then the display area is rolled up so that only a part of the display area is visible to the user). The electronic device (1) according to one or more embodiments may exhibit a deformation such as the area of ​​the entire display area (DA) increasing or decreasing as the electronic device (1) is deformed in the x direction, y direction, and / or z direction.

[0206] Referring to FIG. 16, the electronic device (1) may include a processor (1100), memory (1200), input module (1300), display module (1400), power module (1500), built-in module (1600), and external module (1700). According to one or more embodiments, at least one of the above-described components may be omitted from the electronic device (1), or one or more other components may be added. According to one or more embodiments, some of the above-described components (e.g., built-in module (1600)) may be integrated into another component (e.g., display module (1400)).

[0207] The processor (1100) can execute software to control at least one other component (e.g., a hardware or software component) of the electronic device (1) connected to the processor (1100) and can perform various data processing or operations. According to one or more embodiments, as at least part of the data processing or operations, the processor (1100) may store commands or data received from other components (e.g., an input module (1300), a sensor module (1610) and / or a communication module (1730)) in a volatile memory (1210), process the commands or data stored in the volatile memory (1210), and store the resulting data in a non-volatile memory (1220).

[0208] The processor (1100) may include a main processor (1110) and an auxiliary processor (1120). The main processor (1110) may include at least one of a central processing unit (1111, CPU) and an application processor (AP). The main processor (1110) may further include at least one of a graphic processing unit (1112, GPU), a communication processor (CP), and an image signal processor (ISP). The main processor (1110) may further include a neural processing unit (1113, NPU). The neural processing unit is a processor specialized for processing artificial intelligence models, and the artificial intelligence model may be generated through machine learning. The artificial intelligence model may include a plurality of artificial neural network layers. An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially. At least two of the processing unit and processor described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0209] The auxiliary processor (1120) may include a controller (1121). The controller (1121) may include an interface conversion circuit and a timing control circuit. The controller (1121) receives a video signal from the main processor (1110), converts the data format of the video signal to match the interface specifications with the display module (1400), and outputs video data. The controller (1121) may output various control signals required for driving the display module (1400).

[0210] The auxiliary processor (1120) may further include data processing circuits such as a data conversion circuit (1122), a gamma correction circuit (1123), and a rendering circuit (1124). The data conversion circuit (1122) receives image data from the controller (1121) and can compensate the image data so that the image is displayed at a desired brightness according to the characteristics of the electronic device (1) or user settings and / or similar, or can convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit (1123) can convert image data, gamma reference voltage, and / or similar things so that the image displayed on the electronic device (1) has desired gamma characteristics. The rendering circuit (1124) receives image data from the controller (1121) and can render the image data by considering the pixel arrangement of the display panel (10) applied to the electronic device (1). At least one of the data conversion circuit (1122), gamma correction circuit (1123), and rendering circuit (1124) may be integrated into another component (e.g., main processor (1110) or controller (1121)). In one or more embodiments, the auxiliary processor (1120) may be integrated into the data driver (1430).

[0211] The memory (1200) can store various data used by at least one component of the electronic device (1) (e.g., a processor (1100) or a sensor module (1610)) and input or output data for related commands. The memory (1200) may include at least one of a volatile memory (1210) and a non-volatile memory (1220).

[0212] The input module (1300) can receive commands or data to be used for components of the electronic device (1) (e.g., processor (1100), sensor module (1610) or sound output module (1630)) from outside the electronic device (1) (e.g., user or external electronic device (2000)).

[0213] The input module (1300) may include a first input module (1310) into which commands or data are input from a user and a second input module (1320) into which commands or data are input from an external electronic device (2000).

[0214] The first input module (1310) may include a microphone, a mouse, a keyboard and / or a pen (e.g., a passive pen or an active pen). The first input module (1310) may include mechanical input means or touch input means, such as a button, a dome switch, a jog wheel, a jog switch, etc., located on the rear or side of the electronic device (1). The touch input means may include a touchscreen layer of the display panel (10).

[0215] The second input module (1320) can be connected wired or wirelessly to various types of external electronic devices (2000) connected to the electronic device (1). In one or more embodiments, the second input module (1320) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, and / or an audio interface. The second input module (1320) may include a connector capable of physically connecting the electronic device (1) to the external electronic device (2000), for example, an HDMI connector, a USB connector, an SD card connector, and / or an audio connector (e.g., a headphone connector). The electronic device (1) can perform appropriate control related to the connected external electronic device (2000) in response to the external electronic device (2000) being connected to the second input module (1320).

[0216] The display module (1400) provides information visually to the user. The display module (1400) may include a display panel (10), a scan driver (1420), and a data driver (1430).

[0217] The display panel (10) displays (outputs) information processed by the electronic device (1). The display panel (10) can display information on the execution screen of an application running on the electronic device (1), or UI (User Interface) and GUI (Graphic User Interface) information based on the execution screen information.

[0218] The scan driver (1420) may be mounted on the display panel (10) as a driving chip. Alternatively, the scan driver (1420) may be formed directly on the display panel (10). For example, the scan driver (1420) may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, and / or an OSG (Oxide Semiconductor TFT Gate driver circuit) embedded in the display panel (10). The scan driver (1420) receives a control signal from the controller (1121) and outputs scan signals to the display panel (10) in response to the control signal.

[0219] The display panel (10) may further include a light emission control driver. The light emission driver outputs a light emission control signal to the display panel (10) in response to a control signal received from the controller (1121). The light emission control driver may be formed separately from the scan driver (1420) or may be integrated into the scan driver (1420).

[0220] The data driver (1430) receives a control signal from the controller (1121), converts the image data into an analog voltage data voltage in response to the control signal, and then outputs the data voltages to the display panel (10).

[0221] The data driver (1430) may be integrated with some components of the auxiliary processor (1120). For example, the data driver (1430) may be provided as a timing controller embedded driver integrated circuit (Timing controller embedded driver IC) including a controller (1121).

[0222] The power module (1500) supplies power to the components of the electronic device (1). The power module (1500) may include a battery that charges the power voltage. Additionally, the power module (1500) is provided with a connection port, and the connection port may be included in a second input module (1320) to which an external charger that supplies power for charging the battery is connected. Alternatively, the power module (1500) may include a wireless power transmission and reception member so that the battery can be charged wirelessly. The wireless power transmission and reception member may include a plurality of coil-shaped antenna radiators. The power module (1500) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the components of the electronic device (1).

[0223] The electronic device (1) may further include an internal module (1600) and an external module (1700). The internal module (1600) may include a sensor module (1610), an antenna module (1620), and an audio output module (1630). The external module (1700) may include a camera module (1710), a light module (1720), and / or a communication module (1730).

[0224] The sensor module (1610) may include touch electrodes of the touchscreen layer of the display panel (10) and a touch sensor driver. The sensor module (1610) may detect input by the user's body or input by a pen and generate an electrical signal or data value corresponding to the input. The sensor module (1610) may include at least one of a fingerprint sensor (1611), an input sensor (1612), and a digitizer (1613).

[0225] The fingerprint sensor (1611) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (1611) may include either an optical or capacitive fingerprint sensor.

[0226] The input sensor (1612) can generate a data value corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (1612) generates a data value of the amount of change in capacitance due to the input. The input sensor (1612) can detect input by a passive pen or transmit and receive data with an active pen.

[0227] The input sensor (1612) may also measure biosignals such as blood pressure, water content, and / or body fat. For example, if a user contacts a part of their body with the sensor layer or sensing panel and does not move for a certain period of time, the input sensor (1612) may detect biosignals based on changes in the electric field caused by the part of the body and output information desired by the user to the display module (1400).

[0228] The digitizer (1613) can generate a data value corresponding to the coordinate information of the input by the pen. The digitizer (1613) generates the amount of electromagnetic change caused by the input as a data value. The digitizer (1613) can detect input by a passive pen or transmit and receive data with an active pen.

[0229] In one or more embodiments, at least one of a fingerprint sensor (1611), an input sensor (1612), and a digitizer (1613) may be embedded in the display panel (10). For example, at least one of the fingerprint sensor (1611), the input sensor (1612), and the digitizer (1613) may be formed through a process that is continuous with the process of forming the pixel circuits and light-emitting diodes of the display panel (10). As a result, the display panel (10) may function as one of the input modules (1300) that provide an input interface between the electronic device (1) and the user, and may also function as a display module (1400) that provides an output interface between the electronic device (1) and the user.

[0230] In one or more embodiments, at least two of the fingerprint sensor (1611), input sensor (1612), and digitizer (1613) may be formed to be integrated into a single sensing panel through the same process. The sensing panel may be positioned between the display panel (10) and a window positioned above the display panel (10), but the present invention is not limited thereto.

[0231] The antenna module (1620) may include one or more antennas for transmitting a signal or power to or from the outside. In one or more embodiments, the communication module (1730) may transmit a signal to or from an external electronic device through an antenna suitable for the communication method. The antenna pattern of the antenna module (1620) may be integrated with one component of the display module (1400) (e.g., a display panel (10)) or an input sensor (1612), etc.

[0232] The sound output module (1630) is a device for outputting sound signals to the outside of the electronic device (1), and can output sound data received from the communication module (1730) or stored in the memory (1200) in call signal reception, call mode or recording mode, voice recognition mode, broadcast reception mode and / or similar. The sound output module (1630) can output sound signals related to functions performed in the electronic device (1) (e.g., call signal reception tone, message reception tone and / or similar). The sound output module (1630) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the bottom of the display panel (10) to vibrate the display panel (10) and output sound. The sound generating device may be a piezoelectric element or a piezoelectric actuator that contracts and expands according to an electric signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0233] The camera module (1710) can capture still images and video. In one or more embodiments, the camera module (1710) may include one or more lenses, image sensors, and image signal processors. The camera module (1710) may further include an infrared camera capable of measuring the presence or absence of a user, the location of the user, the user's gaze, and / or similar things.

[0234] The light module (1720) can use light from a light source to output a signal to indicate the occurrence of an event or provide light for image acquisition. Here, examples of event occurrences may include receiving a message, receiving a call signal, a missed call, an alarm, a schedule notification, receiving an email, receiving battery charge capacity information, and / or similar items. The light module (1720) may include a light-emitting diode and / or a xenon lamp. The light module (1720) may emit single-color or multiple-color light toward the front or rear of the electronic device (1). The light module (1720) may operate in conjunction with the camera module (1710) or operate independently.

[0235] The communication module (1730) can support the establishment of a wired or wireless communication channel between the electronic device (1) and an external electronic device (2000), and the performance of communication through the established communication channel. The communication module (1730) may include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, and / or a GNSS (global navigation satellite system) communication module, and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module (1730) may include a WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity) / Wi-Fi ® (Wi-Fi ® is a registered trademark of the non-profit organization Wi-Fi Alliance), Wi-Fi (Wireless Fidelity) Direct, (Wi-Fi Direct TM Wireless signals can be transmitted and received over the internet network using at least one of the following technologies: (which is a registered trademark of the non-profit organization Wi-Fi Alliance), and DLNA (Digital Living Network Alliance). Additionally, the communication module (1730) can transmit and receive wireless signals over the internet network using Bluetooth (BluetoothTM ,Bluetooth ® (is a registered trademark of Bluetooth Sig, Inc., Kirkland, WA), RFID (Radio Frequency Identification), Infrared Communication (Infrared Data Association; IrDA), UWB (Ultra Wideband), ZigBee ® (ZigBee ® is a registered trademark of the Connectivity Standards Alliance (CA), NFC (Near Field Communication), Wi-Fi ® , Wi-Fi Direct TM Short-range communication can be supported by using at least one of Wireless USB (Wireless Universal Serial Bus) technologies. The various types of communication modules (1730) described above may be implemented as a single chip or as separate chips.

[0236] In the embodiment described with reference to FIG. 15, the display panel (10) is described as being included in an electronic device (1) that provides a three-dimensionally deformable image surface by being freely deformed in three dimensions, but the present invention is not limited thereto. As shown in FIG. 17 and FIG. 18, the electronic device may include an image providing area having a fixed shape, and in the process of manufacturing the electronic device, the display panel may be placed in the image providing area of ​​the electronic device described above. The display panel may be fixed to the electronic device in a three-dimensionally deformed state.

[0237] FIGS. 17 and FIGS. 18 are perspective views showing electronic devices (1A, 1B) according to one or more embodiments, respectively.

[0238] FIG. 17 illustrates a robot as an electronic device (1A) according to one or more embodiments. The robot can move or perceive objects using a camera module (1710) and can display a predetermined image to a user through a display unit (3420, 3430). In one or more embodiments, the display panels according to one or more embodiments can be extended in various directions as described above, so they can be assembled to the frame of the electronic device (3A) while being extended three-dimensionally along a body frame having a hemispherical shape to form a display unit (3420, 3430).

[0239] FIG. 18 illustrates a vehicle display device as an electronic device (1B) according to one or more embodiments. The vehicle display device may include a cluster (3510), a Center Information Display (CID) (3520), and / or a passenger display. Since the display panel according to one or more embodiments can be extended in various directions, it can be used for the cluster (3510), the Center Information Display (CID) (3520), and / or the passenger display (3530, co-driver display) regardless of the shape of the vehicle's internal frame.

[0240] FIG. 18 illustrates the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display being separated, but the invention is not limited thereto. In another embodiment, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected as a single unit.

[0241] In some embodiments, the vehicle display device may include a button (3540) capable of displaying a predetermined image. The hemispherical button (3540) can sense touch input from a user (e.g., driver) in the z-direction or -z-direction.

[0242] FIGS. 17 and 18 illustrate that the electronic device (1A, 1B) is used for a robot or a vehicle, but the present invention is not limited thereto. The electronic device of the present invention may include electronic devices for various uses, such as commercial electronic devices, office electronic devices, educational electronic devices, wearable electronic devices, medical electronic devices, and / or similar ones. In other words, a display panel according to one or more embodiments may be provided in various electronic devices as long as it includes an area capable of providing an image.

[0243] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

[0244] The embodiments described herein are to be considered merely for illustrative purposes and not for limiting purposes. Descriptions of aspects within each embodiment are generally to be considered applicable to other similar aspects of other embodiments. Although one or more embodiments have been described with reference to the drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope defined by the following claims, and that functional equivalents thereof may be incorporated herein.

Claims

1. A base layer comprising a first surface and a second surface opposite to the first surface; A first pixel circuit layer disposed on the first surface of the base layer and comprising transistors and insulating layers; A second pixel circuit layer disposed on the first surface of the base layer, spaced apart from the first pixel circuit layer, and comprising transistors and insulating layers; A first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; A second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; A first line electrically connected to the transistor of the first pixel circuit layer; A second line electrically connected to the transistor of the second pixel circuit layer; and A connecting line that electrically connects the first line and the second line; is included, A display panel in which a first portion of the first line extends toward the connection line, and at least a portion of the first portion is embedded within the connection line.

2. In Paragraph 1, A display panel in which the bottom surface and side surface of the first part of the first line are in direct contact with the connecting line.

3. In Paragraph 1, The insulating layers of each of the first pixel circuit layer and the second pixel circuit layer are, An inorganic insulating stack comprising inorganic insulating layers; and A first organic insulating layer disposed on the above-mentioned inorganic insulating stack; comprising, A display panel in which the first organic insulating layer of the first pixel circuit layer overlaps with the first portion of the first line.

4. In Paragraph 3, A display panel in which the first organic insulating layer is in direct contact with the upper surface of the first part of the first line.

5. In Paragraph 3, A display panel in which a portion of the above base layer is in direct contact with a portion of the side of the above inorganic insulation stack.

6. In Paragraph 3, The above connection line is, A first portion that overlaps with the first organic insulating layer but does not overlap with the first portion of the first line; and It includes a second portion located between the first organic insulating layer of the first pixel circuit layer and the first organic insulating layer of the second pixel circuit layer, A display panel in which the first thickness of the first part of the above connection line is greater than the second thickness of the second part of the above connection line.

7. In Paragraph 6, A display panel, wherein the above connecting line further includes a third portion that overlaps with the first portion of the above first line, and the third thickness of the third portion of the above connecting line is smaller than the first thickness.

8. In Paragraph 3, The insulating layers of each of the first pixel circuit layer and the second pixel circuit layers are, A second organic insulating layer on the first organic insulating layer; and It further includes a third organic insulating layer located between the inorganic insulating stack and the first organic insulating layer and overlapping with the side of the inorganic insulating stack, A display panel in which a portion of the first line is disposed between the third organic insulating layer and the first organic insulating layer.

9. In Paragraph 3, A display panel in which the width of the first organic insulating layer is greater than the width of the inorganic insulating stack.

10. In Paragraph 1, The above first line is, A first layer comprising a first metal; and The first layer comprises a metal different from the first layer and includes a second layer disposed on the first layer, wherein the second layer includes a tip protruding laterally from the point where the side of the first layer and the bottom surface of the second layer meet. The above connecting line is a display panel that is in direct contact with the side and bottom surfaces of the tip.

11. In Paragraph 1, A display panel further comprising a protective layer on the first light-emitting diode and the second light-emitting diode, wherein the protective layer is in direct contact with the connection line.

12. A base layer comprising two mutually spaced first regions and a second region between the two first regions; A first pixel circuit layer disposed in either of the two first regions of the base layer and comprising transistors and insulating layers; A second pixel circuit layer disposed in the other of the two first regions of the base layer, spaced apart from the first pixel circuit layer, and comprising transistors and an insulating layer; A first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; A second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; A first line electrically connected to the transistor of the first pixel circuit layer; A second line electrically connected to the transistor of the second pixel circuit layer; and A connecting line that electrically connects the first line and the second line; is included, A display panel in which the first line extends toward the connecting line, and the bottom surface and side surface of the first part of the first line are in direct contact with the connecting line.

13. In Paragraph 12, The insulating layers of each of the first pixel circuit layer and the second pixel circuit layer are, An inorganic insulating stack comprising inorganic insulating layers; and A first organic insulating layer disposed on the above-mentioned inorganic insulating stack; comprising, A display panel in which the first organic insulating layer overlaps with the first portion of the first line.

14. In Paragraph 13, The above connection line is, A first portion that overlaps with the first organic insulating layer but does not overlap with the first portion of the first line; and It includes a second part located in the second area above, and A display panel in which the first thickness of the first part of the above connection line is greater than the second thickness of the second part of the above connection line.

15. In Paragraph 14, The above connecting line further includes a third part that overlaps with the first part of the above first line, and A display panel in which the third thickness of the third part of the above connection line is smaller than the first thickness.

16. In Paragraph 13, The insulating layers of each of the first pixel circuit layer and the second pixel circuit layers are, It further includes a second organic insulating layer interposed between the inorganic insulating stack and the first organic insulating layer and overlapping with the side of the inorganic insulating stack, A display panel in which a portion of the first line is disposed between the second organic insulating layer and the first organic insulating layer.

17. In Paragraph 13, A display panel in which a portion of the above base layer is in direct contact with a portion of the side of the above inorganic insulation stack.

18. In Paragraph 13, The first organic insulating layer is in direct contact with the upper surface of the first part of the first line, and The display panel further comprises a protective layer on the first light-emitting diode and the second light-emitting diode, wherein the protective layer is in direct contact with the connection line.

19. In Paragraph 12, The above first line is, A first layer comprising a first metal; and The first layer comprises a metal different from the first layer and includes a second layer disposed on the first layer, wherein the second layer includes a tip protruding laterally from the point where the side of the first layer and the bottom surface of the second layer meet. The above connecting line is a display panel that is in direct contact with the side and bottom surfaces of the tip.

20. An electronic device comprising a display panel, wherein the display panel is, A base layer comprising a first surface and a second surface opposite to the first surface; A first pixel circuit layer disposed on the first surface of the base layer and comprising transistors and insulating layers; A second pixel circuit layer disposed on the first surface of the base layer, spaced apart from the first pixel circuit layer, and comprising transistors and insulating layers; A first light-emitting diode disposed on the first pixel circuit layer and electrically connected to the transistor of the first pixel circuit layer; A second light-emitting diode disposed on the second pixel circuit layer and electrically connected to the transistor of the second pixel circuit layer; A first line electrically connected to the transistor of the first pixel circuit layer; A second line electrically connected to the transistor of the second pixel circuit layer; and A connecting line that electrically connects the first line and the second line; is included, An electronic device in which a first portion of the first line extends toward the connecting line, and at least a portion of the first portion is embedded within the connecting line.

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