Array substrate and display apparatus

Abstract

An array substrate, the array substrate comprising a first conductive layer (200), wherein the side of the first conductive layer (200) away from a base substrate (100) is provided with a second protective layer (500), a third protective layer (600) and a fourth protective layer (700) for protection, such that an auxiliary reference signal line (2) can be better isolated from moisture. The thickness of the first conductive layer (200) is much greater than the thickness of the second conductive layer (300), such that the impedance of the first conductive layer (200) is much less than the impedance of the second conductive layer (300), and the heat generation of the first conductive layer (200) is much lower than the heat generation of the second conductive layer (300). Even if the current of the auxiliary reference signal line (2) is high, the heat generation of the auxiliary reference signal line (2) is low. Thus, the design can greatly improve the corrosion resistance of the auxiliary reference signal line (2), and reduce or avoid poor light emission of MiniLED light-emitting devices (21) in a lamp area. Further provided is a display apparatus comprising the array substrate.

Description

Array substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate and a display device. Background Technology

[0002] For narrow-bezel and high-zone display devices using MiniLED, due to the limited in-plane space, the array substrate needs to use two or more conductive layers to fabricate the driving circuit.

[0003] During reliability testing, it was found that the top conductive layer would corrode. When the auxiliary reference signal line was located on the top conductive layer and the current passing through it was large, corrosion was more likely to occur, resulting in poor light emission of the MiniLED light-emitting devices in the lamp area.

[0004] It should be noted that the information in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide an array substrate and a display device.

[0007] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising a substrate, a first conductive layer, and a second conductive layer. The first conductive layer is disposed on one side of the substrate, and the second conductive layer is disposed on the side of the first conductive layer away from the substrate. The array substrate further comprises at least two main reference signal lines, a first lead, and an auxiliary reference signal line. The at least two main reference signal lines are disposed on the first conductive layer and extend along a first direction. The at least two main reference signal lines are spaced apart along a second direction. The first lead extends along the first direction and includes a first lead segment and a second lead segment. At least two first lead segments are disposed on the first conductive layer, and at least two first lead segments are provided. The two first lead segments are spaced apart along the first direction. The second lead segment is located on the second conductive layer, and both ends of the second lead segment are connected to the two first lead segments through vias. The auxiliary reference signal line is disposed on the first conductive layer and extends along the second direction. The auxiliary reference signal line is connected to two adjacent main reference signal lines, and the orthographic projection of the auxiliary reference signal line on the substrate is located between the orthographic projections of the two first lead segments on the substrate.

[0008] In one embodiment of the present invention, at least two main reference signal lines include a first main reference signal line and a second main reference signal line. A first lead includes a first clock signal line, which is disposed between the first main reference signal line and the second main reference signal line. The first clock signal line includes a first clock signal segment and a second clock signal segment. When the first lead is the first clock signal line, the first lead segment is the first clock signal segment, and the second lead segment is the second clock signal segment. The two ends of the second clock signal segment are respectively connected to the two first clock signal segments through vias. An auxiliary reference signal line includes a first auxiliary reference signal line. At least a portion of the orthographic projection of the first auxiliary reference signal line on the substrate is located between the orthographic projections of the two first clock signal segments on the substrate. The first auxiliary reference signal line is connected to the first main reference signal line and the second main reference signal line, respectively.

[0009] In one embodiment of the present invention, the main reference signal line further includes a third main reference signal line, which is disposed along a second direction on the side of the first main reference signal line away from the second main reference signal line. The first lead includes a first power signal line, which is disposed between the first main reference signal line and the third main reference signal line. The first power signal line includes a first power signal segment and a second power signal segment. When the first lead is the first power signal line, the first lead segment is the first power signal segment, and the second lead segment is the second power signal segment. The two ends of the second power signal segment are respectively connected to the two first power signal segments through vias. The auxiliary reference signal line further includes a second auxiliary reference signal line. The orthographic projection of the second auxiliary reference signal line on the substrate is located between the orthographic projections of the two first power signal segments on the substrate. The second auxiliary reference signal line is connected to the first main reference signal line and the third main reference signal line respectively.

[0010] In one embodiment of the present invention, the main reference signal line further includes a fourth main reference signal line, which is disposed along a second direction on the side of the second main reference signal line away from the first main reference signal line. The first lead also includes a first data signal line, which is disposed between the second main reference signal line and the fourth main reference signal line. The first data signal line includes a first data signal segment and a second data signal segment. When the first lead is the first data signal line, the first lead segment is the first data signal segment, and the second lead segment is the second data signal segment. The two ends of the second data signal segment are respectively connected to the two first data signal segments through vias. The auxiliary reference signal line further includes a third auxiliary reference signal line, the orthographic projection of the third auxiliary reference signal line on the substrate is located between the orthographic projections of the two first data signal segments on the substrate, and the third auxiliary reference signal line is respectively connected to the second main reference signal line and the fourth main reference signal line.

[0011] In one embodiment of the present invention, the first auxiliary reference signal line includes a first auxiliary reference signal segment, a second auxiliary reference signal segment, and a third auxiliary reference signal segment. The first auxiliary reference signal segment is connected to the second main reference signal line, and the second auxiliary reference signal segment is connected to the first main reference signal line. The first and second auxiliary reference signal segments both extend along a second direction and are located on different straight lines. The third auxiliary reference signal segment extends along a first direction, and its two ends are respectively connected to the first and second auxiliary reference signal segments. The orthographic projection of the first auxiliary reference signal segment on the substrate is located between the orthographic projections of the two first clock signal segments on the substrate.

[0012] In one embodiment of the present invention, the second auxiliary reference signal segment is located between the first auxiliary reference signal segment and the second auxiliary reference signal line.

[0013] In one embodiment of the present invention, the first auxiliary reference signal segment and the third auxiliary reference signal line extend along a second direction and are located on the same straight line, and the width of the first auxiliary reference signal segment is not equal to the width of the third auxiliary reference signal line.

[0014] In one embodiment of the present invention, the first auxiliary reference signal segment and the third auxiliary reference signal line extend along a second direction and are located on the same straight line, and the width of the first auxiliary reference signal segment is equal to the width of the third auxiliary reference signal line.

[0015] In one embodiment of the present invention, the array substrate further includes a second data signal line, a third data signal line, and a fourth data signal line. The second data signal line is spaced apart from the first data signal line and located on the same straight line along a first direction. The third data signal line is connected to the first data signal line, and the fourth data signal line is connected to the second data signal line. The fourth data signal line includes a third data signal segment and a fourth data signal segment. The third data signal segment extends along the first direction, and the third data signal segment and the third data signal line are spaced apart in a second direction. The fourth data signal segment and the fourth data signal line extend along the second direction, and the fourth data signal segment and the third data signal line are spaced apart in the first direction.

[0016] In one embodiment of the present invention, the main reference signal line further includes a fourth main reference signal line, which is disposed along a second direction on the side of the second main reference signal line away from the first main reference signal line. The auxiliary reference signal line further includes a third auxiliary reference signal line, which is connected to the second main reference signal line and the fourth main reference signal line respectively. The array substrate further includes a first data signal line and a second data signal line, which are spaced apart from the first data signal line and located on the same straight line along a first direction. The third auxiliary reference signal line is disposed between the first data signal line and the second data signal line.

[0017] In one embodiment of the present invention, the array substrate further includes a third data signal line and a fourth data signal line disposed on the second conductive layer. The third data signal line is connected to the first data signal line, and the fourth data signal line is connected to the second data signal line. The fourth data signal line includes a third data signal segment and a fourth data signal segment. The third data signal segment extends along a first direction, and the third data signal segment and the third data signal line are spaced apart in the first direction. The fourth data signal segment and the fourth data signal line are respectively disposed on both sides of the third auxiliary reference signal line.

[0018] In one embodiment of the present invention, the array substrate further includes light-emitting leads disposed on the second conductive layer. The light-emitting leads include a first light-emitting lead, a second light-emitting lead, a third light-emitting lead, and a fourth light-emitting lead. The first light-emitting lead and the second light-emitting lead are disposed on one side of the second auxiliary reference signal segment, and the third light-emitting lead and the fourth light-emitting lead are disposed on the other side of the second auxiliary reference signal segment.

[0019] In one embodiment of the present invention, the array substrate further includes a second power signal line, a connection reference signal line, a third clock signal line, and a fourth clock signal line disposed on the second conductive layer. The second power signal line is connected to the second power signal segment, the connection reference signal line is connected to the second main reference signal line, the third clock signal line is connected to the first clock signal line, and the fourth clock signal line is connected to the second clock signal line. The connection reference signal line and the third clock signal line are located between the third light-emitting lead and the third data signal line, and the second power signal line and the fourth clock signal line are located between the fourth light-emitting lead and the third data signal segment.

[0020] In one embodiment of the present invention, the array substrate further includes chip pads disposed between a first clock signal line and a second clock signal line. The chip pads include a first chip pad, a second chip pad, a third chip pad, a fourth chip pad, a fifth chip pad, and a sixth chip pad. The first chip pad is disposed on a first auxiliary reference signal line. The second chip pad is disposed at the adjacent ends of the first light-emitting lead and the second light-emitting lead. The third chip pad is disposed at the adjacent ends of the third light-emitting lead and the fourth light-emitting lead. The fourth chip pad is disposed at the adjacent ends of the second power signal line and the connection reference signal line. The fifth chip pad is disposed at the adjacent ends of the third clock signal line and the fourth clock signal line. The sixth chip pad is disposed at the adjacent ends of the third data signal line and the fourth data signal line. The chip pads are used to connect to the control chip.

[0021] In one embodiment of the present invention, the first light-emitting lead includes a first light-emitting segment and a second light-emitting segment connected in sequence. The first light-emitting segment extends along a first direction, the second light-emitting segment extends along a second direction, and a third auxiliary reference signal segment is located between the first light-emitting segment and the first clock signal line. The first auxiliary reference signal segment is located on the side of the second auxiliary reference signal segment away from the second light-emitting segment.

[0022] In one embodiment of the present invention, the orthographic projection of the first conductive layer on the substrate is a first orthographic projection, the orthographic projection of the second conductive layer on the substrate is a second orthographic projection, and the distance between the first orthographic projection and the second orthographic projection is greater than or equal to 91 μm.

[0023] In one embodiment of the present invention, the widths of the first auxiliary reference signal line, the second auxiliary reference signal line, and the third auxiliary reference signal line are all greater than or equal to 218 μm.

[0024] According to another aspect of the present invention, a display device is provided, comprising an array substrate provided by any one of the present invention.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 is a cross-sectional schematic diagram of the array substrate involved in an embodiment of the present invention.

[0028] Figure 2 is a planar schematic diagram of the first conductive layer in an embodiment of the present invention when the auxiliary reference signal line is located in the second conductive layer.

[0029] Figure 3 is a planar schematic diagram of the second conductive layer in an embodiment of the present invention when the auxiliary reference signal line is located in the second conductive layer.

[0030] Figure 4 is a planar schematic diagram of the array substrate involved in the embodiment of the present invention when the auxiliary reference signal line is located in the second conductive layer.

[0031] Figure 5 is a planar schematic diagram of the first conductive layer involved in the embodiment of the present invention when the first auxiliary reference signal segment and the third auxiliary reference signal line are located on the same straight line, and the width of the first auxiliary reference signal segment is not equal to the width of the third auxiliary reference signal line.

[0032] Figure 6 is a planar schematic diagram of the second conductive layer in this embodiment of the invention when the first auxiliary reference signal segment and the third auxiliary reference signal line are located on the same straight line, and the width of the first auxiliary reference signal segment is not equal to the width of the third auxiliary reference signal line.

[0033] Figure 7 is a planar schematic diagram of the array substrate involved in the embodiment of the present invention when the first auxiliary reference signal segment and the third auxiliary reference signal line are located on the same straight line, and the width of the first auxiliary reference signal segment is not equal to the width of the third auxiliary reference signal line.

[0034] Figure 8 is a planar schematic diagram of the first conductive layer in this embodiment of the invention, when the first auxiliary reference signal segment and the third auxiliary reference signal line are located on the same straight line, and the width of the first auxiliary reference signal segment is equal to the width of the third auxiliary reference signal line.

[0035] Figure 9 is a planar schematic diagram of the array substrate involved in the embodiment of the present invention when the first auxiliary reference signal segment and the third auxiliary reference signal line are located on the same straight line, and the width of the first auxiliary reference signal segment is equal to the width of the third auxiliary reference signal line.

[0036] Figure 10 is a planar schematic diagram of the first conductive layer in an embodiment of the present invention when the third auxiliary reference signal line is disposed between the first data signal line and the second data signal line.

[0037] Figure 11 is a planar schematic diagram of the second conductive layer in an embodiment of the present invention when the third auxiliary reference signal line is disposed between the first data signal line and the second data signal line.

[0038] Figure 12 is a planar schematic diagram of the array substrate involved in the embodiment of the present invention when the third auxiliary reference signal line is disposed between the first data signal line and the second data signal line.

[0039] Figure 13 is a planar schematic diagram of the light-emitting substrate according to an embodiment of the present invention when the third auxiliary reference signal line is disposed between the first data signal line and the second data signal line.

[0040] Explanation of reference numerals in the attached figures: 100 - Substrate, 200 - First conductive layer, 300 - Second conductive layer, 400 - First protective layer, 500 - Second protective layer, 600 - Third protective layer, 700 - Fourth protective layer, 800 - First insulating layer, 900 - Second insulating layer, 1 - Main reference signal line, 101 - First main reference signal line, 102 - Second main reference signal line, 103 - Third main reference signal line, 104 - Fourth main reference signal line, 2 - Auxiliary reference signal line, 201 - First auxiliary reference signal line, 2011 - First auxiliary reference signal segment, 2012 - Second auxiliary reference signal segment, 2013 - Third auxiliary reference... Signal segment, 202-Second auxiliary reference signal line, 203-Third auxiliary reference signal line, 3-First clock signal line, 301-First clock signal segment, 302-Second clock signal segment, 4-Second clock signal line, 5-First power signal line, 501-First power signal segment, 502-Second power signal segment, 6-Second power signal line, 7-First data signal line, 701-First data signal segment, 702-Second data signal segment, 8-Second data signal line, 9-Third data signal line. 10 - Fourth data signal line, 1001 - Third data signal segment, 1002 - Fourth data signal segment, 11 - Connection reference signal line, 12 - First light-emitting lead, 121 - First light-emitting segment, 122 - Second light-emitting segment, 123 - Third light-emitting segment, 13 - Second light-emitting lead, 1301 - Fourth light-emitting segment, 1302 - Fifth light-emitting segment, 1303 - Sixth light-emitting segment, 14 - Third light-emitting lead, 1401 - Seventh light-emitting segment, 1402 - Eighth light-emitting segment, 15 - Fourth light-emitting lead. 1501 - Ninth light-emitting segment, 1502 - Tenth light-emitting segment, 16 - Chip pad, 1601 - First chip pad, 1602 - Second chip pad, 1603 - Third chip pad, 1604 - Fourth chip pad, 1605 - Fifth chip pad, 1606 - Sixth chip pad, 17 - Via, 18 - First opening area, 19 - Second opening area, 20 - Third opening area, 21 - MiniLED light-emitting device, 22 - Third clock signal line, 23 - Fourth clock signal line. Detailed Implementation

[0041] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted. Furthermore, the drawings are merely illustrative of the invention and are not necessarily drawn to scale.

[0042] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0043] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0044] Currently, common MiniLED display panels typically use a single conductive layer to create the driving circuit. However, for MiniLED display panels with narrow bezels and multiple partitions, due to limited in-plane space, two or more conductive layers are required to create the driving circuit. As shown in Figure 1, this display panel includes a substrate 100, a first protective layer 400, a first conductive layer 200, a second protective layer 500, a first insulating layer 800, a third protective layer 600, a second conductive layer 300, a fourth protective layer 700, and a second insulating layer 900. The driving circuit is created using the first conductive layer 200 and the second conductive layer 300. The side of the second conductive layer 300 furthest from the substrate 100 covers the fourth protective layer 700 and the second insulating layer 900, and its reliability is directly related to the thickness of the fourth protective layer 700.

[0045] When the thickness of the fourth protective layer 700 is constant, reliability testing revealed that because the fourth protective layer 700 cannot completely isolate moisture, the entry of moisture corrodes the traces on the second conductive layer 300. As shown in Figures 2 to 4, the first conductive layer 200 has a main reference signal line 1 extending along a first direction. The main reference signal line 1 includes a first main reference signal line 101, a second main reference signal line 102, a third main reference signal line 103, and a fourth main reference signal line 104 arranged along a second direction. The second conductive layer 300 has an auxiliary reference signal line 2, which connects the first main reference signal line 101, the second main reference signal line 102, the third main reference signal line 103, and the fourth main reference signal line 104 together. The auxiliary reference signal line 2 carries a large current, and the thickness of the second conductive layer 300 is relatively thin, resulting in a large temperature rise and a lot of heat generation during display, making it more susceptible to corrosion.

[0046] A chip pad 16 is provided between the first main reference signal line 101 and the second main reference signal line 102, which can be used to bond the control chip to the chip pad 16. The light-emitting lead and the auxiliary reference signal line 2 are both connected to the chip pad 16. Actual observations from reliability results show that the portion of the auxiliary reference signal line 2 closest to the chip pad 16 is more prone to corrosion. Corrosion mostly occurs at the edge adjacent to the light-emitting lead. Due to the potential difference between the auxiliary reference signal line 2 and the light-emitting lead and the small trace spacing (minimum spacing is only 51µm), the corrosion is aggravated and migrates, leading to a short circuit between the auxiliary reference signal line 2 and the light-emitting lead. This, in turn, causes the MiniLED light-emitting device 21 in the lamp area to explode, resulting in the failure of the MiniLED display panel, as shown in Figure 2.

[0047] Based on this, embodiments of the present invention provide an array substrate. As shown in Figures 5 to 13, the array substrate includes a substrate 100, a first conductive layer 200, and a second conductive layer 300. The first conductive layer 200 is disposed on one side of the substrate 100, and the second conductive layer 300 is disposed on the side of the first conductive layer 200 away from the substrate 100. The array substrate also includes at least two main reference signal lines 1, a first lead, and an auxiliary reference signal line 2. At least two main reference signal lines 1 are disposed on the first conductive layer 200, and the main reference signal lines 1 extend along a first direction. The at least two main reference signal lines 1 are spaced apart along a second direction. The first lead extends along the first direction and includes a first... A first conductive layer 200 has at least two first conductive layers 200, and the two first conductive layers 200 are spaced apart along a first direction. The second conductive layer 300 has two ends connected to the two first conductive layers 17 through vias 17. An auxiliary reference signal line 2 is disposed on the first conductive layer 200 and extends along a second direction. The auxiliary reference signal line 2 is connected to two adjacent main reference signal lines 1. The orthographic projection of the auxiliary reference signal line 2 on the substrate 100 is located between the orthographic projections of the two first conductive layers 100 on the substrate 100.

[0048] The first conductive layer 200 is protected by a second protective layer 500, a third protective layer 600, and a fourth protective layer 700 on the side away from the substrate 100, which can effectively isolate the auxiliary reference signal line 2 from moisture. The thickness of the first conductive layer 200 is much greater than that of the second conductive layer 300. Therefore, the impedance of the first conductive layer 200 is much lower than that of the second conductive layer 300, and the heat generation of the first conductive layer 200 is much lower than that of the second conductive layer 300. Even if the current of the auxiliary reference signal line 2 is large, the heat generation of the auxiliary reference signal line 2 is relatively small. Therefore, this design can significantly improve the corrosion resistance of the auxiliary reference signal line 2 and reduce or avoid the poor light emission of the MiniLED light-emitting device 21 in the lamp area.

[0049] The array substrate involved in this invention will be described in detail below with reference to specific embodiments.

[0050] As shown in Figures 5 to 9, the array substrate may include a main reference signal line 1, which is disposed on the first conductive layer 200. The main reference signal line 1 may include a first main reference signal line 101, a second main reference signal line 102, a third main reference signal line 103, and a fourth main reference signal line 104 extending along a first direction. The first main reference signal line 101 and the second main reference signal line 102 are disposed adjacent to each other. The third main reference signal line 103 is disposed on the side of the first main reference signal line 101 away from the second main reference signal line 102, and the fourth main reference signal line 104 is disposed on the side of the second main reference signal line 102 away from the first main reference signal line 101.

[0051] The array substrate may further include a first lead, which may include a first clock signal line 3, a second clock signal line 4, a first power signal line 5, and a first data signal line 7 extending along a first direction. The first clock signal line 3 is disposed between the first main reference signal line 101 and the second main reference signal line 102, the second clock signal line 4 is disposed between the first clock signal line 3 and the first main reference signal line 101, the first power signal line 5 is disposed between the first main reference signal line 101 and the third main reference signal line 103, and the first data signal line 7 is disposed between the second main reference signal line 102 and the fourth main reference signal line 104.

[0052] The first clock signal line 3 includes a first clock signal segment 301 and a second clock signal segment 302. The first clock signal segment 301 is disposed on the first conductive layer 200, and the second clock signal segment 302 is disposed on the second conductive layer 300. There are two first clock signal segments 301, which are spaced apart. The two ends of the second clock signal segment 302 are respectively connected to the two first clock signal segments 301 through vias 17. The array substrate may also include an auxiliary reference signal line 2, which is disposed on the first conductive layer 200. The auxiliary reference signal line 2 may include a first auxiliary reference signal line 201. The orthographic projection of the first auxiliary reference signal line 201 on the substrate 100 is located between the orthographic projections of the two first clock signal segments 301 on the substrate 100. The first auxiliary reference signal line 201 is connected to the first main reference signal line 101 and the second main reference signal line 102.

[0053] The first power signal line 5 includes a first power signal segment 501 and a second power signal segment 502. The first power signal segment 501 is disposed on the first conductive layer 200, and the second power signal segment 502 is disposed on the second conductive layer 300. There are two first power signal segments 501, which are spaced apart. The two ends of the second power signal segment 502 are respectively connected to the two first power signal segments 501 through vias 17. The auxiliary reference signal line 2 may also include a second auxiliary reference signal line 202. The orthographic projection of the second auxiliary reference signal line 202 on the substrate 100 is located between the orthographic projections of the two first power signal segments 501 on the substrate 100. The second auxiliary reference signal line 202 is connected to the first main reference signal line 101 and the third main reference signal line 103, respectively.

[0054] The first data signal line 7 includes a first data signal segment 701 and a second data signal segment 702. The first data signal segment 701 is disposed on the first conductive layer 200, and the second data signal segment 702 is disposed on the second conductive layer 300. There are two first data signal segments 701, which are spaced apart. The two ends of the second data signal segment 702 are connected to the two first data signal segments 701 through vias 17. The third auxiliary reference signal line 203 is connected to the first main reference signal line 101 and the second main reference signal line 102, the second auxiliary reference signal line 202 and the third main reference signal line 103, and the third auxiliary reference signal line 203 and the second main reference signal line 102 and the fourth main reference signal line 104, respectively.

[0055] The first auxiliary reference signal line 201 includes a first auxiliary reference signal segment 2011, a second auxiliary reference signal segment 2012, and a third auxiliary reference signal segment 2013. The first auxiliary reference signal segment 2011 is connected to the second main reference signal line 102, and the second auxiliary reference signal segment 2012 is connected to the first main reference signal line 101. The first auxiliary reference signal segment 2011 and the second auxiliary reference signal segment 2012 both extend along a second direction and are located on different straight lines. The third auxiliary reference signal segment 2013 extends along a first direction, and the two ends of the third auxiliary reference signal segment 2013 are respectively connected to the first auxiliary reference signal segment 2011 and the second auxiliary reference signal segment 2012.

[0056] The array substrate also includes light-emitting leads, comprising a first light-emitting lead 12, a second light-emitting lead 13, a third light-emitting lead 14, and a fourth light-emitting lead 15. The first light-emitting lead 12 and the second light-emitting lead 13 are located on one side of the second auxiliary reference signal segment 2012, while the third light-emitting lead 14 and the fourth light-emitting lead 15 are located on the other side of the second auxiliary reference signal segment 2012. The second auxiliary reference signal segment 2012 can shield the light-emitting signals on both sides, preventing interference between the light-emitting signals on the first light-emitting lead 12 and the second light-emitting lead 13 and the light-emitting signals on the third light-emitting lead 14 and the fourth light-emitting lead 15.

[0057] The first light-emitting lead 12 includes a first light-emitting segment 121, a second light-emitting segment 122, and a third light-emitting segment 123. The first light-emitting segment 121 extends along a first direction, the second light-emitting segment 122 extends along a second direction, and the second light-emitting segment 122 is connected to the end of the first light-emitting segment 121 that is away from the second auxiliary reference signal segment 2012. The third light-emitting segment 123 extends along the first direction and is connected to the end of the second light-emitting segment 122 that is away from the first main reference signal line 101.

[0058] The second light-emitting lead 13 includes a fourth light-emitting segment 1301, a fifth light-emitting segment 1302, and a sixth light-emitting segment 1303. The fourth light-emitting segment 1301 extends along a first direction, the fifth light-emitting segment 1302 extends along a second direction, and the fifth light-emitting segment 1302 is connected to the end of the fourth light-emitting segment 1301 that is away from the second auxiliary reference signal segment 2012. The sixth light-emitting segment 1303 extends along the first direction and is connected to the end of the fifth light-emitting segment 1302 that is away from the second auxiliary reference signal segment 2012.

[0059] The orthographic projection of the second light-emitting segment 122 on the substrate 100 overlaps with the orthographic projection of the first clock signal segment 301 above the first reference signal segment on the substrate 100 and the orthographic projection of the first data signal segment 701 above the first reference signal segment on the substrate 100, respectively. The orthographic projection of the fifth light-emitting segment 1302 on the substrate 100 overlaps with the orthographic projection of the power signal line above the second reference signal segment on the substrate 100 and the orthographic projection of the first main reference signal line 101 above the second reference signal segment on the substrate 100.

[0060] The third light-emitting lead 14 includes a seventh light-emitting segment 1401 and an eighth light-emitting segment 1402. The seventh light-emitting segment 1401 extends along a second direction, and the eighth light-emitting segment 1402 is connected to the end of the seventh light-emitting segment 1401 away from the first main reference signal segment. The eighth light-emitting segment 1402 extends along a first direction. The third light-emitting lead 14 also includes a ninth light-emitting segment 1501 and a tenth light-emitting segment 1502. The ninth light-emitting segment 1501 extends along a second direction, and the tenth light-emitting segment 1502 is connected to the end of the ninth light-emitting segment 1501 away from the second main reference signal segment. The ninth light-emitting segment 1501 extends along a first direction.

[0061] The orthographic projection of the seventh light-emitting segment 1401 on the substrate 100 overlaps with the orthographic projections of the first clock signal segment 301 below the first reference signal segment and the first data signal segment 701 below the first reference signal segment on the substrate 100, respectively. The orthographic projection of the ninth light-emitting segment 1501 on the substrate 100 overlaps with the orthographic projections of the power signal line below the second reference signal segment and the first main reference signal line 101 below the first reference signal segment on the substrate 100.

[0062] To save routing space, a section of the first main reference signal line 101 can be shortened or bent in a direction away from the second main reference signal line 102, and a section of the second main reference signal line 102 can be shortened or bent in a direction away from the first main reference signal line 101. Since the first clock signal line 3 and the second clock signal line 4 are relatively thin, the first clock signal line 3 can be bent in a direction away from the second clock signal line 4, and the second clock signal line 4 can be bent in a direction away from the first clock signal line 3, forming a first opening area 18. A chip pad 16 is provided in the first opening area 18, and the chip pad 16 is located between the first clock signal line 3 and the second clock signal line 4.

[0063] A first trace gap is formed between the first main reference signal line 101 and the third main reference signal line 103, and a second trace gap is formed between the second main reference signal line 102 and the fourth main reference signal line 104. The orthographic projection of part of the second light-emitting lead 13 on the substrate 100 and the orthographic projection of part of the fourth light-emitting lead 15 on the substrate 100 are located within the first trace gap, and the orthographic projection of part of the first light-emitting lead 12 on the substrate 100 and the orthographic projection of part of the third light-emitting lead 14 on the substrate 100 are located within the second trace gap. This can save wiring space and at the same time avoid forming parasitic capacitance with other traces located on the first conductive layer 200.

[0064] The array substrate may also include chip pads 16 for connecting control chips. Chip pads 16 may include a first chip pad 1601, a second chip pad 1602, and a third chip pad 1603. The first chip pad 1601 is disposed on the second auxiliary reference signal segment 2012, the second chip pad 1602 is disposed on the side of the first chip pad 1601 away from the second auxiliary reference signal line 202, and the third chip pad 1603 is disposed between the second auxiliary reference signal segment 2012 and the second auxiliary reference signal line 202. The second chip pad 1602 is disposed on the first light-emitting lead 12 and the second light-emitting lead 13, and the third chip pad 1603 is disposed on the third light-emitting lead 14 and the fourth light-emitting lead 15, respectively.

[0065] The chip pad 16 may also include a fourth chip pad 1604, which is located on the side of the third chip pad 1603 away from the first chip pad 1601. The array substrate also includes a second power signal line 6, which is connected to the second power signal segment 502. A fourth chip pad 1604 is provided on the second power line. The array substrate also includes a connection reference signal line 11, which is connected to the second main reference signal line 102. Another fourth chip pad 1604 is provided on the connection reference signal line 11.

[0066] The chip pad 16 may also include a fifth chip pad 1605, which is located on the side of the fourth chip pad 1604 away from the first chip pad 1601. The array substrate also includes a third clock signal line 22 and a fourth clock signal line 23. The third clock signal line 22 is connected to the first clock signal line 3, and the fourth clock signal line 23 is connected to the second clock signal line 4. The first clock signal line 3 extends toward the first reference signal line, and the second clock signal line 4 extends away from the first reference signal line. The fifth chip pad 1605 is provided on the third clock signal line 22 and the fourth clock signal line 23.

[0067] The chip pad 16 may also include a sixth chip pad 1606, which is located on the side of the fifth chip pad 1605 away from the first chip pad 1601. The array substrate also includes a second data signal line 8, a third data signal line 9, and a fourth data signal line 10. The second data signal line 8 is spaced apart from the first data signal line 7 and is located on the same straight line along a first direction. The third data signal line 9 is connected to the first data signal line 7, and the fourth data signal line 10 is connected to the second data signal line 8. The fourth data signal line 10 includes a third data signal segment 1001 and a fourth data signal segment 1002. The third data signal segment 1001 extends along the first direction, and the third data signal segment 1001 and the third data signal line 9 are spaced apart in a second direction. The fourth data signal segment 1002 and the fourth data signal line 10 extend along the second direction, and the fourth data signal segment 1002 and the third data signal line 9 are spaced apart in the first direction. The sixth chip pad 1606 is respectively provided at the ends of the third data signal line 9 and the fourth data signal line 10 that are close to each other.

[0068] It should be noted that reference signals are loaded onto the auxiliary reference signal line 2 via the first chip pad 1601, reference signals are loaded onto the connecting reference signal line 11 via the fourth chip pad 16, power signals are loaded via the second power signal line 6, the first clock signal is loaded via the third clock signal line 22, the second clock signal is loaded via the fourth clock signal line 23, the first data signal is loaded via the third data signal line 9, and the second data signal is loaded via the fourth data signal line 10. The voltage of the reference signals is lower than the voltages of the power signals, the first clock signal, the second clock signal, the first data signal, and the second data signal. The first light-emitting signal is loaded via the first light-emitting lead 12, the second light-emitting signal via the second light-emitting lead 13, the third light-emitting signal via the third light-emitting lead 14, and the fourth light-emitting signal via the fourth light-emitting lead 15.

[0069] The second auxiliary reference signal line 202 extends along the second direction, and the second auxiliary reference signal line 202 and the second auxiliary reference signal segment 2012 are located on different straight lines. The third auxiliary reference signal line 203 extends along the second direction, and the third auxiliary reference signal line 203 and the first auxiliary reference signal segment 2011 are located on the same straight line. The orthographic projection of the first auxiliary reference signal segment 2011 on the substrate 100 is located between the orthographic projections of the two first clock signal segments 301 on the substrate 100. The second auxiliary reference signal segment 2012 is connected to the first chip pad 1601. Since the first chip pad 1601 is located on the side of the second clock signal segment 302 away from the second light-emitting segment 122, the second auxiliary reference signal segment 2012 is located on the side of the first auxiliary reference signal segment 2011 away from the second light-emitting segment 122. The first auxiliary reference signal line 201 is located on the side of the second auxiliary reference signal segment 2012 away from the first auxiliary reference signal segment 2011, specifically on the side of the second power signal line 6 away from the second auxiliary reference signal segment 2012.

[0070] As shown in Figures 5 to 7, the width of the first auxiliary reference signal segment 2011 can be set to be unequal to the width of the third auxiliary reference signal line 203. The width of the first auxiliary reference signal segment 2011 can be less than the width of the third auxiliary reference signal line 203, or the width of the first auxiliary reference signal segment 2011 can be greater than the width of the third auxiliary reference signal line 203. As shown in Figures 8 and 9, the width of the first auxiliary reference signal segment 2011 can also be set to be equal to the width of the third auxiliary reference signal line 203.

[0071] As shown in Figures 10 to 12, the difference from Figures 5 to 9 is that the first data signal line 7 and the second data signal line 8 are both located on the first conductive layer 200. The second data signal line 8 is moved away from the first data signal line 7. The third auxiliary reference signal line is placed between the first data signal line 7 and the second data signal line 8. The fourth data signal segment 1002 and the fourth data signal line 10 are placed on both sides of the third auxiliary reference signal line 203. The third auxiliary reference signal line 203 and the second auxiliary reference signal line 202 can be aligned on the same straight line along the second direction.

[0072] In other embodiments, the second auxiliary reference signal segment 2012 can be disposed between the fourth light-emitting segment 1301 and the ninth light-emitting segment 1501. Alternatively, the second auxiliary reference signal segment 2012 can be disposed on the side of the fourth light-emitting segment 1301 away from the ninth light-emitting segment 1501. The first auxiliary reference signal segment 2011 and the third auxiliary reference signal line 203 can also be disposed on the side of the second light-emitting segment 122 away from the second auxiliary reference signal segment 2012. Alternatively, the first auxiliary reference signal segment 2011 and the third auxiliary reference signal line 203 can be disposed on different straight lines. The first auxiliary reference signal segment 2011 can be disposed between the second light-emitting segment 122 and the seventh light-emitting segment 1401, and the third auxiliary reference signal line 203 can be disposed on the side of the second light-emitting segment 122 away from the first auxiliary reference signal segment 2011. The third auxiliary reference signal line 203 can be set between the second light-emitting segment 122 and the seventh light-emitting segment 1401, and the first auxiliary reference signal segment 2011 can be set on the side of the second light-emitting segment 122 away from the third auxiliary reference signal line 203.

[0073] The third auxiliary reference signal segment 2013 is located between the first light-emitting segment 121 and the first clock signal line 3, and the first auxiliary reference signal segment 2011 is located on the side of the second auxiliary reference signal segment 2012 away from the third reference signal line. Without affecting the routing path of the first light-emitting lead 12, the distance from the first clock signal line 3 can be maintained, avoiding crosstalk between the clock signal and the reference signal. Simultaneously, overlap with the first light-emitting lead 12 can be avoided, preventing interference with the first light-emitting signal and the reference signal.

[0074] The orthographic projection of the first conductive layer 200 on the substrate 100 is the first orthographic projection, and the orthographic projection of the second conductive layer 300 on the substrate 100 is the second orthographic projection. The distance between the first orthographic projection and the second orthographic projection is greater than or equal to 91 μm, which can prevent corrosion from being deteriorated and migrating, reduce the probability of short circuits in the first lead and the light-emitting lead, and reduce or avoid the MiniLED light-emitting device 21 in the lamp area from exploding.

[0075] The widths of the first auxiliary reference signal line 201, the second auxiliary reference signal line 202, and the third auxiliary reference signal line 203 are all greater than or equal to 218 μm to ensure that the heat generated by the auxiliary reference signal line 2 is relatively small even when the current is large. The width of each auxiliary reference signal line 2 can vary, and its maximum size depends on the length of the second clock signal segment 302, the second power signal segment 502, and the second data signal segment 702.

[0076] The array substrate of the present invention can be bonded to light-emitting devices and used as a light-emitting substrate with light-emitting function. An embodiment of the present invention also provides a light-emitting substrate, which includes the array substrate described in the above embodiments. Since this light-emitting substrate includes the array substrate described above, it has the same beneficial effects, and will not be described again here.

[0077] As shown in Figure 13, the first light-emitting lead 12, the second light-emitting lead 13, the third light-emitting lead 14, and the fourth light-emitting lead 15 are respectively connected to four MiniLED light-emitting devices 21. The third main reference signal line 103 is recessed inward in a direction away from the first main reference signal line 101, forming four second opening regions 19. The fourth main reference signal line 104 is recessed inward in a direction away from the second main reference signal line 102, so that four third opening regions 20 are formed between the first main reference signal line 101 and the third main reference signal line 103.

[0078] The second light-emitting lead 13 and the fourth light-emitting lead 15 cross the third main reference signal line 103. Two MiniLED light-emitting devices 21 on the second light-emitting lead 13 and the fourth light-emitting lead 15 are disposed within the second opening area 19. Two other MiniLED light-emitting devices 21 are connected to the portion of the second light-emitting lead 13 and the fourth light-emitting lead 15 away from the first main reference signal line 101. The first light-emitting lead 12 and the third light-emitting lead 14 cross the fourth main reference signal line 104. Two MiniLED light-emitting devices 21 on the first light-emitting lead 12 and the third light-emitting lead 14 are disposed within the third opening area 20. Two other MiniLED light-emitting devices 21 are connected to the portion of the first light-emitting lead 12 and the third light-emitting lead 14 away from the second main reference signal line 102.

[0079] The light-emitting substrate of the present invention can also be further applied as a backlight unit in a display device. An embodiment of the present invention also provides a display device comprising the light-emitting substrate described in the above embodiments. Since this display device includes the aforementioned light-emitting substrate, it has the same beneficial effects, and will not be described again here.

[0080] This invention does not impose specific limitations on the application of display devices, which can be any product or component with flexible display function, such as televisions, laptops, tablets, wearable display devices, mobile phones, in-vehicle displays, navigation systems, e-books, digital photo frames, and advertising light boxes.

[0081] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention described herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not invented herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. An array substrate, comprising a substrate, a first conductive layer, and a second conductive layer, wherein the first conductive layer is disposed on one side of the substrate, and the second conductive layer is disposed on the side of the first conductive layer away from the substrate, wherein... The array substrate further includes: At least two main reference signal lines are disposed on the first conductive layer, the main reference signal lines extend along a first direction, and the at least two main reference signal lines are spaced apart along a second direction; A first lead extends along a first direction. The first lead includes a first lead segment and a second lead segment. The at least two first lead segments are disposed on a first conductive layer. At least two first lead segments are provided. The two first lead segments are spaced apart along the first direction. The second lead segment is located in the second conductive layer. The two ends of the second lead segment are respectively connected to the two first lead segments through vias. An auxiliary reference signal line is disposed on the first conductive layer. The auxiliary reference signal line extends along the second direction and is connected to two adjacent main reference signal lines respectively. The orthographic projection of the auxiliary reference signal line on the substrate is located between the orthographic projections of the two first lead segments on the substrate.

2. The array substrate according to claim 1, wherein, The at least two main reference signal lines include a first main reference signal line and a second main reference signal line. The first lead includes a first clock signal line, which is located between the first main reference signal line and the second main reference signal line. The first clock signal line includes a first clock signal segment and a second clock signal segment. When the first lead is the first clock signal line, the first lead segment is the first clock signal segment, and the second lead segment is the second clock signal segment. The two ends of the second clock signal segment are respectively connected to the two first clock signal segments through vias. The auxiliary reference signal line includes a first auxiliary reference signal line. At least a portion of the orthographic projection of the first auxiliary reference signal line on the substrate is located between the orthographic projections of the two first clock signal segments on the substrate. The first auxiliary reference signal line is connected to the first main reference signal line and the second main reference signal line, respectively.

3. The array substrate according to claim 2, wherein, The main reference signal line further includes a third main reference signal line, which is disposed along the second direction on the side of the first main reference signal line away from the second main reference signal line. The first lead includes a first power signal line, which is disposed between the first main reference signal line and the third main reference signal line. The first power signal line includes a first power signal segment and a second power signal segment. When the first lead is the first power signal line, the first lead segment is the first power signal segment, and the second lead segment is the second power signal segment. The two ends of the second power signal segment are respectively connected to the two first power signal segments through vias. The auxiliary reference signal line further includes a second auxiliary reference signal line. The orthographic projection of the second auxiliary reference signal line on the substrate is located between the orthographic projections of the two first power signal segments on the substrate. The second auxiliary reference signal line is connected to the first main reference signal line and the third main reference signal line respectively.

4. The array substrate according to claim 3, wherein, The primary reference signal line further includes a fourth primary reference signal line, which is disposed along the second direction on the side of the second primary reference signal line away from the first primary reference signal line. The first lead also includes a first data signal line, which is disposed between the second primary reference signal line and the fourth primary reference signal line. The first data signal line includes a first data signal segment and a second data signal segment. When the first lead is the first data signal line, the first lead segment is the first data signal segment, and the second lead segment is the second data signal segment. The two ends of the second data signal segment are respectively connected to the two first data signal segments through vias. The secondary reference signal line further includes a third secondary reference signal line, the orthographic projection of which is located between the orthographic projections of the two first data signal segments on the substrate. The third secondary reference signal line is connected to the second primary reference signal line and the fourth primary reference signal line respectively.

5. The array substrate according to claim 4, wherein, The first auxiliary reference signal line includes a first auxiliary reference signal segment, a second auxiliary reference signal segment, and a third auxiliary reference signal segment. The first auxiliary reference signal segment is connected to the second main reference signal line, and the second auxiliary reference signal segment is connected to the first main reference signal line. The first and second auxiliary reference signal segments both extend along a second direction and are located on different straight lines. The third auxiliary reference signal segment extends along a first direction, and its two ends are respectively connected to the first and second auxiliary reference signal segments. The orthographic projection of the first auxiliary reference signal segment on the substrate is located between the orthographic projections of the two first clock signal segments on the substrate.

6. The array substrate according to claim 5, wherein, The second auxiliary reference signal segment is located between the first auxiliary reference signal segment and the second auxiliary reference signal line.

7. The array substrate according to claim 6, wherein, The first auxiliary reference signal segment and the third auxiliary reference signal line extend along the second direction and are located on the same straight line. The width of the first auxiliary reference signal segment is not equal to the width of the third auxiliary reference signal line.

8. The array substrate according to claim 6, wherein, The first auxiliary reference signal segment and the third auxiliary reference signal line extend along the second direction and are located on the same straight line. The width of the first auxiliary reference signal segment is equal to the width of the third auxiliary reference signal line.

9. The array substrate according to claim 5, wherein, The array substrate further includes a second data signal line, a third data signal line, and a fourth data signal line. The second data signal line is spaced apart from the first data signal line and located on the same straight line along the first direction. The third data signal line is connected to the first data signal line, and the fourth data signal line is connected to the second data signal line. The fourth data signal line includes the third data signal segment and a fourth data signal line. The third data signal segment extends along the first direction, and the third data signal segment and the third data signal line are spaced apart in the second direction. The fourth data signal segment and the fourth data signal line extend along the second direction, and the fourth data signal segment and the third data signal line are spaced apart in the first direction.

10. The array substrate according to claim 3, wherein, The main reference signal line further includes a fourth main reference signal line, which is disposed along the second direction on the side of the second main reference signal line away from the first main reference signal line. The auxiliary reference signal line further includes a third auxiliary reference signal line, which is connected to the second main reference signal line and the fourth main reference signal line respectively. The array substrate further includes a first data signal line and a second data signal line, which are spaced apart from the first data signal line and located on the same straight line along the first direction. The third auxiliary reference signal line is disposed between the first data signal line and the second data signal line.

11. The array substrate according to claim 10, wherein, The array substrate further includes a third data signal line and a fourth data signal line disposed on the second conductive layer. The third data signal line is connected to the first data signal line, and the fourth data signal line is connected to the second data signal line. The fourth data signal line includes a third data signal segment and a fourth data signal line. The third data signal segment extends along the first direction, and the third data signal segment and the third data signal line are spaced apart in the first direction. The fourth data signal segment and the fourth data signal line are respectively disposed on both sides of the third auxiliary reference signal line.

12. The array substrate according to claim 9 or 11, wherein, The array substrate further includes light-emitting leads disposed on the second conductive layer. The light-emitting leads include a first light-emitting lead, a second light-emitting lead, a third light-emitting lead, and a fourth light-emitting lead. The first light-emitting lead and the second light-emitting lead are disposed on one side of the second auxiliary reference signal segment, and the third light-emitting lead and the fourth light-emitting lead are disposed on the other side of the second auxiliary reference signal segment.

13. The array substrate according to claim 12, wherein, The array substrate further includes a second power signal line, a connection reference signal line, a third clock signal line, and a fourth clock signal line disposed on the second conductive layer. The second power signal line is connected to the second power signal segment, the connection reference signal line is connected to the second main reference signal line, the third clock signal line is connected to the first clock signal line, and the fourth clock signal line is connected to the second clock signal line. The connection reference signal line and the third clock signal line are located between the third light-emitting lead and the third data signal line, and the second power signal line and the fourth clock signal line are located between the fourth light-emitting lead and the third data signal segment.

14. The array substrate according to claim 13, wherein, The array substrate further includes chip pads disposed between the first clock signal line and the second clock signal line. The chip pads include a first chip pad, a second chip pad, a third chip pad, a fourth chip pad, a fifth chip pad, and a sixth chip pad. The first chip pad is disposed on a first auxiliary reference signal line. The second chip pad is disposed at the adjacent ends of the first light-emitting lead and the second light-emitting lead. The third chip pad is disposed at the adjacent ends of the third light-emitting lead and the fourth light-emitting lead. The fourth chip pad is disposed at the adjacent ends of the second power signal line and the connection reference signal line. The fifth chip pad is disposed at the adjacent ends of the third clock signal line and the fourth clock signal line. The sixth chip pad is disposed at the adjacent ends of the third data signal line and the fourth data signal line. The chip pads are used to connect to the control chip.

15. The array substrate according to claim 12, wherein, The first light-emitting lead includes a first light-emitting segment and a second light-emitting segment connected in sequence. The first light-emitting segment extends along a first direction, and the second light-emitting segment extends along a second direction. The third auxiliary reference signal segment is located between the first light-emitting segment and the first clock signal line, and the first auxiliary reference signal segment is located on the side of the second auxiliary reference signal segment away from the second light-emitting segment.

16. The array substrate according to claim 1, wherein, The orthographic projection of the first conductive layer on the substrate is the first orthographic projection, and the orthographic projection of the second conductive layer on the substrate is the second orthographic projection. The distance between the first orthographic projection and the second orthographic projection is greater than or equal to 91 μm.

17. The array substrate according to claim 6 or 10, wherein, The widths of the first auxiliary reference signal line, the second auxiliary reference signal line, and the third auxiliary reference signal line are all greater than or equal to 218 μm.

18. A display device, wherein, Includes the array substrate as described in any one of claims 1 to 17.

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