Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor capable of achieving lower ESL.　A multilayer ceramic capacitor 10 according to the present invention is provided with a multilayer body having a first surface and a second surface opposing each other in the stacking direction, a third surface and a fourth surface opposing each other in a first direction orthogonal to the stacking direction, and a fifth surface and a sixth surface opposing each other in a second direction orthogonal to the stacking direction and to the first direction, a first external electrode disposed on the first and the third surfaces, a second external electrode disposed on the first and the third surfaces, a third external electrode disposed on the first and the fourth surfaces, a fourth external electrode disposed on the first and the fourth surfaces, a fifth external electrode disposed on the first and the third surfaces so as to be positioned between the first external electrode and the second external electrode, a sixth external electrode disposed on the first and the sixth surfaces, a seventh external electrode disposed on the first and the fourth surfaces so as to be positioned between the third external electrode and the fourth external electrode, and an eighth external electrode disposed on the first and the fifth surfaces. The multilayer body has a first internal electrode exposed on the third and the fourth surfaces and connected to the first external electrode or to the fourth external electrode, and a second internal electrode exposed on the third, the fourth, the fifth, and the sixth surfaces and connected to the fifth external electrode or to the eighth external electrode. When L denotes the dimension in the first direction, and W denotes the dimension in the second direction, 0.85 ≤ L / W ≤ 1.00 is satisfied.

Description

Multilayer ceramic capacitor

[0001] This invention relates to a multilayer ceramic capacitor.

[0002] In recent years, electronic devices such as mobile phones and portable music players have become smaller and thinner. Along with this, multilayer ceramic capacitors used in these smaller and thinner electronic devices have also become smaller and thinner (see Patent Document 1). In particular, multilayer ceramic capacitors that have become thinner are now being used, for example, embedded in wiring boards, or mounted on the surface of wiring boards, even in very narrow gaps.

[0003] Japanese Patent Publication No. 2021-103730

[0004] As a multilayer ceramic capacitor that can accommodate such thinning, a multilayer ceramic capacitor described in Patent Document 1 is disclosed. The multilayer ceramic capacitor described in Patent Document 1 has external electrodes at the four corners of the multilayer ceramic capacitor, and when two adjacent sides are designated as the first side and the second side, the ratio of the lengths of the first side to the second side is 0.9 or more and 1.1 or less. When the shape of a multilayer ceramic capacitor with a ratio of the lengths of the first side to the second side of 0.9 or more and 1.1 or less approaches a tetragonal crystal, it becomes easier to close-pack it into the mounting substrate, resulting in good efficiency relative to the mounting area.

[0005] However, the square-type multilayer ceramic capacitor described in Patent Document 1, etc., has four external electrodes and two lead-out sections for each internal electrode, which presents further challenges in reducing ESL.

[0006] Therefore, the primary objective of this invention is to provide a multilayer ceramic capacitor that can achieve even lower ESL.

[0007] The multilayer ceramic capacitor according to this invention comprises a laminate having a first surface and a second surface facing each other in the lamination direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the lamination direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the third surface; a third external electrode disposed on the first surface and the fourth surface; a fourth external electrode disposed on the first surface and the fourth surface; a fifth external electrode disposed on the first surface and the third surface between the first external electrode and the second external electrode; and the first surface The laminate comprises a sixth external electrode positioned on the top and sixth surfaces, a seventh external electrode positioned on the first and fourth surfaces between the third and fourth external electrodes, and an eighth external electrode positioned on the first and fifth surfaces, wherein the laminate has a first internal electrode exposed on the third and fourth surfaces and connected to the first to fourth external electrodes, and a second internal electrode exposed on the third, fourth, fifth, and sixth surfaces and connected to the fifth to eighth external electrodes, and the dimension in the first direction is L and the dimension in the second direction is W, such that 0.85 ≤ L / W ≤ 1.00.

[0008] According to the multilayer ceramic capacitor of this invention, a first external electrode is disposed on a first surface and a third surface, a second external electrode is disposed on a first surface and a third surface, a third external electrode is disposed on a first surface and a fourth surface, a fourth external electrode is disposed on a first surface and a fourth surface, a fifth external electrode is disposed on the first surface and a third surface between the first external electrode and the second external electrode, a sixth external electrode is disposed on the first surface and a sixth surface, and a third external electrode is disposed on the first surface and a fourth surface between the third external electrode and the fourth external electrode. The laminate comprises seven external electrodes and eighth external electrodes positioned on the first and fifth surfaces. The laminate also includes a first internal electrode exposed on the third and fourth surfaces and connected to the first to fourth external electrodes, and a second internal electrode exposed on the third, fourth, fifth, and sixth surfaces and connected to the fifth to eighth external electrodes. As a result, the current path between the external electrode connected to the first internal electrode and the external electrode connected to the second internal electrode can be shortened, making it possible to obtain a multilayer ceramic capacitor with low ESL under high-frequency current.

[0009] This invention provides a multilayer ceramic capacitor that can achieve even lower ESL (Electronic Stress Line) levels.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

[0011] This is an external perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is a plan view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is a bottom view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is a right side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is a schematic cross-sectional view along line VI-VI in Figure 2. This is a schematic cross-sectional view along line VII-VII in Figure 2. This is a schematic cross-sectional view along line VIII-VIII in Figure 2. This is a schematic cross-sectional view along line IX-IX in Figure 2. This is a schematic cross-sectional view along line XA-XA in Figure 4. This is a schematic cross-sectional view along line XB-XB in Figure 4. This is a schematic cross-sectional view showing the state when the first internal electrode and the second internal electrode are superimposed. (a) and (b) are schematic cross-sectional views showing modified examples of the first internal electrode of the multilayer ceramic capacitor according to the first embodiment of the present invention. (a) to (e) are schematic cross-sectional views showing modified examples of the second internal electrode of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is an external perspective view of the laminate shown in Figure 1. This is an exploded perspective view of the laminate shown in Figure 1. This is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to modified example 1-A of the first embodiment of the present invention. (a) is a cross-sectional view showing an example of a multilayer ceramic capacitor according to modified example 1-B1 of the first embodiment of the present invention, and (b) is a cross-sectional view showing an example of a multilayer ceramic capacitor according to modified example 1-B2 of the first embodiment of the present invention. This is a schematic cross-sectional view showing an example of a dummy electrode shown in Figure 16. (a) to (c) are schematic cross-sectional views showing modified examples of dummy electrodes. This is an external perspective view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. This is a plan view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. This is a bottom view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. This is a front view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. This is a right side view showing an example of a multilayer ceramic capacitor according to the second embodiment of the present invention.This is a schematic cross-sectional view of the line XXIV-XXIV in Figure 20. This is a schematic cross-sectional view of the line XXV-XXV in Figure 20. This is a schematic cross-sectional view of the line XXVI-XXVI in Figure 20. This is a schematic cross-sectional view of the line XXVII-XXVII in Figure 20. This is a schematic cross-sectional view of the line XXVIII-XXVIII in Figure 22. This is an exploded perspective view of the laminate shown in Figure 19. This is an external perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a plan view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a bottom view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a front view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a right side view showing an example of a multilayer ceramic capacitor according to the third embodiment of this invention. This is a schematic cross-sectional view of the line XXXV-XXXV in Figure 31. This is a schematic cross-sectional view of the line XXXVI-XXXVI in Figure 31. This is a schematic cross-sectional view of the line XXXVII-XXXVII shown in Figure 31. This is a schematic cross-sectional view of the line XXXVIIII-XXXVII shown in Figure 31.

[0012] A. First Embodiment 1. Multilayer Ceramic Capacitor Next, an example of a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0013] Figure 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 is a plan view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 is a bottom view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 4 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 5 is a right side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 6 is a schematic cross-sectional view along line VI-VI in Figure 2. Figure 7 is a schematic cross-sectional view along line VII-VII in Figure 2. Figure 8 is a schematic cross-sectional view along line VIII-VIII in Figure 2. Figure 9 is a schematic cross-sectional view along line IX-IX in Figure 2. Figure 10A is a schematic cross-sectional view along line XA-XA in Figure 4. Figure 10B is a schematic cross-sectional view along line XB-XB in Figure 4. Figure 11 is a schematic cross-sectional view showing the state when the first internal electrode and the second internal electrode are superimposed. Figures 12(a) and 12(b) are schematic cross-sectional views showing modified examples of the first internal electrode of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figures 13(a) to 13(e) are schematic cross-sectional views showing modified examples of the second internal electrode of a multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 14A is an external perspective view of the laminate shown in Figure 1. Figure 14B is an exploded perspective view of the laminate shown in Figure 1.

[0014] The multilayer ceramic capacitor 10 comprises a laminated body 12 and a plurality of external electrodes 30.

[0015] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b that are opposite to the lamination direction x, a third surface 12c and a fourth surface 12d that are opposite to a first direction y that is perpendicular to the lamination direction x, and a fifth surface 12e and a sixth surface 12f that are opposite to a second direction z that is perpendicular to the lamination direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the lamination direction x.

[0016] Further, it is preferable that the laminate 12 has rounded corners and ridgelines. Here, the corner is a portion where three adjacent surfaces of the laminate 12 intersect, and the ridgeline is a portion where two adjacent surfaces of the laminate 12 intersect. Also, unevenness or the like may be formed on part or all of the third surface 12c and the fourth surface 12d, and the fifth surface 12e and the sixth surface 12f.

[0017] Further, either the first surface 12a or the second surface 12b may have a roughened surface.

[0018] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layer 14 has an inner dielectric layer 14a and an outer dielectric layer 14b. Also, the internal electrode 16 has a first internal electrode 16a and a second internal electrode 16b.

[0019] Further, the laminate 12 has an inner layer portion 18, a first outer layer portion 20a located on the first surface 12a side, and a second outer layer portion 20b located on the second surface 12b side.

[0020] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of a plurality of outer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0021] The second outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of a plurality of outer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0022] And the region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0023] The inner layer portion 18 has a first internal electrode 16a exposed on the third surface 12c and the fifth surface 12e, the third surface 12c and the sixth surface 12f, the fourth surface 12d and the sixth surface 12f, and the fourth surface 12d and the fifth surface 12e, a second internal electrode 16b exposed on the third surface 12c, the fourth surface 12d, the fifth surface 12e, and the sixth surface 12f, and an inner dielectric layer 14a.

[0024] As the material of the dielectric layer 14, for example, it can be formed of a dielectric material. As the dielectric material, for example, a dielectric ceramic composed of a main component such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. Further, those obtained by adding sub-components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc. to these main components may also be used. Also, the inner dielectric layer 14a and the outer dielectric layer 14b may be composed of the same dielectric material, or may be composed of different dielectric materials for the purpose of separating functions between the inner layer portion 18 and the outer layer portions 20a, 20b. Further, at least one of Si, Mg, Ba, Mn, etc. may be added as an additive.

[0025] For example, when the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it is possible to make it difficult for dielectric breakdown to occur between the first internal electrode 16a and the second internal electrode 16b. Also, without being limited thereto, the inner dielectric layer 14a may have SrTiO3, etc. as a main component. Separately from this, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferably formed of a material having a high dielectric constant, for example, BaTiO3, etc.

[0026] The dielectric layer 14 can have a plurality of crystal grains containing a perovskite-type compound having BaTiO3 as a basic structure.

[0027] Since the smaller the thickness of the dielectric layer 14, the larger the capacitance as a capacitor, the crystal grain size is preferably 1 μm or less.

[0028] The number of dielectric layers 14 to be laminated is not particularly limited. Also, the thickness of the inner dielectric layer 14a is preferably, for example, 0.4 μm or more and 1.0 μm or less, and the total thickness of the outer dielectric layer 14b is preferably 2.0 μm or more and 50.0 μm or less. Also, the total thickness of the outer dielectric layer 14a may be 5.0 μm or more and 40.0 μm or less.

[0029] In each of the surfaces of the laminate 12, it is preferable that there be a recess in the region located between the internal electrodes 16 exposed on the third surface 12c to the sixth surface 12f, at the intersection (ridge) portions of the first surface 12a and the third surface 12c, the first surface 12a and the fourth surface 12d, the first surface 12a and the fifth surface 12e, and the first surface 12a and the sixth surface 12f.

[0030] The dimension of the central portion of the first surface 12a of the laminate 12 in the stacking direction x is T. C When T0 is the dimension in the stacking direction of the region located 5 μm from the end of the internal electrode 16 that is located at the center of the first direction y or the second direction z among the internal electrodes 16 that are drawn out onto the third surface 12c to the sixth surface 12f, C The length is preferably greater than T0 inches.

[0031] When the direction in which the third surface 12c and the fourth surface 12d face each other is defined as the first direction y, and the direction in which the fifth surface 12e and the sixth surface 12f face each other is defined as the second direction z, the dimension W in the first direction y and the dimension L in the second direction z of the laminate 12 satisfy the condition 0.85 ≤ L / W ≤ 1.00. In other words, the laminate 12 has a substantially tetragonal shape.

[0032] (Internal electrodes) The internal electrode 16 has a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are stacked via an inner dielectric layer 14a.

[0033] The first internal electrode 16a is positioned on the surface of the inner dielectric layer 14a. The first internal electrode 16a has a first opposing electrode portion 22a that faces the first surface 12a and the second surface 12b, and faces the second internal electrode 16b, and is stacked in the direction connecting the first surface 12a and the second surface 12b.

[0034] As shown in Figure 10A, the first internal electrode 16a is drawn out to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extraction electrode portion 24a, drawn out to the third surface 12c and the sixth surface 12f of the laminate 12 by the second extraction electrode portion 24b, drawn out to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the third extraction electrode portion 24c, and drawn out to the fourth surface 12d and the fifth surface 12e by the fourth extraction electrode portion 24d. Furthermore, the width to which the first lead-out electrode portion 24a is drawn out to the third surface 12c may be approximately equal to the width to which it is drawn out to the fifth surface 12e, the width to which the second lead-out electrode portion 24b is drawn out to the third surface 12c may be approximately equal to the width to which it is drawn out to the sixth surface 12f, the width to which the third lead-out electrode portion 24c is drawn out to the fourth surface 12d may be approximately equal to the width to which it is drawn out to the sixth surface 12f, and the width to which the fourth lead-out electrode portion 24d is drawn out to the fourth surface 12d may be approximately equal to the width to which it is drawn out to the fifth surface 12e.

[0035] Furthermore, the first internal electrode 16a is drawn out continuously to the third surface 12c and the fifth surface 12e of the laminate 12 by the first extraction electrode portion 24a, continuously to the third surface 12c and the sixth surface 12f of the laminate 12 by the second extraction electrode portion 24b, continuously to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the third extraction electrode portion 24c, and continuously to the fourth surface 12d and the fifth surface 12e of the laminate 12 by the fourth extraction electrode portion 24d, but is not limited to this, and may be drawn out discontinuously.

[0036] The width a between the first opposing electrode portion 22a of the first internal electrode 16a and the third surface 12c on the third surface 12c side. 11 It is preferable that the width a is between 10 μm and 60 μm. 12 The width c between the first opposing electrode portion 22a of the first internal electrode 16a and the fifth surface 12e on the fifth surface 12e side. 11is preferably 10 μm or more and 60 μm or less. The width c between the first opposed electrode portion 22a of the first internal electrode 16a and the sixth surface 12f on the sixth surface 12f side 12 is preferably 10 μm or more and 60 μm or less.

[0037] The dimension b between the first lead-out electrode portion 24a and the second lead-out electrode portion 24b located on the third surface 12c side 11 is preferably 100 μm or more. The dimension b between the third lead-out electrode portion 24c and the fourth lead-out electrode portion 24d located on the fourth surface 12d side 12 is preferably 100 μm or more. The dimension d between the first lead-out electrode portion 24a and the fourth lead-out electrode portion 24d located on the fifth surface 12e side 11 is preferably 100 μm or more. The dimension d between the second lead-out electrode portion 24b and the third lead-out electrode portion 24c located on the sixth surface 12f side 12 is preferably 100 μm or more.

[0038] As shown in FIG. 10B, the second internal electrode 16b is disposed on the surface of the inner dielectric layer 14a different from the inner dielectric layer 14a on which the first internal electrode 16a is disposed. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposed electrode portion 22b facing the first internal electrode 16a, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0039] The second internal electrode 16b is drawn out to the third surface 12c of the laminate 12 by the fifth lead-out electrode portion 24e, drawn out to the sixth surface 12f of the laminate 12 by the sixth lead-out electrode portion 24f, drawn out to the fourth surface 12d of the laminate 12 by the seventh lead-out electrode portion 24g, and drawn out to the fifth surface 12e of the laminate 12 by the eighth lead-out electrode portion 24h.

[0040] The width a between the second opposed electrode portion 22b of the second internal electrode 16b and the third surface 12c on the third surface 12c side 21 is preferably 10 μm or more and 60 μm or less. The width a between the second opposed electrode portion 22b of the second internal electrode 16b and the fourth surface 12d on the fourth surface 12d side 22The width c between the second opposing electrode portion 22b of the second internal electrode 16b and the fifth surface 12e on the fifth surface 12e side. 21 The width c between the second opposing electrode portion 22b of the second internal electrode 16b and the sixth surface 12f on the sixth surface 12f side. 22 It is preferable that the particle size is between 10 μm and 60 μm.

[0041] The width of the fifth extraction electrode portion 24e in the direction (second direction z) connecting the fifth surface 12e and the sixth surface 12f is 0.8 × b 11 Preferably, the width of the sixth extraction electrode portion 24f in the direction connecting the third surface 12c and the fourth surface 12d (first direction y) is 0.8 × d 12 Preferably, the width of the seventh extraction electrode portion 24g in the direction connecting the fifth surface 12e and the sixth surface 12f (second direction z) is 0.8 × b 12 Preferably, the width of the eighth extraction electrode portion 24h in the direction (first direction y) connecting the third surface 12c and the fourth surface 12d is 0.8 × d 11 The following is preferable:

[0042] Figure 11 shows the state when the first internal electrode 16a and the second internal electrode 16b are stacked, viewed in the direction from the first surface 12a to the second surface 12b (stacking direction x). The width a between the first opposing electrode portion 22a of the first internal electrode 16a and the third surface 12c on the third surface 12c side. 11 and the width a between the second opposing electrode portion 22b of the second internal electrode 16b on the third surface 12c side and the third surface 12c 21 The difference e1 (= |a 21 -a 11 The width a) is preferably 30 μm or less. 12 and the width a between the second opposing electrode portion 22b of the second internal electrode 16b on the fourth surface 12d side and the fourth surface 12d 22 The difference e² (= |a 22 -a 12The width c between the first opposing electrode portion 22a of the first internal electrode 16a and the fifth surface 12e on the fifth surface 12e side. 11 and the width c between the second opposing electrode portion 22b of the second internal electrode 16b on the fifth surface 12e side and the fifth surface 12e 21 The difference between e3 (= |c 21 -c 11 The width c between the first opposing electrode portion 22a of the first internal electrode 16a and the sixth surface 12f on the sixth surface 12f side. 12 and the width c between the second opposing electrode portion 22b of the second internal electrode 16b on the sixth surface 12f side and the sixth surface 12f 22 The difference between e4 (= |c 22 -c 12 The thickness of the horizontal bar (|) is preferably 30 μm or less.

[0043] The distance between the end of the first lead-out electrode portion 24a of the first internal electrode 16a that is exposed on the third surface 12c and the end of the fifth lead-out electrode portion 24e of the second internal electrode 16b that is exposed on the third surface 12c is f 11 In this case, it is preferable that the distance is 1.0 μm or more, and the distance between the end of the second lead electrode portion 24b of the first internal electrode 16a that is exposed on the third surface 12c and the end of the fifth lead electrode portion 24e of the second internal electrode 16b that is exposed on the third surface 12c that is on the sixth surface 12f side is f 12 In this case, it is preferable that it be 1.0 μm or more. The distance between the end of the fourth lead electrode portion 24d of the first internal electrode 16a that is exposed on the fourth surface 12d and the end of the seventh lead electrode portion 24g of the second internal electrode 16b that is exposed on the fourth surface 12d that is on the fifth surface 12e side is f 21 In this case, it is preferable that the distance is 1.0 μm or more, and the distance between the end of the third lead electrode portion 24c of the first internal electrode 16a that is exposed on the fourth surface 12d and the end of the fifth lead electrode portion 24e of the second internal electrode 16b that is exposed on the fourth surface 12d that is on the sixth surface 12f side is f 22In this case, it is preferable that it be 1.0 μm or more. The distance between the end of the first lead electrode portion 24a of the first internal electrode 16a that is exposed on the fifth surface 12e and the end of the eighth lead electrode portion 24h of the second internal electrode 16b that is exposed on the fifth surface 12e that is on the third surface 12c side is f 31 In this case, it is preferable that the distance is 1.0 μm or more, and the distance between the end of the fourth lead electrode portion 24d of the first internal electrode 16a that is exposed on the fifth surface 12e and the end of the eighth lead electrode portion 24h of the second internal electrode 16b that is exposed on the fifth surface 12e that is on the fourth surface 12d side is f 32 In this case, it is preferable that it be 1.0 μm or more. The distance between the end of the second lead electrode portion 24b of the first internal electrode 16a that is exposed on the sixth surface 12f and the end of the sixth lead electrode portion 24f of the second internal electrode 16b that is exposed on the sixth surface 12f that is on the third surface 12c side is f 41 In this case, it is preferable that the distance is 1.0 μm or more, and the distance between the end of the third lead electrode portion 24c of the first internal electrode 16a that is exposed on the sixth surface 12f and the end of the sixth lead electrode portion 24f of the second internal electrode 16b that is exposed on the sixth surface 12f that is on the fourth surface 12d side is f 42 In that case, it is preferable that the particle size is 1.0 μm or larger.

[0044] Here, we will describe a modified shape of the internal electrode 16. Figures 12(a) and (b) show the first internal electrode 16a1 and 16a2, which are modified shapes of the first internal electrode 16a. In the multilayer ceramic capacitor 10 according to the present invention, the first internal electrodes 16a1 and 16a2 can be used.

[0045] The first internal electrode 16a1 has a first opposing electrode portion 22a which includes a rectangular electrode positioned to connect the first leading electrode portion 24a and the third leading electrode portion 24c, and a rectangular electrode positioned to connect the second leading electrode portion 24b and the fourth leading electrode portion 24d, and these electrodes are positioned to intersect at their centers. By reducing the area of ​​the first opposing electrode portion 22a in this way, the capacitance of the multilayer ceramic capacitor 10 can be reduced. The first internal electrode 16a2 is curved such that the edge facing the third surface 12c of the first opposing electrode portion 22a is convex toward the third surface 12c, the edge facing the fourth surface 12d of the first opposing electrode portion 22a is curved such that it is convex toward the fourth surface 12d, the edge facing the fifth surface 12e of the first opposing electrode portion 22a is curved such that it is convex toward the fifth surface 12e, and the edge facing the sixth surface 12f of the first opposing electrode portion 22a is curved such that it is convex toward the sixth surface 12f. In this way, by increasing the area of ​​the first opposing electrode portion 22a, the capacitance of the multilayer ceramic capacitor 10 can be increased.

[0046] Furthermore, Figures 13(a) to (e) show modified examples of the second internal electrode 16b, namely second internal electrodes 16b1 to 16b5. In the multilayer ceramic capacitor 10 according to the present invention, the second internal electrodes 16b1 to 16b5 can be used.

[0047] The second internal electrode 16b1 has a second opposing electrode portion 22b which includes a rectangular electrode positioned to connect the fifth lead electrode portion 24e and the seventh lead electrode portion 24g, and a rectangular electrode positioned to connect the sixth lead electrode portion 24f and the eighth lead electrode portion 24h, and these electrodes are positioned to intersect at their centers. By reducing the area of ​​the second opposing electrode portion 22b in this way, the capacitance of the multilayer ceramic capacitor 10 can be reduced. The second internal electrode 16b2 has a radius (R) provided at the corners of the second opposing electrode portion 22b where the lead electrode portions 24e to 24h are not positioned. The second internal electrode 16b3 has no corners formed in the second opposing electrode portion 22b where the extraction electrode portions 24e to 24h are not arranged, and has a hypotenuse 22b1 connecting the fifth extraction electrode portion 24e and the eighth extraction electrode portion 24h, a hypotenuse 22b2 connecting the fifth extraction electrode portion 24e and the sixth extraction electrode portion 24f, a hypotenuse 22b3 connecting the seventh extraction electrode portion 24g and the sixth extraction electrode portion 24f, and a hypotenuse 22b4 connecting the seventh extraction electrode portion 24g and the eighth extraction electrode portion 24h. The second internal electrode 16b4 has, in the second opposing electrode portion 22b, a hypotenuse 24e1 and a hypotenuse 24h1 that sandwich the corner between the fifth extraction electrode portion 24e and the eighth extraction electrode portion 24h, a hypotenuse 24e2 and a hypotenuse 24f1 that sandwich the corner between the fifth extraction electrode portion 24e and the sixth extraction electrode portion 24f, a hypotenuse 24f2 and a hypotenuse 24g2 that sandwich the corner between the seventh extraction electrode portion 24g and the sixth extraction electrode portion 24f, and a hypotenuse 24g1 and a hypotenuse 24h2 that sandwich the corner between the seventh extraction electrode portion 24g and the eighth extraction electrode portion 24h.The second internal electrode 16b5 has, in the second opposing electrode portion 22b, a hypotenuse 22b5 connecting the exposed end on the fifth surface 12e side of the fifth lead-out electrode portion 24e and the exposed end on the third surface 12c side of the eighth lead-out electrode portion 24h, a 22b6 connecting the exposed end on the sixth surface 12f side of the fifth lead-out electrode portion 24e and the exposed end on the third surface 12c side of the sixth lead-out electrode portion 24f, a 22b7 connecting the exposed end on the sixth surface 12f side of the seventh lead-out electrode portion 24g and the exposed end on the fourth surface 12d side of the sixth lead-out electrode portion 24f, and a hypotenuse 22b8 connecting the exposed end on the fifth surface 12e side of the seventh lead-out electrode portion 24g and the exposed end on the fourth surface 12d side of the eighth lead-out electrode portion 24h.

[0048] As shown in Figure 10A, the laminate 12 includes a side portion (W gap) 26a1 of the laminate 12 located between one end of the first opposing electrode portion 22a of the first internal electrode 16a in the first direction y and the third surface 12c, and a side portion (W gap) 26b1 of the laminate 12 located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the first direction y and the fourth surface 12d. Furthermore, as shown in Figure 10A, the laminate 12 includes an end portion (L gap) 27a1 of the laminate 12 located between one end of the first opposing electrode portion 22a of the first internal electrode 16a in the second direction z and the fifth surface 12e, and an end portion (L gap) 26b1 of the laminate 12 located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the first direction y and the sixth surface 12f.

[0049] Furthermore, as shown in Figure 10B, the laminate 12 includes a side portion (W gap) 26a2 of the laminate 12 located between one end of the second opposing electrode portion 22b of the second internal electrode 16b in the first direction y and the third surface 12c, and a side portion (W gap) 26b2 of the laminate 12 located between the other end of the second opposing electrode portion 22b of the second internal electrode 16b in the first direction y and the fourth surface 12d. The laminate 12 also includes an end portion (L gap) 27a2 of the laminate 12 located between one end of the second opposing electrode portion 22b of the second internal electrode 16b in the second direction z and the fifth surface 12e, and a side portion (L gap) 27b2 of the laminate 12 located between the other end of the first opposing electrode portion 22a of the first internal electrode 16a in the second direction z and the sixth surface 12f.

[0050] The first internal electrode 16a and the second internal electrode 16b can be made of, but are not limited to, suitable conductive materials such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys. Furthermore, the first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or of different conductive materials.

[0051] Furthermore, by including a Sn layer between the first internal electrode 16a and the second internal electrode 16b and the inner dielectric layer 14a, electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0052] Furthermore, the number of first internal electrodes 16a and second internal electrodes 16b is not particularly limited, but it is preferable that the total number is between 3 and 300. Also, the thickness of the first internal electrodes 16a and second internal electrodes 16b is not particularly limited, but it is preferable that it is, for example, between 0.2 μm and 0.6 μm. Furthermore, the thickness of the first internal electrodes 16a and second internal electrodes 16b may be between 0.3 μm and 0.5 μm.

[0053] The laminated body 12 of the multilayer ceramic capacitor 10 may have the configuration described below.

[0054] In the multilayer ceramic capacitor 10, the third surface 12c to the sixth surface 12f of the laminate 12 may be curved in a concave shape toward the center of the laminate 12 when viewed in the stacking direction x. In other words, the third surface 12c to the sixth surface 12f of the laminate 12 may be partially curved. In this case, the center of the curvature and curvature is preferably near the center between the internal electrodes exposed on the third surface 12c to the sixth surface 12f. This makes it possible to increase the distance between adjacent external electrodes 30, as described later, and thus reduces the risk of electrical conductivity between each external electrode 30.

[0055] Furthermore, in at least one of the first direction y-view and the second direction z-view, the region where the internal electrode 16 is drawn out onto the third surface 12c to the sixth surface 12f may have a radius (R) from the first surface 12a to the second surface 12b. This increases the exposed area of ​​the internal electrode 16, thereby improving the contact area between the internal electrode 16 and the external electrode 30.

[0056] (External electrodes) External electrodes 30 are arranged on the laminate 12 as shown in Figures 1 to 9. The external electrodes 30 have a plurality of external electrodes 30 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, a fourth external electrode 30d, a fifth external electrode 30e, a sixth external electrode 30f, a seventh external electrode 30g, and an eighth external electrode 30h.

[0057] The first external electrode 30a is positioned on the third surface 12c and the fifth surface 12e so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a. The second external electrode 30b is positioned on the third surface 12c and the sixth surface 12f so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a. The third external electrode 30c is positioned on the fourth surface 12d and the sixth surface 12f so as to cover the third lead electrode portion 24c of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the first internal electrode 16a. The fourth external electrode 30d is positioned on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the first internal electrode 16a.

[0058] The fifth external electrode 30e is positioned on the third surface 12c so as to cover the fifth lead electrode portion 24e of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a. The fifth external electrode 30e is electrically connected to the fifth lead electrode portion 24e of the second internal electrode 16b. The sixth external electrode 30f is positioned on the sixth surface 12f so as to cover the sixth lead electrode portion 24f of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a. The sixth external electrode 30f is electrically connected to the sixth lead electrode portion 24f of the second internal electrode 16b. The seventh external electrode 30g is positioned on the fourth surface 12d so as to cover the seventh lead electrode portion 24g of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a. The seventh external electrode 30g is electrically connected to the seventh lead electrode portion 24g of the second internal electrode 16b. The eighth external electrode 30h is positioned on the fifth surface 12e so as to cover the eighth lead electrode portion 24h of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a. The eighth external electrode 30h is electrically connected to the eighth lead electrode portion 24h of the second internal electrode 16b.

[0059] As shown in Figure 2, when the maximum value of the dimension of the first external electrode 30a in the second direction z is eL1, the maximum value of the dimension of the fifth external electrode 30e in the second direction z is eL2, and the maximum value of the dimension of the second external electrode 30b in the second direction z is eL3, and when the maximum distance in the second direction z between the end of the first external electrode 30a on the fifth surface side and the end of the second external electrode 30b on the sixth surface side is L1 (i.e., the dimension of the multilayer ceramic capacitor 10 in the second direction z on the third surface 12c side), it is preferable that 0.23 ≤ (eL1 + eL2 + eL3) / L1 ≤ 0.84, and more preferably that 0.48 ≤ (eL1 + eL2 + eL3) / L1 ≤ 0.72. This improves the alignment when mounting the multilayer ceramic capacitor 10 onto the mounting substrate.

[0060] Furthermore, as shown in Figure 2, when the maximum value of the dimension of the fourth external electrode 30d in the second direction z is eL4, the maximum value of the dimension of the seventh external electrode 30g in the second direction z is eL5, and the maximum value of the dimension of the third external electrode 30c in the second direction z is eL6, and L2 is the maximum distance in the second direction z between the end of the fourth external electrode 30d on the fifth surface 12e side and the end of the third external electrode 30c on the sixth surface 12f side (i.e., the dimension of the multilayer ceramic capacitor 10 in the second direction z on the fourth surface 12d side), it is preferable that 0.22 ≤ (eL4 + eL5 + eL6) / L2 ≤ 0.85, and more preferably that 0.48 ≤ (eL4 + eL5 + eL6) / L2 ≤ 0.72. This improves the alignment of the multilayer ceramic capacitor 10 when it is mounted on the mounting substrate.

[0061] As shown in Figure 2, in a view from the first surface 12a toward the second surface 12b (view in the stacking direction x), the surface area of ​​the first external electrode 30a located on the first surface 12a side of the stacked body 12 is A1, the surface area of ​​the second external electrode 30b is A2, the surface area of ​​the third external electrode 30c is A3, the surface area of ​​the fourth external electrode 30d is A4, the surface area of ​​the fifth external electrode 30e is A5, the surface area of ​​the sixth external electrode 30f is A6, the surface area of ​​the seventh external electrode 30g is A7, and the surface area of ​​the eighth external electrode 30h is A8.

[0062] When the sum of surface areas A1, A2, A3, and A4 is defined as SS1, and the sum of surface areas A5, A6, A7, and A8 is defined as SS2, it is preferable that 0.66 ≤ SS1 / SS2 ≤ 1.24. This improves the adhesion force of the multilayer ceramic capacitor 10 to the mounting substrate.

[0063] When the smallest area among surface areas A1, A2, A3, and A4 is denoted as min[A1, A2, A3, A4], and the largest area among surface areas A1, A2, A3, and A4 is denoted as max[A1, A2, A3, A4], it is preferable that min[A1, A2, A3, A4] / max[A1, A2, A3, A4] ≥ 0.33. Furthermore, when the smallest area among surface areas A5, A6, A7, and A8 is represented as min[A5, A6, A7, A8], and the largest area among surface areas A5, A6, A7, and A8 is represented as max[A5, A6, A7, A8], it is preferable that min[A5, A6, A7, A8] / max[A5, A6, A7, A8] ≥ 0.38. This makes it possible to further improve the alignment of the multilayer ceramic capacitor 10 when it is mounted on the mounting substrate.

[0064] Within the laminate 12, capacitance is formed when the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a. As a result, capacitance can be obtained between the first external electrode 30a, second external electrode 30b, third external electrode 30c, and fourth external electrode 30d, to which the first internal electrode 16a is connected, and the fifth external electrode 30e, sixth external electrode 30f, seventh external electrode 30g, and eighth external electrode 30h, to which the second internal electrode 16b is connected, and the characteristics of a capacitor are exhibited.

[0065] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, the fourth external electrode 30d, the fifth external electrode 30e, the sixth external electrode 30f, the seventh external electrode 30g, and the eighth external electrode 30h each preferably have a seed electrode layer 32 and a plating layer. The plating layer preferably has an undercoat plating layer 34, a lower plating layer 36, and a surface plating layer 38.

[0066] In other words, it is preferable that the first external electrode 30a has a first seed electrode layer 32a, a first undercoat plating layer 34a, a first lower plating layer 36a, and a first surface plating layer 38a. It is preferable that the second external electrode 30b has a second seed electrode layer 32b, a second undercoat plating layer 34b, a second lower plating layer 36b, and a second surface plating layer 38b. It is preferable that the third external electrode 30c has a third seed electrode layer 32c, a third undercoat plating layer 34c, a third lower plating layer 36c, and a third surface plating layer 38c. It is preferable that the fourth external electrode 30d has a fourth seed electrode layer 32d, a fourth undercoat plating layer 34d, a fourth lower plating layer 36d, and a fourth surface plating layer 38d.

[0067] Furthermore, it is preferable that the fifth external electrode 30e has a fifth seed electrode layer 32e, a fifth under-plating layer 34e, a fifth lower-plating layer 36e, and a fifth surface-plating layer 38e. It is preferable that the sixth external electrode 30f has a sixth seed electrode layer 32f, a sixth under-plating layer 34f, a sixth lower-plating layer 36f, and a sixth surface-plating layer 38f. It is preferable that the seventh external electrode 30g has a seventh seed electrode layer 32g, a seventh under-plating layer 34g, a seventh lower-plating layer 36g, and a seventh surface-plating layer 38g. It is preferable that the eighth external electrode 30h has an eighth seed electrode layer 32h, an eighth under-plating layer 34h, an eighth lower-plating layer 36h, and an eighth surface-plating layer 38h.

[0068] (Seed electrode layer) The seed electrode layer 32 includes a first seed electrode layer 32a, a second seed electrode layer 32b, a third seed electrode layer 32c, a fourth seed electrode layer 32d, a fifth seed electrode layer 32e, a sixth seed electrode layer 32f, a seventh seed electrode layer 32g, and an eighth seed electrode layer 32h.

[0069] The first seed electrode layer 32a is positioned to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the fifth surface 12e side. The second seed electrode layer 32b is positioned to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the sixth surface 12f side. The third seed electrode layer 32c is positioned to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side. The fourth seed electrode layer 32d is positioned to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side.

[0070] The fifth seed electrode layer 32e is positioned to cover a portion of the first surface 12a of the laminate 12 in the intermediate portion between the fifth surface 12e and the sixth surface 12f on the third surface 12c side. The sixth seed electrode layer 32f is positioned to cover a portion of the first surface 12a of the laminate 12 in the intermediate portion between the third surface 12c and the fourth surface 12d on the sixth surface 12f side. The seventh seed electrode layer 32g is positioned to cover a portion of the first surface 12a of the laminate 12 in the intermediate portion between the fifth surface 12e and the sixth surface 12f on the fourth surface 12d side. The eighth seed electrode layer 32h is positioned to cover a portion of the first surface 12a of the laminate 12 in the intermediate portion between the third surface 12c and the fourth surface 12d on the fifth surface 12e side.

[0071] Preferably, each of the first seed electrode layer 32a to the eighth seed electrode layer 32h is formed by depositing metal particles using a sputtering method or a vapor deposition method. This allows the thickness of the first seed electrode layer 32a to the eighth seed electrode layer 32h in the direction connecting the first surface 12a and the second surface 12b of the laminate 12 to be 1 μm or less, and the dimension of the multilayer ceramic capacitor 10 in the stacking direction x can be sufficiently reduced, thus enabling the multilayer ceramic capacitor 10 to be made low-profile.

[0072] Furthermore, the method for measuring the dimension in the stacking direction x of the first seed electrode layer 32a to the eighth seed electrode layer 32h can be as follows. That is, when forming the seed electrode layer by depositing metal particles, a method can be used in which a fluorescence X-ray device is used to calculate the thickness from the concentration of a predetermined element using a calibration curve method for the relevant metal species. Alternatively, the thickness can be measured by observing the cross-section of the component using FIB with a scanning microscope and taking the actual observed image.

[0073] Furthermore, when the first seed electrode layer 32a to the fourth seed electrode layer 32d are formed by a thin-film formation method, these seed electrode layers are preferably made of a metal such as Cu or Ni.

[0074] The seed electrode layer 32 of the multilayer ceramic capacitor 10 shown in Figure 1 is formed by depositing metal particles by sputtering. In this case, if the thickness of the seed electrode layer 32 is 1 μm or less, the dimension in the stacking direction x can be made sufficiently small.

[0075] When forming the seed electrode layer 32 by sputtering, the first seed electrode layer 32a to the eighth seed electrode layer 32h can be configured considering their respective functions. For example, considering adhesion to the laminate 12, it is preferable to use NiCr or NiCu as the main component. Also, the first seed electrode layer 32a to the fourth seed electrode layer 32d may consist of multiple layers, and may have a two-layer structure of NiCr and NiCu.

[0076] The seed electrode layer 32 may be formed by screen printing or the like and contain a dielectric material and a metal component. In this case, in addition to the metal component, it may also contain a ceramic component having the same main component as the inner dielectric layer 14a. Including a ceramic component in the seed electrode layer 32 reduces the difference in thermal expansion coefficient between the laminate 12 and the seed electrode layer 32, thereby easing the stress on the seed electrode layer 32. However, the metal component is not limited to Cu and Ni and may contain other metal components, and may also contain a glass component in addition to the ceramic component. Examples of glass components include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Examples of other metal components may include Mg, Cr, Sr, Al, Na, Fe, etc. Furthermore, the seed electrode layer 32 may have a discontinuous shape. Discontinuity means that it is formed discontinuously when viewed from a direction perpendicular to the longitudinal direction.

[0077] For example, when forming a seed electrode layer 32 using a material containing ceramic, one method involves performing cross-sectional polishing, then acquiring cross-sectional images using a digital microscope (Keyence VHX-5000), and performing thickness calculations from these images. Alternatively, one method involves measuring the thickness and other properties from the actual observed image of the part cross-section created by FIB using a scanning microscope.

[0078] (Undercoat plating layer) The undercoat plating layer 34 includes a first undercoat plating layer 34a, a second undercoat plating layer 34b, a third undercoat plating layer 34c, a fourth undercoat plating layer 34d, a fifth undercoat plating layer 34e, a sixth undercoat plating layer 34f, a seventh undercoat plating layer 34g, and an eighth undercoat plating layer 34h.

[0079] The first undercoat plating layer 34a is positioned to cover a portion of each of the third surface 12c and the fifth surface 12e of the laminate 12, as well as the first lead-out electrode portion 24a of the first internal electrode 16a that is exposed from the ridge between them. The first undercoat plating layer 34a is also positioned to cover the first seed electrode layer 32a. The first undercoat plating layer 34a is electrically directly connected to the first lead-out electrode portion 24a of the first internal electrode 16a. The second undercoat plating layer 34b is positioned to cover a portion of each of the third surface 12c and the sixth surface 12f of the laminate 12, as well as the second lead-out electrode portion 24b of the first internal electrode 16a that is exposed from the ridge between them. The second undercoat plating layer 34b is also positioned to cover the second seed electrode layer 32b. The second undercoat plating layer 34b is electrically directly connected to the second lead electrode portion 24b of the first internal electrode 16a. The third undercoat plating layer 34c is positioned to cover a portion of each of the fourth surface 12d and the sixth surface 12f of the laminate 12, as well as the third lead electrode portion 24c of the first internal electrode 16a that is exposed from the ridge between them. The third undercoat plating layer 34c is also positioned to cover the third seed electrode layer 32c. The third undercoat plating layer 34c is electrically directly connected to the third lead electrode portion 24c of the first internal electrode 16a. The fourth undercoat plating layer 34d is positioned to cover a portion of each of the fourth surface 12d and the fifth surface 12e of the laminate 12, as well as the fourth lead electrode portion 24d of the first internal electrode 16a that is exposed from the ridge between them. Furthermore, the fourth undercoat plating layer 34d is positioned to cover the fourth seed electrode layer 32d. The fourth undercoat plating layer 34d is electrically directly connected to the fourth lead electrode portion 24d of the first internal electrode 16a.

[0080] The fifth underplating layer 34e is positioned to cover the fifth lead electrode portion 24e of the second internal electrode 16b, which is exposed from a portion of the third surface 12c of the laminate 12. The fifth underplating layer 34e is also positioned to cover the fifth seed electrode layer 32e. The fifth underplating layer 34e is electrically directly connected to the fifth lead electrode portion 24e of the second internal electrode 16b. The sixth underplating layer 34f is positioned to cover the sixth lead electrode portion 24f of the second internal electrode 16b, which is exposed from a portion of the sixth surface 12f of the laminate 12. The sixth underplating layer 34f is also positioned to cover the sixth seed electrode layer 32f. The sixth underplating layer 34f is electrically directly connected to the sixth lead electrode portion 24f of the second internal electrode 16b. The seventh underplating layer 34g is positioned to cover the seventh lead electrode portion 24g of the second internal electrode 16b, which is exposed from a part of the fourth surface 12d of the laminate 12. The seventh underplating layer 34g is also positioned to cover the seventh seed electrode layer 32g. The seventh underplating layer 34g is electrically directly connected to the seventh lead electrode portion 24g of the second internal electrode 16b. The eighth underplating layer 34h is positioned to cover the eighth lead electrode portion 24h of the second internal electrode 16b, which is exposed from a part of the fifth surface 12e of the laminate 12. The eighth underplating layer 34h is also positioned to cover the eighth seed electrode layer 32h. The eighth underplating layer 34h is electrically directly connected to the eighth lead electrode portion 24h of the second internal electrode 16b.

[0081] The undercoat plating layer 34 is not particularly limited as long as it contains at least one metal selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc., as the main metal component. For example, when the first internal electrode 16a and the second internal electrode 16b are formed using Ni, it is preferable to use Cu plating, which has good bonding properties with Ni. Alternatively, there may be another layer of Cu plating with a different particle size.

[0082] The undercoat plating layer 34 is formed by the growth of plating from the internal electrode 16 and the seed electrode layer 32.

[0083] The thickness of each undercoat plating layer 34 is preferably 0.5 μm or more and 10.0 μm or less.

[0084] (Underlayer plating) The underlayer plating layer 36 includes a first underlayer plating layer 36a, a second underlayer plating layer 36b, a third underlayer plating layer 36c, a fourth underlayer plating layer 36d, a fifth underlayer plating layer 36e, a sixth underlayer plating layer 36f, a seventh underlayer plating layer 36g, and an eighth underlayer plating layer 36h.

[0085] The first lower plating layer 36a is positioned to cover the first base plating layer 34a. The second lower plating layer 36b is positioned to cover the second base plating layer 34b. The third lower plating layer 36c is positioned to cover the third base plating layer 34c. The fourth lower plating layer 36d is positioned to cover the fourth base plating layer 34d.

[0086] The fifth lower plating layer 36e is positioned to cover the fifth base plating layer 34e. The sixth lower plating layer 36f is positioned to cover the sixth base plating layer 34f. The seventh lower plating layer 36g is positioned to cover the seventh base plating layer 34g. The eighth lower plating layer 36h is positioned to cover the eighth base plating layer 34h.

[0087] The lower plating layer 36 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The lower plating layer 36 is preferably Ni plating.

[0088] Furthermore, the thickness of the lower plating layer 36 is preferably, for example, 1 μm or more and 10 μm or less.

[0089] (Surface Plating Layer) The surface plating layer 38 includes a first surface plating layer 38a, a second surface plating layer 38b, a third surface plating layer 38c, a fourth surface plating layer 38d, a fifth surface plating layer 38e, a sixth surface plating layer 38f, a seventh surface plating layer 38g, and an eighth surface plating layer 38h.

[0090] The first surface plating layer 38a is arranged to cover the first lower plating layer 36a. The second surface plating layer 38b is arranged to cover the second lower plating layer 36b. The third surface plating layer 38c is arranged to cover the third lower plating layer 36c. The fourth surface plating layer 38d is arranged to cover the fourth lower plating layer 36d.

[0091] The fifth surface plating layer 38e is arranged to cover the fifth lower plating layer 36e. The sixth surface plating layer 38f is arranged to cover the sixth lower plating layer 36f. The seventh surface plating layer 38g is arranged to cover the seventh lower plating layer 36g. The eighth surface plating layer 38h is arranged to cover the eighth lower plating layer 36h.

[0092] The surface plating layer 38 is preferably, for example, Sn plating.

[0093] Furthermore, the thickness of the surface plating layer 38 is preferably, for example, 0.5 μm or more and 10 μm or less.

[0094] The plating layer may consist only of the lower plating layer 36. In this case, the first lower plating layer 36a is arranged to cover the first seed electrode layer 32a, and the second lower plating layer 36b is arranged to cover the second seed electrode layer 32b. Similarly, the third lower plating layer 36c is arranged to cover the third seed electrode layer 32c, and the fourth lower plating layer 36d is arranged to cover the fourth seed electrode layer 32d. Similarly, the fifth lower plating layer 36e is arranged to cover the fifth seed electrode layer 32e, the sixth lower plating layer 36f is arranged to cover the sixth seed electrode layer 32f, the seventh lower plating layer 36g is arranged to cover the seventh seed electrode layer 32g, and the eighth lower plating layer 36h is arranged to cover the eighth seed electrode layer 32h.

[0095] The plating layer preferably contains at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal. The plating layer preferably does not contain glass.

[0096] The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0097] The thickness of each plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0098] The dimension of the multilayer ceramic capacitor 10, including the laminate 12 and external electrodes 30, in the first direction y is defined as L, the dimension of the multilayer ceramic capacitor 10, including the laminate 12 and external electrodes 30, in the stacking direction x is defined as T, and the dimension of the multilayer ceramic capacitor 10, including the laminate 12 and external electrodes 30, in the second direction z is defined as W. Preferably, the dimensions of the multilayer ceramic capacitor 10 are such that the W dimension in the first direction y is 400 μm or more and 1300 μm or less, the T dimension in the stacking direction x is 50 μm or more and 220 μm or less, and the L dimension in the second direction z is 400 μm or more and 1300 μm or less. Preferably, the dimensions of the multilayer ceramic capacitor 10 are such that 0.85 ≤ L / W ≤ 1.00. By doing so, the laminate 12 becomes approximately tetragonal in shape, which improves the degree of freedom in mounting.

[0099] According to the multilayer ceramic capacitor 10 shown in Figure 1, a first external electrode 30a is arranged on the first surface 12a and the third surface 12c, a second external electrode 30b is arranged on the first surface 12a and the third surface 12c, a third external electrode 30c is arranged on the first surface 12a and the fourth surface 12d, a fourth external electrode 30d is arranged on the first surface 12a and the fourth surface 12d, a fifth external electrode 30e is arranged on the first surface 12a and the third surface 12c between the first external electrode 30a and the second external electrode 30b, a sixth external electrode 30f is arranged on the first surface 12a and the sixth surface 12f, and a third external electrode 30c is arranged on the first surface 12a and the fourth surface 12d between the third external electrode 30c and the fourth external electrode 30d The laminate 12 includes a seventh external electrode 30g and an eighth external electrode positioned on the first surface 12a and the fifth surface 12e. The laminate 12 includes a first internal electrode 16a exposed on at least the third surface 12c and the fourth surface 12d and connected to the first external electrode 30a to the fourth external electrode 30d, and a second internal electrode 16b exposed on the third surface 12c, the fourth surface 12d, the fifth surface 12e and the sixth surface 12f and connected to the fifth external electrode 30e to the eighth external electrode 30h. As a result, the current path between the external electrode 30 connected to the first internal electrode 16a and the external electrode 30 connected to the second internal electrode 16b can be shortened, making it possible to obtain a multilayer ceramic capacitor 10 with low ESL under high-frequency current.

[0100] 2. Modified Examples Next, an example of a multilayer ceramic capacitor 10A according to Modified Example 1-A of the First Embodiment of the present invention will be described. Figure 15 is a schematic cross-sectional view showing an example of a multilayer ceramic capacitor according to Modified Example 1-A of the First Embodiment of the present invention. However, components that are the same as or corresponding to those in Figures 1 to 9 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0101] As shown in Figure 15, in the modified example 1-A of the first embodiment, the external electrode 30 of the multilayer ceramic capacitor 10A has a configuration in which the undercoat plating layer 34 does not cover the seed electrode layer 32.

[0102] Figure 15 shows the first external electrode 30a, the second external electrode 30b, and the fifth external electrode 30e as examples. The first external electrode 30a includes a first seed electrode layer 32a, a first under-plating layer 34a, a first lower-layer plating layer 36a covering the first seed electrode layer 32a and the first under-plating layer 34a, and a first surface-layer plating layer 38a covering the first lower-layer plating layer 36a. The second external electrode 30b includes a second seed electrode layer 32b, a second under-plating layer 34b, a second lower-layer plating layer 36b covering the second seed electrode layer 32b and the second under-plating layer 34b, and a second surface-layer plating layer 38b covering the second lower-layer plating layer 36b. The fifth external electrode 30e includes a fifth seed electrode layer 32e, a fifth under-plating layer 34e (not shown), a fifth lower-layer plating layer 36e covering the fifth seed electrode layer 32e and the fifth under-plating layer 34e, and a fifth surface-layer plating layer 38e covering the fifth lower-layer plating layer 36e.

[0103] The first undercoat plating layer 34a is arranged to cover a portion of each of the third surface 12c and the fifth surface 12e of the laminate 12, as well as the ridge portion sandwiched between them. The first undercoat plating layer 34a is electrically directly connected to the first lead electrode portion 24a of the first internal electrode 16a. The second undercoat plating layer 34b is arranged to cover a portion of each of the third surface 12c and the sixth surface 12f of the laminate 12, as well as the ridge portion sandwiched between them. The second undercoat plating layer 34b is electrically directly connected to the second lead electrode portion 24b of the first internal electrode 16a. The fifth undercoat plating layer 34e, although not shown, is arranged to cover a portion of the third surface 12c of the laminate 12. The fifth undercoat plating layer 34e is electrically directly connected to the fifth lead electrode portion 24e of the second internal electrode 16b. Furthermore, although not shown in the figures, the same applies to the third underplating layer of the third external electrode 30c, the fourth underplating layer of the fourth external electrode 30d, the fifth underplating layer of the sixth external electrode 30f, the sixth underplating layer of the seventh external electrode 30g, and the eighth underplating layer of the eighth external electrode 30h.

[0104] Preferably, the upper end of the first undercoat 34a of the first external electrode 30a is positioned to overlap the lower side of the first seed electrode layer 32a on the ridge formed by the first surface 12a, the third surface 12c, and the fifth surface 12e of the laminate 12. Preferably, the upper end of the second undercoat 34b of the second external electrode 30b is positioned to overlap the lower side of the second seed electrode layer 32b on the ridge formed by the first surface 12a, the third surface 12c, and the sixth surface 12f of the laminate 12. Preferably, the upper end of the fifth undercoat 34e of the fifth external electrode 30e is positioned to overlap the lower side of the fifth seed electrode layer 32e on the ridge formed by the first surface 12a and the third surface 12c of the laminate 12 (not shown). Furthermore, although not shown in the figures, the same applies to the third underplating layer of the third external electrode 30c, the fourth underplating layer of the fourth external electrode 30d, the fifth underplating layer of the sixth external electrode 30f, the sixth underplating layer of the seventh external electrode 30g, and the eighth underplating layer of the eighth external electrode 30h.

[0105] The upper ends of the first undercoat 34a, the second undercoat 34b, and the fifth undercoat 34e may be positioned at a distance from the first seed electrode layer 32a, the second seed electrode layer 32b, and the fifth seed electrode layer 32e, respectively. The same applies to the third undercoat of the third external electrode 30c, the fourth undercoat of the fourth external electrode 30d, the fifth undercoat of the sixth external electrode 30f, the sixth undercoat of the seventh external electrode 30g, and the eighth undercoat of the eighth external electrode 30h, although these are not shown in the figures.

[0106] The multilayer ceramic capacitor 10A according to modification 1-A of the first embodiment shown in Figure 15 provides the same effects as the multilayer ceramic capacitor 10 described above, as well as the following effects. That is, by forming the undercoat plating layer 34 only on each side surface of the laminate 12, the thickness of the external electrode 30 formed on the first surface 12a in the stacking direction can be reduced, so that a low-profile multilayer ceramic capacitor can be provided without impairing the mountability during mounting.

[0107] (2) Second Modification Next, examples of multilayer ceramic capacitors 10B1 and 10B2 according to the first embodiment of the present invention will be described. Figure 16(a) is a cross-sectional view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention, and Figure 16(b) is a cross-sectional view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention, 10B1. Figure 17 is a schematic cross-sectional view showing an example of a dummy electrode shown in Figure 16. However, components that are the same as or corresponding to those in Figures 1 to 9 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0108] In the multilayer ceramic capacitor 10B1, the dummy electrode 28 is placed on the outer dielectric layer 14b. Therefore, as shown in Figure 16(a), the dummy electrode 28 is placed inside the first outer layer 20a and on a dielectric layer 14 different from the dielectric layer 14 on which the first internal electrode 16a and the second internal electrode 16b are placed. In this case, the dummy electrode 28 may have a thickness in the stacking direction x greater than that of the first internal electrode 16a and the second internal electrode 16b.

[0109] More specifically, as shown in Figure 17, the dummy electrode 28 includes a first dummy electrode 28a, a second dummy electrode 28b, a third dummy electrode 28c, a fourth dummy electrode 28d, a fifth dummy electrode 28e, a sixth dummy electrode 28f, a seventh dummy electrode 28g, and an eighth dummy electrode 28h.

[0110] The first dummy electrode 28a is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b on the third surface 12c side and the fifth surface 12e side. The first dummy electrode 28a is exposed from the third surface 12c and the fifth surface 12e. The second dummy electrode 28b is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b on the third surface 12c side and the sixth surface 12f side. The second dummy electrode 28b is exposed from the third surface 12c and the sixth surface 12f. The third dummy electrode 28c is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b on the fourth surface 12d side and the sixth surface 12f side. The third dummy electrode 28c is exposed from the fourth surface 12d and the sixth surface 12f. The fourth dummy electrode 28d is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b on the fourth surface 12d side and the fifth surface 12e side. The fourth dummy electrode 28d is exposed from the fourth surface 12d and the fifth surface 12e.

[0111] The fifth dummy electrode 28e is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b in the intermediate portion between the fifth surface 12e and the sixth surface 12f on the third surface 12c side. The fifth dummy electrode 28e is exposed from the third surface 12c. The sixth dummy electrode 28f is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b in the intermediate portion between the third surface 12c and the fourth surface 12d on the sixth surface 12f side. The sixth dummy electrode 28f is exposed from the sixth surface 12f. The seventh dummy electrode 28g is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b in the intermediate portion between the fifth surface 12e and the sixth surface 12f on the fourth surface 12d side. The seventh dummy electrode 28g is exposed from the fourth surface 12d. The eighth dummy electrode 28h is arranged in a rectangular shape so as to cover a portion of the outer dielectric layer 14b in the intermediate area between the third surface 12c and the fourth surface 12d on the fifth surface 12e side. The eighth dummy electrode 28h is exposed from the fifth surface 12e.

[0112] Furthermore, the dummy electrode 28 in the multilayer ceramic capacitor 10B2 is placed on the outer dielectric layer 14b. In addition, as shown in Figure 16(b), it may be placed exposed on the surface of the first surface 12a, not just the first outer layer portion 20a. Furthermore, although not shown, the dummy electrode 28 may also be placed on the surface of the second surface 12b. This eliminates the need to add a new step in the manufacturing process of placing a base electrode on the first surface 12a or the second surface 12b, thereby reducing manufacturing costs.

[0113] The material of the dummy electrode 28 is preferably made of a metal such as Cu or Ni, and preferably has the same main components as the main components contained in the seed electrode layer 32.

[0114] Here, a modified example of the dummy electrode 28 will be described. Figures 18(a) to 18(c) are schematic cross-sectional views showing modified examples of the dummy electrode. In the multilayer ceramic capacitors 10A, B1, and B2 according to the present invention, dummy electrodes 281 to 283 can be used.

[0115] As shown in Figure 18(a), the dummy electrode 281 includes a first dummy electrode 28a1, a second dummy electrode 28b1, a third dummy electrode 28c1, a fourth dummy electrode 28d1, a fifth dummy electrode 28e1, a sixth dummy electrode 28f1, a seventh dummy electrode 28g1, and an eighth dummy electrode 28h1.

[0116] The first dummy electrode 28a1 is arranged in an L-shape so as to cover a portion of the outer dielectric layer 14b along the third surface 12c and the fifth surface 12e. The first dummy electrode 28a1 is exposed from the third surface 12c and the fifth surface 12e. The second dummy electrode 28b1 is arranged in an L-shape so as to cover a portion of the outer dielectric layer 14b along the third surface 12c and the sixth surface 12f. The second dummy electrode 28b1 is exposed from the third surface 12c and the sixth surface 12f. The third dummy electrode 28c1 is arranged in an L-shape so as to cover a portion of the outer dielectric layer 14b along the fourth surface 12d and the sixth surface 12f. The third dummy electrode 28c1 is exposed from the fourth surface 12d and the sixth surface 12f. The fourth dummy electrode 28d1 is arranged in an L-shape so as to cover a portion of the outer dielectric layer 14b along the fourth surface 12d and the fifth surface 12e. The fourth dummy electrode 28d1 is exposed from the fourth surface 12d and the fifth surface 12e.

[0117] The fifth dummy electrode 28e1 is common to the fifth dummy electrode 28e, the sixth dummy electrode 28f1 is common to the sixth dummy electrode 28f, the seventh dummy electrode 28g1 is common to the seventh dummy electrode 28g, and the eighth dummy electrode 28h1 is common to the eighth dummy electrode 28h.

[0118] As shown in Figure 18(b), the dummy electrode 282 includes a first dummy electrode 28a2, a second dummy electrode 28b2, a third dummy electrode 28c2, a fourth dummy electrode 28d2, a fifth dummy electrode 28e2, a sixth dummy electrode 28f2, a seventh dummy electrode 28g2, and an eighth dummy electrode 28h2.

[0119] The first dummy electrode 28a2 is common to the first dummy electrode 28a, the second dummy electrode 28b2 is common to the second dummy electrode 28b, the third dummy electrode 28c2 is common to the third dummy electrode 28c, and the fourth dummy electrode 28d2 is common to the eighth dummy electrode 28h.

[0120] The fifth dummy electrode 28e2 is arranged in an I-shape along the third surface 12c so as to cover a portion of the outer dielectric layer 14b in the intermediate portion between the fifth surface 12e and the sixth surface 12f. The fifth dummy electrode 28e2 is exposed from the third surface 12c. The sixth dummy electrode 28f2 is arranged in an I-shape along the sixth surface 12f so as to cover a portion of the outer dielectric layer 14b in the intermediate portion between the third surface 12c and the fourth surface 12d. The sixth dummy electrode 28f2 is exposed from the sixth surface 12f. The seventh dummy electrode 28g2 is arranged in an I-shape along the fourth surface 12d so as to cover a portion of the outer dielectric layer 14b in the intermediate portion between the fifth surface 12e and the sixth surface 12f. The seventh dummy electrode 28g2 is exposed from the fourth surface 12d. The eighth dummy electrode 28h2 is arranged in an I-shape along the fifth surface 12e, covering a portion of the outer dielectric layer 14b in the intermediate area between the third surface 12c and the fourth surface 12d. The eighth dummy electrode 28h2 is exposed from the fifth surface 12e.

[0121] As shown in Figure 18(c), the dummy electrode 283 includes a first dummy electrode 28a3, a second dummy electrode 28b3, a third dummy electrode 28c3, a fourth dummy electrode 28d3, a fifth dummy electrode 28e3, a sixth dummy electrode 28f3, a seventh dummy electrode 28g3, and an eighth dummy electrode 28h3.

[0122] The first dummy electrode 28a3 is common to the first dummy electrode 28a1, the second dummy electrode 28b3 is common to the second dummy electrode 28b1, the third dummy electrode 28c3 is common to the third dummy electrode 28c1, and the fourth dummy electrode 28d3 is common to the eighth dummy electrode 28h1.

[0123] The fifth dummy electrode 28e3 is common to the fifth dummy electrode 28e2, the sixth dummy electrode 28f3 is common to the sixth dummy electrode 28f2, the seventh dummy electrode 28g3 is common to the seventh dummy electrode 28g2, and the eighth dummy electrode 28h3 is common to the eighth dummy electrode 28h2.

[0124] The multilayer ceramic capacitors 10B1 and B2 according to the modified examples 1-B1 and 1-B2 of the first embodiment shown in Figure 16 have the same effects as the multilayer ceramic capacitor 10 described above, as well as the following effects. Specifically, by providing dummy electrodes 28 in the outer layers 20a and 20b, the thickness of the plated electrodes arranged on the outer layer and the plated electrodes arranged in the inner layer region can be made nearly uniform. Furthermore, in the multilayer ceramic capacitor 10B2 according to the modified example 1-B2 of the first embodiment shown in Figure 16, if the dummy electrodes 28 are arranged on at least one of the first surface 12a and the second surface 12b, the manufacturing process does not require an additional step of placing a seed electrode layer 32 on at least one of the first surface 12a and the second surface 12b, thus reducing manufacturing costs. Note that the shape of the dummy electrode 28 arranged as a seed electrode on the surface of the first surface 12a and the dummy electrode 28 arranged inside the laminate 12 may be different.

[0125] 3. Method for Manufacturing a Multilayer Ceramic Capacitor The method for manufacturing a multilayer ceramic capacitor 10 according to the first embodiment will be described below.

[0126] First, prepare the dielectric sheet and the conductive paste for the internal electrodes. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0127] Next, a conductive paste for internal electrodes is printed on the dielectric sheet in a predetermined pattern, for example, by inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode and a dielectric sheet with the pattern for the second internal electrode. Subsequently, the sheet with the pattern for the first internal electrode and the sheet with the pattern for the second internal electrode are laminated together to form the inner layer portion 18.

[0128] When printing patterns using conductive pastes, the first step is to print the pattern using conductive paste for the internal electrodes.

[0129] Furthermore, for example, when forming the printed pattern of the internal electrode by gravure printing, the desired internal electrodes can be formed by changing the design of the gravure plate used for gravure printing to match the graphic pattern of the first internal electrode, and to the corresponding structure for the graphic pattern of the second internal electrode.

[0130] Furthermore, when forming the printed pattern of the internal electrode by screen printing, the desired internal electrode can be formed by designing the screen printing mask to match the graphic pattern of the first internal electrode and modifying the structure to match the graphic pattern of the second internal electrode.

[0131] Next, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked to form the first outer layer portion 20a on the first surface 12a side. Then, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode patterns are stacked on top of this inner layer portion 18 to form the second outer layer portion 20b on the second surface 12b side. This completes the production of the laminated sheet.

[0132] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block.

[0133] Next, the laminated block is cut to the specified size, and the laminated chips are cut out. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0134] Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the ceramic and internal electrode materials, but it is preferably between 900°C and 1400°C.

[0135] Next, an external electrode 30 is formed on the laminate 12. That is, the obtained laminate 12 is aligned on a workbench, and a seed electrode layer 32 is formed on the first surface 12a by sputtering using a predetermined mask.

[0136] Subsequently, an undercoat plating layer 34 is formed on the seed electrode layer 32 and on the surface of the laminate 12, a lower plating layer 36 is formed to cover the undercoat plating layer 34, and a surface plating layer 38 is formed to cover the lower plating layer 36. More specifically, a Cu plating layer is formed on the seed electrode layer 32 as the undercoat plating layer 34. Subsequently, a Ni plating layer is formed on the surface of the undercoat plating layer 34 as the lower plating layer 36. Subsequently, a Sn plating layer is formed on the surface of the lower plating layer 36 as the surface plating layer 38. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0137] As described above, the multilayer ceramic capacitor 10 according to the embodiment shown in Figure 1 can be manufactured. When manufacturing the modified multilayer ceramic capacitor 10A shown in Figure 15, the shape of each part of each corresponding section is appropriately changed in the process of forming the external electrodes. Furthermore, when manufacturing the modified multilayer ceramic capacitors 10B1 and B2 shown in Figure 16, the outer dielectric layer 14b can be formed by printing conductive paste for dummy electrodes onto the ceramic green sheet for forming the outer dielectric layer 14b in the pattern of each dummy electrode.

[0138] B. Second Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 110 according to the second embodiment of this invention will be described.

[0139] Figure 19 is an external perspective view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 20 is a plan view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 21 is a bottom view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 22 is a front view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 23 is a right side view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 24 is a schematic cross-sectional view along line XXIV-XXIV in Figure 20. Figure 25 is a schematic cross-sectional view along line XXV-XXV in Figure 20. Figure 26 is a schematic cross-sectional view along line XXVI-XXVI in Figure 20. Figure 27 is a schematic cross-sectional view along line XXVII-XXVII in Figure 20. Figure 28 is a schematic cross-sectional view along line XXVIII-XXVIII in Figure 22. Figure 29 is an exploded perspective view of the laminate shown in Figure 19. Components identical to or corresponding to those in Figures 1 through 9 are denoted by the same reference numerals, and detailed explanations are omitted.

[0140] The multilayer ceramic capacitor 110 comprises a laminate 112 and a plurality of external electrodes 130.

[0141] (Laminate) The laminate 112 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layer 114 has an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 have a first internal electrode 116a and a second internal electrode 116b.

[0142] The laminate 112 has an inner layer 118, a first outer layer 120a located on the first surface 112a side, and a second outer layer 120b located on the second surface 112b side.

[0143] The first outer layer 120a is located on the first surface 112a side of the laminate 112 and is an aggregate of multiple outer dielectric layers 114b located between the first surface 112a and the internal electrode 116 closest to the first surface 112a.

[0144] The second outer layer 120b is located on the second surface 112b side of the laminate 112 and is an aggregate of multiple outer dielectric layers 114b located between the second surface 112b and the internal electrode 116 closest to the second surface 112b.

[0145] The region sandwiched between the first outer layer 120a and the second outer layer 120b is the inner layer 118.

[0146] The inner layer 118 has a first internal electrode 116a, a second internal electrode 116b, and an inner dielectric layer 114a.

[0147] The materials of the dielectric layer 114 are the same as those of the dielectric layer 14, so their explanation will be omitted.

[0148] (Internal electrodes) The internal electrode 116 has a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are stacked via a dielectric layer 114.

[0149] The first internal electrode 116a is positioned on the surface of the inner dielectric layer 114a. The first internal electrode 116a has a first opposing electrode portion 122a that faces the first surface 112a and the second surface 112b and faces the second internal electrode 116b, and is stacked in the direction connecting the first surface 112a and the second surface 112b.

[0150] As shown in Figure 28, the first internal electrode 116a is drawn out by the first extraction electrode portion 124a to the third surface 112c on the fifth surface 112e side of the laminate 112, drawn out by the second extraction electrode portion 124b to the third surface 112c on the sixth surface 112f side of the laminate 112, drawn out by the third extraction electrode portion 124c to the fourth surface 112d on the sixth surface 112f side of the laminate 112, and drawn out by the fourth extraction electrode portion 124d to the fourth surface 112d on the fifth surface 112e side of the laminate 112.

[0151] The first internal electrode 116a is not exposed to the fifth surface 112e and the sixth surface 112f of the laminate 112.

[0152] The second internal electrode 116b is positioned on a surface of an inner dielectric layer 114a different from the inner dielectric layer 114a on which the first internal electrode 116a is positioned. The second internal electrode 116b has a second opposing electrode portion 122b that faces the first surface 112a and the second surface 112b and faces the first internal electrode 116a, and is stacked in a direction connecting the first surface 112a and the second surface 112b.

[0153] The second internal electrode 116b is the same as the second internal electrode 16b of the multilayer ceramic capacitor 10 according to the first embodiment.

[0154] (External electrodes) External electrodes 130 are arranged on the laminate 112 as shown in Figures 19 to 27. The external electrodes 130 have a plurality of external electrodes 130 connected to the first internal electrode 116a and the second internal electrode 116b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, a fourth external electrode 130d, a fifth external electrode 130e, a sixth external electrode 130f, a seventh external electrode 130g, and an eighth external electrode 130h.

[0155] The first external electrode 130a is positioned on the third surface 112c so as to cover the first lead electrode portion 124a of the first internal electrode 116a, and further positioned so as to cover a part of the first surface 112a. The first external electrode 130a is electrically connected to the first lead electrode portion 124a of the first internal electrode 116a. The second external electrode 130b is positioned on the third surface 112c so as to cover the second lead electrode portion 124b of the first internal electrode 116a, and further positioned so as to cover a part of the first surface 112a. The second external electrode 130b is electrically connected to the second lead electrode portion 124b of the first internal electrode 116a. The third external electrode 130c is positioned on the fourth surface 112d so as to cover the third lead electrode portion 124c of the first internal electrode 116a, and further positioned so as to cover a part of the first surface 112a. The third external electrode 130c is electrically connected to the third lead electrode portion 124c of the first internal electrode 116a. The fourth external electrode 130d is positioned on the fourth surface 112d so as to cover the fourth lead electrode portion 124d of the first internal electrode 116a, and further positioned so as to cover a part of the first surface 112a. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 124d of the first internal electrode 116a.

[0156] The fifth external electrode 130e is positioned on the third surface 112c so as to cover the fifth lead electrode portion 124e of the second internal electrode 116b, and further positioned so as to cover a part of the first surface 112a. The fifth external electrode 130e is electrically connected to the fifth lead electrode portion 124e of the second internal electrode 116b. The sixth external electrode 130f is positioned on the sixth surface 112f so as to cover the sixth lead electrode portion 124f of the second internal electrode 116b, and further positioned so as to cover a part of the first surface 112a. The sixth external electrode 130f is electrically connected to the sixth lead electrode portion 124f of the second internal electrode 116b. The seventh external electrode 130g is positioned on the fourth surface 112d so as to cover the seventh lead electrode portion 124g of the second internal electrode 116b, and further positioned so as to cover a part of the first surface 112a. The seventh external electrode 130g is electrically connected to the seventh lead electrode portion 124g of the second internal electrode 116b. The eighth external electrode 130h is positioned on the fifth surface 112e so as to cover the eighth lead electrode portion 124h of the second internal electrode 116b, and further positioned so as to cover a part of the first surface 112a. The eighth external electrode 130h is electrically connected to the eighth lead electrode portion 124h of the second internal electrode 16b.

[0157] Furthermore, as shown in Figure 19, it is preferable that the first external electrodes 130a to the fourth external electrodes 130d, which are positioned on the fifth surface 112e or the sixth surface 112f from which the first internal electrode 116a is not drawn out, cover in an L-shape the short side of either of the sides from which the first internal electrode 116a is not drawn out and the portion from the end of that short side to the middle of the long side on the first surface 112a side.

[0158] Within the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b face each other via the inner dielectric layer 114a, thereby forming capacitance. As a result, capacitance can be obtained between the first external electrodes 130a to the fourth external electrodes 130d, to which the first internal electrode 116a is connected, and the fifth external electrodes 130e to the eighth external electrodes 130h, to which the second internal electrode 16b is connected, thus exhibiting capacitor characteristics.

[0159] The first external electrode 130a, the second external electrode 130b, the third external electrode 130c, the fourth external electrode 130d, the fifth external electrode 130e, the sixth external electrode 130f, the seventh external electrode 130g, and the eighth external electrode 130h each preferably have a seed electrode layer 132 and a plating layer. The plating layer preferably has an under-plating layer 134, a lower plating layer 136, and a surface plating layer 138.

[0160] The multilayer ceramic capacitor 110 shown in Figure 19 provides the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0161] Furthermore, the multilayer ceramic capacitor 110 according to the second embodiment of this invention may also be combined with all or part of the above-described modified examples 1-A and 1-B1, 1-B2. In addition, the multilayer ceramic capacitor 10 of the first embodiment may be combined with all or part of the modified examples shown in modified examples 1-A and 1-B1, 1-B2.

[0162] 2. Method for Manufacturing Multilayer Ceramic Capacitors The method for manufacturing multilayer ceramic capacitors according to the second embodiment will be described below.

[0163] First, prepare the dielectric sheet and the conductive paste for the internal electrodes. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0164] Next, a conductive paste for internal electrodes is printed on the dielectric sheet in a predetermined pattern, for example, by inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode and a dielectric sheet with the pattern for the second internal electrode. Subsequently, the sheet with the pattern for the first internal electrode and the sheet with the pattern for the second internal electrode are laminated together to form the inner layer portion 118.

[0165] When printing patterns using conductive pastes, the first step is to print the pattern using conductive paste for the internal electrodes.

[0166] Next, a predetermined number of dielectric sheets without printed internal electrode patterns are stacked to form the first outer layer portion 120a on the first surface 112a side. Then, the portion that will become the inner layer portion 118 prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode patterns are stacked on top of this inner layer portion 118 to form the second outer layer portion 120b on the second surface 112b side. This completes the production of the laminated sheet.

[0167] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block.

[0168] Next, the laminated block is cut to the specified size, and the laminated chips are cut out. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0169] Next, the laminated chips are fired to produce the laminated body 112. The firing temperature depends on the ceramic and internal electrode materials, but it is preferably between 900°C and 1400°C.

[0170] Next, an external electrode 130 is formed on the laminate 112. That is, the obtained laminate 112 is aligned on a workbench, and a seed electrode layer 32 is formed on the first surface 112a as a sputtered electrode by sputtering using a predetermined mask.

[0171] Subsequently, an undercoat plating layer 134 is formed on the seed electrode layer 132 and on the surface of the laminate 112, a lower plating layer 136 is formed to cover the undercoat plating layer 134, and a surface plating layer 138 is formed to cover the lower plating layer 136. More specifically, a Cu plating layer is formed on the seed electrode layer 132 as the undercoat plating layer 134. Subsequently, a Ni plating layer is formed on the surface of the undercoat plating layer 134 as the lower plating layer 136. Subsequently, a Sn plating layer is formed on the surface of the lower plating layer 136 as the surface plating layer 138. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0172] As described above, the multilayer ceramic capacitor 110 according to the second embodiment shown in Figure 19 can be manufactured.

[0173] C. Third Embodiment 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor 210 according to the third embodiment of this invention will be described.

[0174] Figure 30 is an external perspective view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 31 is a plan view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 32 is a bottom view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 33 is a front view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 34 is a right side view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Figure 35 is a schematic cross-sectional view along line XXXV-XXXV in Figure 31. Figure 36 is a schematic cross-sectional view along line XXXVI-XXXVI in Figure 31. Figure 37 is a schematic cross-sectional view along line XXXVII-XXXVII in Figure 31. Figure 38 is a schematic cross-sectional view along line XXXVIII-XXXVIII in Figure 31. Components identical or corresponding to those in Figures 1 to 9 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0175] The multilayer ceramic capacitor 210 comprises a laminate 12 and a plurality of external electrodes 230.

[0176] (Laminated structure) In the laminated ceramic capacitor 210 according to the second embodiment, the laminated structure 12 has the same configuration as the laminated structure 12 of the first embodiment of this invention shown in Figure 1.

[0177] (Internal Electrode) The first internal electrode 16a is drawn out to the third surface 12c and the fifth surface 12e of the laminate 12 by the first drawing electrode portion 24a, drawn out to the third surface 12c and the sixth surface 12f of the laminate 12 by the second drawing electrode portion 24b, drawn out to the fourth surface 12d and the sixth surface 12f of the laminate 12 by the third drawing electrode portion 24c, and drawn out to the fourth surface 12d and the fifth surface 12e by the fourth drawing electrode portion 24d.

[0178] The second internal electrode 16b is drawn out to the third surface 12c of the laminate 12 by the fifth drawing electrode portion 24e, drawn out to the sixth surface 12f of the laminate 12 by the sixth drawing electrode portion 24f, drawn out to the fourth surface 12d of the laminate 12 by the seventh drawing electrode portion 24g, and drawn out to the fifth surface 12e of the laminate 12 by the eighth drawing electrode portion 24h.

[0179] (External electrodes) In the multilayer ceramic capacitor 210 according to the third embodiment, the external electrodes 230 are arranged to cover the first surface 12a and the second surface 12b of the laminate 12.

[0180] As shown in Figures 30 to 38, external electrodes 230 are arranged on the laminate 12. The external electrodes 230 have a plurality of external electrodes 230 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrodes 230 include a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, a fourth external electrode 230d, a fifth external electrode 230e, a sixth external electrode 230f, a seventh external electrode 230g, and an eighth external electrode 230h.

[0181] The first external electrode 230a is positioned on the third surface 12c and the fifth surface 12e so as to cover the first lead-out electrode portion 24a of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The first external electrode 230a is electrically connected to the first lead-out electrode portion 24a of the first internal electrode 16a. The second external electrode 230b is positioned on the third surface 12c and the sixth surface 12f so as to cover the second lead-out electrode portion 24b of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The second external electrode 230b is electrically connected to the second lead-out electrode portion 24b of the first internal electrode 16a. The third external electrode 230c is positioned on the fourth surface 12d and the sixth surface 12f so as to cover the third lead electrode portion 24c of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The third external electrode 230c is electrically connected to the third lead electrode portion 24c of the first internal electrode 16a. The fourth external electrode 230d is positioned on the fourth surface 12d and the fifth surface 12e so as to cover the fourth lead electrode portion 24d of the first internal electrode 16a, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The fourth external electrode 230d is electrically connected to the fourth lead electrode portion 24d of the first internal electrode 16a.

[0182] The fifth external electrode 230e is positioned on the third surface 12c so as to cover the fifth lead electrode portion 24e of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The fifth external electrode 230e is electrically connected to the fifth lead electrode portion 24e of the second internal electrode 16b. The sixth external electrode 230f is positioned on the sixth surface 12f so as to cover the sixth lead electrode portion 24f of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The sixth external electrode 230f is electrically connected to the sixth lead electrode portion 24f of the second internal electrode 16b. The seventh external electrode 230g is positioned on the fourth surface 12d so as to cover the seventh lead electrode portion 24g of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a and a part of the second surface 12b. The seventh external electrode 230g is electrically connected to the seventh lead electrode portion 24g of the second internal electrode 16b. The eighth external electrode 230h is positioned on the fifth surface 12e so as to cover the eighth lead electrode portion 24h of the second internal electrode 16b, and further positioned so as to cover a part of the first surface 12a. The eighth external electrode 230h is electrically connected to the eighth lead electrode portion 24h of the second internal electrode 16b.

[0183] The first external electrode 230a, the second external electrode 230b, the third external electrode 230c, the fourth external electrode 230d, the fifth external electrode 230e, the sixth external electrode 230f, the seventh external electrode 230g, and the eighth external electrode 230h each preferably have a seed electrode layer 232 and a plating layer. The plating layer preferably has an under-plating layer 234, a lower plating layer 236, and a surface plating layer 238.

[0184] The surface roughness of the seed electrode layer 232 positioned on the surface of the second surface 12b is preferably rougher than the surface roughness of the seed electrode layer 232 positioned on the first surface 12a. This improves the mountability when soldering the multilayer ceramic capacitor 210 to a mounting substrate by making the second surface 12b side the mounting side.

[0185] The multilayer ceramic capacitor 210 according to the third embodiment shown in Figure 30 provides the same effects as the multilayer ceramic capacitor 10 described above.

[0186] Furthermore, the multilayer ceramic capacitor 210 according to the third embodiment of this invention may also be combined with all or part of the above-described modified examples 1-A and 1-B1, 1-B2. In addition, it may be combined with all or part of the modified examples shown in modified examples 1-A and 1-B1, 1-B2 of the multilayer ceramic capacitor 10 of the first embodiment.

[0187] D. Experimental Example 1. Experimental Example 1 Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, the alignment performance during mounting on a mounting substrate was evaluated.

[0188] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample in Experimental Example 1 Multilayer ceramic capacitors, which are the samples for Examples 1 to 5, were fabricated using the manufacturing method according to the above embodiment. ・Structure of the multilayer ceramic capacitor: Multilayer ceramic capacitor shown in Figure 1 ・Dimensions of the multilayer ceramic capacitor (L): 600 μm ± 10 μm ・Dimensions of the multilayer ceramic capacitor (W): 600 μm ± 10 μm ・Dimensions of the multilayer ceramic capacitor (T): 90 μm ± 10 μm ・Ceramic material: BaTiO3 ・Material of internal electrodes: Ni - External electrode structure - Structure of the external electrode on the first surface: A seed electrode layer made of Ni, Cr, and Cu is formed, and Cu plating, Ni plating, and Sn plating are applied to the seed electrode. - When the maximum value of the dimension in the second direction z of the first external electrode is eL1, the maximum value of the dimension in the second direction z of the fifth external electrode is eL2, and the maximum value of the dimension in the second direction z of the second external electrode is eL3, and L1 is the maximum distance in the second direction z between the end of the first external electrode on the fifth surface side and the end of the second external electrode on the sixth surface side (i.e., the dimension in the second direction z of the multilayer ceramic capacitor on the third surface side), the settings are as shown in Table 1. - When the maximum value of the dimension in the second direction z of the fourth external electrode is eL4, the maximum value of the dimension in the second direction z of the seventh external electrode 30g is eL5, and the maximum value of the dimension in the second direction z of the third external electrode is eL6, and the maximum distance in the second direction z between the end of the fifth face side of the fourth external electrode and the end of the sixth face side of the third external electrode (i.e., the dimension in the second direction z of the multilayer ceramic capacitor on the fourth face side) is L2, the settings are as shown in Table 1.

[0189] (2) Evaluation Method The value of (eL1 + eL2 + eL3) / L1 was calculated for each sample of multilayer ceramic capacitors of Examples 1 to 4 and Comparative Examples 1 and 2 having the above configuration, and the value of (eL4 + eL5 + eL6) / L2 was calculated for Examples 1 to 4 and Comparative Examples 1 and 2. A mounting experiment was performed on each sample, and when mounted on a mounting board with solder, any multilayer ceramic capacitor that rotated by more than 5° was counted as defective. The number of each sample was 100.

[0190] (3) Results The evaluation results from the implementation experiment are shown in Table 1. Table 1 shows the evaluation results of the alignment when the multilayer ceramic capacitors of each sample are mounted on the implementation substrate, in relation to the change in the value of (eL1 + eL2 + eL3) / L1 and the change in the value of (eL4 + eL5 + eL6) / L2 for each sample.

[0191]

[0192] According to Table 1, in Comparative Example 1, when (eL1 + eL2 + eL3) / L1 was 0.22, the sample multilayer ceramic capacitor rotated 5.6°, which is greater than 5°. In Comparative Example 2, when (eL1 + eL2 + eL3) / L2 was 0.85, the sample multilayer ceramic capacitor rotated 5.1°, which is greater than 5°.

[0193] On the other hand, in Examples 1 to 4, (eL1 + eL2 + eL3) / L1 was in the range of 0.23 to 0.84, so the multilayer ceramic capacitors of all samples had a rotation angle of 5° or less, and relatively good results were obtained. In particular, better results were obtained when (eL1 + eL2 + eL3) / L2 was in the range of 0.48 to 0.72.

[0194] 2. Experimental Example 2 Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors, which are the comparative examples and samples of Examples 6 to 9, were fabricated. • Structure of the multilayer ceramic capacitor: Multilayer ceramic capacitor shown in Figure 1 • Dimensions of the multilayer ceramic capacitor (L): 600 μm ± 10 μm • Dimensions of the multilayer ceramic capacitor (W): 600 μm ± 10 μm • Dimensions of the multilayer ceramic capacitor (T): 90 μm ± 10 μm • Ceramic material: BaTiO3 • Material of internal electrodes: Ni - External electrode structure - Structure of the external electrode on the first surface: A seed electrode layer made of Ni, Cr, and Cu is formed, and Cu plating, Ni plating, and Sn plating are applied to the seed electrode. - When viewed from the direction from the first surface 12a toward the second surface 12b (view in the stacking direction x), the surface area of ​​the first external electrode located on the first surface side of the stack is A1, the surface area of ​​the second external electrode is A2, the surface area of ​​the third external electrode is A3, the surface area of ​​the fourth external electrode is A4, the surface area of ​​the fifth external electrode is A5, the surface area of ​​the sixth external electrode is A6, the surface area of ​​the seventh external electrode is A7, and the surface area of ​​the eighth external electrode is A8, the surface area of ​​each is varied as shown in Table 2.

[0195] (2) Evaluation Method For each sample of the multilayer ceramic capacitors of Examples 5 to 9 and Comparative Example 3 having the above configuration, when viewed from the first surface 12a toward the second surface 12b (view in the stacking direction x), the surface area of ​​the first external electrode located on the first surface side of the stack is A1, the surface area of ​​the second external electrode is A2, the surface area of ​​the third external electrode is A3, the surface area of ​​the fourth external electrode is A4, the surface area of ​​the fifth external electrode is A5, the surface area of ​​the sixth external electrode is A6, the surface area of ​​the seventh external electrode is A7, and the surface area of ​​the eighth external electrode is A8, the respective surface areas were changed as shown in Table 2. For each sample, the smallest surface area among surface areas A1, A2, A3, and A4 was denoted as min[A1, A2, A3, A4], and the largest surface area among surface areas A1, A2, A3, and A4 was denoted as max[A1, A2, A3, A4]. Then, min[A1, A2, A3, A4] / max[A1, A2, A3, A4] was calculated. Furthermore, for each sample, the smallest surface area among surface areas A5, A6, A7, and A8 was denoted as min[A5, A6, A7, A8], and the largest surface area among surface areas A5, A6, A7, and A8 was denoted as max[A5, A6, A7, A8]. Then, min[A5, A6, A7, A8] / max[A5, A6, A7, A8] was calculated. Mounting experiments were then conducted on each sample, and when mounted on a mounting board using solder, any multilayer ceramic capacitor that rotated more than 5° was counted as defective. The number of each sample was set to 100.

[0196] (3) Results The evaluation results from the implementation experiment are shown in Table 2. Table 2 shows the evaluation results of the alignment when the multilayer ceramic capacitor 10 of each sample is mounted on the mounting substrate, in response to the changes in min[A1,A2,A3,A4] / max[A1,A2,A3,A4] and min[A5,A6,A7,A8] / max[A5,A6,A7,A8] of the multilayer ceramic capacitor of each sample.

[0197]

[0198] According to Table 2, in Comparative Example 3, min[A1,A2,A3,A4] / max[A1,A2,A3,A4] was 0.32 and min[A5,A6,A7,A8] / max[A5,A6,A7,A8] was 0.37, so the multilayer ceramic capacitor sample rotated by 5.1°, which is greater than 5°.

[0199] On the other hand, in Examples 5 to 9, min[A1,A2,A3,A4] / max[A1,A2,A3,A4] was 0.33 or higher, and min[A5,A6,A7,A8] / max[A5,A6,A7,A8] was 0.38 or higher. Therefore, the multilayer ceramic capacitors in all samples had a rotation angle of 5° or less, and relatively good results were obtained.

[0200] 3. Experimental Example 3 Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors, which are the samples for the comparative example and Examples 6 to 9, were fabricated. • Structure of the multilayer ceramic capacitor: Multilayer ceramic capacitor shown in Figure 1 • Dimensions of the multilayer ceramic capacitor (L): 600 μm ± 10 μm • Dimensions of the multilayer ceramic capacitor (W): 600 μm ± 10 μm • Dimensions of the multilayer ceramic capacitor (T): 90 μm ± 10 μm • Ceramic material: BaTiO3 • Material of internal electrodes: Ni - External electrode structure - Structure of the external electrode on the first surface: A seed electrode layer made of Ni, Cr, and Cu is formed, and Cu plating, Ni plating, and Sn plating are applied to the seed electrode. - When viewed from the direction from the first surface 12a to the second surface 12b (view in the stacking direction x), the surface area of ​​the first external electrode located on the first surface side of the stack is A1, the surface area of ​​the second external electrode is A2, the surface area of ​​the third external electrode is A3, the surface area of ​​the fourth external electrode is A4, the surface area of ​​the fifth external electrode is A5, the surface area of ​​the sixth external electrode is A6, the surface area of ​​the seventh external electrode is A7, and the surface area of ​​the eighth external electrode is A8, the surface area of ​​each is varied as shown in Table 3.

[0201] (2) Method for testing adhesion strength For each sample of the multilayer ceramic capacitors of Examples 10 to 15 and Comparative Example 4 having the above configuration, when viewed from the first surface 12a toward the second surface 12b (view in the stacking direction x), the surface area of ​​the first external electrode located on the first surface side of the stack is denoted as A1, the surface area of ​​the second external electrode as A2, the surface area of ​​the third external electrode as A3, the surface area of ​​the fourth external electrode as A4, the surface area of ​​the fifth external electrode as A5, the surface area of ​​the sixth external electrode as A6, the surface area of ​​the seventh external electrode as A7, and the surface area of ​​the eighth external electrode as A8, the surface areas of each were changed as shown in Table 3. For each sample, the sum of surface areas A1, A2, A3, and A4 was calculated as SS1, and the sum of surface areas A5, A6, A7, and A8 was calculated as SS2. Then, for each sample, a pressing jig was placed at a height of 0.030 mm from the surface of the first face of the multilayer ceramic capacitor to the second face side, and the adhesion strength was evaluated by a lateral pressing test in the first direction y of the multilayer ceramic capacitor.

[0202] (3) Results The evaluation results from the adhesion strengthening test are shown in Table 3. For each sample of multilayer ceramic capacitor, the SS1 / SS2 values ​​were calculated, and the evaluation results of the adhesion strength test performed on each sample of multilayer ceramic capacitor 10 to the mounting substrate are shown in relation to the change in these values.

[0203]

[0204] According to Table 2, in Comparative Example 3, the SS1 / SS2 value was greater than 1.24, resulting in a relatively high defect rate of 14% in the adhesion strength test.

[0205] On the other hand, in Examples 10 to 15, the SS1 / SS2 value was between 0.66 and 1.24, and as a result of the adhesion strength test, a good result was obtained with a defect rate of 5% or less.

[0206] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto.

[0207] Without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these modifications are included in the present invention.

[0208] 10, 10A, 10B1, 10B2, 110, 210 Multilayer ceramic capacitor 12, 112 Laminate 12a, 112a First surface 12b, 112b Second surface 12c, 112c Third surface 12d, 112d Fourth surface 12e, 112e Fifth surface 12f, 112f Sixth surface 14, 114 Dielectric layer 14a, 114a Inner dielectric layer 14b, 114b Outer dielectric layer 16, 116 Internal electrode 16a, 116a First internal electrode 16b, 116b Second internal electrode 18, 118 Inner layer 20a, 120a First outer layer 20b, 120b Second outer layer 22a, 122a First opposing electrode 22b, 122b Second opposing electrode section 24a, 124a First extraction electrode section 24b, 124b Second extraction electrode section 24c, 124c Third extraction electrode section 24d, 124d Fourth extraction electrode section 24e, 124e Fifth extraction electrode section 24f, 124f Sixth extraction electrode section 24g, 124g Seventh extraction electrode section 24h, 124h Eighth extraction electrode section 26a1, 26b1, 26b1, 26b2 Side section of the laminate (W gap) 27a1, 27a2, 27b1, 27b2 End section of the laminate (L gap) 28, 281, 282, 283 Dummy electrode 30, 130, 210 External electrode 30a, 130a, 230a First external electrode 30b, 130b, 230b Second external electrode 30c, 130c, 230c Third external electrode 30d, 130d, 230d Fourth external electrode 30e, 130e, 230e Fifth external electrode 30f, 130f, 230f Sixth external electrode 30g, 130g, 230g Seventh external electrode 30h, 130h, 230h Eighth external electrode 32, 132, 232 Seed electrode layer 32a, 132a, 232a First seed electrode layer 32b, 132b, 232b Second seed electrode layer 32c, 132c, 232c Third seed electrode layer 32d, 132d, 232d Fourth seed electrode layer: 32e, 132e, 232e Fifth seed electrode layer: 32f, 132f, 232f Sixth seed electrode layer: 32g, 132g, 232g Seventh seed electrode layer: 32h, 132h, 232h Eighth seed electrode layer34, 134, 234 Under-plating layers 34a, 134a, 234a First under-plating layer 34b, 134b, 234b Second under-plating layer 34c, 134c, 234c Third under-plating layer 34d, 134d, 234d Fourth under-plating layer 34e, 134e, 234e Fifth under-plating layer 34f, 134f, 234f Sixth under-plating layer 34g, 134g, 234g Seventh under-plating layer 34h, 134h, 234h Eighth under-plating layer 36, 136, 236 Under-plating layers 36a, 136a, 236a First under-plating layer 36b, 136b, 236b Second under-plating layer 36c, 136c, 236c Third lower plating layer: 36d, 136d, 236d Fourth lower plating layer: 36e, 136e, 236e Fifth lower plating layer: 36f, 136f, 236f Sixth lower plating layer: 36g, 136g, 236g Seventh lower plating layer: 36h, 134h, 236h Eighth lower plating layer: 38, 138, 238 Surface plating layer: 38a, 138a, 238a First surface plating layer: 38b, 138b, 238b Second surface plating layer: 38c, 138c, 238c Third surface plating layer: 38d, 138d, 238d Fourth surface plating layer: 38e, 138e, 238e Fifth surface plating layer: 38f, 138f, 238f Sixth surface plating layer: 38g, 138g, 238g Seventh surface plating layer: 38h, 138h, 238h Eighth surface plating layer x: Lamination direction y: First direction z: Second direction W: Dimension of the multilayer ceramic capacitor in the first direction L: Dimension of the multilayer ceramic capacitor in the second direction T: Dimension of the multilayer ceramic capacitor in the lamination direction

Claims

1. A laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the third surface; a third external electrode disposed on the first surface and the fourth surface; a fourth external electrode disposed on the first surface and the fourth surface; a fifth external electrode disposed on the first surface and the third surface between the first external electrode and the second external electrode; a sixth external electrode disposed on the first surface and the sixth surface; and a seventh external electrode disposed on the first surface and the fourth surface between the third external electrode and the fourth external electrode. A multilayer ceramic capacitor comprising: an eighth external electrode disposed on the first surface and the fifth surface, wherein the laminate has a first internal electrode exposed on the third surface and the fourth surface and connected to the first to the fourth external electrode; and a second internal electrode exposed on the third surface, the fourth surface, the fifth surface and the sixth surface and connected to the fifth to the eighth external electrode, wherein when the dimension in the first direction is L and the dimension in the second direction is W, 0.85 ≤ L / W ≤ 1.

00.

2. A multilayer ceramic capacitor according to claim 1, comprising: a first external electrode disposed on the first surface, the third surface and the fifth surface; a second external electrode disposed on the first surface, the third surface and the sixth surface; a third external electrode disposed on the first surface, the fourth surface and the sixth surface; a fourth external electrode disposed on the first surface, the fourth surface and the fifth surface; a fifth external electrode disposed on the first surface and the third surface between the first external electrode and the second external electrode; a sixth external electrode disposed on the first surface and the sixth surface; a seventh external electrode disposed on the first surface and the fourth surface between the third external electrode and the fourth external electrode; and an eighth external electrode disposed on the first surface and the fifth surface.

3. The multilayer ceramic capacitor according to claim 2, wherein when eL4 is the dimension of the fourth external electrode in the second direction, eL5 is the dimension of the seventh external electrode in the second direction, eL6 is the dimension of the third external electrode in the second direction, and L is the maximum distance in the second direction between the end of the fourth external electrode on the fifth face side and the end of the third external electrode on the sixth face side, 0.22 ≤ (eL4 + eL5 + eL6) / L ≤ 0.

85.

4. In a view from the first surface toward the second surface of the laminate, when the surface area of ​​the first external electrode located on the first surface side of the laminate is A1, the surface area of ​​the second external electrode is A2, the surface area of ​​the third external electrode is A3, the surface area of ​​the fourth external electrode is A4, the surface area of ​​the fifth external electrode is A5, the surface area of ​​the sixth external electrode is A6, the surface area of ​​the seventh external electrode is A7, and the surface area of ​​the eighth external electrode is A8, the sum of the surface areas A1, A2, A3, and A4 is SS1, and the sum of the surface areas A5, A6, A7, and A8 is SS2, the multilayer ceramic capacitor according to claim 2 or 3, wherein 0.66 ≤ SS1 / SS2 ≤ 1.

24.

5. When the smallest area among surface areas A1, A2, A3, and A4 is denoted as min[A1, A2, A3, A4], the largest area among surface areas A1, A2, A3, and A4 is denoted as max[A1, A2, A3, A4], the smallest area among surface areas A5, A6, A7, and A8 is denoted as min[A5, A6, A7, A8], and the largest area among surface areas A5, A6, A7, and A8 is denoted as max[A5, A6, A7, A8], A multilayer ceramic capacitor according to any one of claims 2 to 4, wherein min[A1,A2,A3,A4] / max[A1,A2,A3,A4] ≥ 0.33 and min[A5,A6,A7,A8] / max[A5,A6,A7,A8] ≥ 0.

38.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the first internal electrode comprises: a first lead electrode portion exposed on the third and fifth surfaces; a second lead electrode portion exposed on the third and sixth surfaces; a third lead electrode portion exposed on the fourth and sixth surfaces; and a fourth lead electrode portion exposed on the fourth and fifth surfaces.

7. The laminate has an inner layer in which the first internal electrode and the second internal electrode are laminated, and an outer layer arranged to sandwich the inner layer in the lamination direction, wherein the outer layer includes dummy electrodes exposed on the third to sixth surfaces, according to any one of claims 1 to 6.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein the first external electrode comprises a first seed electrode layer disposed on the first surface and a first plating layer disposed on the first seed electrode layer, and the first seed electrode layer is a sputtered electrode.

9. The laminate comprises an inner layer on which the first internal electrode and the second internal electrode are laminated, and an outer layer positioned to sandwich the inner layer in the lamination direction, wherein the outer layer includes a dummy electrode exposed on the third to sixth surfaces, and the first outer electrode comprises a first seed electrode layer positioned on the first surface, and a first plating layer positioned on the first seed electrode layer, wherein the main component contained in the first seed electrode layer and the dummy electrode is the same main component, as described in any one of claims 1 to 6.

10. The multilayer ceramic capacitor according to claim 9, wherein the first external electrode comprises a second seed electrode layer disposed on the second surface, the main component of the second seed electrode layer is the same as that of the first seed electrode layer, and the surface roughness of the second seed electrode layer is rougher than that of the first seed electrode layer.

11. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein the first external electrode comprises a first seed electrode layer disposed on the first surface and a first plating layer disposed on the first seed electrode layer, and the first seed electrode layer mainly consists of Ni and includes a dielectric component.

12. The multilayer ceramic capacitor according to any one of claims 1 to 11, wherein the first external electrode to the eighth external electrode is arranged on the second surface.

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