Display device and electronic device comprising same

Abstract

A display device according to an embodiment of the present invention comprises a complementary metal oxide semiconductor (CMOS) wafer and a light emitting structure layer disposed on the CMOS wafer. The light emitting structure layer includes: multiple first light emitting diodes which are arranged on the CMOS wafer and emit light of a first wavelength; multiple second light emitting diodes which are arranged on the CMOS wafer and emit light of a second wavelength different from the first wavelength; and multiple third light emitting diodes which are arranged on the CMOS wafer and emit light of a third wavelength different from the first wavelength and the second wavelength. Each of the multiple first light emitting diodes includes a first light emitting structure and a first insulating film covering a side surface of the first light emitting structure, each of the multiple second light emitting diodes includes a second light emitting structure and a second insulating film covering a side surface of the second light emitting structure, and each of the multiple third light emitting diodes includes a third light emitting structure and a third insulating film covering a side surface of the third light emitting structure. At least one of the first insulating layer, the second insulating layer, and the third insulating layer includes a material different from that of the other insulating layers.

Description

Display device and electronic device including the same

[0001] The present invention relates to a display device and an electronic device including the same, and more specifically, to a display device including a CMOS wafer and a light-emitting diode and an electronic device including the same.

[0002] Electronic devices such as smartphones, laptop computers, navigation systems, and smart televisions that provide images to users include a display device for displaying images. Augmented reality devices, virtual reality devices, and video projection devices may include a micro-display device. The micro-display device may include a CMOS wafer and a light-emitting diode placed on the CMOS wafer to display high-brightness images while operating at low power.

[0003] The objective of the present invention is to provide a display device with improved display efficiency and an electronic device including the same.

[0004] A display device according to one embodiment of the present invention includes a CMOS (complementary metal oxide semiconductor) wafer and a light-emitting structure layer disposed on the CMOS wafer. The light-emitting structure layer includes a plurality of first light-emitting diodes disposed on the CMOS wafer and emitting light of a first wavelength, a plurality of second light-emitting diodes disposed on the CMOS wafer and emitting light of a second wavelength different from the first wavelength, and a plurality of third light-emitting diodes disposed on the CMOS wafer and emitting light of a third wavelength different from the first wavelength and the second wavelength. Each of the plurality of first light-emitting diodes comprises a first light-emitting structure and a first insulating film covering the side of the first light-emitting structure, each of the plurality of second light-emitting diodes comprises a second light-emitting structure and a second insulating film covering the side of the second light-emitting structure, and each of the plurality of third light-emitting diodes comprises a third light-emitting structure and a third insulating film covering the side of the third light-emitting structure. At least one of the first insulating film, the second insulating film, and the third insulating film comprises a material different from the remaining insulating film.

[0005] The first insulating film comprises a material different from the second insulating film, and the second insulating film and the third insulating film may comprise the same material.

[0006] Each of the first insulating film, the second insulating film, and the third insulating film may contain different materials.

[0007] The first insulating film may be in contact with the side of the first light-emitting structure, the second insulating film may be in contact with the side of the second light-emitting structure, and the third insulating film may be in contact with the side of the third light-emitting structure.

[0008] Each of the plurality of first light-emitting diodes may further include a first additional insulating layer spaced apart from the first light-emitting structure with the first insulating layer in between, each of the plurality of second light-emitting diodes may further include a second additional insulating layer spaced apart from the second light-emitting structure with the second insulating layer in between, and each of the plurality of third light-emitting diodes may further include a third additional insulating layer spaced apart from the third light-emitting structure with the third insulating layer in between.

[0009] At least some of each of the plurality of first light-emitting diodes can be non-overlapping in a plane with the plurality of second light-emitting diodes and the plurality of third light-emitting diodes.

[0010] The first insulating material included in the first insulating film may include a high dielectric constant (High-K) material compared to the second insulating material included in the second insulating film.

[0011] The first insulating material may include at least one of hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, hafnium nitrate, zirconium nitrate, tantalum nitrate, hafnium nitrate, lanthanum nitrate, and zirconium nitrate.

[0012] The second insulating material may include at least one of silicon oxide and aluminum oxide.

[0013] The first wavelength may be shorter than the second wavelength and the third wavelength.

[0014] Each of the plurality of first light-emitting diodes further includes a first lower conductive pattern disposed below the first light-emitting structure and a first upper conductive pattern disposed above the first light-emitting structure, each of the plurality of second light-emitting diodes further includes a second lower conductive pattern disposed below the second light-emitting structure and a second upper conductive pattern disposed above the second light-emitting structure, and each of the plurality of third light-emitting diodes may further include a third lower conductive pattern disposed below the third light-emitting structure and a third upper conductive pattern disposed above the third light-emitting structure.

[0015] A display device according to one embodiment of the present invention may further include a plurality of lenses disposed on the light-emitting structure layer and overlapping at least some of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes.

[0016] The CMOS wafer may include a first region in which each of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes is disposed, and a second region provided on the outside of the first region on a plane.

[0017] The light-emitting structure layer may further include a common electrode connected to at least some of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes.

[0018] The light-emitting structure layer may further include a flattening layer disposed between at least some of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes.

[0019] An electronic device according to one embodiment of the present invention includes a display module and a processor comprising at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller. The display module includes a CMOS (complementary metal oxide semiconductor) wafer and a light-emitting structure layer disposed on the CMOS wafer. The light-emitting structure layer comprises a first layer disposed on the CMOS wafer and comprising a plurality of first light-emitting diodes emitting light of a first wavelength, and a second layer disposed on the first layer and comprising a plurality of second light-emitting diodes emitting light of a second wavelength different from the first wavelength. Each of the plurality of first light-emitting diodes comprises a first light-emitting structure and a first insulating film covering the side of the first light-emitting structure. Each of the plurality of second light-emitting diodes comprises a second light-emitting structure and a second insulating film covering the side of the second light-emitting structure. The first insulating film and the second insulating film comprise different materials.

[0020] The first insulating film may be in contact with the side of the first light-emitting structure, and the second insulating film may be in contact with the side of the second light-emitting structure.

[0021] The first layer may further include a first flattening layer disposed between each of the plurality of first light-emitting diodes, and the second layer may further include a second flattening layer disposed between each of the plurality of second light-emitting diodes.

[0022] The first insulating material included in the first insulating film may include a high dielectric constant (High-K) material compared to the second insulating material included in the second insulating film.

[0023] The first insulating material comprises at least one of hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, hafnium nitrate, zirconium nitrate, tantalum nitrate, hafnium nitrate, lanthanum nitrate, and zirconium nitrate, and the second insulating material may comprise at least one of silicon oxide and aluminum oxide.

[0024] A display device according to one embodiment has a light-emitting diode stacked structure provided in multiple layers, having high resolution, while some of the multiple light-emitting diodes include different insulating films. In the display device according to one embodiment, the external quantum efficiency of the light-emitting diodes can be improved by providing insulating films of different materials suitable for the emission wavelengths of each of the light-emitting diodes emitting light of different wavelengths. Accordingly, the display efficiency of the display device can be improved.

[0025] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

[0026] FIG. 2 is a cross-sectional view of a display device according to one embodiment of the present invention.

[0027] FIGS. 3a and FIGS. 3b are plan views of a display device according to one embodiment of the present invention.

[0028] FIG. 4 is a detailed perspective view of a single light-emitting diode included in a display device according to one embodiment.

[0029] FIG. 5 is an enlarged plan view of a part of a display device according to one embodiment of the present invention.

[0030] FIG. 6 is an enlarged cross-sectional view of a part of a display device according to one embodiment of the present invention.

[0031] FIGS. 7a to 7c are each plan views of a part of a display device according to an embodiment of the present invention.

[0032] FIGS. 8a to 8c are each enlarged cross-sectional views of a part of a display device according to one embodiment of the present invention.

[0033] FIG. 9 is an enlarged plan view of a part of a display device according to one embodiment of the present invention.

[0034] FIG. 10 is an enlarged cross-sectional view of a part of a display device according to one embodiment of the present invention.

[0035] FIGS. 11a to 11c are each plan views of a part of a display device according to an embodiment of the present invention.

[0036] FIG. 12 is a block diagram of an electronic device according to one embodiment.

[0037] FIG. 13 is a schematic diagram of an embodiment of various electronic devices.

[0038] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0039] Meanwhile, in the present application, "direct placement" may mean that there are no additional layers, films, regions, plates, etc. added between a part such as a layer, film, region, or plate and another part. For example, "direct placement" may mean that two layers or two members are placed without using additional members such as adhesive members between them.

[0040] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0041] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0042] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0043] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0045] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0046] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

[0047] Referring to FIG. 1, a display device (DD) according to an embodiment of the present invention may have a rectangular shape having long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2) that intersects the first direction (DR1). However, the display device (DD) is not limited thereto and may have various shapes such as a circle or a polygon. Hereinafter, a direction that intersects substantially perpendicularly with the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In this specification, the meaning of "when viewed in a plane" is defined as the state viewed from the third direction (DR3).

[0048] The upper surface of the display device (DD) can be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images generated by the display device (DD) can be provided to the user through the display surface (DS).

[0049] The display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) displays an image, and the non-display area (NDA) does not display an image. The non-display area (NDA) may surround the display area (DA), but is not limited thereto, and the non-display area (NDA) may be placed on one side of the display area (DA).

[0050] Multiple pixels (PX) may be arranged in a display area (DA). The pixels (PX) may be arranged in a matrix form. Each of the pixels (PX) may include a pixel circuit and a light-emitting diode. All pixels (PX) may generate light of the same color. In one embodiment of the present invention, the pixels (PX) may include multiple groups that generate light of different colors.

[0051] FIG. 2 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 2 exemplarily illustrates a cross-section of the display device (DD) shown in FIG. 1.

[0052] Referring to FIG. 2, the display device (DD) may include a circuit element layer (10), a light-emitting structure layer (20), and a lens layer (30). However, it is not limited thereto, and in one embodiment of the present invention, the lens layer (30) may be omitted and another functional layer may be added.

[0053] The circuit element layer (10) may include a pixel circuit. The pixel circuit can control the operation of the light-emitting diode of the light-emitting structure layer (20) described later. The pixel circuit may include at least one transistor. The circuit element layer (10) may include a CMOS (complementary metal oxide semiconductor) wafer. The CMOS wafer may include a complementarily connected nMOSFET (NMOS) and pMOSFET (PMOS). A plurality of pixel regions are regularly arranged on the CMOS wafer, and a pixel circuit is disposed in each pixel region.

[0054] The light-emitting structure layer (20) may include a plurality of light-emitting diodes electrically connected to a pixel circuit. The light-emitting diode is a type of compound semiconductor and is an electrically driven light-emitting diode that includes gallium (Ga), phosphorus (P), and arsenic (As) as main semiconductor materials. When a forward current is applied to the pn junction structure, electrons and holes combine at the junction surface to generate light of a specific wavelength corresponding to the band gap energy.

[0055] The lens layer (30) is disposed on the light-emitting structure layer (20) and may include a plurality of lenses. The lenses may be disposed to overlap at least the light-emitting diode. The lenses concentrate light emitted from the light-emitting diode. The light concentrated through the lenses may be transmitted through a light guide unit.

[0056] FIGS. 3a and FIGS. 3b are plan views of a display device according to an embodiment of the present invention. FIGS. 3a is a plan view in which a common electrode (CME) according to an embodiment of the present invention is placed in a display area (DA) and a non-display area (NDA) of a display device (DD). The display area (DA) and the non-display area (NDA) of the display device (DD) can be applied in the same way to the circuit element layer (10) described in FIG. 2, i.e., a CMOS wafer. Hereinafter, the circuit element layer (10) is described as a CMOS wafer (10) and references are given to the same reference numerals.

[0057] The common electrode (CME) can cover at least the display area (DA). The common electrode (CME) transmits a power supply voltage applied from the outside to the entire display area (DA). Hereinafter, the display area (DA) is described as the first area (DA) and refers to the same reference numerals.

[0058] A display device (DD) of one embodiment may include a plurality of common electrodes (CME) disposed on different layers. The display device (DD) may include a first common electrode (CME1, see FIG. 6) and a second common electrode (CME2, see FIG. 6) disposed on different layers, which will be described later, and the first common electrode (CME1, see FIG. 6) and the second common electrode (CME2, see FIG. 6) may be electrically connected to each other. A detailed description thereof will be provided later.

[0059] The non-display area (NDA) may be divided into multiple areas. In this embodiment, the non-display area (NDA) may include a second area (NDA1) and a third area (NDA2).

[0060] The second region (NDA1) is positioned outside the first region (DA) and may be a region in which dummy light-emitting diodes are positioned. In this embodiment, the second region (NDA1) may surround the first region (DA), but is not necessarily limited thereto. The dummy light-emitting diodes have the same stacked structure as the light-emitting diodes of the first region (DA), but are not electrically connected to the common electrode (CME) so they cannot be driven (or light-emitting).

[0061] When forming light-emitting diodes in a specific area using the same process, the outer area may have different process conditions compared to the inner area. For example, the thickness of the deposited metal layer may be smaller, or the etching rate may differ. Consequently, defective light-emitting diodes may be formed in the outer area; taking this into consideration, the light-emitting diodes formed in the outer area are not used as effective light-emitting diodes but are used as dummy light-emitting diodes. Since dummy light-emitting diodes can be omitted if the process conditions and process efficiency are consistent regardless of the areas, the second area (NDA1) may be omitted in one embodiment of the present invention.

[0062] Meanwhile, a dummy light-emitting diode may not be placed in some parts of the second region (NDA1). A common electrode (CME) may be placed in some parts of the second region (NDA1), but a light-emitting diode or a dummy light-emitting diode may not be placed. For example, a dummy light-emitting diode may be placed in the area of ​​the second region (NDA1) adjacent to the first region (DA), and a dummy light-emitting diode may not be placed in the area of ​​the second region (NDA1) adjacent to the third region (NDA2).

[0063] The third region (NDA2) may be an area where a common electrode (CME) is not placed. In this embodiment, the third region (NDA2) may surround the entire border of the second region (NDA1), but is not necessarily limited thereto. Multiple driving circuits may be placed in the third region (NDA2) of the CMOS wafer (10, see FIG. 2). For example, a scan driver may be placed in the left and right regions of the third region (NDA2), respectively, with the first region (DA) in between. A data driver may be placed in a part of the third region (NDA2) located below the first region (DA). In addition, an analog circuit, such as a power circuit, may be placed in a part of the third region (NDA2). The above-described scan driver, data driver, and analog circuit may be embedded in the CMOS wafer. That is, the scan driver, data driver, and analog circuit may include transistors formed in the same manner as the pixel circuit.

[0064] A pad area (PDA) having a plurality of pad electrodes (PD) may be disposed on one side of the third area (NDA2). The pad area (PDA) may correspond to a part of the third area (NDA2). A circuit board may be connected to the pad area (PDA). Although only four pad electrodes (PD) receiving power voltage applied to the common electrode (CME) are shown in FIG. 3a, more pad electrodes may be disposed in the pad area (PDA). The unillustrated pad electrodes may receive data image signals or control signals from the outside and provide them to a data driver.

[0065] Referring to FIG. 3a, a voltage transfer electrode (VTE) may be disposed in the third region (NDA2). Four voltage transfer electrodes (VTE) corresponding to four pad electrodes (PD) are illustrated. The voltage transfer electrode (VTE) may extend from the common electrode (CME) toward the pad region (PDA). The voltage transfer electrode (VTE) may be formed through the same process as the common electrode (CME), have the same stacked structure, and have a single shape. The voltage transfer electrode (VTE) and the common electrode (CME) may be different parts of a single electrode formed through the same process.

[0066] FIG. 3b is a plan view illustrating the arrangement relationship of a common electrode (CME), a voltage transfer electrode (VTE), and an electrode pattern (EP) according to one embodiment of the present invention.

[0067] The electrode pattern (EP) overlaps the common electrode (CME) and the voltage transfer electrode (VTE), respectively. In the third direction (DR3), the electrode pattern (EP) is positioned below the common electrode (CME) and the voltage transfer electrode (VTE).

[0068] The electrode pattern (EP) may include a plurality of first lines (EP-a) extended in a first direction (DR1) and a plurality of second lines (EP-b) extended in a second direction (DR2). The first lines (EP-a) are arranged in the second direction (DR2), and the second lines (EP-b) are arranged in the first direction (DR1).

[0069] A unit area (UA) may be located within the area defined by the two closest first lines (EP-a) among the first lines (EP-a) and the two closest second lines (EP-b) among the second lines (EP-b). However, the unit area (UA) is placed within the display area (DA) of FIG. 3a. A representative unit area (UA) is illustrated in FIG. 3b. A plurality of light-emitting diodes are placed in the unit area (UA).

[0070] A portion of the electrode pattern (EP) overlaps the common electrode (CME), and the portion overlapping the common electrode (CME) is entirely connected to the common electrode (CME), thereby reducing the voltage drop occurring in the common electrode (CME). Another portion of the electrode pattern (EP) overlaps the voltage transfer electrode (VTE), and the portion overlapping the voltage transfer electrode (VTE) is entirely connected to the voltage transfer electrode (VTE), thereby lowering the resistance of the voltage transfer path between the pad electrode (PD, see FIG. 3a) and the common electrode (CME). The electrode pattern (EP) is formed by the same process regardless of the regions and can have a monolithic shape. The electrode pattern (EP) can electrically connect the first common electrode (CME1, see FIG. 6) and the second common electrode (CME2, see FIG. 6) disposed on the aforementioned different layers.

[0071] FIG. 4 is a detailed perspective view illustrating a single light-emitting diode included in a display device according to one embodiment. A light-emitting diode (LED) will be described in detail with reference to FIG. 4. Meanwhile, each of the first to third light-emitting diodes (LED1, LED2, LED3, see FIG. 6) to be described later may have a stacked structure of the light-emitting diode (LED) described through FIG. 4.

[0072] The light-emitting diode (LED) may be columnar in shape. The light-emitting diode (LED) may be nanoscale to microscale in size. The light-emitting diode (LED) may have a diameter (or width) and / or length of nanoscale to microscale. The diameter (or width) may refer to the diameter (or width) in one direction perpendicular to the thickness direction (DR3), and the length may refer to the length in the thickness direction (DR3). However, the size of the light-emitting diode (LED) is not limited to this, and the size of the light-emitting diode (LED) may vary depending on the design conditions of various devices, such as those using a light-emitting device utilizing the light-emitting diode (LED) as a light source.

[0073] In FIG. 4, the lower conductive pattern (LE) and the upper conductive pattern (UE) are briefly illustrated as a single layer, and the light-emitting structure (SJS) is illustrated in detail. In FIG. 4, the lower conductive pattern (LE) in the shape of a disc, the light-emitting structure (SJS) in the shape of a cylinder, and the upper conductive pattern (UE) are illustrated as examples, but the shapes of the lower conductive pattern (LE), the light-emitting structure (SJS), and the upper conductive pattern (UE) are not limited thereto. For example, each of the lower conductive pattern (LE), the light-emitting structure (SJS), and the upper conductive pattern (UE) may have a polygonal column shape, such as a square column.

[0074] The light-emitting structure (SJS) may be a layer that substantially performs a light-emitting function in a light-emitting diode (LED). The light-emitting structure (SJS) may be described as a light-emitting layer. The light-emitting structure (SJS) may include an active layer (ACT), a p-type semiconductor layer (SP) disposed on one side of the active layer (ACT), and an n-type semiconductor layer (SN) disposed on the other side of the active layer (ACT). In this embodiment, the p-type semiconductor layer (SP) is disposed on the lower side of the active layer (ACT) because the lower conductive pattern (LE), which is an anode, is disposed on the lower side of the active layer (ACT). Unlike what is illustrated, if the upper conductive pattern (UE), which is disposed on the upper side of the active layer (ACT), is an anode, the p-type semiconductor layer (SP) may be disposed on the upper side of the active layer (ACT).

[0075] The active layer (ACT) can be formed into a single-quantum well or multi-quantum well structure. It can emit light through the coupling of electron-hole pairs according to an electric signal applied through the p-type semiconductor layer (SP) and the n-type semiconductor layer (SN). The active layer (ACT) can emit light having a wavelength of 400 nm to 900 nm and can use a double heterostructure.

[0076] In one embodiment of the present invention, the active layer (ACT) may have a structure in which semiconductor materials with a large band gap energy and semiconductor materials with a small band gap energy are alternately stacked, and may include semiconductor materials of group 3 to group 5 selected according to the wavelength range of the emitted light.

[0077] The p-type semiconductor layer (SP) comprises at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), or barium (Ba). For example, the p-type semiconductor layer (SP) may be p-GaN doped with magnesium (Mg). However, the material constituting the p-type semiconductor layer (SP) is not limited to this, and various other materials may also constitute the p-type semiconductor layer (SP).

[0078] The n-type semiconductor layer (SN) comprises at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may be doped with a second conductivity type dopant such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the n-type semiconductor layer (SN) is not limited to this, and various other materials may also constitute the n-type semiconductor layer (SN).

[0079] Although not shown, the light-emitting diode (LED) may further include a clad layer. The clad layer may be disposed on the upper and / or lower side of the active layer (ACT). The clad layer may include an AlGaN layer or an InAlGaN layer. The light-emitting diode (LED) may further include a tensile strain barrier reducing layer (TSBR) disposed on the upper and / or lower side of the active layer (ACT). The TSBR layer may be a strain relief layer disposed between semiconductor layers with different lattice structures to act as a buffer to reduce the difference in lattice constants. The TSBR layer may be composed of a p-type semiconductor layer such as p-GaInP, p-AlInP, p-AlGaInP, etc., but the present invention is not limited thereto.

[0080] In this embodiment, the lower conductive pattern (LE) may include at least one of a metal layer and a transparent conductive oxide layer. The lower conductive pattern (LE) may include, for example, both a metal layer and a transparent conductive oxide layer. Alternatively, the lower conductive pattern (LE) may include either a metal layer or a transparent conductive oxide layer. The lower conductive pattern (LE) may further include a reflective layer. The lower conductive pattern (LE) may further include a functional layer disposed between each of the metal layer, the transparent conductive oxide layer, and the reflective layer. The functional layer may be a layer that improves the adhesion of each layer and prevents atomic diffusion between adjacent layers.

[0081] The metal layer may correspond to an adhesive layer that bonds a CMOS wafer and a semiconductor substrate during the manufacturing process of a display device. That is, the metal layer may be a layer formed by bonding the metal layer of the CMOS wafer and the metal layer of the semiconductor substrate.

[0082] The metal layer may be provided as a single layer or as multiple layers. The metal layer may include any one of gold (Au), copper (Cu), silver (Ag), tin (Sn), titanium (Ti), zirconium (Zr), and tantalum (Ta), or may include an alloy of two of these metals. When the metal layer is provided as multiple layers, the metal layers provided as multiple layers may have a structure in which sub-metal layers having different materials are alternately stacked.

[0083] The transparent conductive oxide layer may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), or IGZO (indium gallium zinc oxide). The transparent conductive oxide layer included in the lower conductive pattern (LE) can inject holes into the light-emitting structure (SJS).

[0084] The reflective layer may be a layer that reflects light generated in the light-emitting structure (SJS) toward the light-emitting structure (SJS). The reflective layer may include gold (Au), copper (Cu), silver (Ag), titanium (Ti), or aluminum (Al).

[0085] In this embodiment, the upper conductive pattern (UE) may include a transparent conductive oxide layer. The transparent conductive oxide layer may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ZTO (zinc tin oxide), or IGZO (indium gallium zinc oxide). The transparent conductive oxide layer included in the upper conductive pattern (UE) can inject electrons into the light-emitting structure (SJS).

[0086] The upper conductive pattern (UE) may further include an electrode metal layer disposed between a transparent conductive oxide layer composed of a transparent conductive oxide and a light-emitting structure (SJS). The electrode metal layer may include a metal having a lower work function compared to the transparent conductive oxide layer. The electrode metal layer may improve the electron injection performance of the upper conductive pattern (UE). The electrode metal layer may include aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), nickel (Ni), copper (Cu), oxides thereof, or alloys thereof.

[0087] A light-emitting diode (LED) includes an insulating film (SI1) that covers at least a portion of the side of a light-emitting structure (SJS). Although a portion of the insulating film (SI1) is omitted in FIG. 4 for convenience of explanation, the insulating film (SI1) can cover the entire side of the light-emitting structure (SJS). By covering the side of the light-emitting structure (SJS), the insulating film (SI1) can prevent a reduction in efficiency caused by the etching surface during the etching process that forms the light-emitting structure (SJS). The insulating film (SI1) covers at least the side of the light-emitting structure (SJS) and can cover at least a portion of the upper conductive pattern (UE) and the lower conductive pattern (LE).

[0088] The light-emitting diode (LED) may further include an additional insulating film (SI2) disposed outside the insulating film (SI1). Although a portion of the additional insulating film (SI2) is omitted in FIG. 4 for convenience of explanation, the additional insulating film (SI2) can fully cover the side of the insulating film (SI1). The additional insulating film (SI2) can prevent a reduction in efficiency due to the etching surface and prevent contact between the external components and the light-emitting diode (LED). Although only one additional insulating film (SI2) is shown in FIG. 4, the additional insulating film (SI2) may be provided in multiple layers of two or more. The additional insulating film (SI2) covers at least the side of the light-emitting structure (SJS) and can cover at least a portion of the upper conductive pattern (UE) and the lower conductive pattern (LE).

[0089] Although not illustrated, the light-emitting diode (LED) may further include a side reflective layer disposed outside the additional insulating film (SI2). The side reflective layer can increase light efficiency by reflecting light generated from the light-emitting diode (LED) so that the light generated from the light-emitting diode (LED) is emitted in an upward direction. The side reflective layer may include gold, copper, silver, titanium, or aluminum.

[0090] FIG. 5 is an enlarged plan view of a part of a display device according to an embodiment of the present invention. FIG. 6 is an enlarged cross-sectional view of a part of a display device according to an embodiment of the present invention. FIG. 7a to 7c are plan views of a part of a display device according to an embodiment of the present invention. FIG. 5 is an enlarged plan view of a part region (A1) of the first region (DA) shown in FIG. 3a. FIG. 6 is a cross-sectional view corresponding to the II' cutting line shown in FIG. 5. FIG. 7a to 7c are plan views showing the planar arrangement of the components arranged corresponding to the first layer (L1), the second layer (L2), and the third layer (L3) among the components shown in FIG. 5.

[0091] Referring to FIG. 5, the first region (DA) may include a plurality of unit regions (UA) and a boundary region (BA) between the unit regions (UA). The boundary region (BA) may be an area where the aforementioned electrode pattern (EP) overlaps.

[0092] A plurality of light-emitting diodes (LED1, LED2, LED3) are disposed in each of the unit regions (UA). The unit regions (UA) may include a first unit region (UA1) in which the first light-emitting diode (LED1) and the second light-emitting diode (LED2) overlap, and a second unit region (UA2) in which the second light-emitting diode (LED2) and the third light-emitting diode (LED3) overlap. Each of the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) is disposed on different layers, and two or more light-emitting diodes may be correspondingly disposed in each unit region (UA). The first unit region (UA1) and the second unit region (UA2) may be disposed alternately along the first direction (DR1) and the second direction (DR2), respectively.

[0093] Referring together to FIGS. 5 to 7c, a display device (DD) of one embodiment may include a CMOS wafer (10), a light-emitting structure layer (20), and a lens layer (30).

[0094] A CMOS wafer (10) may include a silicon substrate (101). The silicon substrate (101) may include source / drain regions and a gate that define a transistor. Shallow trench isolation (STI) regions that isolate the transistor to prevent leakage current may be defined in the silicon substrate (101).

[0095] A CMOS wafer (10) may include a contact layer (102) disposed on a silicon substrate (101). In a first region (DA), the contact layer (102) may include a plurality of contact electrodes (CTE). The contact electrodes (CTE) may be connected to source / drain regions of the silicon substrate (101). The contact electrodes (CTE) may be formed by a damascene process. The contact electrodes (CTE) may include a metal such as copper or tungsten. The contact electrodes (CTE) may include a tungsten structure, a titanium layer surrounding the sides and bottom of the tungsten structure, and a titanium nitride layer surrounding the titanium layer. Alternatively, the contact electrodes (CTE) may include a copper structure, a tantalum layer surrounding the sides and bottom of the copper structure, and a tantalum nitride layer surrounding the tantalum layer.

[0096] The contact layer (102) may include a lower insulating layer (INS-a) disposed on a silicon substrate (101). The lower insulating layer (INS-a) may include an oxide layer such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. Although a single layer of the lower insulating layer (INS-a) is shown, the lower insulating layer (INS-a) may be provided in multiple layers. The upper surface of the contact electrodes (CTE) may define a plane (or flat surface) identical to the upper surface of the lower insulating layer (INS-a).

[0097] The light-emitting structure layer (20) is disposed on a CMOS wafer (10) and may include a plurality of layers (L1, L2, L3). In the first region (DA), each of the plurality of layers (L1, L2, L3) may include a plurality of light-emitting diodes (LED1, LED2, LED3). The plurality of light-emitting diodes (LED1, LED2, LED3) may include a plurality of first light-emitting diodes (LED1), a plurality of second light-emitting diodes (LED2), and a plurality of third light-emitting diodes (LED3) disposed on different layers. Meanwhile, unlike as shown in FIG. 6, the stacking order of the first layer (L1) containing the first light-emitting diodes (LED1), the second layer (L2) containing the second light-emitting diodes (LED2), and the third layer (L3) containing the third light-emitting diodes (LED3) may be changed.

[0098] The first layer (L1) is disposed on the contact layer (102) of the CMOS wafer (10) and may include a plurality of first light-emitting diodes (LED1). The plurality of first light-emitting diodes (LED1) may be disposed corresponding to a first unit area (UA1). The plurality of first light-emitting diodes (LED1) may emit light of a first wavelength.

[0099] Each of the first light-emitting diodes (LED1) comprises a first light-emitting structure (SJS1) and a first insulating film (SI1-1) disposed on the side of the first light-emitting structure (SJS1). Each of the first light-emitting diodes (LED1) may further comprise a first lower conductive pattern (LE1) disposed on the lower side of the first light-emitting structure (SJS1) and a first upper conductive pattern (UE1) disposed on the upper side of the first light-emitting structure (SJS1). Each of the first light-emitting diodes (LED1) may further comprise a first additional insulating film (SI2-1) disposed on the outer side of the first insulating film (SI1-1).

[0100] The first lower conductive pattern (LE1) may be placed directly on the contact layer (102). The first lower conductive pattern (LE1) may contact each of the contact electrodes (CTE) of the contact layer (102). The first lower conductive pattern (LE1) may include at least a metal. The first lower conductive pattern (LE1) may include a metal layer. The metal layer of the first lower conductive pattern (LE1) may be provided to connect the contact electrodes (CTE) of the CMOS wafer (10) with the first lower conductive pattern (LE1). The first lower conductive pattern (LE1) may further include a transparent conductive oxide layer.

[0101] A first light-emitting structure (SJS1) is disposed on a first lower conductive pattern (LE1) and may include at least an active layer. The first light-emitting structure (SJS1) may have a planar area that is smaller than or equal to the first lower conductive pattern (LE1) disposed below it. The first light-emitting structure (SJS1) may be fully superimposed on the first lower conductive pattern (LE1). As illustrated in FIG. 6, the side of the first light-emitting structure (SJS1) may be inclined with respect to the thickness direction (DR3). The first light-emitting structure (SJS1) may not be perpendicular to the upper surface of the first lower conductive pattern (LE1). The first light-emitting structure (SJS1) may be formed by a dry etching process and may include a side that is not parallel to the thickness direction (DR3).

[0102] The first upper conductive pattern (UE1) is disposed on the first light-emitting structure (SJS1) and may include a transparent conductive oxide. The first upper conductive pattern (UE1) may be fully superimposed on the first light-emitting structure (SJS1). The first upper conductive pattern (UE1) may have a planar area that is smaller than or equal to that of the first light-emitting structure (SJS1).

[0103] The first insulating film (SI1-1) can fully cover the side of the first light-emitting structure (SJS1). By covering the side of the first light-emitting structure (SJS1), the first insulating film (SI1-1) can prevent a reduction in efficiency caused by the etching surface during the etching process for forming the first light-emitting structure (SJS1). The first insulating film (SI1-1) covers at least the side of the first light-emitting structure (SJS1) and can cover at least a portion of the first upper conductive pattern (UE1) and the first lower conductive pattern (LE1).

[0104] The first light-emitting diode (LED1) may further include a first additional insulating layer (SI2-1) disposed outside the first insulating layer (SI1-1). The first additional insulating layer (SI2-1) may fully cover the side of the first insulating layer (SI1-1). The first additional insulating layer (SI2-1) may be provided in multiple layers of two or more. The first additional insulating layer (SI2-1) covers at least the side of the first light-emitting structure (SJS1) and may cover at least a portion of the first upper conductive pattern (UE1) and the first lower conductive pattern (LE1).

[0105] The first layer (L1) may further include first layer additional conductive patterns (AP1, AP2). The first layer additional conductive patterns (AP1, AP2) contact each of the contact electrodes (CTE) of the contact layer (102) and may be provided for electrical connection between the second light-emitting diodes (LED2) and third light-emitting diodes (LED3) placed on top and the CMOS wafer (10). The first layer additional conductive patterns (AP1, AP2) may be placed on the same layer as the first lower conductive pattern (LE1). The first layer additional conductive patterns (AP1, AP2) are formed through the same process as the first lower conductive pattern (LE1) and may include the same stacked structure and the same material. The first layer additional conductivity pattern (AP1, AP2) may include a first additional conductivity pattern (AP1) that overlaps with the second light-emitting diodes (LED2), and a second additional conductivity pattern (AP2) that overlaps with the third light-emitting diodes (LED3).

[0106] The second layer (L2) is disposed on the first layer (L1) and includes a plurality of second light-emitting diodes (LED2). The plurality of second light-emitting diodes (LED2) may be disposed corresponding to both the first unit area (UA1) and the second unit area (UA2). The plurality of second light-emitting diodes (LED2) may emit light of a second wavelength different from the first wavelength.

[0107] On a unit area, the number of second light-emitting diodes (LED2) arranged may be twice the number of first light-emitting diodes (LED1) arranged. As shown in FIG. 5, when a unit area area is defined as an area including two first unit areas (UA1) and two second unit areas (UA2), two first light-emitting diodes (LED1) and four second light-emitting diodes (LED2) may be arranged in the unit area area.

[0108] Each of the second light-emitting diodes (LED2) comprises a second light-emitting structure (SJS2) and a second insulating film (SI1-2) disposed on the side of the second light-emitting structure (SJS2). Each of the second light-emitting diodes (LED2) may further comprise a second lower conductive pattern (LE2) disposed on the lower side of the second light-emitting structure (SJS2) and a second upper conductive pattern (UE2) disposed on the upper side of the second light-emitting structure (SJS2). Each of the second light-emitting diodes (LED2) may further comprise a second additional insulating film (SI2-2) disposed on the outer side of the second insulating film (SI1-2).

[0109] The second lower conductive pattern (LE2) may include a transparent conductive oxide. The second lower conductive pattern (LE2) may not include metal. Unlike the first lower conductive pattern (LE1), the second lower conductive pattern (LE2) may include only a transparent conductive oxide without including metal. The second lower conductive pattern (LE2) may include only a transparent conductive oxide so as not to block light generated from the first light-emitting diode (LED1) placed at the bottom.

[0110] The second light-emitting structure (SJS2) is disposed on the second lower conductive pattern (LE2) and may include at least an active layer. The second light-emitting structure (SJS2) may have a planar area that is smaller than or equal to the second lower conductive pattern (LE2) disposed below it. The second light-emitting structure (SJS2) may be fully superimposed on the second lower conductive pattern (LE2). As illustrated in FIG. 6, the side of the second light-emitting structure (SJS2) may be inclined with respect to the thickness direction (DR3). The second light-emitting structure (SJS2) may not be perpendicular to the upper surface of the second lower conductive pattern (LE2). The second light-emitting structure (SJS2) may be formed by a dry etching process and may include a side that is not parallel to the thickness direction (DR3).

[0111] The second upper conductive pattern (UE2) is disposed on the second light-emitting structure (SJS2) and may include a transparent conductive oxide. The second upper conductive pattern (UE2) may be fully superimposed on the second light-emitting structure (SJS2). The second upper conductive pattern (UE2) may have a planar area that is smaller than or equal to that of the second light-emitting structure (SJS2).

[0112] The second insulating film (SI1-2) can fully cover the side of the second light-emitting structure (SJS2). By covering the side of the second light-emitting structure (SJS2), the second insulating film (SI1-2) can prevent a reduction in efficiency caused by the etching surface during the etching process for forming the second light-emitting structure (SJS2). The second insulating film (SI1-2) covers at least the side of the second light-emitting structure (SJS2) and can cover at least a portion of the second upper conductive pattern (UE2) and the second lower conductive pattern (LE2).

[0113] The second light-emitting diode (LED2) may further include a second additional insulating layer (SI2-2) disposed outside the second insulating layer (SI1-2). The second additional insulating layer (SI2-2) may fully cover the side of the second insulating layer (SI1-2). The second additional insulating layer (SI2-2) may be provided in multiple layers of two or more. The second additional insulating layer (SI2-2) covers at least the side of the second light-emitting structure (SJS2) and may cover at least a portion of the second upper conductive pattern (UE2) and the second lower conductive pattern (LE2).

[0114] The planar area of ​​each of the plurality of second light-emitting diodes (LED2) may be greater than or equal to the planar area of ​​each of the plurality of first light-emitting diodes (LED1). The planar area of ​​each of the second light-emitting structures (SJS2) included in the second light-emitting diodes (LED2) may be greater than or equal to the planar area of ​​each of the first light-emitting structures (SJS1) included in the first light-emitting diodes (LED1).

[0115] The second layer (L2) may further include a second layer additional conductive pattern (AP3, AP4). The second layer additional conductive pattern (AP3, AP4) may be provided for electrical connection between the first light-emitting diodes (LED1) placed at the bottom and the first common electrode (CME1), and for electrical connection between the third light-emitting diodes (LED3) placed at the top and the CMOS wafer (10). The second layer additional conductive pattern (AP3, AP4) may be placed on the same layer as the second bottom conductive pattern (LE2). The second layer additional conductive pattern (AP3, AP4) is formed through the same process as the second bottom conductive pattern (LE2) and may include the same stacked structure and the same material. The second layer additional conduction pattern (AP3, AP4) may include a third additional conduction pattern (AP3) overlapping with the first light-emitting diodes (LED1), and a fourth additional conduction pattern (AP4) overlapping with the third light-emitting diodes (LED3).

[0116] The third layer (L3) is disposed on the second layer (L2) and includes a plurality of third light-emitting diodes (LED3). The plurality of third light-emitting diodes (LED3) may be disposed corresponding to the second unit area (UA2). The plurality of third light-emitting diodes (LED3) may emit light of a third wavelength different from the first wavelength and the second wavelength.

[0117] On a unit area, the number of second light-emitting diodes (LED2) arranged may be twice the number of third light-emitting diodes (LED3) arranged. As illustrated in FIG. 5, when a unit area is defined as an area including two first unit areas (UA1) and two second unit areas (UA2), two third light-emitting diodes (LED3) and four second light-emitting diodes (LED2) may be arranged in the unit area.

[0118] Each of the third light-emitting diodes (LED3) comprises a third light-emitting structure (SJS3) and a third insulating film (SI1-3) disposed on the side of the third light-emitting structure (SJS3). Each of the third light-emitting diodes (LED3) may further comprise a third lower conductive pattern (LE3) disposed on the lower side of the third light-emitting structure (SJS3) and a third upper conductive pattern (UE3) disposed on the upper side of the third light-emitting structure (SJS3). Each of the third light-emitting diodes (LED3) may further comprise a third additional insulating film (SI2-3) disposed on the outer side of the third insulating film (SI1-3).

[0119] The third lower conductive pattern (LE3) may include a transparent conductive oxide. The third lower conductive pattern (LE3) may not include metal. Unlike the first lower conductive pattern (LE1), the third lower conductive pattern (LE3) may include only a transparent conductive oxide without including metal. The third lower conductive pattern (LE3) may include only a transparent conductive oxide so as not to block light generated from the first light-emitting diode (LED1) and the second light-emitting diode (LED2) placed at the bottom.

[0120] A third light-emitting structure (SJS3) is disposed on a third lower conductive pattern (LE3) and may include at least an active layer. The third light-emitting structure (SJS3) may have a planar area that is smaller than or equal to the third lower conductive pattern (LE3) disposed below it. The third light-emitting structure (SJS3) may be fully superimposed on the third lower conductive pattern (LE3). As illustrated in FIG. 6, the side of the third light-emitting structure (SJS3) may be inclined with respect to the thickness direction (DR3). The third light-emitting structure (SJS3) may not be perpendicular to the upper surface of the third lower conductive pattern (LE3). The third light-emitting structure (SJS3) may be formed by a dry etching process and may include a side that is not parallel to the thickness direction (DR3).

[0121] The third upper conductive pattern (UE3) is disposed on the third light-emitting structure (SJS3) and may include a transparent conductive oxide. The third upper conductive pattern (UE3) may be fully superimposed on the third light-emitting structure (SJS3). The third upper conductive pattern (UE3) may have a planar area that is smaller than or equal to that of the third light-emitting structure (SJS3).

[0122] The third insulating film (SI1-3) can fully cover the side of the third light-emitting structure (SJS3). By covering the side of the third light-emitting structure (SJS3), the third insulating film (SI1-3) can prevent a reduction in efficiency caused by the etching surface during the etching process for forming the third light-emitting structure (SJS3). The third insulating film (SI1-3) covers at least the side of the third light-emitting structure (SJS3) and can cover at least a portion of the third upper conductive pattern (UE3) and the third lower conductive pattern (LE3).

[0123] The third light-emitting diode (LED3) may further include a third additional insulating layer (SI2-3) disposed outside the third insulating layer (SI1-3). The third additional insulating layer (SI2-3) may fully cover the side of the third insulating layer (SI1-3). The third additional insulating layer (SI2-3) may be provided in multiple layers of two or more. The third additional insulating layer (SI2-3) covers at least the side of the third light-emitting structure (SJS3) and may cover at least a portion of the third upper conductive pattern (UE3) and the third lower conductive pattern (LE3).

[0124] The planar area of ​​each of the plurality of third light-emitting diodes (LED3) may be greater than or equal to the planar area of ​​each of the plurality of second light-emitting diodes (LED2). The planar area of ​​each of the third light-emitting structures (SJS3) included in the third light-emitting diodes (LED3) may be greater than or equal to the planar area of ​​each of the second light-emitting structures (SJS2) included in the second light-emitting diodes (LED2).

[0125] The light-emitting structure layer (20) may include flattening layers (INS1, INS2, INS3) disposed between at least some of the plurality of light-emitting diodes (LED1, LED2, LED3). The first layer (L1) may further include a first flattening layer (INS1) disposed between each of the first light-emitting diodes (LED1). The second layer (L2) may further include a second flattening layer (INS2) disposed between each of the second light-emitting diodes (LED2). The third layer (L3) may further include a third flattening layer (INS3) disposed between each of the third light-emitting diodes (LED3).

[0126] The first flattening layer (INS1) overlaps the unit regions (UA) and the boundary region (BA) and can fill the area where the first light-emitting diodes (LED1) are not placed. The first flattening layer (INS1) may include an organic material. The upper surface of the first flattening layer (INS1) may define a plane (or flat surface) identical to the upper surface of the first upper conductive pattern (UE1) of the first light-emitting diodes (LED1). The second flattening layer (INS2) overlaps the unit regions (UA) and the boundary region (BA) and can fill the area where the second light-emitting diodes (LED2) are not placed. The second flattening layer (INS2) may include an organic material. The upper surface of the second flattening layer (INS2) may define a plane (or flat surface) identical to the upper surface of the second upper conductive pattern (UE2) of the second light-emitting diodes (LED2). The third flattening layer (INS3) overlaps the unit regions (UA) and the boundary region (BA) and can fill the region where the third light-emitting diodes (LED3) are not placed. The third flattening layer (INS3) may include an organic material. The upper surface of the third flattening layer (INS3) may define a plane (or flat surface) identical to the upper surface of the third upper conductive pattern (UE3) of the third light-emitting diodes (LED3).

[0127] The light-emitting structure layer (20) may further include a common electrode (CME1, CME2) that is electrically connected to at least some of the plurality of light-emitting diodes (LED1, LED2, LED3). The common electrode (CME1, CME2) may include a first common electrode (CME1) and a second common electrode (CME2). The first common electrode (CME1) is connected to at least some of the first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3). The second common electrode (CME2) is connected to at least some of the remaining first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3) that are not connected to the first common electrode (CME1). In a display device (DD) of one embodiment illustrated in FIGS. 5 to 7c, the first common electrode (CME1) is connected to the first light-emitting diodes (LED1) and the second light-emitting diodes (LED2), and the second common electrode (CME2) can be connected to the third light-emitting diodes (LED3).

[0128] The first common electrode (CME1) may be disposed on the same layer as the third lower conductive pattern (LE3). The first common electrode (CME1) is formed through the same process as the third lower conductive pattern (LE3) and may include the same stacked structure and the same material. The first common electrode (CME1) may include a transparent conductive oxide. The second common electrode (CME2) may be disposed on the third layer (L3). The second common electrode (CME2) may include a transparent conductive oxide.

[0129] The light-emitting structure layer (20) further includes an electrode pattern (EP), and the electrode pattern (EP) has a mesh structure in a planar plane. The electrode pattern (EP) can be positioned corresponding to a boundary region (BA). The electrode pattern (EP) can be non-overlapping in a planar plane with each of the first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3).

[0130] The electrode pattern (EP) is disposed within the third layer (L3) and electrically connects the first common electrode (CME1) and the second common electrode (CME2). The electrode pattern (EP) may be disposed on the same layer as the third light-emitting structure (SJS3) of the third light-emitting diode (LED3). The electrode pattern (EP) may electrically connect the first common electrode (CME1) and the second common electrode (CME2) by contacting the upper surface of the first common electrode (CME1) and the lower surface of the second common electrode (CME2).

[0131] The light-emitting structure layer (20) may further include optical layers (DBR1, DBR2). The optical layers (DBR1, DBR2) may be disposed between the first layer (L1) and the second layer (L2), and between the second layer (L2) and the third layer (L3). The optical layers (DBR1, DBR2) may include, for example, a first optical layer (DBR1) disposed between the first layer (L1) and the second layer (L2), and a second optical layer (DBR2) disposed between the second layer (L2) and the third layer (L3). Either the first optical layer (DBR1) or the second optical layer (DBR2) may be omitted.

[0132] Each of the first optical layer (DBR1) and the second optical layer (DBR2) may include a plurality of sublayers (SL1, SL2). Each of the first optical layer (DBR1) and the second optical layer (DBR2) may include a first sublayer (SL1) having a first refractive index and a second sublayer (SL2) having a second refractive index different from the first refractive index. Each of the first sublayer (SL1) and the second sublayer (SL2) may be provided in a plurality and may be arranged alternately with respect to each other. As the first sublayer (SL1) and the second sublayer (SL2) having different refractive indices are arranged alternately, each of the first optical layer (DBR1) and the second optical layer (DBR2) may reflect light of a specific wavelength and transmit light of other wavelengths. For example, the first optical layer (DBR1) can transmit light of a wavelength emitted from the first light-emitting diode (LED1) and reflect light of a wavelength emitted from the second light-emitting diode (LED2) and the third light-emitting diode (LED3). The second optical layer (DBR2) can transmit light of a wavelength emitted from the first light-emitting diode (LED1) and the second light-emitting diode (LED2) and reflect light of a wavelength emitted from the third light-emitting diode (LED3).

[0133] The light-emitting structure layer (20) may further include connecting wires (CL1, CL2, CL3). Each of the connecting wires (CL1, CL2, CL3) may be provided for electrical connection between light-emitting diodes (LED1, LED2, LED3), a first common electrode (CME1), and a CMOS wafer (10). Each of the connecting wires (CL1, CL2, CL3) may be formed by a damascene process. Each of the connecting wires (CL1, CL2, CL3) may include a metal such as copper or tungsten.

[0134] A first connecting wire (CL1) may be disposed on the upper portion of each of the first light-emitting diodes (LED1). The first connecting wire (CL1) overlaps with the first light-emitting diodes (LED1) in a plane and may be provided to electrically connect the first common electrode (CME1) and the first light-emitting diodes (LED1). The first connecting wire (CL1) may include a first-1 connecting wire (CL1-1) disposed between the first upper conductive pattern (UE1) and the third additional conductive pattern (AP3) of the first light-emitting diodes (LED1), and a first-2 connecting wire (CL1-2) disposed between the third additional conductive pattern (AP3) and the first common electrode (CME1). The first lower conductive pattern (LE1) of the first light-emitting diodes (LED1) can be electrically connected to the CMOS wafer (10) by directly contacting the contact electrode (CTE). The first upper conductive pattern (UE1) of the first light-emitting diodes (LED1) can be electrically connected to the first common electrode (CME1) by the first-1 connecting wire (CL1-1), the third additional conductive pattern (AP3), and the first-2 connecting wire (CL1-2) arranged sequentially between them.

[0135] A second connecting wire (CL2) may be disposed on the upper and lower portions of each of the second light-emitting diodes (LED2). The second connecting wire (CL2) overlaps with the second light-emitting diodes (LED2) in a plane and may be provided to electrically connect the second light-emitting diodes (LED2) with the first common electrode (CME1) and the CMOS wafer (10). The second connecting wire (CL2) may include a second-1 connecting wire (CL2-1) disposed between the second lower conductive pattern (LE2) and the first additional conductive pattern (AP1) of the second light-emitting diodes (LED2), and a second-2 connecting wire (CL2-2) disposed between the second upper conductive pattern (UE2) and the first common electrode (CME1) of the second light-emitting diodes (LED2). The second lower conductive pattern (LE2) of the second light-emitting diodes (LED2) can be electrically connected to the CMOS wafer (10) by the second-1 connecting wire (CL2-1) and the first additional conductive pattern (AP1) arranged sequentially between them. The second upper conductive pattern (UE2) of the second light-emitting diodes (LED2) can be electrically connected to the first common electrode (CME1) by the second-2 connecting wire (CL2-2) arranged between them.

[0136] A third connecting wire (CL3) may be disposed at the bottom of each of the third light-emitting diodes (LED3). The third connecting wire (CL3) may overlap with the third light-emitting diodes (LED3) in a plane and may be provided to electrically connect the CMOS wafer and the third light-emitting diodes (LED3). The third connecting wire (CL3) may include a third-1 connecting wire (CL3-1) disposed between the third lower conductive pattern (LE3) and the fourth additional conductive pattern (AP4) of the third light-emitting diodes (LED3), and a third-2 connecting wire (CL3-2) disposed between the fourth additional conductive pattern (AP4) and the second additional conductive pattern (AP2). The third upper conductive pattern (UE3) of the third light-emitting diodes (LED3) may be electrically connected to the second common electrode (CME2) by directly contacting the second common electrode (CME2). The third lower conductive pattern (LE3) of the third light-emitting diodes (LED3) can be electrically connected to the CMOS wafer (10) by the third-1 connecting wire (CL3-1), the fourth additional conductive pattern (AP4), the third-2 connecting wire (CL3-2), and the second additional conductive pattern (AP2) arranged sequentially between them.

[0137] Each of the first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3) may have at least a portion that is non-overlapping in a plane. Each of the first light-emitting diodes (LED1) may have a portion that overlaps with the second light-emitting diodes (LED2) in a plane, and a remainder that is non-overlapping. Each of the first light-emitting diodes (LED1) may have a portion that overlaps with the third light-emitting diodes (LED3) in a plane. Each of the second light-emitting diodes (LED2) may have a portion that overlaps with the first light-emitting diodes (LED1) and the third light-emitting diodes (LED3), respectively, and a remainder that is non-overlapping. Each of the third light-emitting diodes (LED3) may have a portion that overlaps with the second light-emitting diodes (LED2) in a plane, and a remainder that is non-overlapping. Each of the first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3) can be non-overlapping with other light-emitting diodes in the area connected to the connecting wires (CL1, CL2, CL3).

[0138] The lens layer (30) is disposed on the light-emitting structure layer (20) and may include a plurality of lenses (LS). The lens layer (30) may further include a passivation layer (BS-L) that provides a base surface on which the lenses (LS) are disposed. The passivation layer (BS-L) may be disposed on the second common electrode (CME2) to protect the second common electrode (CME2). The passivation layer (BS-L) may include an organic material or an inorganic material.

[0139] Lenses (LS) may be arranged to overlap at least the light-emitting diodes (LED1, LED2, LED3). As illustrated in FIG. 6, lenses (LS) may be arranged corresponding to each of the first unit area (UA1) and the second unit area (UA2). One lens (LS) may be provided in each of the first unit area (UA1) and one lens may be provided in each of the second unit area (UA2). The lenses (LS) provided in the first unit area (UA1) may be arranged corresponding to one first light-emitting diode (LED1) and one second light-emitting diode (LED2), and the lenses (LS) provided in the second unit area (UA2) may be arranged corresponding to one second light-emitting diode (LED2) and one third light-emitting diode (LED3). Each of the lenses (LS) may have a circular shape in a planar shape, and the diameter of each lens (LS) may be 1 micrometer or less.

[0140] A display device (DD) of one embodiment has a structure in which light-emitting diodes (LED1, LED2, LED3) are provided in multiple layers, and can have high resolution. Meanwhile, although a large voltage drop may occur at the common electrode due to the high resolution of the display device (DD), the display device (DD) of one embodiment includes a first common electrode (CME1) and a second common electrode (CME2) provided in multiple layers, and has a structure in which the first common electrode (CME1) and the second common electrode (CME2) are electrically connected through an electrode pattern (EP), thereby reducing the voltage drop occurring at the common electrode. Accordingly, the resolution of the display device (DD) can be improved and defects can be reduced.

[0141] FIGS. 8a to 8c are each enlarged cross-sectional views of a portion of a display device according to an embodiment of the present invention. FIG. 8a is a cross-sectional view centered on the cross-section of a first light-emitting diode (LED1) included in a display device (DD) of an embodiment, FIG. 8b is a cross-sectional view centered on the cross-section of a second light-emitting diode (LED2) included in a display device (DD) of an embodiment, and FIG. 8c is a cross-sectional view centered on the cross-section of a third light-emitting diode (LED3) included in a display device (DD) of an embodiment.

[0142] Referring to FIG. 8a, the side (SJS1_SF) of the first light-emitting structure (SJS1) may be inclined. The side (SJS1_SF) of the first light-emitting structure (SJS1) may not be parallel to the thickness direction (DR3). The side (SJS1_SF) of the first light-emitting structure (SJS1) may not be perpendicular to the upper surface (LE1_UF) of the first lower conductive pattern (LE1). The first light-emitting structure (SJS1) may be formed by a dry etching process and may include a side (SJS1_SF) that is not parallel to the thickness direction (DR3). The width of the first light-emitting structure (SJS1) may decrease from the bottom to the top.

[0143] The side (UE1_SF) of the first upper conductive pattern (UE1) may be substantially parallel with respect to the thickness direction (DR3). Substantially parallel includes not only cases where they are parallel without error but also cases where they differ within a process error range.

[0144] The first insulating film (SI1-1) may be in contact with the side (SJS1_SF) of the first light-emitting structure (SJS1) and the side (UE1_SF) of the first upper conductive pattern (UE1). The extension direction of the portion of the first insulating film (SI1-1) in contact with the side (SJS1_SF) of the first light-emitting structure (SJS1) may be inclined with respect to the thickness direction (DR3). The extension direction of the portion of the first insulating film (SI1-1) in contact with the side (UE1_SF) of the first upper conductive pattern (UE1) may be substantially parallel to the thickness direction (DR3). The first insulating film (SI1-1) may be further disposed on a portion of the upper surface (UE1_UF) of the first upper conductive pattern (UE1). The first insulating film (SI1-1) may be further disposed in an area of ​​the upper surface (LE1_UF) of the first lower conductive pattern (LE1) where the first light-emitting structure (SJS1) is not disposed. A first-1 sub-opening (S11_OH) exposing a connection area (AA1) of the upper surface (UE1_UF) of the first upper conductive pattern (UE1) may be defined in the first insulating film (SI1-1).

[0145] The first additional insulating film (SI2-1) may be spaced apart from the side (SJS1_SF) of the first light-emitting structure (SJS1), the side (UE1_SF) of the first upper conductive pattern (UE1), and the upper surface (UE1_UF) of the first upper conductive pattern (UE1) with the first insulating film (SI1-1) in between. The first additional insulating film (SI2-1) may be disposed on the side (LE1_SF) of the first lower conductive pattern (LE1), the side (SJS1_SF) of the first light-emitting structure (SJS1), the side (UE1_SF) of the first upper conductive pattern (UE1), and the upper surface (UE1_UF) of the first upper conductive pattern (UE1). The first additional insulating film (SI2-1) may be further disposed on the upper surface (LE1_UF) of the first lower conductive pattern (LE1). On the side (SJS1_SF) of the first light-emitting structure (SJS1), the extension direction of the first additional insulating film (SI2-1) may be inclined with respect to the thickness direction (DR3). A second-1 sub-opening (S21_OH) exposing a connection area (AA1) of the upper surface (UE1_UF) of the first upper conductive pattern (UE1) may be defined in the first additional insulating film (SI2-1).

[0146] The first side reflective layer (SRL1) may be spaced apart from the first light-emitting structure (SJS1) with the first insulating film (SI1-1) and the first additional insulating film (SI2-1) in between. The first side reflective layer (SRL1) may be disposed on the side (LE1_SF) of the first lower conductive pattern (LE1), the side (SJS1_SF) of the first light-emitting structure (SJS1), the side (UE1_SF) of the first upper conductive pattern (UE1), and the upper surface (UE1_UF) of the first upper conductive pattern (UE1). On the side (SJS1_SF) of the first light-emitting structure (SJS1), the extension direction of the first side reflective layer (SRL1) may be inclined with respect to the thickness direction (DR3). A third-1 sub-opening (R1_OH) that exposes a connection area (AA1) of the upper surface (UE1_UF) of the first upper conductive pattern (UE1) may be defined in the first side reflective layer (SRL1).

[0147] The first-1 sub-opening (S11_OH) of the first insulating film (SI1-1), the second-1 sub-opening (S21_OH) of the first additional insulating film (SI2-1), and the third-1 sub-opening (R1_OH) of the first side reflective layer (SRL1) may constitute the first opening (COP1). The inner surface of the first insulating film (SI1-1) defining the first-1 sub-opening (S11_OH), the inner surface of the first additional insulating film (SI2-1) defining the second-1 sub-opening (S21_OH), and the inner surface of the first side reflective layer (SRL1) defining the third-1 sub-opening (R1_OH) may be parallel. The first-1 connecting wire (CL1-1) can contact the connection area (AA1) of the upper surface (UE1_UF) of the first upper conductive pattern (UE1) through the first opening (COP1).

[0148] The first flattening layer (INS1) may be placed on the side (LE1_SF) of the first lower conductive pattern (LE1) and on the side (SJS1_SF) of the first light-emitting structure (SJS1). A portion of the first flattening layer (INS1) may be placed corresponding to the side (UE1_SF) of the first upper conductive pattern (UE1), and another portion may be placed on the first upper conductive pattern (UE1) and overlap with the first side reflective layer (SRL1).

[0149] Referring to FIG. 8b, the side (SJS2_SF) of the second light-emitting structure (SJS2) may be inclined. The side (SJS2_SF) of the second light-emitting structure (SJS2) may not be parallel to the thickness direction (DR3). The side (SJS2_SF) of the second light-emitting structure (SJS2) may not be perpendicular to the upper surface (LE2_UF) of the second lower conductive pattern (LE2). The second light-emitting structure (SJS2) may be formed by a dry etching process and may include a side (SJS2_SF) that is not parallel to the thickness direction (DR3). The width of the second light-emitting structure (SJS2) may decrease from the bottom to the top.

[0150] The side (UE2_SF) of the second upper conductive pattern (UE2) may be substantially parallel with respect to the thickness direction (DR3). Being substantially parallel includes not only cases where they are parallel without error, but also cases where they differ within a process error range.

[0151] The second insulating film (SI1-2) may come into contact with the side (SJS2_SF) of the second light-emitting structure (SJS2) and the side (UE2_SF) of the second upper conductive pattern (UE2). The extension direction of the portion of the second insulating film (SI1-2) that comes into contact with the side (SJS2_SF) of the second light-emitting structure (SJS2) may be inclined with respect to the thickness direction (DR3). The extension direction of the portion of the second insulating film (SI1-2) that comes into contact with the side (UE2_SF) of the second upper conductive pattern (UE2) may be substantially parallel to the thickness direction (DR3). The second insulating film (SI1-2) may be further disposed on a portion of the upper surface (UE2_UF) of the second upper conductive pattern (UE2). The second insulating film (SI1-2) may be further disposed in the area of ​​the upper surface (LE2_UF) of the second lower conductive pattern (LE2) where the second light-emitting structure (SJS2) is not disposed. In the second insulating film (SI1-2), a first-second sub-opening (S12_OH) may be defined that exposes the connection area (AA2) of the upper surface (UE2_UF) of the second upper conductive pattern (UE2).

[0152] The second additional insulating film (SI2-2) may be spaced apart from the side (SJS2_SF) of the second light-emitting structure (SJS2), the side (UE2_SF) of the second upper conductive pattern (UE2), and the upper surface (UE2_UF) of the second upper conductive pattern (UE2) with the second insulating film (SI1-2) in between. The second additional insulating film (SI2-2) may be disposed on the side (LE2_SF) of the second lower conductive pattern (LE2), the side (SJS2_SF) of the second light-emitting structure (SJS2), the side (UE2_SF) of the second upper conductive pattern (UE2), and the upper surface (UE2_UF) of the second upper conductive pattern (UE2). The second additional insulating film (SI2-2) may be further disposed on the upper surface (UE2_UF) of the second lower conductive pattern (LE2). On the side (SJS2_SF) of the second light-emitting structure (SJS2), the extension direction of the second additional insulating film (SI2-2) may be inclined with respect to the thickness direction (DR3). A second-2 sub-opening (S22_OH) may be defined in the second additional insulating film (SI2-2) to expose a connection area (AA2) of the upper surface (UE2_UF) of the second upper conductive pattern (UE2).

[0153] The second side reflective layer (SRL2) may be spaced apart from the second light-emitting structure (SJS2) with the second insulating film (SI1-2) and the second additional insulating film (SI2-2) in between. The second side reflective layer (SRL2) may be disposed on the side (LE2_SF) of the second lower conductive pattern (LE2), the side (SJS2_SF) of the second light-emitting structure (SJS2), the side (UE2_SF) of the second upper conductive pattern (UE2), and the upper surface (UE2_UF) of the second upper conductive pattern (UE2). On the side (SJS2_SF) of the second light-emitting structure (SJS2), the extension direction of the second side reflective layer (SRL2) may be inclined with respect to the thickness direction (DR3). A third-2 sub-opening (R2_OH) that exposes a connection area (AA2) of the upper surface (UE2_UF) of the second upper conductive pattern (UE2) may be defined in the second side reflective layer (SRL2).

[0154] The first-2 sub-opening (S12_OH) of the second insulating film (SI1-2), the second-2 sub-opening (S22_OH) of the second additional insulating film (SI2-2), and the third-2 sub-opening (R2_OH) of the second side reflective layer (SRL2) may constitute the second opening (COP2). The inner surface of the second insulating film (SI1-2) defining the first-2 sub-opening (S12_OH), the inner surface of the second additional insulating film (SI2-2) defining the second-2 sub-opening (S22_OH), and the inner surface of the second side reflective layer (SRL2) defining the third-2 sub-opening (R2_OH) may be parallel. The second-2 connecting wire (CL2-2) can contact the connection area (AA2) of the upper surface (UE2_UF) of the second upper conductive pattern (UE2) through the second opening (COP2).

[0155] The second flattening layer (INS2) may be placed on the side (LE2_SF) of the second lower conductive pattern (LE2) and on the side (SJS2_SF) of the second light-emitting structure (SJS2). A portion of the second flattening layer (INS2) may be placed corresponding to the side (UE2_SF) of the second upper conductive pattern (UE2), and another portion may be placed on the second upper conductive pattern (UE2) and overlap with the second side reflective layer (SRL2).

[0156] Referring to FIG. 8c, the side (SJS3_SF) of the third light-emitting structure (SJS3) may be inclined. The side (SJS3_SF) of the third light-emitting structure (SJS3) may not be parallel to the thickness direction (DR3). The side (SJS3_SF) of the third light-emitting structure (SJS3) may not be perpendicular to the upper surface (LE3_UF) of the third lower conductive pattern (LE3). The third light-emitting structure (SJS3) may be formed by a dry etching process and may include a side (SJS3_SF) that is not parallel to the thickness direction (DR3). The width of the third light-emitting structure (SJS3) may decrease from the bottom to the top.

[0157] The side (UE3_SF) of the third upper conductive pattern (UE3) may be substantially parallel with respect to the thickness direction (DR3). Substantially parallel includes not only cases where they are parallel without error but also cases where they differ within a process error range.

[0158] The third insulating film (SI1-3) may be in contact with the side (SJS3_SF) of the third light-emitting structure (SJS3) and the side (UE3_SF) of the third upper conductive pattern (UE3). The extension direction of the portion of the third insulating film (SI1-3) in contact with the side (SJS3_SF) of the third light-emitting structure (SJS3) may be inclined with respect to the thickness direction (DR3). The extension direction of the portion of the third insulating film (SI1-3) in contact with the side (UE3_SF) of the third upper conductive pattern (UE3) may be substantially parallel to the thickness direction (DR3). The third insulating film (SI1-3) may be further disposed on a portion of the upper surface (UE3_UF) of the third upper conductive pattern (UE3). A third insulating film (SI1-3) may be further disposed in an area of ​​the upper surface (LE3_UF) of the third lower conductive pattern (LE3) where the third light-emitting structure (SJS3) is not disposed. A first-third sub-opening (S13_OH) exposing a connection area (AA3) of the upper surface (UE3_UF) of the third upper conductive pattern (UE3) may be defined in the third insulating film (SI1-3).

[0159] The third additional insulating film (SI2-3) may be spaced apart from the side (SJS3_SF) of the third light-emitting structure (SJS3), the side (UE3_SF) of the third upper conductive pattern (UE3), and the upper surface (UE3_UF) of the third upper conductive pattern (UE3) with the third insulating film (SI1-3) in between. The third additional insulating film (SI2-3) may be disposed on the side (LE3_SF) of the third lower conductive pattern (LE3), the side (SJS3_SF) of the third light-emitting structure (SJS3), the side (UE3_SF) of the third upper conductive pattern (UE3), and the upper surface (UE3_UF) of the third upper conductive pattern (UE3). The third additional insulating film (SI2-3) may be further disposed on the upper surface (UE3_UF) of the third lower conductive pattern (LE3). On the side (SJS3_SF) of the third light-emitting structure (SJS3), the extension direction of the third additional insulating film (SI2-3) may be inclined with respect to the thickness direction (DR3). A second-third sub-opening (S23_OH) may be defined in the third additional insulating film (SI2-3) to expose a connection area (AA3) of the upper surface (UE3_UF) of the third upper conductive pattern (UE3).

[0160] The third side reflective layer (SRL3) may be spaced apart from the third light-emitting structure (SJS3) with the third insulating film (SI1-3) and the third additional insulating film (SI2-3) in between. The third side reflective layer (SRL3) may be disposed on the side (LE3_SF) of the third lower conductive pattern (LE3), the side (SJS3_SF) of the third light-emitting structure (SJS3), the side (UE3_SF) of the third upper conductive pattern (UE3), and the upper surface (UE3_UF) of the third upper conductive pattern (UE3). On the side (SJS3_SF) of the third light-emitting structure (SJS3), the extension direction of the third side reflective layer (SRL3) may be inclined with respect to the thickness direction (DR3). A third-third sub-opening (R3_OH) that exposes a connection area (AA3) of the upper surface (UE3_UF) of the third upper conductive pattern (UE3) may be defined in the third side reflective layer (SRL3).

[0161] The first-third sub-opening (S13_OH) of the third insulating film (SI1-3), the second-third sub-opening (S23_OH) of the third additional insulating film (SI2-3), and the third-third sub-opening (R3_OH) of the third side reflective layer (SRL3) may constitute the third opening (COP3). The inner surface of the third insulating film (SI1-3) defining the first-third sub-opening (S13_OH), the inner surface of the third additional insulating film (SI2-3) defining the second-third sub-opening (S23_OH), and the inner surface of the third side reflective layer (SRL3) defining the third-third sub-opening (R3_OH) may be parallel. The second common electrode (CME2) can contact the connection area (AA3) of the upper surface (UE3_UF) of the third upper conductive pattern (UE3) through the third opening (COP3).

[0162] The third flattening layer (INS3) may be placed on the side (LE3_SF) of the third lower conductive pattern (LE3) and on the side (SJS3_SF) of the third light-emitting structure (SJS3). A portion of the third flattening layer (INS3) may be placed corresponding to the side (UE3_SF) of the third upper conductive pattern (UE3), and another portion may be placed on the third upper conductive pattern (UE3) and overlapped with the third side reflective layer (SRL3).

[0163] Referring together to FIGS. 8a to 8c, with respect to a first insulating film (SI1-1) covering a side (SJS1_SF) of a first light-emitting structure (SJS1), a second insulating film (SI1-2) covering a side (SJS2_SF) of a second light-emitting structure (SJS2), and a third insulating film (SI1-3) covering a side (SJS3_SF) of a third light-emitting structure (SJS3), at least one of the first insulating film (SI1-1), the second insulating film (SI1-2), and the third insulating film (SI1-3) comprises a material different from the remaining insulating film.

[0164] In one embodiment, the first insulating film (SI1-1) may comprise a material different from that of the second insulating film (SI1-2). The first light-emitting diode (LED1) comprising the first insulating film (SI1-1) emits light of a different wavelength than the second light-emitting diode (LED2) comprising the second insulating film (SI1-2), and the first insulating film (SI1-1) and the second insulating film (SI1-2) may comprise different materials.

[0165] The first insulating layer (SI1-1) may contain a material different from that of the third insulating layer (SI1-3). The first light-emitting diode (LED1) containing the first insulating layer (SI1-1) emits light of a different wavelength than the third light-emitting diode (LED3) containing the third insulating layer (SI1-3), and the first insulating layer (SI1-1) and the third insulating layer (SI1-3) may contain different materials.

[0166] In one embodiment, the second insulating layer (SI1-2) and the third insulating layer (SI1-3) may comprise the same material. The first light-emitting diode (LED1) emits light of a first wavelength, the second light-emitting diode (LED2) emits light of a second wavelength, and the third light-emitting diode (LED3) emits light of a third wavelength, and the first wavelength may be shorter than the second wavelength and the third wavelength. In one embodiment, the first insulating layer (SI1-1) included in the first light-emitting diode (LED1) that emits light of a short wavelength may comprise a material different from the insulating layers of the other light-emitting diodes. The second insulating layer (SI1-2) and the third insulating layer (SI1-3) included in the second light-emitting diode (LED2) and the third light-emitting diode (LED3), respectively that emit light of a relatively long wavelength, may each comprise the same material. However, not limited thereto, the second insulating film (SI1-2) and the third insulating film (SI1-3) may comprise different materials.

[0167] The first insulating film (SI1-1) comprises a first insulating material, and the second insulating film (SI1-2) may comprise a second insulating material different from the first insulating material. The first insulating material may comprise a high-dielectric constant (High-K) material compared to the second insulating material. For example, the first insulating material may comprise at least one of hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, hafnium nitrate, zirconium nitrate, tantalum nitrate, hafnium nitride, lanthanum nitride, and zirconium nitride. The first insulating material may comprise a material having a dielectric constant (K) of 10 or more. As the first insulating film (SI1-1) comprises a high-dielectric constant material, the external quantum efficiency (EQE) of the first light-emitting diode (LED1) may be improved compared to when the first insulating film (SI1-1) comprises a material with a relatively low dielectric constant, such as silicon oxide and aluminum oxide.

[0168] The second insulating material has a band gap energy (E g It may include a material with a high bandgap energy (E). For example, the second insulating material may include at least one of silicon oxide and aluminum oxide. The second insulating material may include a bandgap energy (E g It may include a material having a band gap energy of 6 eV or higher. As the second insulating film (SI1-2) includes a material with a high band gap energy, the external quantum efficiency of the second light-emitting diode (LED2) can be improved compared to when the second insulating film (SI1-2) includes materials such as hafnium oxide and zirconium oxide.

[0169] The third insulating film (SI1-3) may include a third insulating material different from the first insulating material. The third insulating material has a band gap energy (E g It may include a material with a high bandgap energy. For example, the third insulating material may include at least one of silicon oxide and aluminum oxide. The third insulating material has a bandgap energy (E gIt may include a material having a bandgap energy of 6 eV or higher. As the third insulating film (SI1-3) includes a material with a high bandgap energy, the external quantum efficiency of the third light-emitting diode (LED3) may be improved compared to when the third insulating film (SI1-3) includes materials such as hafnium oxide and zirconium oxide. The third insulating material may include the same material as the second insulating material. Alternatively, the third insulating material may include a material different from the second insulating material.

[0170] A display device (DD) of one embodiment includes a plurality of light-emitting diodes (LED1, LED2, LED3) that emit light of different wavelengths, and at least one of the insulating films (SI1-1, SI1-2, SI1-3) covering the sides of the light-emitting structures (SJS1, SJS2, SJS3) included in the plurality of light-emitting diodes (LED1, LED2, LED3) comprises a material different from that of the other insulating films. For example, the first insulating film (SI1-1) included in the first light-emitting diode (LED1) that emits light of a short wavelength may comprise a material different from that of the insulating films of the other light-emitting diodes. In the display device (DD) of one embodiment, the external quantum efficiency of each of the light-emitting diodes (LED1, LED2, LED3) can be improved by providing insulating films of different materials suitable for the emission wavelength of each of the light-emitting diodes (LED1, LED2, LED3). Accordingly, the display efficiency of a display device (DD) including light-emitting diodes (LED1, LED2, LED3) can be improved.

[0171] The first additional insulating layer (SI2-1) may include the same material as the first insulating layer (SI1-1). The second additional insulating layer (SI2-2) may include the same material as the second insulating layer (SI1-2). The third additional insulating layer (SI2-3) may include the same material as the third insulating layer (SI1-3). That is, the first additional insulating layer (SI2-1) includes a first insulating material including the aforementioned high dielectric constant material, and the second additional insulating layer (SI2-2) and the third additional insulating layer (SI2-3) may each include the aforementioned second insulating material and third insulating material having high bandgap energy, respectively. The material included in the first additional insulating layer (SI2-1) may be different from the material included in the second additional insulating layer (SI2-2) and the third additional insulating layer (SI2-3), respectively. However, not limited thereto, the first additional insulating film (SI2-1), the second additional insulating film (SI2-2), and the third additional insulating film (SI2-3) may each contain the same material. For example, the first additional insulating film (SI2-1), the second additional insulating film (SI2-2), and the third additional insulating film (SI2-3) may each contain at least one of silicon oxide and aluminum oxide.

[0172] Each of the first side reflective layer (SRL1), the second side reflective layer (SRL2), and the third side reflective layer (SRL3) may include a reflective metal. Each of the first side reflective layer (SRL1), the second side reflective layer (SRL2), and the third side reflective layer (SRL3) may include the same material. For example, each of the first side reflective layer (SRL1), the second side reflective layer (SRL2), and the third side reflective layer (SRL3) may include gold, copper, silver, titanium, or aluminum.

[0173] FIG. 9 is an enlarged plan view of a portion of a display device according to an embodiment of the present invention. FIG. 10 is an enlarged cross-sectional view of a portion of a display device according to an embodiment of the present invention. FIG. 11a to FIG. 11c are plan views of a portion of a configuration of a display device according to an embodiment of the present invention. FIG. 9 is an enlarged plan view of a portion of a region (A1) of a first region (DA) shown in FIG. 3a. FIG. 10 is a cross-sectional view corresponding to the III-III' cutting line shown in FIG. 9. FIG. 11a to FIG. 11c are plan views showing the planar arrangement of configurations arranged corresponding to the first layer (L1), the second layer (L2), and the third layer (L3) among the configurations shown in FIG. 9. Meanwhile, FIG. 9 to FIG. 11c show a plan and a cross-section corresponding to a portion of the first region (DA) in a display device (DD) of an embodiment and a display device (DD-1) of a different embodiment shown in FIG. 5 to FIG. 7c.

[0174] Referring to FIG. 9, the first region (DA) may include a plurality of unit regions (UA) and a boundary region (BA) between the unit regions (UA). The boundary region (BA) may be an area where the aforementioned electrode pattern (EP) overlaps.

[0175] A plurality of light-emitting diodes (LED1, LED2, LED3) are disposed in each of the unit regions (UA). The unit regions (UA) may include a first unit region (UA1) in which the first light-emitting diode (LED1) and the third light-emitting diode (LED3) overlap, and a second unit region (UA2) in which the first light-emitting diode (LED1) and the second light-emitting diode (LED2) overlap. Each of the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) is disposed on different layers, and two or more light-emitting diodes may be disposed correspondingly in each unit region (UA). The first unit region (UA1) and the second unit region (UA2) may be disposed alternately along the first direction (DR1) and the second direction (DR2), respectively.

[0176] Referring together to FIGS. 9 to 11c, a display device (DD-1) of one embodiment may include a CMOS wafer (10), a light-emitting structure layer (20), and a lens layer (30).

[0177] A CMOS wafer (10) may include a silicon substrate (101). The silicon substrate (101) may include source / drain regions and a gate that define a transistor. Shallow trench isolation (STI) regions that isolate the transistor to prevent leakage current may be defined in the silicon substrate (101).

[0178] A CMOS wafer (10) may include a contact layer (102) disposed on a silicon substrate (101). In a first region (DA), the contact layer (102) may include a plurality of contact electrodes (CTE). The contact electrodes (CTE) may be connected to source / drain regions of the silicon substrate (101). The contact electrodes (CTE) may be formed by a damascene process. The contact electrodes (CTE) may include a metal such as copper or tungsten. The contact electrodes (CTE) may include a tungsten structure, a titanium layer surrounding the sides and bottom of the tungsten structure, and a titanium nitride layer surrounding the titanium layer. Alternatively, the contact electrodes (CTE) may include a copper structure, a tantalum layer surrounding the sides and bottom of the copper structure, and a tantalum nitride layer surrounding the tantalum layer.

[0179] The contact layer (102) may include a lower insulating layer (INS-a) disposed on a silicon substrate (101). The lower insulating layer (INS-a) may include an oxide layer such as a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. Although a single layer of the lower insulating layer (INS-a) is shown, the lower insulating layer (INS-a) may be provided in multiple layers. The upper surface of the contact electrodes (CTE) may define a plane (or flat surface) identical to the upper surface of the lower insulating layer (INS-a).

[0180] The light-emitting structure layer (20) is disposed on a CMOS wafer (10) and may include a plurality of layers (L1, L2, L3). In the first region (DA), each of the plurality of layers (L1, L2, L3) may include a plurality of light-emitting diodes (LED1, LED2, LED3). Meanwhile, unlike as shown in FIG. 10, the stacking order of the first layer (L1) containing the first light-emitting diodes (LED1), the second layer (L2) containing the second light-emitting diodes (LED2), and the third layer (L3) containing the third light-emitting diodes (LED3) may be changed.

[0181] The first layer (L1) is disposed on the contact layer (102) of the CMOS wafer (10) and may include a plurality of first light-emitting diodes (LED1). The plurality of first light-emitting diodes (LED1) may be disposed corresponding to each of the first unit area (UA1) and the second unit area (UA2).

[0182] Each of the first light-emitting diodes (LED1) comprises a first light-emitting structure (SJS1) and a first insulating film (SI1-1) disposed on the side of the first light-emitting structure (SJS1). Each of the first light-emitting diodes (LED1) may further comprise a first lower conductive pattern (LE1) disposed on the lower side of the first light-emitting structure (SJS1) and a first upper conductive pattern (UE1) disposed on the upper side of the first light-emitting structure (SJS1). Each of the first light-emitting diodes (LED1) may further comprise a first additional insulating film (SI2-1) disposed on the outer side of the first insulating film (SI1-1).

[0183] The first lower conductive pattern (LE1) may be placed directly on the contact layer (102). The first lower conductive pattern (LE1) may contact each of the contact electrodes (CTE) of the contact layer (102). The first lower conductive pattern (LE1) may include at least a metal. The first lower conductive pattern (LE1) may include a metal layer. The metal layer of the first lower conductive pattern (LE1) may be provided to connect the contact electrodes (CTE) of the CMOS wafer (10) with the first lower conductive pattern (LE1). The first lower conductive pattern (LE1) may further include a transparent conductive oxide layer.

[0184] A first light-emitting structure (SJS1) is disposed on a first lower conductive pattern (LE1) and may include at least an active layer. The first light-emitting structure (SJS1) may have a planar area that is smaller than or equal to the first lower conductive pattern (LE1) disposed below it. The first light-emitting structure (SJS1) may be fully superimposed on the first lower conductive pattern (LE1). As illustrated in FIG. 10, the side of the first light-emitting structure (SJS1) may be inclined with respect to the thickness direction (DR3). The first light-emitting structure (SJS1) may not be perpendicular to the upper surface of the first lower conductive pattern (LE1). The first light-emitting structure (SJS1) may be formed by a dry etching process and may include a side that is not parallel to the thickness direction (DR3).

[0185] The first upper conductive pattern (UE1) is disposed on the first light-emitting structure (SJS1) and may include a transparent conductive oxide. The first upper conductive pattern (UE1) may be fully superimposed on the first light-emitting structure (SJS1). The first upper conductive pattern (UE1) may have a planar area that is smaller than or equal to that of the first light-emitting structure (SJS1).

[0186] The first insulating film (SI1-1) can fully cover the side of the first light-emitting structure (SJS1). By covering the side of the first light-emitting structure (SJS1), the first insulating film (SI1-1) can prevent a reduction in efficiency caused by the etching surface during the etching process for forming the first light-emitting structure (SJS1). The first insulating film (SI1-1) covers at least the side of the first light-emitting structure (SJS1) and can cover at least a portion of the first upper conductive pattern (UE1) and the first lower conductive pattern (LE1).

[0187] The first light-emitting diode (LED1) may further include a first additional insulating layer (SI2-1) disposed outside the first insulating layer (SI1-1). The first additional insulating layer (SI2-1) may completely cover the side of the first insulating layer (SI1-1). The first additional insulating layer (SI2-1) may be provided in multiple layers of two or more. The first additional insulating layer (SI2-1) covers at least the side of the first light-emitting structure (SJS1) and may cover at least a portion of the first upper conductive pattern (UE1) and the first lower conductive pattern (LE1). Although not illustrated, the first light-emitting diode (LED1) may further include a first side reflective layer (SRL1, see FIG. 8a) disposed outside the first additional insulating layer (SI2-1).

[0188] The first layer (L1) may further include first layer additional conductive patterns (AP1, AP2). The first layer additional conductive patterns (AP1, AP2) contact each of the contact electrodes (CTE) of the contact layer (102) and may be provided for electrical connection between the second light-emitting diodes (LED2) and third light-emitting diodes (LED3) placed on top and the CMOS wafer (10). The first layer additional conductive patterns (AP1, AP2) may be placed on the same layer as the first lower conductive pattern (LE1). The first layer additional conductive patterns (AP1, AP2) are formed through the same process as the first lower conductive pattern (LE1) and may include the same stacked structure and the same material. The first layer additional conductivity pattern (AP1, AP2) may include a first additional conductivity pattern (AP1) that overlaps with the second light-emitting diodes (LED2), and a second additional conductivity pattern (AP2) that overlaps with the third light-emitting diodes (LED3).

[0189] The first layer (L1) may further include a first flattening layer (INS1) disposed between each of at least the first light-emitting diodes (LED1). The first flattening layer (INS1) overlaps the unit regions (UA) and the boundary region (BA) and can fill the region where the first light-emitting diodes (LED1) are not disposed. The first flattening layer (INS1) may include an organic material. The upper surface of the first flattening layer (INS1) may define a plane (or flat surface) identical to the upper surface of the first upper conductive pattern (UE1) of the first light-emitting diodes (LED1).

[0190] The second layer (L2) is disposed on the first layer (L1) and includes a plurality of second light-emitting diodes (LED2). The plurality of second light-emitting diodes (LED2) may be disposed corresponding to the second unit area (UA2). On a unit area, the number of first light-emitting diodes (LED1) disposed may be twice the number of second light-emitting diodes (LED2) disposed. As illustrated in FIG. 10, when a unit area is defined as an area including two first unit areas (UA1) and two second unit areas (UA2), four first light-emitting diodes (LED1) and two second light-emitting diodes (LED2) may be disposed in the unit area.

[0191] Each of the second light-emitting diodes (LED2) comprises a second light-emitting structure (SJS2) and a second insulating film (SI1-2) disposed on the side of the second light-emitting structure (SJS2). Each of the second light-emitting diodes (LED2) may further comprise a second lower conductive pattern (LE2) disposed on the lower side of the second light-emitting structure (SJS2) and a second upper conductive pattern (UE2) disposed on the upper side of the second light-emitting structure (SJS2). Each of the second light-emitting diodes (LED2) may further comprise a second additional insulating film (SI2-2) disposed on the outer side of the second insulating film (SI1-2).

[0192] The second lower conductive pattern (LE2) may include a transparent conductive oxide. The second lower conductive pattern (LE2) may not include metal. Unlike the first lower conductive pattern (LE1), the second lower conductive pattern (LE2) may include only a transparent conductive oxide without including metal. The second lower conductive pattern (LE2) may include only a transparent conductive oxide so as not to block light generated from the first light-emitting diode (LED1) placed at the bottom.

[0193] The second light-emitting structure (SJS2) is disposed on the second lower conductive pattern (LE2) and may include at least an active layer. The second light-emitting structure (SJS2) may have a planar area that is smaller than or equal to the second lower conductive pattern (LE2) disposed below it. The second light-emitting structure (SJS2) may be fully superimposed on the second lower conductive pattern (LE2). As illustrated in FIG. 10, the side of the second light-emitting structure (SJS2) may be inclined with respect to the thickness direction (DR3). The second light-emitting structure (SJS2) may not be perpendicular to the upper surface of the second lower conductive pattern (LE2). The second light-emitting structure (SJS2) may be formed by a dry etching process and may include a side that is not parallel to the thickness direction (DR3).

[0194] The second upper conductive pattern (UE2) is disposed on the second light-emitting structure (SJS2) and may include a transparent conductive oxide. The second upper conductive pattern (UE2) may be fully superimposed on the second light-emitting structure (SJS2). The second upper conductive pattern (UE2) may have a planar area that is smaller than or equal to that of the second light-emitting structure (SJS2).

[0195] The second insulating film (SI1-2) can fully cover the side of the second light-emitting structure (SJS2). By covering the side of the second light-emitting structure (SJS2), the second insulating film (SI1-2) can prevent a reduction in efficiency caused by the etching surface during the etching process for forming the second light-emitting structure (SJS2). The second insulating film (SI1-2) covers at least the side of the second light-emitting structure (SJS2) and can cover at least a portion of the second upper conductive pattern (UE2) and the second lower conductive pattern (LE2).

[0196] The second light-emitting diode (LED2) may further include a second additional insulating layer (SI2-2) disposed outside the second insulating layer (SI1-2). The second additional insulating layer (SI2-2) may completely cover the side of the second insulating layer (SI1-2). The second additional insulating layer (SI2-2) may be provided in multiple layers of two or more. The second additional insulating layer (SI2-2) may cover at least the side of the second light-emitting structure (SJS2) and cover at least a portion of the second upper conductive pattern (UE2) and the second lower conductive pattern (LE2). Although not illustrated, the second light-emitting diode (LED2) may further include a second side reflective layer (SRL2, see FIG. 8b) disposed outside the second additional insulating layer (SI2-2).

[0197] The planar area of ​​each of the plurality of second light-emitting diodes (LED2) may be greater than or equal to the planar area of ​​each of the plurality of first light-emitting diodes (LED1). The planar area of ​​each of the second light-emitting structures (SJS2) included in the second light-emitting diodes (LED2) may be greater than or equal to the planar area of ​​each of the first light-emitting structures (SJS1) included in the first light-emitting diodes (LED1).

[0198] The second layer (L2) may further include a second layer additional conductivity pattern (AP3). The second layer additional conductivity pattern (AP3) may be provided for electrical connection between the third light-emitting diodes (LED3) placed on top and the CMOS wafer (10). The second layer additional conductivity pattern (AP3) may be placed on the same layer as the second lower conductivity pattern (LE2). The second layer additional conductivity pattern (AP3) is formed through the same process as the second lower conductivity pattern (LE2) and may include the same stacked structure and the same material. At least a portion of the second layer additional conductivity pattern (AP3) may overlap with the third light-emitting diodes (LED3).

[0199] The second layer (L2) may further include a second flattening layer (INS2) disposed between each of the second light-emitting diodes (LED2). The second flattening layer (INS2) overlaps the unit regions (UA) and the boundary region (BA) and can fill the region where the second light-emitting diodes (LED2) are not disposed. The second flattening layer (INS2) may include an organic material. The upper surface of the second flattening layer (INS2) may define a plane (or flat surface) identical to the upper surface of the second upper conductive pattern (UE2) of the second light-emitting diodes (LED2).

[0200] The third layer (L3) is disposed on the second layer (L2) and includes a plurality of third light-emitting diodes (LED3). The plurality of third light-emitting diodes (LED3) may be disposed corresponding to the first unit area (UA1). On a unit area, the number of first light-emitting diodes (LED1) disposed may be twice the number of third light-emitting diodes (LED3) disposed. As illustrated in FIG. 10, when a unit area is defined as an area including two first unit areas (UA1) and two second unit areas (UA2), two third light-emitting diodes (LED3) and four first light-emitting diodes (LED1) may be disposed in the unit area.

[0201] Each of the third light-emitting diodes (LED3) may include a third light-emitting structure (SJS3), a third lower conductive pattern (LE3) disposed below the third light-emitting structure (SJS3), and a third upper conductive pattern (UE3) disposed above the third light-emitting structure (SJS3).

[0202] The third lower conductive pattern (LE3) may include a transparent conductive oxide. The third lower conductive pattern (LE3) may not include metal. Unlike the first lower conductive pattern (LE1), the third lower conductive pattern (LE3) may include only a transparent conductive oxide without including metal. The third lower conductive pattern (LE3) may include only a transparent conductive oxide so as not to block light generated from the first light-emitting diode (LED1) and the second light-emitting diode (LED2) placed at the bottom.

[0203] A third light-emitting structure (SJS3) is disposed on a third lower conductive pattern (LE3) and may include at least an active layer. The third light-emitting structure (SJS3) may have a planar area that is smaller than or equal to the third lower conductive pattern (LE3) disposed below it. The third light-emitting structure (SJS3) may be fully superimposed on the third lower conductive pattern (LE3). As illustrated in FIG. 10, the side of the third light-emitting structure (SJS3) may be inclined with respect to the thickness direction (DR3). The third light-emitting structure (SJS3) may not be perpendicular to the upper surface of the third lower conductive pattern (LE3). The third light-emitting structure (SJS3) may be formed by a dry etching process and may include a side that is not parallel to the thickness direction (DR3).

[0204] The third upper conductive pattern (UE3) is disposed on the third light-emitting structure (SJS3) and may include a transparent conductive oxide. The third upper conductive pattern (UE3) may be fully superimposed on the third light-emitting structure (SJS3). The third upper conductive pattern (UE3) may have a planar area that is smaller than or equal to that of the third light-emitting structure (SJS3).

[0205] The third insulating film (SI1-3) can fully cover the side of the third light-emitting structure (SJS3). By covering the side of the third light-emitting structure (SJS3), the third insulating film (SI1-3) can prevent a reduction in efficiency caused by the etching surface during the etching process for forming the third light-emitting structure (SJS3). The third insulating film (SI1-3) covers at least the side of the third light-emitting structure (SJS3) and can cover at least a portion of the third upper conductive pattern (UE3) and the third lower conductive pattern (LE3).

[0206] The third light-emitting diode (LED3) may further include a third additional insulating layer (SI2-3) disposed outside the third insulating layer (SI1-3). The third additional insulating layer (SI2-3) may completely cover the side of the third insulating layer (SI1-3). The third additional insulating layer (SI2-3) may be provided in multiple layers of two or more. The third additional insulating layer (SI2-3) may cover at least the side of the third light-emitting structure (SJS3) and cover at least a portion of the third upper conductive pattern (UE3) and the third lower conductive pattern (LE3). Although not illustrated, the third light-emitting diode (LED3) may further include a third side reflective layer (SRL3, see FIG. 8c) disposed outside the third additional insulating layer (SI2-3).

[0207] The planar area of ​​each of the plurality of third light-emitting diodes (LED3) may be greater than or equal to the planar area of ​​each of the plurality of second light-emitting diodes (LED2). The planar area of ​​each of the third light-emitting structures (SJS3) included in the third light-emitting diodes (LED3) may be greater than or equal to the planar area of ​​each of the second light-emitting structures (SJS2) included in the second light-emitting diodes (LED2).

[0208] The third layer (L3) may further include a third flattening layer (INS3) disposed between each of at least the third light-emitting diodes (LED3). The third flattening layer (INS3) overlaps the unit regions (UA) and the boundary region (BA) and can fill the region where the third light-emitting diodes (LED3) are not disposed. The third flattening layer (INS3) may include an organic material. The upper surface of the third flattening layer (INS3) may define a plane (or flat surface) identical to the upper surface of the third upper conductive pattern (UE3) of the third light-emitting diodes (LED3).

[0209] The light-emitting structure layer (20) further includes an electrode pattern (EP), and the electrode pattern (EP) has a mesh structure on a plane. The electrode pattern (EP) may include sub-electrode patterns (EP1-S1, EP1-S2, EP1-S3) arranged corresponding to each of the plurality of layers (L1, L2, L3).

[0210] Each of the sub-electrode patterns (EP1-S1, EP1-S2, EP1-S3) can be connected to any one of the corresponding light-emitting diodes (LED1, LED2, LED3). In one embodiment, the first sub-electrode pattern (EP1-S1) disposed within the first layer (L1) is connected to the first upper conductive pattern (UE1) of the first light-emitting diodes (LED1), the second sub-electrode pattern (EP1-S2) disposed within the second layer (L2) is connected to the second upper conductive pattern (UE2) of the second light-emitting diodes (LED2), and the third sub-electrode pattern (EP1-S3) disposed within the third layer (L3) can be connected to the third upper conductive pattern (UE3) of the third light-emitting diodes (LED3). The first sub-electrode pattern (EP1-S1) can be in contact with the lower part of the first upper conductive pattern (UE1), the second sub-electrode pattern (EP1-S2) can be in contact with the lower part of the second upper conductive pattern (UE2), and the third sub-electrode pattern (EP1-S3) can be in contact with the lower part of the third upper conductive pattern (UE3).

[0211] Each of the sub-electrode patterns (EP1-S1, EP1-S2, EP1-S3) may not overlap in a plane with the first light-emitting structure (SJS1), the second light-emitting structure (SJS2), and the third light-emitting structure (SJS3), respectively. Each of the sub-electrode patterns (EP1-S1, EP1-S2, EP1-S3) may be placed overlappingly in a boundary region (BA). In the first region (DA), the sub-electrode patterns (EP1-S1, EP1-S2, EP1-S3) may not connect the light-emitting diodes (LED1, LED2, LED3) placed in each of the multiple layers (L1, L2, L3). The light-emitting diodes (LED1, LED2, LED3) placed in each of the multiple layers (L1, L2, L3) can be electrically connected by sub-electrode patterns (EP1-S1, EP1-S2, EP1-S3) placed in the second region (NDA1, see FIG. 3a).

[0212] The light-emitting structure layer (20) may further include optical layers (DBR1, DBR2). The optical layers (DBR1, DBR2) may be disposed between the first layer (L1) and the second layer (L2), and between the second layer (L2) and the third layer (L3). The optical layers (DBR1, DBR2) may include, for example, a first optical layer (DBR1) disposed between the first layer (L1) and the second layer (L2), and a second optical layer (DBR2) disposed between the second layer (L2) and the third layer (L3). Either the first optical layer (DBR1) or the second optical layer (DBR2) may be omitted.

[0213] The light-emitting structure layer (20) may further include connecting wires (CL2-1, CL3-1, CL3-2). Each of the connecting wires (CL2-1, CL3-1, CL3-2) may be provided for electrical connection between the second light-emitting diodes (LED2) and the third light-emitting diodes (LED3) and the CMOS wafer (10). Each of the connecting wires (CL2-1, CL3-1, CL3-2) may be formed by a damascene process. Each of the connecting wires (CL2-1, CL3-1, CL3-2) may include a metal such as copper or tungsten.

[0214] A second-1 connecting wire (CL2-1) may be disposed on the lower portion of each of the second light-emitting diodes (LED2). The second-1 connecting wire (CL2-1) overlaps the second light-emitting diodes (LED2) in a plane and may be provided to electrically connect the CMOS wafer (10) and the second light-emitting diodes (LED2). The second lower conductive pattern (LE2) of the second light-emitting diodes (LED2) may be electrically connected to the CMOS wafer (10) by the second-1 connecting wire (CL2-1) and the first additional conductive pattern (AP1) disposed sequentially between them.

[0215] A third connecting wire (CL3) may be disposed at the bottom of each of the third light-emitting diodes (LED3). The third connecting wire (CL3) overlaps with the third light-emitting diodes (LED3) in a plane and may be provided to electrically connect the CMOS wafer and the third light-emitting diodes (LED3). The third connecting wire (CL3) may include a third-1 connecting wire (CL3-1) disposed between the third lower conductive pattern (LE3) and the third additional conductive pattern (AP3) of the third light-emitting diodes (LED3), and a third-2 connecting wire (CL3-2) disposed between the third additional conductive pattern (AP3) and the second additional conductive pattern (AP2). The third lower conductive pattern (LE3) of the third light-emitting diodes (LED3) can be electrically connected to the CMOS wafer (10) by the third-1 connecting wire (CL3-1), the third additional conductive pattern (AP3), the third-2 connecting wire (CL3-2), and the second additional conductive pattern (AP2) arranged sequentially between them.

[0216] Each of the first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3) may have at least a portion that is non-overlapping in a plane. Each of the first light-emitting diodes (LED1) may have a portion that overlaps with the second light-emitting diodes (LED2) in a plane, and a remainder that is non-overlapping. Each of the first light-emitting diodes (LED1) may have a portion that overlaps with the third light-emitting diodes (LED3) in a plane. Each of the second light-emitting diodes (LED2) may have a portion that overlaps with the first light-emitting diodes (LED1) and the third light-emitting diodes (LED3), respectively, and a remainder that is non-overlapping. Each of the third light-emitting diodes (LED3) may have a portion that overlaps with the second light-emitting diodes (LED2) in a plane, and a remainder that is non-overlapping. Each of the first light-emitting diodes (LED1), the second light-emitting diodes (LED2), and the third light-emitting diodes (LED3) can be non-overlapping with other light-emitting diodes in the area connected to the connecting wires (CL2-1, CL3-1, CL3-2).

[0217] The lens layer (30) is disposed on the light-emitting structure layer (20) and may include a plurality of lenses (LS). The lens layer (30) may further include a passivation layer (BS-L) that provides a base surface on which the lenses (LS) are disposed. The passivation layer (BS-L) is disposed on the third layer (L3) to protect light-emitting diodes (LED1, LED2, LED3) disposed below. The passivation layer (BS-L) may include an organic material or an inorganic material.

[0218] Lenses (LS) may be arranged to overlap at least the light-emitting diodes (LED1, LED2, LED3). As illustrated in FIG. 10, lenses (LS) may be arranged corresponding to each of the first unit area (UA1) and the second unit area (UA2). One lens (LS) may be provided in each of the first unit area (UA1) and one lens may be provided in each of the second unit area (UA2). The lenses (LS) provided in the first unit area (UA1) may be arranged corresponding to one first light-emitting diode (LED1) and one third light-emitting diode (LED3), and the lenses (LS) provided in the second unit area (UA2) may be arranged corresponding to one first light-emitting diode (LED1) and one second light-emitting diode (LED2). Each of the lenses (LS) may have a circular shape in a planar shape, and the diameter of each lens (LS) may be 1 micrometer or less.

[0219] The display device according to the present embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device described above and may further include a module or device having additional functions in addition to the display device.

[0220] FIG. 12 is a block diagram of an electronic device according to one embodiment.

[0221] Referring to FIG. 12, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0222] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0223] The memory (13) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (13), an image data signal and / or an input control signal are transmitted to the display module (11), and the display module (11) can process the received signal and output image information through a display screen. The display module (11) may include a display panel that displays an image.

[0224] The power module (14) may include a power conversion module. The power conversion module can convert power supplied by a power supply module, such as a power adapter or battery device, to generate power required for the operation of the electronic device (10).

[0225] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0226] FIG. 13 is a schematic diagram of an embodiment of various electronic devices.

[0227] Referring to FIG. 13, various electronic devices including a display device according to one embodiment may include not only electronic devices for displaying images such as a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e), but also wearable electronic devices such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and automotive electronic devices (10_3) such as a CID (Center Information Display) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a car.

[0228] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the relevant technical field will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0229]

[0230]

[0231] Recent display devices, such as augmented reality devices, virtual reality devices, and video projection devices, require high resolution to provide users with new types of images, and may include micro-display devices to provide high-resolution images. A micro-display device may have a stacked structure of light-emitting diodes having multiple layers, wherein each light-emitting diode includes an insulating film covering a light-emitting structure. A display device according to one embodiment may provide insulating films made of different materials to suit the emission wavelengths of each light-emitting diode emitting light of different wavelengths, thereby improving the external quantum efficiency of each light-emitting diode and improving the display efficiency of the display device including the light-emitting diodes. Therefore, the present invention, which provides a display device according to one embodiment, has high industrial applicability.

Claims

CMOS (complementary metal oxide semiconductor) wafer; and A light-emitting structure layer disposed on the above CMOS wafer; comprising, The above light-emitting structure layer A plurality of first light-emitting diodes disposed on the above CMOS wafer and emitting light of a first wavelength; A plurality of second light-emitting diodes disposed on the CMOS wafer and emitting light of a second wavelength different from the first wavelength; and A plurality of third light-emitting diodes disposed on the CMOS wafer and emitting light of a third wavelength different from the first wavelength and the second wavelength; comprising Each of the plurality of first light-emitting diodes comprises a first light-emitting structure and a first insulating film covering the side of the first light-emitting structure, and Each of the plurality of second light-emitting diodes comprises a second light-emitting structure and a second insulating film covering the side of the second light-emitting structure, and Each of the plurality of third light-emitting diodes comprises a third light-emitting structure and a third insulating film covering the side of the third light-emitting structure, and A display device comprising at least one of the first insulating film, the second insulating film, and the third insulating film having a material different from the remaining insulating film. In paragraph 1, A display device in which the first insulating film comprises a material different from the second insulating film, and the second insulating film and the third insulating film comprise the same material. In paragraph 1, A display device in which each of the first insulating film, the second insulating film, and the third insulating film comprises different materials. In paragraph 1, The first insulating film is in contact with the side of the first light-emitting structure, and The second insulating film is in contact with the side of the second light-emitting structure, and The above third insulating film is a display device that contacts the side of the above third light-emitting structure. In paragraph 1, Each of the plurality of first light-emitting diodes further includes a first additional insulating film spaced apart from the first light-emitting structure with the first insulating film in between, and Each of the plurality of second light-emitting diodes further includes a second additional insulating film spaced apart from the second light-emitting structure with the second insulating film in between, and A display device in which each of the above plurality of third light-emitting diodes further comprises a third additional insulating film spaced apart from the third light-emitting structure with the third insulating film in between. In paragraph 1, A display device in which at least a portion of each of the plurality of first light-emitting diodes is not superimposed on the plane with the plurality of second light-emitting diodes and the plurality of third light-emitting diodes. In paragraph 1, A display device in which the first insulating material included in the first insulating film includes a high dielectric constant (High-K) material compared to the second insulating material included in the second insulating film. In Paragraph 7, A display device comprising at least one of the above-mentioned first insulating material, hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, hafnium nitrate, zirconium nitrate, tantalum nitrate, hafnium nitrate, lanthanum nitrate, and zirconium nitrate. In Paragraph 7, The above second insulating material is a display device comprising at least one of silicon oxide and aluminum oxide. In paragraph 1, A display device in which the first wavelength is shorter than the second wavelength and the third wavelength. In paragraph 1, Each of the plurality of first light-emitting diodes further includes a first lower conductive pattern disposed below the first light-emitting structure and a first upper conductive pattern disposed above the first light-emitting structure. Each of the plurality of second light-emitting diodes further includes a second lower conductive pattern disposed below the second light-emitting structure and a second upper conductive pattern disposed above the second light-emitting structure. A display device comprising each of the plurality of third light-emitting diodes further including a third lower conductive pattern disposed below the third light-emitting structure and a third upper conductive pattern disposed above the third light-emitting structure. In paragraph 1, A display device further comprising a plurality of lenses disposed on the light-emitting structure layer and overlapping at least some of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes. In paragraph 1, The above CMOS wafer is A first region in which each of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes is disposed; and A display device comprising a second region provided outside the first region on a plane. In paragraph 1, A display device in which the light-emitting structure layer further comprises a common electrode connected to at least some of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes. In paragraph 1, The above light-emitting structure layer A display device further comprising a flattening layer disposed between at least some of the plurality of first light-emitting diodes, the plurality of second light-emitting diodes, and the plurality of third light-emitting diodes. Display module; and A processor comprising at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, and a controller; and The above display module is CMOS (complementary metal oxide semiconductor) wafer; and A light-emitting structure layer disposed on the above CMOS wafer; comprising, The above light-emitting structure layer A first layer comprising a plurality of first light-emitting diodes disposed on the CMOS wafer and emitting light of a first wavelength; and A second layer comprising a plurality of second light-emitting diodes disposed on the first layer and emitting light of a second wavelength different from the first wavelength; and Each of the plurality of first light-emitting diodes comprises a first light-emitting structure and a first insulating film covering the side of the first light-emitting structure, and Each of the plurality of second light-emitting diodes comprises a second light-emitting structure and a second insulating film covering the side of the second light-emitting structure, and The first insulating film and the second insulating film are electronic devices comprising different materials. In Paragraph 16, The first insulating film is in contact with the side of the first light-emitting structure, and The second insulating film is an electronic device that contacts the side of the second light-emitting structure. In Paragraph 16, The first layer further comprises a first planarization layer disposed between at least one of the plurality of first light-emitting diodes, and The electronic device further comprising a second flattening layer disposed between each of the plurality of second light-emitting diodes, wherein the second layer is at least In Paragraph 16, An electronic device in which the first insulating material included in the first insulating film comprises a high dielectric constant (High-K) material compared to the second insulating material included in the second insulating film. In Paragraph 19, The first insulating material comprises at least one of hafnium oxide, lanthanum oxide, zirconium oxide, tantalum oxide, hafnium nitrate, zirconium nitrate, tantalum nitrate, hafnium nitride, lanthanum nitride, and zirconium nitride. The above second insulating material is an electronic device comprising at least one of silicon oxide and aluminum oxide.

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