Light-emitting substrate and display apparatus

Abstract

A light-emitting substrate, comprising a light-emitting area (A) and a bonding area (B), wherein the light-emitting area comprises a plurality of lamp areas (A10) arranged in a plurality of rows and a plurality of columns, one row comprises at least two lamp areas arranged in a first direction, and one column comprises at least two lamp areas arranged in a second direction; the bonding area is located on one side of the light-emitting area in the second direction; and the light-emitting area comprises a central area (A1) and an edge area (A2) located on at least one side of the central area, the lamp area located in the central area is a central lamp area (A110), and the lamp areas located in the edge area are edge lamp areas (A120). The light-emitting substrate further comprises a bonding portion (101), a device power signal line (131), a driving chip (30) and a plurality of light-emitting devices (20), wherein the device power signal line is connected to the bonding portion; the driving chip is disposed between two adjacent columns of lamp areas; the driving chip comprises driving pins (31); the plurality of light-emitting devices are disposed in the lamp areas; one end of each of the light-emitting devices in one lamp area is coupled to the same driving pin, and the other ends thereof are coupled to the device power signal line; and the number of a plurality of light-emitting devices in the central lamp area is not equal to the number of a plurality of light-emitting devices in the edge lamp areas.

Description

Light-emitting substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a light-emitting substrate and a display device. Background Technology

[0002] With the development of LED technology, backlights using LEDs at the sub-millimeter (micro) or even micrometer (Mini) scale have been widely adopted. This allows products using this backlight, such as liquid crystal displays (LCDs), to achieve the same contrast ratio as organic light-emitting diode (OLED) displays, while retaining the technological advantages of LCDs, thus improving display quality and providing users with a superior visual experience.

[0003] Summary of the Invention

[0004] On one hand, a light-emitting substrate is provided. The light-emitting substrate includes a light-emitting region and a bonding region. The light-emitting region includes multiple lamp areas arranged in multiple rows and columns. Each row includes at least two lamp areas arranged along a first direction, and each column includes at least two lamp areas arranged along a second direction. The second direction intersects the first direction. Along the second direction, the bonding region is located on one side of the light-emitting region. The light-emitting region includes a central region and an edge region located on at least one side of the central region. The lamp areas located in the central region are called central lamp areas, and the lamp areas located in the edge regions are called edge lamp areas.

[0005] The light-emitting substrate further includes a bonding portion, a device power signal line, a driver chip, and multiple light-emitting devices. The bonding portion is disposed in the bonding area. The device power signal line is connected to the bonding portion. The driver chip is disposed between two adjacent rows of lamp areas. The driver chip includes a driver pin. Multiple light-emitting devices are disposed in the lamp areas. Furthermore, one end of a light-emitting device in one lamp area is coupled to the same driver pin, and the other end is coupled to the device power signal line. The number of multiple light-emitting devices in the central lamp area is not equal to the number of multiple light-emitting devices in the edge lamp areas.

[0006] In some embodiments, a plurality of light-emitting devices in the central light area are connected in series to form a first light-emitting unit. A plurality of light-emitting devices in the edge light area are connected in series to form a second light-emitting unit. The number of light-emitting devices in the second light-emitting unit is less than the number of light-emitting devices in the first light-emitting unit.

[0007] In some embodiments, in the second direction, two second light-emitting units of two adjacent edge light areas are connected in series and connected to the same driving pin.

[0008] In some embodiments, the connection method of the plurality of light-emitting devices in the central light area is different from the connection method of the plurality of light-emitting devices in the edge light area.

[0009] In some embodiments, a plurality of light-emitting devices in the central light area are connected in series to form a first light-emitting unit. A plurality of light-emitting devices in the edge light area are divided into a plurality of second light-emitting units, each second light-emitting unit including at least two light-emitting devices connected in series, and the plurality of second light-emitting units are connected in parallel.

[0010] In some embodiments, in the first direction, the distance between two adjacent light-emitting devices in the central light area is a first distance, and the distance between two adjacent light-emitting devices in the edge light area is a second distance. The first distance is greater than the second distance. And / or, in the second direction, the distance between two adjacent light-emitting devices in the central light area is a third distance, and the distance between two adjacent light-emitting devices in the edge light area is a fourth distance. The third distance is greater than the fourth distance.

[0011] In some embodiments, the ratio of the first distance to the second distance is 1.2 to 1.8. And / or, the ratio of the third distance to the fourth distance is 1.2 to 1.8.

[0012] In some embodiments, the plurality of light zones include a first light zone and a second light zone, the first light zone and the second light zone are arranged along the first direction, and the light-emitting devices of the first light zone and the second light zone are connected to the same device power signal line and the same driver chip.

[0013] In some embodiments, the device power signal line includes a first trace segment, a second trace segment, and a third trace segment. The first trace segment is located on the side of the first lamp area away from the second lamp area. The second trace segment is connected to the first trace segment. Along the second direction, the second trace segment is located on one side of the first lamp area. The light-emitting device in the first lamp area is connected to either the first trace segment or the second trace segment. The third trace segment is connected to the second trace segment and is located between the first lamp area and the second lamp area. The light-emitting device in the second lamp area is connected to the third trace segment.

[0014] In some embodiments, the light-emitting substrate further includes first chip interconnects, and the driving chip is connected to the light-emitting devices in the first lamp area and the second lamp area respectively through two first chip interconnects. The first chip interconnect includes a first segment and a second segment. The first segment is located on the side of the second lamp area away from the second trace segment and is connected to the driving chip. The second segment is located on the side of the first segment closer to the second trace segment and is connected to the light-emitting device.

[0015] In some embodiments, along the first direction and from the first lamp area to the second lamp area, the last device power signal line is the target device power signal line, the second lamp area coupled to the target device power signal line is the target second lamp area, and the target second lamp area is the edge lamp area.

[0016] In some embodiments, in the target second light area, a plurality of light-emitting devices are divided into a plurality of second light-emitting units, and the plurality of second light-emitting units are arranged in multiple rows and columns, with the second light-emitting units in the same column connected in parallel. Each second light-emitting unit includes at least two light-emitting devices connected in series, and the light-emitting devices of the same second light-emitting unit are arranged along the first direction.

[0017] In some embodiments, the target device power signal line further includes a fourth trace segment located between two adjacent columns of the second light-emitting units. One end of the fourth trace segment is connected to the second trace segment, and the other end passes between the two adjacent columns of the second light-emitting units, extending to the side of the target second lamp area away from the second trace segment. From the first lamp area towards the target second lamp area, the first column of the second light-emitting units is connected to the third trace segment, and the remaining second light-emitting units are connected to the fourth trace segment.

[0018] In some embodiments, the first chip connection line connecting the driver chip to the light-emitting device of the target second lamp area is a target chip connection line. The target chip connection line further includes a third sub-segment located between two adjacent columns of second light-emitting units. One end of the third sub-segment is connected to the first sub-segment, and the other end passes between two adjacent columns of second light-emitting units, extending to the side of the target second lamp area away from the first sub-segment. In the target second lamp area, pointing from the first lamp area to the second lamp area, the last column of second light-emitting units is connected to the second sub-segment, and the remaining second light-emitting units are connected to the third sub-segment.

[0019] In some embodiments, the target device power signal line further includes a fifth trace segment and a sixth trace segment. The fifth trace segment is connected to the third trace segment and is located on the side of the target second lamp area away from the second trace segment. Two sixth trace segments are located between two adjacent columns of second light-emitting units, with their ends facing each other. The two sixth trace segments extend from both sides of the target second lamp area to between two adjacent rows of second light-emitting units. One sixth trace segment is connected to the second trace segment, and the other sixth trace segment is connected to the fifth trace segment. In the target second lamp area, pointing from the first lamp area to the second lamp area, the first column of second light-emitting units is connected to the third trace segment, and the remaining second light-emitting units are connected to the sixth trace segment.

[0020] In some embodiments, the first chip connection line connecting the driver chip to the light-emitting device of the target second lamp area is a target chip connection line. The target chip connection line further includes a fourth sub-segment and a fifth sub-segment. The fourth sub-segment is connected to the second sub-segment and is located between two adjacent rows of second light-emitting units. Two fifth sub-segments are located between two adjacent columns of second light-emitting units and are connected to the fourth sub-segment on both sides of the fourth sub-segment. In the target second lamp area, pointing from the first lamp area to the second lamp area, the last column of second light-emitting units is connected to the second sub-segment, and the remaining second light-emitting units are connected to the fifth sub-segment.

[0021] In some embodiments, in the second direction, the distance between two adjacent light-emitting devices in the central light area is a third distance, and the distance between two adjacent light-emitting devices in the edge light area is a fourth distance. The third distance is greater than the fourth distance. The routing length of the third segment of the power signal line of the target device is a fifth distance, and the routing length of the third segment of the remaining power signal lines of the other devices is a sixth distance. The difference between the third distance and the fourth distance is a first difference. The difference between the fifth distance and the sixth distance is a second difference. The ratio of the first difference to the second difference is 1.8 to 2.2.

[0022] In some embodiments, the trace segment connecting the device power signal line to the light-emitting device in the second lamp area is the first target trace segment, and the sub-segment connecting the first chip connection line to the light-emitting device in the second lamp area is the first target sub-segment. The first target trace segment and the first target sub-segment are arranged along the first direction.

[0023] In some embodiments, the plurality of light zones includes a third light zone, which is the row of light zones closest to or furthest from the binding area among the plurality of multi-row, multi-column light zones. The third light zone is the edge light zone.

[0024] In some embodiments, the plurality of light-emitting devices in the third lamp area are divided into a plurality of second light-emitting units, which are connected in parallel and arranged along the first direction. Each second light-emitting unit includes at least two light-emitting devices, and the light-emitting devices in the same second light-emitting unit are arranged along the second direction.

[0025] In some embodiments, the device power signal line includes a first trace segment and a second trace segment. Along the first direction, the first trace segment is located on one side of the third lamp area. The second trace segment is connected to the first trace segment. Along the second direction, the second trace segment is located on the side of the third lamp area away from the bonding area. The light-emitting device in the third lamp area is connected to the second trace segment.

[0026] In some embodiments, the light-emitting substrate further includes a second chip connection line, which includes a sixth segment and a seventh segment. The sixth segment is located on the side of the third lamp area away from the first trace segment and is connected to the driving chip. The seventh segment is located on the side of the third lamp area closer to the bonding area and is connected to the light-emitting device.

[0027] In some embodiments, the second trace segment and the seventh sub-segment are arranged along the second direction.

[0028] In some embodiments, along the first direction and pointing from the first line segment to the corresponding third light area, in the last column of light areas, apart from the third light area, the remaining light areas are target second light areas. The multiple light-emitting devices of the target second light area are divided into multiple second light-emitting units. The multiple second light-emitting units are connected in parallel, and the second light-emitting unit includes at least two light-emitting devices connected in series. The light-emitting devices of the same second light-emitting unit are arranged along the first direction.

[0029] In some embodiments, at least one of the driving chips is connected to a light-emitting device in a third lamp zone, a target second lamp zone, and a central lamp zone.

[0030] In some embodiments, in the first direction, the distance between two adjacent light-emitting devices in the central light area is a first distance, and the distance between two adjacent light-emitting devices in the edge light area is a second distance. The first distance is greater than the second distance.

[0031] Along the first direction, pointing from the first trace segment to the corresponding third light zone, the last of the third light zones is the target third light zone. In the target third light zone, the trace length of the second trace segment is a seventh distance; in other third light zones, the trace length of the second trace segment is an eighth distance. The difference between the first distance and the second distance is a third difference. The difference between the seventh distance and the eighth distance is a fourth difference. The ratio of the third difference to the fourth difference is 1.5 to 2.

[0032] In some embodiments, in the edge light area, in the first direction, the line connecting the centers of two adjacent light-emitting devices forms an acute angle with the first direction. And / or, in the second direction, the line connecting the centers of two adjacent light-emitting devices forms an acute angle with the second direction.

[0033] In some embodiments, the plurality of driver chips are arranged in multiple rows and columns along the first direction and the second direction. Along the first direction, the plurality of driver chips are divided into multiple driver chip groups, and each driver chip group includes two driver chips arranged symmetrically.

[0034] In some embodiments, the light-emitting substrate further includes multiple ground signal lines connected to the bonding portion. Along the first direction, the device power signal lines and the ground signal lines are arranged alternately. Two driver chips from the same driver chipset are connected to the same ground signal line.

[0035] In some embodiments, the driving chip includes two ground pins, and the light-emitting substrate further includes multiple ground signal lines. The multiple ground signal lines are spaced apart along the first direction and connected to the bonding portion. Each ground signal line includes a first main trace segment and a ground connection line. The two ground pins are connected to the first main trace segment through two ground connection lines.

[0036] In some embodiments, a plurality of the driver chips are arranged in multiple rows and columns along the first direction and the second direction, and the driver chips include address input pins and data input pins.

[0037] The light-emitting substrate further includes address signal lines and data signal lines. A row of address input pins of the driver chip is connected to the bonding portion via the address signal lines. The address signal lines overlap with the driver chip. A row of data input pins of the driver chip is connected to the bonding portion via the data signal lines. The data signal lines overlap with the driver chip.

[0038] In some embodiments, the driver chip includes a power input pin and a power output pin, and the light-emitting substrate further includes a driving power signal line and a cascading line. The power input pin of the driver chip closest to the bonding region is connected to the bonding portion via the driving power signal line. Along the second direction, in two adjacent driver chips, the power output pin of the driver chip closer to the bonding region is connected to the power input pin of the driver chip farther from the bonding region via the cascading line. At least one of the address signal line, the data signal line, and the driving power signal line overlaps with the row of lamps closest to the bonding region.

[0039] In some embodiments, a plurality of the driving chips are arranged in multiple rows and columns along the first and second directions. In the same column, two adjacent driving chips are cascaded, and the row of driving chips closest to the bonding area is connected to the bonding portion. Each driving chip includes multiple pins, and at least one pin in the row of driving chips furthest from the bonding area is floating. The light-emitting substrate also includes redundant traces connected to the floating pins.

[0040] In some embodiments, the light-emitting substrate further includes device connection lines, through which a plurality of light-emitting devices in the lamp area are connected in series. The device connection lines include a second main trace segment and a device pad portion, the device pad portion being disposed at one end of the second main trace segment and being narrower than the second main trace segment.

[0041] On the other hand, a light-emitting substrate is provided. The light-emitting substrate includes a light-emitting region and a bonding region. The light-emitting region includes multiple lamp areas arranged in multiple rows and columns. Each row includes at least two lamp areas arranged along a first direction, and each column includes at least two lamp areas arranged along a second direction. The second direction intersects the first direction. Along the second direction, the bonding region is located on one side of the light-emitting region. The light-emitting region includes a central region and an edge region located on at least one side of the central region. The lamp areas located in the central region are called central lamp areas, and the lamp areas located in the edge regions are called edge lamp areas.

[0042] The light-emitting substrate further includes a bonding portion, a device power signal line, a driver chip, and multiple light-emitting devices. The bonding portion is disposed in the bonding area. The device power signal line is connected to the bonding portion. The driver chip is disposed between two adjacent rows of lamp areas. The driver chip includes a driver pin. Multiple light-emitting devices are disposed in the lamp areas. Furthermore, one end of a light-emitting device in one lamp area is coupled to the same driver pin, and the other end is coupled to the device power signal line. The connection method of the multiple light-emitting devices in the central lamp area differs from the connection method of the multiple light-emitting devices in the edge lamp areas.

[0043] In another aspect, a display device is provided. The display device includes a light-emitting substrate and a circuit board as described in the above embodiments, wherein the circuit board is connected to a bonding portion of the light-emitting substrate. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0045] Figure 1 is a structural diagram of a display device according to some embodiments;

[0046] Figure 2 is a structural diagram of another display device according to some embodiments;

[0047] Figure 3 is a cross-sectional view along section line AA' in Figure 1;

[0048] Figure 4 is a cross-sectional view along section line BB' in Figure 1;

[0049] Figure 5 is a top view of a light-emitting substrate according to some embodiments;

[0050] Figure 6A is an enlarged view of a device pad assembly of a light-emitting substrate according to some embodiments;

[0051] Figure 6B is an enlarged view of another device pad assembly of a light-emitting substrate according to some embodiments;

[0052] Figure 7A is an enlarged view of a chip pad assembly of a light-emitting substrate according to some embodiments;

[0053] Figure 7B is an enlarged view of another chip pad assembly of a light-emitting substrate according to some embodiments;

[0054] Figure 8 is an enlarged view of multiple lamp zones of a light-emitting substrate according to some embodiments;

[0055] Figure 9 is an enlarged view of multiple lamp areas of another light-emitting substrate according to some embodiments;

[0056] Figure 10 is an enlarged view of multiple lamp areas of another light-emitting substrate according to some embodiments;

[0057] Figure 11 is an enlarged view of multiple lamp zones of another light-emitting substrate according to some embodiments;

[0058] Figure 12 is an enlarged view of multiple lamp zones of another light-emitting substrate according to some embodiments;

[0059] Figure 13A is an enlarged view of an adjacent central lamp area and an edge lamp area of ​​a light-emitting substrate according to some embodiments;

[0060] Figure 13B is an enlarged view of an adjacent central lamp area and an edge lamp area of ​​another light-emitting substrate according to some embodiments;

[0061] Figure 13C is an enlarged view of an adjacent central lamp area and an edge lamp area of ​​another light-emitting substrate according to some embodiments;

[0062] Figure 14A is an enlarged view of two adjacent central lamp areas of a light-emitting substrate according to some embodiments;

[0063] Figure 14B is an enlarged view of two adjacent central lamp areas of another light-emitting substrate according to some embodiments;

[0064] Figure 15 is an enlarged view of two adjacent third lamp areas of a light-emitting substrate according to some embodiments;

[0065] Figure 16 is an enlarged view of multiple lamp zones of another light-emitting substrate according to some embodiments;

[0066] Figure 17 is a cross-sectional view along section line CC' in Figure 16;

[0067] Figure 18 is a cross-sectional view along section line DD' in Figure 8. Detailed Implementation

[0068] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0069] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0070] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0071] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0072] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0073] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0074] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0075] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0076] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0077] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0078] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0079] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0080] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0081] As shown in FIG1, some embodiments of the present disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0082] For example, referring to Figures 1 and 2, the display device 1000 can be any product or component with display function, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), in-vehicle display, in-flight display, navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, extended reality (XR) device, etc.

[0083] For example, as shown in Figure 1, the display device 1000 can be a portable display product; for example, the display device 1000 can be a mobile phone as shown in Figure 1. As another example, referring to Figure 2, the display device 1000 can be a wearable device; for example, the display device 1000 can be a watch as shown in Figure 2.

[0084] It should be noted that the shape of the display surface of the display device 1000 is not unique depending on the application scenario. The shape of the display surface of the display device 1000 can be any of the following: circular, elliptical, or polygonal. This embodiment of the present disclosure does not impose any specific limitation.

[0085] In some embodiments, referring to FIG3, the display device 1000 includes a light-emitting substrate 100, a housing 200 and a cover plate 300, wherein the light-emitting substrate 100 may be disposed within the housing 200.

[0086] For example, as shown in FIG3, the housing 200 can be a box-shaped structure with an opening, the light-emitting substrate 100 is disposed inside the housing 200, and the cover plate 300 is disposed on the light-emitting side of the light-emitting substrate 100 and located at the opening of the housing 200.

[0087] It should be noted that the light-emitting substrate 100 has a light-emitting side and a non-light-emitting side. The light-emitting side refers to the side of the light-emitting substrate 100 that can emit light (the upper side of the light-emitting substrate 100 in Figure 3), and the non-light-emitting side refers to the other side opposite to the light-emitting side (the lower side of the light-emitting substrate 100 in Figure 3).

[0088] In some embodiments, referring to Figures 3 and 4, the display device 1000 further includes a plurality of optical films 400 disposed on the light-emitting side of the light-emitting substrate 100. Light emitted from the light-emitting substrate 100 is emitted after passing through the optical films 400. It should be noted that the optical films 400 perform modulation of the emission wavelength and / or modulation of the propagation direction of the light emitted from the light-emitting substrate 100.

[0089] As shown in Figure 4, the light-emitting substrate 100 can directly emit white light, which is then emitted after its propagation direction is modulated by multiple optical films 400. Alternatively, the light-emitting substrate 100 can also emit light of other colors (e.g., blue light), which is then emitted after its wavelength and / or propagation direction are modulated by multiple optical films 400.

[0090] Referring, as exemplarily to FIG4, a plurality of optical films 400 include a scattering layer 410, a color conversion layer 420, a diffuser 430, and a composite film 440. The scattering layer 410, color conversion layer 420, diffuser 430, and composite film 440 may be sequentially disposed close to the light-emitting substrate 100. That is, the diffuser 430 may be disposed on the light-emitting side of the light-emitting substrate 100, the composite film 440 may be disposed on the side of the diffuser 430 away from the light-emitting substrate 100, and the scattering layer 410 and color conversion layer 420 may be disposed on the side of the diffuser 430 close to the light-emitting substrate 100.

[0091] The scattering layer 410 blurs the light emitted from the light-emitting substrate 100 and provides support for the color conversion layer 420, the diffuser 430, and the composite film 440. The color conversion layer 420, when excited by light of a certain color emitted from the light-emitting substrate 100, converts that light into white light, thereby improving the utilization rate of the light energy of the light-emitting substrate 100. The diffuser 430 homogenizes the light passing through it. The composite film 440 enhances the light extraction efficiency of the light-emitting substrate 100, thereby increasing the display brightness of the display device 1000.

[0092] It should be noted that the composite film 440 may include a brightness enhancement film (BEF) and a reflective polarized brightness enhancement film (DBEF), which utilizes the principles of total internal reflection, refraction and polarization to increase the light flux within a certain angle range, thereby improving the brightness of the display device 1000.

[0093] For example, as shown in Figure 4, the light-emitting substrate 100 emits blue light. The color conversion layer 420 may include red quantum dot material, green quantum dot material, and a transparent material. When the blue light emitted by the light-emitting substrate 100 passes through the red quantum dot material, it is converted into red light; when the blue light passes through the green quantum dot material, it is converted into green light; the blue light can pass directly through the transparent material. Then, the blue, red, and green light are mixed and superimposed in a certain proportion to produce white light. Finally, the scattering layer 410 and the diffuser 430 can modulate the incident light from different propagation directions and emit it in a more uniform state, thereby improving the light shadow produced by the light-emitting substrate 100 and improving the display quality of the display device 1000.

[0094] In some embodiments, referring to FIG3, the display device 1000 may further include a circuit board 500, which may be connected to an end of the light-emitting substrate 100 and bent to the non-light-emitting side of the light-emitting substrate 100 to provide display control signals to the light-emitting substrate 100.

[0095] For example, referring to FIG5, the light-emitting substrate 100 has a light-emitting region A and a bonding region B, and the bonding region B is located on one side of the light-emitting region A along the second direction Y. The light-emitting region A can be configured to house the light-emitting device 20, and the bonding region B can be configured to house the bonding part 101.

[0096] In some embodiments, as shown in FIG3 and FIG5, the light-emitting substrate 100 includes a driving backplate 10 and a bonding portion 101 located in the bonding region B. The bonding portion 101 includes a plurality of bonding pins 12. The circuit board 500 is connected to the bonding pins 12 so that the circuit board 500 is connected to the driving backplate 10.

[0097] In some embodiments, as shown in Figures 3 and 5, the light-emitting substrate 100 includes a driving backplate 10, a light-emitting device 20 located in the light-emitting region A, and a driving chip 30. The light-emitting device 20 and the driving chip 30 are disposed on the driving backplate 10 and connected to the driving backplate 10 to receive driving signals and drive the light-emitting device 20 to emit light.

[0098] It should be noted that the light-emitting device 20 may include Micro LED and / or Mini LED. The size (e.g., length) of the Micro LED is less than 50 micrometers, for example, 10 micrometers to 50 micrometers. The size (e.g., length) of the Mini LED is 50 micrometers to 150 micrometers, for example, 80 micrometers to 120 micrometers.

[0099] For example, referring to Figures 5, 6A and 6B, the light-emitting substrate 100 includes a device pad group 110, which includes two device pad portions 142, namely an anode pad 111 and a cathode pad 112. The light-emitting device 20 includes an anode pin 211 and a cathode pin 212. The anode pin 211 is connected to the anode pad 111, and the cathode pin 212 is connected to the cathode pad 112, so that the light-emitting device 20 is fixed on the driving backplate 10.

[0100] Furthermore, the light-emitting substrate 100 also includes alignment marks 180, which can be disposed on both sides of the device pad group 110 to facilitate the alignment and connection of the light-emitting device 20 with the device pad group 110. Additionally, one of the two alignment marks 180 disposed on both sides of the device pad group 110 can be electrically connected to the anode pad 111, and the other can be electrically connected to the cathode pad 112. Thus, during the lighting test of the light-emitting substrate 100, the alignment marks 180 can also serve as test points on the light-emitting substrate 100, and the test probes of the testing equipment can abut against the alignment marks 180 to perform the test.

[0101] For example, referring to Figures 5, 7A, and 7B, the light-emitting substrate 100 further includes a chip pad group 120, and the driver chip 30 includes a plurality of pins 3, which are connected to the chip pad group 120. For example, the driver chip 30 includes a driver pin 31, a ground pin 32, an address input pin 33, a data input pin 34, a power input pin 35, a power output pin 36, a data output pin 37, and an address output pin 38.

[0102] At this time, the chip pad group 120 includes a driver pad 121, a ground pad 122, an address input pad 123, a data input pad 124, a power input pad 125, a power output pad 126, a data output pad 127, and an address output pad 128. The driver pin 31, the ground pin 32, the address input pin 33, the data input pin 34, the power input pin 35, the power output pin 36, the data output pin 37, and the address output pin 38 are respectively connected to the driver pad 121, the ground pad 122, the address input pad 123, the data input pad 124, the power input pad 125, the power output pad 126, the data output pad 127, and the address output pad 128.

[0103] It should be noted that the alignment mark 180 can also be set on both sides of the chip pad group 120 to facilitate the alignment and connection between the driver chip 30 and the chip pad group 120.

[0104] To more clearly and concisely illustrate the embodiments of this disclosure, the pins 3 of the driver chip 30 in the following description are directly connected to the circuit traces of the light-emitting substrate 100 via the device pad group 110.

[0105] In some embodiments, referring to FIG7B and FIG8, the light-emitting substrate 100 includes a plurality of signal lines 130, which include a device power signal line 131, a ground signal line 132, an address signal line 133, a data signal line 134, and a drive power signal line 135.

[0106] One end of the light-emitting device 20 is coupled to a driving pin 31, and the other end is coupled to a device power signal line 131. The ground signal line 132, address signal line 133, data signal line 134, and driving power signal line 135 can be connected to the ground pin 32, address input pin 33, data input pin 34, and power input pin 35 of the driving chip 30 through the ground pad 122, address input pad 123, data input pad 124, and power input pad 125, respectively.

[0107] The width of the signal line 130 is 100μm to 1000μm. For example, the width of the signal line 130 is any one of 100μm, 200μm, 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, and 1000μm. For instance, the width of the device power signal line 131 is 120μm to 150μm, such as any one of 120μm, 130μm, 135μm, 140μm, 145μm, and 150μm. For example, the width of the ground signal line 132 is 950μm to 1000μm, and the width of the device power signal line 131 is any one of 950μm, 960μm, 975μm, 985μm, 990μm and 1000μm.

[0108] In some embodiments, referring to FIG5, the driver chips 30 can be arranged in multiple rows and columns, with each row including at least two driver chips 30 arranged along a first direction X, and each column including at least two driver chips 30 arranged along a second direction Y. The second direction Y intersects the first direction X, such as the second direction Y being perpendicular to the first direction X.

[0109] Based on this, the ground signal line 132, address signal line 133, data signal line 134 and drive power signal line 135 can be connected to the ground pins 32, address input pins 33, data input pins 34 and power input pins 35 of a row of driver chips 30 through the ground pad 122, address input pad 123, data input pad 124 and power input pad 125 respectively.

[0110] Alternatively, referring to Figures 7B and 8, in the same column of driver chips 30, at least one set of pins 3 of two adjacent driver chips 30 are cascaded. That is, in the second direction Y, in two adjacent driver chips 30, address input pin 33 and address output pin 38 are cascaded, or data input pin 34 and data output pin 37 are cascaded, or power input pin 35 and power output pin 36 are cascaded.

[0111] As exemplarily shown in Figures 7B and 8, the address input pins 33 of a row of driver chips 30 are all connected to the bonding portion 101 via address signal lines 133. The data input pins 34 of a row of driver chips 30 are all connected to the bonding portion 101 via data signal lines 134. Furthermore, the power input pin 35 of the driver chip 30 closest to the bonding area B is connected to the bonding portion 101 via a power signal line 135.

[0112] Based on this, the light-emitting substrate 100 also includes a cascade line 170. Along the second direction Y, the power output pin 36 of the driver chip 30 that is closer to the bonding region B is connected to the power input pin 35 of the driver chip 30 that is farther away from the bonding region B through the cascade line 170.

[0113] At this time, referring to Figure 8, the address signal line 133 and the data signal line 134 can pass through the middle of the chip pad group 120. That is, the address signal line 133 can overlap with the driver chip 30, and the data signal line 134 can overlap with the driver chip 30, so that the wiring of the signal line 130 is more compact, thereby improving the space utilization on the light-emitting substrate 100 and helping to reduce the area of ​​the light-emitting substrate 100.

[0114] It should be understood that when at least one set of pins 3 of two adjacent driver chips 30 are cascaded, at least one pin 3 of the row of driver chips 30 furthest from the bonding area B is floating. The floating pin 3 is connected to the pads of the chip pad group 120, but is not connected to other circuit structures. After the pin 3 is connected to the pads of the chip pad group 120, it is still in an open circuit state.

[0115] Referring to Figures 7A, 7B, and 8, the light-emitting substrate 100 also includes redundant traces 160, which are connected to the floating pins 3 via the pads of the chip pad group 120. The length of the redundant traces 160 is greater than or equal to 600 μm, ensuring that the die-bonding environment of each pin 3 is consistent with that of the pads in the chip pad group 120, resulting in similar heat dissipation rates and reducing the risk of poor soldering.

[0116] For example, as shown in Figures 7B and 8, in two adjacent driver chips 30, if the power output pin 36 of the driver chip 30 closer to the bonding area B is connected to the power input pin 35 of the driver chip 30 farther from the bonding area B through the cascading line 170, the power output pin 36 of the row of driver chips 30 furthest from the bonding area B is floating, and the redundant trace 160 is connected to the power output pin 36.

[0117] In some embodiments, referring to Figures 7A, 7B, and 8, the driver chip 30 includes two ground pins 32, and the ground signal line 132 includes a first main trace segment 1321 and a ground connection line 1322. The first main trace segment 1321 is connected to the bonding pin 12 of the bonding portion 101. Furthermore, the two ground pins 32 are respectively connected to the first main trace segment 1321 via two ground connection lines 1322. This ensures that the die bonding process of the ground pins 32 and the ground pad 122 is consistent with the die bonding process of the other pins 3 of the driver chip 30 and the other pads of the chip pad group 120, resulting in similar heat dissipation rates and reducing the risk of poor soldering.

[0118] In some embodiments, referring to FIG8, at least one of the address signal line 133, the data signal line 134 and the drive power signal line 135 overlaps with at least one row lamp area A10 closest to the bonding area B. This can reduce the border of the light-emitting area A of the light-emitting substrate 100 on the side close to the bonding area B, which is beneficial to the narrow border design of the light-emitting substrate 100.

[0119] For example, as shown in FIG8, both the address signal line 133 and the data signal line 134 overlap with the row lamp area A10 closest to the bonding area B, so as to reduce the border of the light-emitting area A of the light-emitting substrate 100 near the bonding area B. At this time, the light-emitting substrate 100 includes two conductive layers 70 (see FIG18), which can be referred to below for details. The embodiments disclosed herein will not be described in detail here.

[0120] In some embodiments, referring to FIG9, multiple device power signal lines 131 are spaced apart along a first direction X, and multiple ground signal lines 132 are spaced apart along a first direction X.

[0121] As shown in Figure 9, along the first direction X, multiple driver chips 30 are divided into multiple driver chip groups 310, and each driver chip group 310 includes two driver chips 30 symmetrically arranged. In this case, the two driver chips 30 in the same driver chip group 310 can be connected to the same ground signal line 132, and along the first direction X, the device power signal line 131 and the ground signal line 132 are arranged alternately. This reduces the number of ground signal lines 132, simplifies the circuit, and lowers manufacturing costs.

[0122] In some embodiments, as shown in Figures 7B, 8, and 9, a driver chip 30 includes one or more driver pins 31, each of which can be connected to multiple light-emitting devices 20. Figure 8 illustrates an example of a driver chip 30 including four driver pins 31. In this case, the light-emitting area A can be divided into multiple lamp areas A10 according to the arrangement of the multiple light-emitting devices 20 connected to the same driver pin 31.

[0123] Furthermore, as shown in Figures 8 and 9, each lamp area A10 may include multiple light-emitting devices 20 connected in series and / or in parallel. For example, the light-emitting substrate 100 also includes device connection lines 140 and chip connection lines 150. Multiple light-emitting devices 20 in lamp area A10 are connected in series through device connection lines 140 to form a light-emitting unit 40. One end of the light-emitting unit 40 is connected to the device power signal line 131, and the other end is connected to the driver chip 30 through the chip connection line 150. Figure 8 illustrates an example where some lamp areas A10 include one light-emitting unit 40, and some lamp areas A10 include two light-emitting units 40. Figure 9 illustrates an example where all lamp areas A10 include only one light-emitting unit 40.

[0124] It should be noted that the spacing between two adjacent circuit traces, such as device connection lines 140, chip connection lines 150, cascade lines 170, and various signal lines 130, is 10μm to 100μm. For example, the spacing between two adjacent circuit traces can be any of 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, and 100μm.

[0125] Based on this, referring to Figures 6A and 6B, the device connection line 140 may include a second main trace segment 141 and a device pad portion 142. The device pad portion 142 is located at one end of the second main trace segment 141 and is narrower than the second main trace segment 141. That is, the average width of the second main trace segment 141 is greater than the average width of the device pad portion 142. This can reduce the flow of solder (such as solder paste) and reduce the risk of rotation and displacement of the light-emitting device 20.

[0126] For example, as shown in Figure 6B, the device pad portion 142 can be rectangular, and the end of the second main trace segment 141 forms a T-shape with the device pad portion 142. Alternatively, as shown in Figure 6A, the device pad portion 142 can be an isosceles trapezoid, and the long side of the trapezoid is connected to the end of the second main trace segment 141.

[0127] In some embodiments, as shown in FIG9, a plurality of light-emitting devices 20 in a light area A10 may be arranged in multiple rows and columns, with each row including at least two light-emitting devices 20 arranged along a first direction X and each row including at least two light-emitting devices 20 arranged along a second direction Y.

[0128] Based on this, multiple light-emitting devices 20 within a light area A10 can be connected in an S-shape. Furthermore, along the second direction Y, the multiple light-emitting devices 20 can be located on one side of the connected driver chip 30. In this case, the further away a row of light-emitting devices 20 is from the driver chip 30, the longer the trace length in the first direction X can be. This arrangement helps improve the uniformity of the thickness of the conductive layer 70 mentioned below, thus stabilizing the resistance of the circuit traces included in the conductive layer 70.

[0129] In some embodiments, as shown in Figures 5 and 10, the light-emitting area A may include multiple light areas A10, which are arranged in multiple rows and columns in an array. A row includes at least two light areas A10 arranged along a first direction X, and a column includes at least two light areas A10 arranged along a second direction Y.

[0130] One driver chip 30 can be disposed between two adjacent rows of lamp zones A10. The driver chip 30 includes multiple driver pins 31, which can be connected to the light-emitting devices 20 of multiple lamp zones A10 respectively, so as to drive the light-emitting devices 20 of multiple lamp zones A10 to emit light. Figures 5 and 10 illustrate the example of the driver chip 30 driving four lamp zones A10.

[0131] In some embodiments, as shown in FIG5, the light-emitting area A includes a central area A1 and an edge area A2 located at least on one side of the central area A1. The light area A10 located in the central area A1 is the central light area A110, and the light area A10 located in the edge area A2 is the edge light area A120. FIG5 shows an example where the edge area A2 is located on the right side of the central area A1.

[0132] Among them, the edge area A2 is, for example, at least one row and / or at least one column of light areas A10 located at the outermost edge of a plurality of light areas A10 arranged in an array.

[0133] For example, the display device 1000 includes a light-emitting substrate 100, meaning the display device 1000 is not a splicing display device. In this case, the edge region A2 surrounds the central region A1.

[0134] For example, the display device 1000 includes a plurality of light-emitting substrates 100, that is, the display device 1000 is a splicing display device. In this case, among the light-emitting substrates 100 located at the edge of the splicing display device, the edge region A2 is located on the side of the center region A1 close to the corresponding edge. For example, the display device 1000 includes a plurality of light-emitting substrates 100 arranged in multiple rows and columns, and the light-emitting substrate 100 in FIG5 can be one of the light-emitting substrates 100 in the lower right corner of the splicing display device.

[0135] In some embodiments, as shown in FIG5, the number of multiple light-emitting devices 20 in the central light area A110 is not equal to the number of multiple light-emitting devices 20 in the edge light area A120, in order to compensate for the voltage drop difference between the multiple light-emitting devices 20 in the central light area A110 and the multiple light-emitting devices 20 in the edge light area A120, thereby increasing the brightness of the edge area A2 and improving the brightness uniformity of the light-emitting substrate 100.

[0136] Furthermore, referring to Figures 5 and 9, in the central area A1, along the first direction X, the light-emitting devices 20 of two adjacent lamp areas A10, i.e., the circuit traces, can be arranged symmetrically, so that the circuit layout of the light-emitting substrate 100 is more regular, which is convenient for inspection and maintenance, and helps to simplify the circuit (such as sharing a ground signal line 132) and reduce the manufacturing cost.

[0137] In some embodiments, as shown in FIG10, in the first direction X, the distance between two adjacent light-emitting devices 20 in the central light area A110 is a first distance L1, and the distance between two adjacent light-emitting devices 20 in the edge light area A120 is a second distance L2; the first distance L1 is greater than the second distance L2. And / or, in the second direction Y, the distance between two adjacent light-emitting devices 20 in the central light area A110 is a third distance L3, and the distance between two adjacent light-emitting devices 20 in the edge light area A120 is a fourth distance L4; the third distance L3 is greater than the fourth distance L4. In this case, the distribution density of light-emitting devices 20 in the central light area A110 is less than the distribution density of light-emitting devices 20 in the edge light area A120, which can improve the brightness of the edge area A2, thereby improving the brightness uniformity of the light-emitting substrate 100.

[0138] The ratio of the first distance L1 to the second distance L2 is 1.2 to 1.8, for example, the ratio of the first distance L1 to the second distance L2 is any one of 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, and 1.8. And / or, the ratio of the third distance L3 to the fourth distance L4 is 1.2 to 1.8, for example, the ratio of the third distance L3 to the fourth distance L4 is any one of 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, and 1.8.

[0139] For example, the first distance L1 is 3mm to 6mm, for example, the first distance L1 is 3.72mm to 5.58mm, such as any one of 3mm, 3.5mm, 3.72mm, 4mm, 4.5mm, 4.65mm, 4.68mm, 5mm, 5.58mm and 6mm.

[0140] For example, the second distance L2 is 2mm to 4mm, for example, the second distance L2 is 2.4mm to 3.6mm, such as any one of 2mm, 2.4mm, 2.6mm, 3mm, 3.2mm, 3.5mm, 3.6mm, 3.8mm and 4mm.

[0141] Furthermore, referring to Figure 13A, in the central light area A110, the minimum distance between the multiple light-emitting devices 20 is the ninth distance L9; in the edge light area A120, the minimum distance between the multiple light-emitting devices 20 is the tenth distance L10. The ratio of the ninth distance L9 to the tenth distance L10 can be 1.2 to 1.8, for example, the ratio of the ninth distance L9 to the tenth distance L10 is any one of 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, and 1.8.

[0142] In some embodiments, referring to Figures 11 and 12, multiple light-emitting devices 20 in the central light area A110 are connected in series to form a first light-emitting unit 41. Multiple light-emitting devices 20 in the edge light area A120 are connected in series to form a second light-emitting unit 42. The number of light-emitting devices 20 in the second light-emitting unit 42 is less than the number of light-emitting devices 20 in the first light-emitting unit 41. Thus, compared to the central light area A110, the edge light area A120 has fewer light-emitting devices 20 connected in series, resulting in a lower total resistance in the second light-emitting unit 42 and a larger current flowing through the light-emitting devices 20. This increases the brightness of each light-emitting device 20, thereby improving the brightness of the edge area A2 and enhancing the brightness uniformity of the light-emitting substrate 100.

[0143] For example, referring to Figures 11 and 12, the first light-emitting unit 41 includes four light-emitting devices 20 connected in series, and the second light-emitting unit 42 includes two light-emitting devices 20 connected in series. Of course, the first light-emitting unit 41 may also include five, six or more light-emitting devices 20, and the second light-emitting unit 42 may also include two, three or more light-emitting devices 20. The embodiments of this disclosure are not limited to this, as long as the number of light-emitting devices 20 in the second light-emitting unit 42 is less than the number of light-emitting devices 20 in the first light-emitting unit 41.

[0144] Based on this, as shown in Figure 12, in the second direction Y, the two second light-emitting units 42 of two adjacent edge lamp areas A120 are connected in series and connected to the same driving pin 31, which simplifies the circuit and reduces the manufacturing cost. Furthermore, the number of light-emitting devices 20 and driving chips 30 connected by a single device power signal line 131 is reduced, which can increase the luminous brightness of each light-emitting device 20, thereby improving the brightness of the edge area A2 and thus enhancing the brightness uniformity of the light-emitting substrate 100.

[0145] In some embodiments, referring to FIG10, the connection method of the plurality of light-emitting devices 20 in the central light area A110 is different from the connection method of the plurality of light-emitting devices 20 in the edge light area A120, so that the light-emitting devices 20 in the central light area A110 and the light-emitting devices 20 in the edge light area A120 have different brightness. In this way, the brightness difference between the central light area A110 and the edge light area A120 can be compensated by changing the connection method.

[0146] For example, multiple light-emitting devices 20 in the central light area A110 are connected in series to form a first light-emitting unit 41. Multiple light-emitting devices 20 in the edge light area A120 are divided into multiple second light-emitting units 42, each second light-emitting unit 42 including at least two light-emitting devices 20 connected in series, and the multiple second light-emitting units 42 are connected in parallel. In this case, by connecting them in parallel, the total resistance of the multiple light-emitting devices 20 in the edge light area A120 can be reduced, the current flowing through each light-emitting device 20 can be increased, and the luminous brightness of each light-emitting device 20 can be increased, thereby improving the brightness of the edge area A2 and thus improving the brightness uniformity of the light-emitting substrate 100.

[0147] For example, referring to Figures 10, 13A, and 13B, the number of light-emitting devices 20 in the second light-emitting unit 42 is less than or equal to the number of light-emitting devices 20 in the first light-emitting unit 41. In this case, the total resistance of the multiple light-emitting devices 20 in the edge lamp area A120 is less than the total resistance of the multiple light-emitting devices 20 in the center lamp area A110, which can increase the current flowing through each light-emitting device 20, increase the luminous brightness of each light-emitting device 20, thereby increasing the brightness of the edge area A2, and thus improving the brightness uniformity of the light-emitting substrate 100.

[0148] For example, as shown in Figure 13A, the first light-emitting unit 41 includes four light-emitting devices 20 connected in series, and the second light-emitting unit 42 includes two second light-emitting units 42, each of which includes four light-emitting devices 20 connected in series. Alternatively, as shown in Figure 13B, the second light-emitting unit 42 includes four second light-emitting units 42, each of which includes two light-emitting devices 20 connected in series. Of course, the number of light-emitting devices 20 in the first light-emitting unit 41 and the second light-emitting unit 42 is not limited to these.

[0149] The following example illustrates some embodiments of this disclosure, using the central light area A110 comprising four light-emitting devices 20 connected in series and the edge light area A120 comprising multiple second light-emitting units 42 connected in parallel. However, the implementation of this disclosure is not limited thereto.

[0150] In some embodiments, referring to FIG13A, the arrangement of the plurality of light-emitting devices 20 in the central light area A110 is different from the arrangement of the plurality of light-emitting devices 20 in the edge light area A120. In this case, the overall luminous efficacy of the light area 10 can be adjusted by the arrangement of the light-emitting devices 20, thereby improving the uniformity of light output in the light area 10.

[0151] For example, referring to Figure 13A, the light-emitting centers of multiple light-emitting devices 20 in the central light area A110 are connected and arranged in a rhombus shape, with the diagonals of the rhombus set along either the first direction X or the second direction Y. In this case, because the light from the light-emitting devices 20 diffuses outwards, the rhombus arrangement of the multiple light-emitting devices 20 results in relatively uniform light mixing at various positions in the light area A10, which is beneficial for improving the overall luminous efficiency of the central light area A110. In the edge light area A120, the multiple light-emitting devices 20 are arranged along either the first direction X or the second direction Y, which facilitates the routing design of the device connection lines 140, chip connection lines 150, and device power signal lines 131, resulting in a simple structure.

[0152] In some embodiments, referring to FIG10, the plurality of lamp zones A10 include a first lamp zone A11 and a second lamp zone A12, which are arranged along a first direction X. The light-emitting devices 20 of the first lamp zone A11 and the second lamp zone A12 are connected to the same device power signal line 131 and the same driver chip 30. That is, one device power signal line 131 is connected to the light-emitting devices 20 of two rows of lamp zones A10. Of course, one device power signal line 131 can also be connected to the light-emitting devices 20 of more rows of lamp zones A10; the embodiments of this disclosure are not limited thereto.

[0153] At this time, the device power signal line 131 includes a first trace segment 1311, a second trace segment 1312, and a third trace segment 1313. The first trace segment 1311 is located on the side of the first lamp area A11 away from the second lamp area A12. The second trace segment 1312 is connected to the first trace segment 1311 and is located along the second direction Y. The second trace segment 1312 is located on one side of the first lamp area A11. The light-emitting device 20 of the first lamp area A11 is connected to either the first trace segment 1311 (see Figure 14A) or the second trace segment 1312 (see Figure 14B). The third trace segment 1313 is connected to the second trace segment 1312 and is located between the first lamp area A11 and the second lamp area A12. The light-emitting device 20 of the second lamp area A12 is connected to the third trace segment 1313 to transmit power signals to the first lamp area A11 and the second lamp area A12.

[0154] Furthermore, referring to Figures 13A and 14A, the driver chip 30 is connected to the light-emitting devices 20 in the first lamp area A11 and the second lamp area A12 respectively via two first chip connection lines 1510. The first chip connection line 1510 includes a first sub-segment 151 and a second sub-segment 152. The first sub-segment 151 is located on the side of the second lamp area A12 away from the second trace segment 1312 and is connected to the driver chip 30. The second sub-segment 152 is located on the side of the first sub-segment 151 closer to the second trace segment 1312 and is connected to the light-emitting device 20 to transmit driving signals to the first lamp area A11 and the second lamp area A12.

[0155] In some embodiments, as shown in Figures 14A and 14B, in the central lamp area A110, the boundary of the device connection line 140 is disposed along a first direction X or a second direction Y. The shape of the device connection line 140 can be, for example, any one of a rectangle, an L-shape, or an S-shape, and the edges of the rectangle, L-shape, or S-shape can be concave or convex.

[0156] In some embodiments, as shown in Figures 13A, 13B, 13C and 15, in the edge lamp area A120, the device connection line 140 is a quadrilateral, and one set of two opposite sides of the quadrilateral is arranged along the first direction X, while the other set of two opposite sides can be arranged along the second direction Y, or the angle between the quadrilateral and the second direction Y is an acute angle.

[0157] For example, as shown in Figures 13A, 13B and 13C, in the target second lamp area M120 mentioned below, the shape of the device connection line 140 can be, for example, rectangular or trapezoidal.

[0158] For example, as shown in FIG15, in the third lamp area A13 mentioned below, the shape of the device connection line 140 can be, for example, rectangular. Furthermore, the device connection lines 140 are arranged in multiple rows and columns, and in one column of device connection lines 140, multiple boundaries of adjacent columns of device connection lines 140 are staggered; for example, in one column of device connection lines 140, multiple boundaries of adjacent columns of device connection lines 140 can have a stepped structure.

[0159] The following describes some embodiments of the present disclosure by taking as an example that the light area points from the first light area A11 to the second light area A12 along the first direction X, and the last column of light areas A10 is the edge light area A120. However, the implementation of the present disclosure is not limited to this. For example, the first column of light areas A10 can also be the edge light area A120, pointing from the first light area A11 to the second light area A12.

[0160] At this point, as shown in Figures 13B and 13C, along the first direction X, pointing from the first lamp area A11 to the second lamp area A12, the last device power signal line 131 is the target device power signal line 1310. The second lamp area A12 coupled to the target device power signal line 1310 can be, for example, the target second lamp area M120, which is the edge lamp area A120. That is, along the first direction X, pointing from the first lamp area A11 to the second lamp area A12, the edge lamp area A120 is the last column of lamp areas A10 in the array of multiple lamp areas A10.

[0161] In some embodiments, referring to Figures 13B and 13C, in the target second lamp area M120, multiple light-emitting devices 20 are divided into multiple second light-emitting units 42. The multiple second light-emitting units 42 are arranged in multiple rows and columns, with the second light-emitting units 42 in the same column connected in parallel. Each second light-emitting unit 42 includes at least two light-emitting devices 20 connected in series. The light-emitting devices 20 of the same second light-emitting unit 42 are arranged along a first direction X, resulting in low resistance and a simple structure. Figures 13B and 13C illustrate an example where the second light-emitting unit 42 includes two light-emitting devices 20 connected in series.

[0162] At this time, the first chip connection line 1510 connecting the driver chip 30 to the light-emitting device 20 of the target second lamp area M120 is the target chip connection line 1511. There are two examples of the routing methods for the target device power signal line 1310 and the target chip connection line 1511.

[0163] Example 1:

[0164] As shown in Figure 13B, the target device power signal line 1310 also includes a fourth trace segment 1314, which is located between two adjacent columns of second light-emitting units 42. One end of the fourth trace segment 1314 is connected to the second trace segment 1312, and the other end passes between the two adjacent columns of second light-emitting units 42, extending to the side of the target second lamp area M120 away from the second trace segment 1312. At this point, pointing from the first lamp area A11 to the target second lamp area M120, the first column of second light-emitting units 42 is connected to the third trace segment 1313, and the remaining second light-emitting units 42 are connected to the fourth trace segment 1314. This facilitates the connection of each second light-emitting unit 42 to the target device power signal line 1310, resulting in low manufacturing costs.

[0165] As shown in Figure 13B, the target chip connection line 1511 also includes a third segment 153. The third segment 153 is located between two adjacent columns of second light-emitting units 42. One end of the third segment 153 is connected to the first segment 151, and the other end passes between the two adjacent columns of second light-emitting units 42, extending to the side of the target second lamp area M120 away from the first segment 151. At this time, in the target second lamp area M120, from the first lamp area A11 to the second lamp area A12, the last column of second light-emitting units 42 is connected to the second segment 152, and the remaining second light-emitting units 42 are connected to the third segment 153. This facilitates the connection of each second light-emitting unit 42 to the target chip connection line 1511, resulting in low manufacturing costs.

[0166] Example 2:

[0167] As shown in Figure 13C, the target device power signal line 1310 also includes a fifth trace segment 1315 and a sixth trace segment 1316. The fifth trace segment 1315 is connected to the third trace segment 1313 and is located on the side of the target second lamp area M120 away from the second trace segment 1312. The two sixth trace segments 1316 are located between two adjacent rows of second light-emitting units 42, with their ends facing each other. The two sixth trace segments 1316 extend from both sides of the target second lamp area M120 to the space between the two adjacent rows of second light-emitting units 42, with one sixth trace segment 1316 connected to the second trace segment 1312 and the other sixth trace segment 1316 connected to the fifth trace segment 1315. At this time, in the target second lamp area M120, from the first lamp area A11 to the second lamp area A12, the first column of second light-emitting units 42 are connected to the third wiring segment 1313, and the remaining second light-emitting units 42 are connected to the sixth wiring segment 1316. This facilitates the connection of each second light-emitting unit 42 to the power signal line 1310 of the target device, resulting in low manufacturing cost.

[0168] As shown in Figure 13C, the target chip connection line 1511 also includes a fourth sub-segment 154 and a fifth sub-segment 155. The fourth sub-segment 154 is connected to the second sub-segment 152 and is located between two adjacent rows of second light-emitting units 42. The two fifth sub-segments 155 are located between two adjacent columns of second light-emitting units 42 and are connected to the fourth sub-segment 154 on both sides. At this time, in the target second lamp area M120, from the first lamp area A11 to the second lamp area A12, the last column of second light-emitting units 42 is connected to the second sub-segment 152, and the remaining second light-emitting units 42 are connected to the fifth sub-segment 155. This facilitates the connection of each second light-emitting unit 42 to the target chip connection line 1511, resulting in low manufacturing cost.

[0169] In some embodiments, referring to Figures 13A, 13B and 13C, the trace segment connecting the device power signal line 131 to the light-emitting device 20 in the second lamp area A12 is the first target trace segment, and the sub-segment connecting the first chip connection line 1510 to the light-emitting device 20 in the second lamp area A12 is the first target sub-segment. The first target trace segment and the first target sub-segment are arranged along the first direction X.

[0170] The aforementioned first target routing segment may include, for example, at least one of the third routing segment 1313, the fourth routing segment 1314, and the sixth routing segment 1316. The aforementioned first target sub-segment may include, for example, at least one of the second sub-segment 152, the third sub-segment 153, and the fifth sub-segment 155.

[0171] In some embodiments, referring to FIG10, the routing length of the third routing segment 1313 of the target device power signal line 1310 is the fifth distance L5, and the routing length of the third routing segment 1313 of the remaining other device power signal lines 131 is the sixth distance L6, wherein the fifth distance L5 is greater than the sixth distance L6.

[0172] Furthermore, the difference between the third distance L3 and the fourth distance L4 is the first difference, and the difference between the fifth distance L5 and the sixth distance L6 is the second difference. The ratio of the first difference to the second difference is between 1.8 and 2.2. For example, the ratio of the first difference to the second difference can be any one of 1.8, 1.9, 2, 2.1, and 2.2.

[0173] The following description uses the row light area A10, which is closest to or furthest from the binding area B, as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure is not limited thereto.

[0174] At this point, referring to Figures 5 and 10, the multiple light zones A10 include a third light zone A13. The third light zone A13 is the row of light zones A10 that is closest to or furthest from the binding area among the multiple light zones A10 in multiple rows and columns. The third light zone A13 is the edge light zone A120.

[0175] In some embodiments, referring to Figures 10 and 15, the plurality of light-emitting devices 20 in the third lamp area A13 are divided into a plurality of second light-emitting units 42, which are connected in parallel and arranged along a first direction X. Each second light-emitting unit 42 includes at least two light-emitting devices 20, and the light-emitting devices 20 in the same second light-emitting unit 42 are arranged along a second direction Y, resulting in low resistance and a simple structure. Figures 10 and 15 illustrate an example where the second light-emitting unit 42 includes four light-emitting devices 20 connected in series.

[0176] The device power signal line 131 includes a first trace segment 1311 and a second trace segment 1312. Along the first direction X, the first trace segment 1311 is located on one side of the third lamp area A13. The second trace segment 1312 is connected to the first trace segment 1311. And, along the second direction Y, the second trace segment 1312 is located on the side of the third lamp area A13 away from the bonding area B (the upper side in Figures 10 and 15), and the light-emitting device 20 of the third lamp area A13 is connected to the second trace segment 1312.

[0177] Furthermore, the driver chip 30 is connected to the light-emitting device 20 of the third lamp area A13 via a second chip connection line 1520. The second chip connection line 1520 includes a sixth sub-segment 1521 and a seventh sub-segment 1522. The sixth sub-segment 1521 is located on the side of the third lamp area A13 away from the first trace segment 1311 and is connected to the driver chip 30. The seventh sub-segment 1522 is located on the side of the third lamp area A13 closer to the bonding area B and is connected to the light-emitting device 20 to transmit a drive signal to the third lamp area A13. At this time, the second trace segment 1312 and the seventh sub-segment 1522 are arranged along the second direction Y. Of course, the structure of the second chip connection line 1520 is not limited to this.

[0178] In some embodiments, referring to FIG10, along the first direction X, and pointing from the first line segment 1311 to the corresponding third lamp area A13, in the last column of lamp areas A10, apart from the third lamp area A13, the remaining lamp areas A10 are the target second lamp area M120. The multiple light-emitting devices 20 of the target second lamp area M120 are divided into multiple second light-emitting units 42. The multiple second light-emitting units 42 are connected in parallel, and the second light-emitting unit 42 includes at least two light-emitting devices 20 connected in series. The light-emitting devices 20 of the same second light-emitting unit 42 are arranged along the first direction X.

[0179] It should be noted that, along the first direction X, and pointing from the first line segment 1311 to the corresponding third light area A13, the last row of light areas A10 can all be the target second light area M120. That is, in the row of light areas A10 closest to the binding area B, except for the last light area A10 which is the target second light area M120, the others are all the third light area A13.

[0180] Based on this, as shown in Figure 10, at least one driver chip 30 is connected to the light-emitting devices 20 of a third lamp zone A13, a target second lamp zone M120, and a central lamp zone A110. For example, among the multiple driver chips 30 arranged in an array, the driver chip 30 at the bottom right corner is connected to the two rows and two columns of lamp zones A10 at the bottom right corner. That is, the driver chip 30 at the bottom right corner is connected to the light-emitting devices 20 of two third lamp zones A13, a target second lamp zone M120, and a central lamp zone A110.

[0181] In some embodiments, referring to FIG10, along the first direction X, and pointing from the first wiring segment 1311 to the corresponding third light area A13, the last third light area A13 is the target third light area A130. In the target third light area A130, the wiring length of the second wiring segment 1312 is the seventh distance L7, and in other third light areas A13, the wiring length of the second wiring segment 1312 is the eighth distance L8, where the seventh distance L7 is greater than the eighth distance L8.

[0182] Furthermore, the difference between the first distance L1 and the second distance L2 is the third difference, and the difference between the seventh distance L7 and the eighth distance L8 is the fourth difference. The ratio of the third difference to the fourth difference is between 1.5 and 2. For example, the ratio of the third difference to the fourth difference can be any one of 1.5, 1.6, 1.7, 1.8, 1.9, and 2.

[0183] In some embodiments, referring to Figures 14A and 16, in at least one lamp area A10, in the first direction X, the line connecting the centers of two adjacent light-emitting devices 20 forms an acute angle with the first direction X. And / or, in the second direction Y, the line connecting the centers of two adjacent light-emitting devices 20 forms an acute angle with the second direction Y.

[0184] For example, as shown in Figures 14A and 14B, in the central lamp area A110, in the first direction X, the line connecting the centers of two adjacent light-emitting devices 20 forms an acute angle with the first direction X. And / or, in the second direction Y, the line connecting the centers of two adjacent light-emitting devices 20 forms an acute angle with the second direction Y. In this case, the light-emitting devices 20 are staggered in the first direction X and / or the second direction Y, which helps to improve the light emission uniformity of the central lamp area A110.

[0185] For example, referring to Figures 15 and 16, in the edge lighting area A120, in the first direction X, the line connecting the centers of two adjacent light-emitting devices 20 forms an acute angle with the first direction X. And / or, in the second direction Y, the line connecting the centers of two adjacent light-emitting devices 20 forms an acute angle with the second direction Y. In this case, the light-emitting devices 20 are staggered in the first direction X and / or the second direction Y, which helps to improve the light emission uniformity of the edge lighting area A120.

[0186] The following describes some embodiments of this disclosure by way of example, with reference to the specific film layers of the light-emitting substrate 100. The implementation of this disclosure is not limited thereto.

[0187] In some embodiments, as shown in Figures 17 and 18, the light-emitting substrate 100 includes a substrate 60 and at least one conductive layer 70.

[0188] Among them, the aforementioned device pad group 110, chip pad group 120, signal line 130, device connection line 140, chip connection line 150, redundant trace 160, cascade line 170 and alignment mark 180 can all be located on the conductive layer 70.

[0189] The substrate 60 can be a rigid substrate or a flexible substrate. The rigid substrate is made of at least one of glass, quartz, sapphire, ceramic, and polymethyl methacrylate (PMMA). The flexible substrate is made of at least one of epoxy resin, triazine, silicone resin, and polyimide.

[0190] The conductive layer 70 described above can be a multilayer structure or a single-layer structure. The material of the conductive layer 70 may include at least one of copper, molybdenum-niobium alloy, nickel, and indium tin oxide, but the embodiments disclosed herein are not limited thereto.

[0191] For example, referring to Figures 16 and 17, the light-emitting substrate 100 includes a substrate 60 and a first conductive layer 71 stacked sequentially. In this case, referring to Figures 6A, 7A, 16, and 17, the device pad group 110, the chip pad group 120, the signal line 130, the device connection line 140, the chip connection line 150, the redundant trace 160, the cascade line 170, and the alignment mark 180 can all be located in the first conductive layer 71.

[0192] For example, referring to FIG8 and FIG18, the light-emitting substrate 100 includes a substrate 60, a first conductive layer 71, a first insulating layer 81, a second conductive layer 72 and a second insulating layer 82 stacked sequentially.

[0193] The materials of the first insulating layer 81 and the second insulating layer 82 may include at least one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. For example, both the first insulating layer 81 and the second insulating layer 82 may be made of silicon nitride.

[0194] As shown in Figure 18, the first conductive layer 71 is disposed on one side of the substrate 60, the first insulating layer 81 is disposed on the side of the first conductive layer 71 away from the substrate 60, the second conductive layer 72 is disposed on the side of the first insulating layer 81 away from the substrate 60, and the second insulating layer 82 is disposed on the side of the second conductive layer 72 away from the substrate 60.

[0195] The second insulating layer 82 has multiple openings, one of which can expose at least a portion of a pad in the device pad group 110 or the chip pad group 120. For example, an opening exposing a portion of a device pad portion 142 can reduce the flow of soldering flux (such as solder paste) and reduce the risk of rotation and misalignment during the connection of the light-emitting device 20 to the device pad group 110.

[0196] Furthermore, as shown in Figures 6A, 7B, 8, and 18, the device pad group 110, chip pad group 120, and alignment mark 180 can be located on the second conductive layer 72, while the various signal lines 130, redundant traces 160, and cascade lines 170 can be located on the first conductive layer 71. Additionally, for the device connection line 140 and chip connection line 150, a portion of the connection segment can be located on the first conductive layer 71, and a portion can be located on the second conductive layer 72. This can be specifically configured according to the actual wiring to stagger the intersections of different circuit traces and avoid short circuits.

[0197] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A light-emitting substrate, comprising a light-emitting region and a bonding region, wherein the light-emitting region includes a plurality of lamp regions arranged in multiple rows and columns, a row including at least two lamp regions arranged along a first direction, and a column including at least two lamp regions arranged along a second direction; the second direction intersects the first direction; wherein, Along the second direction, the bonding area is located on one side of the light-emitting area; the light-emitting area includes a central area and an edge area located on at least one side of the central area, the light area located in the central area is the central light area, and the light area located in the edge area is the edge light area; The light-emitting substrate further includes: A binding part is provided in the binding area; The device power signal line is connected to the bonding part; A driver chip is disposed between two adjacent columns of the lamp areas; the driver chip includes driver pins. Multiple light-emitting devices are disposed in the lamp area; and one end of the light-emitting device in one lamp area is coupled to the same driving pin, and the other end is coupled to the device power signal line. The number of light-emitting devices in the central light area is not equal to the number of light-emitting devices in the edge light area.

2. The light-emitting substrate according to claim 1, wherein, The multiple light-emitting devices in the central light area are connected in series to form a first light-emitting unit; the multiple light-emitting devices in the edge light area are connected in series to form a second light-emitting unit; the number of light-emitting devices in the second light-emitting unit is less than the number of light-emitting devices in the first light-emitting unit.

3. The light-emitting substrate according to claim 2, wherein, In the second direction, the two second light-emitting units of two adjacent edge light areas are connected in series and connected to the same driving pin.

4. The light-emitting substrate according to claim 1, wherein, The connection method of the multiple light-emitting devices in the central light area is different from the connection method of the multiple light-emitting devices in the edge light area.

5. The light-emitting substrate according to claim 4, wherein, The multiple light-emitting devices in the central light area are connected in series to form a first light-emitting unit; the multiple light-emitting devices in the edge light area are divided into multiple second light-emitting units, each second light-emitting unit includes at least two light-emitting devices connected in series, and the multiple second light-emitting units are connected in parallel.

6. The light-emitting substrate according to any one of claims 1 to 5, wherein, In the first direction, the distance between two adjacent light-emitting devices in the central light area is a first distance, and the distance between two adjacent light-emitting devices in the edge light area is a second distance; the first distance is greater than the second distance; and / or, in the second direction, the distance between two adjacent light-emitting devices in the central light area is a third distance, and the distance between two adjacent light-emitting devices in the edge light area is a fourth distance; the third distance is greater than the fourth distance.

7. The light-emitting substrate according to claim 6, wherein, The ratio of the first distance to the second distance is 1.2 to 1.8; and / or the ratio of the third distance to the fourth distance is 1.2 to 1.

8.

8. The light-emitting substrate according to any one of claims 1 to 7, wherein, The multiple light zones include a first light zone and a second light zone, which are arranged along the first direction, and the light-emitting devices of the first light zone and the second light zone are connected to the same device power signal line and the same driver chip.

9. The light-emitting substrate according to claim 8, wherein, The device power signal line includes: The first wiring segment is located on the side of the first light area that is far from the second light area; The second wiring segment is connected to the first wiring segment; along the second direction, the second wiring segment is located on one side of the first lamp area; the light-emitting device of the first lamp area is connected to the first wiring segment or the second wiring segment; The third wiring segment is connected to the second wiring segment and is located between the first lamp area and the second lamp area; the light-emitting device in the second lamp area is connected to the third wiring segment.

10. The light-emitting substrate according to claim 9, further comprising first chip connection lines, wherein the driving chip is connected to the light-emitting devices in the first lamp area and the second lamp area respectively via two first chip connection lines; wherein, The first chip connection line includes: The first sub-segment is located on the side of the second lamp area away from the second trace segment and is connected to the driver chip; The second sub-segment is located on the side of the first sub-segment closest to the second trace segment and is connected to the light-emitting device.

11. The light-emitting substrate according to claim 10, wherein, Along the first direction, and from the first lamp area to the second lamp area, the last device power signal line is the target device power signal line, the second lamp area coupled to the target device power signal line is the target second lamp area, and the target second lamp area is the edge lamp area.

12. The light-emitting substrate according to claim 11, wherein, In the target second light area, multiple light-emitting devices are divided into multiple second light-emitting units, and the multiple second light-emitting units are arranged in multiple rows and columns, with the second light-emitting units in the same column connected in parallel; each second light-emitting unit includes at least two light-emitting devices connected in series, and the light-emitting devices of the same second light-emitting unit are arranged along the first direction.

13. The light-emitting substrate according to claim 12, wherein, The target device power signal line also includes: The fourth wiring segment is located between two adjacent columns of the second light-emitting units; one end of the fourth wiring segment is connected to the second wiring segment, and the other end passes through the space between two adjacent columns of the second light-emitting units and extends to the side of the target second light area away from the second wiring segment; from the first light area to the target second light area, the first column of the second light-emitting units is connected to the third wiring segment, and the remaining second light-emitting units are connected to the fourth wiring segment.

14. The light-emitting substrate according to claim 13, wherein, The first chip connection line connecting the driver chip to the light-emitting device of the target second lamp area is the target chip connection line; The target chip connection line also includes: The third sub-segment is located between two adjacent columns of the second light-emitting units; Furthermore, one end of the third sub-segment is connected to the first sub-segment, and the other end passes between two adjacent columns of the second light-emitting units and extends to the side of the target second light area away from the first sub-segment; in the target second light area, from the first light area to the second light area, the last column of the second light-emitting units is connected to the second sub-segment, and the remaining second light-emitting units are connected to the third sub-segment.

15. The light-emitting substrate according to claim 11, wherein, The target device power signal line also includes: The fifth wiring segment is connected to the third wiring segment and is located on the side of the target second lamp area away from the second wiring segment; The sixth routing segment consists of two segments located between two adjacent columns of the second light-emitting units, with their ends facing each other. Each of the two sixth routing segments extends from both sides of the target second light area to the same adjacent two rows of the second light-emitting units. One sixth routing segment connects to the second routing segment, and the other sixth routing segment connects to the fifth routing segment. In the target second light area, pointing from the first light area to the second light area, the first column of the second light-emitting units connects to the third routing segment, and the remaining second light-emitting units connect to the sixth routing segment.

16. The light-emitting substrate according to claim 15, wherein, The first chip connection line connecting the driver chip to the light-emitting device of the target second lamp area is the target chip connection line; The target chip connection line also includes: The fourth sub-segment is connected to the second sub-segment and is located between two adjacent rows of second light-emitting units; The fifth sub-segment, two of which are located between two adjacent columns of the second light-emitting units, and are connected to the fourth sub-segment on both sides of the fourth sub-segment respectively; in the target second light area, from the first light area to the second light area, the last column of the second light-emitting units is connected to the second sub-segment, and the remaining second light-emitting units are connected to the fifth sub-segment.

17. The light-emitting substrate according to any one of claims 11 to 16, wherein, In the second direction, the distance between two adjacent light-emitting devices in the central light area is the third distance, and the distance between two adjacent light-emitting devices in the edge light area is the fourth distance; the third distance is greater than the fourth distance. The routing length of the third segment of the power signal line of the target device is the fifth distance, and the routing length of the third segment of the remaining power signal lines of the other devices is the sixth distance. The difference between the third distance and the fourth distance is the first difference; the difference between the fifth distance and the sixth distance is the second difference; the ratio of the first difference to the second difference is 1.8 to 2.

2.

18. The light-emitting substrate according to any one of claims 10 to 17, wherein, The trace segment connecting the device power signal line to the light-emitting device in the second lamp area is the first target trace segment, and the sub-segment connecting the first chip connection line to the light-emitting device in the second lamp area is the first target sub-segment. The first target trace segment and the first target sub-segment are arranged along the first direction.

19. The light-emitting substrate according to any one of claims 1 to 7, wherein, The plurality of light zones include a third light zone, which is the row of light zones in a multi-row, multi-column configuration that is closest to or furthest from the binding area; the third light zone is the edge light zone.

20. The light-emitting substrate according to claim 19, wherein, The plurality of light-emitting devices in the third light zone are divided into a plurality of second light-emitting units, which are connected in parallel and arranged along the first direction; each second light-emitting unit includes at least two light-emitting devices, and the light-emitting devices in the same second light-emitting unit are arranged along the second direction.

21. The light-emitting substrate according to claim 20, wherein, The device power signal line includes: The first wiring segment is located along the first direction and is situated on one side of the third light area; The second trace segment is connected to the first trace segment; along the second direction, the second trace segment is located on the side of the third lamp area away from the bonding area; the light-emitting device of the third lamp area is connected to the second trace segment.

22. The light-emitting substrate according to claim 21, further comprising a second chip interconnect line, the second chip interconnect line comprising: The sixth sub-segment is located on the side of the third lamp area away from the first trace segment and is connected to the driver chip; The seventh sub-segment is located on the side of the third lamp area near the binding area and is connected to the light-emitting device.

23. The light-emitting substrate according to claim 22, wherein, The second routing segment and the seventh sub-segment are arranged along the second direction.

24. The light-emitting substrate according to any one of claims 19 to 23, wherein, Along the first direction, and from the first line segment to the corresponding third light area, in the last column of light areas, except for the third light area, the remaining light areas are the target second light areas. The multiple light-emitting devices of the target second light area are divided into multiple second light-emitting units. The multiple second light-emitting units are connected in parallel, and the second light-emitting unit includes at least two light-emitting devices connected in series. The light-emitting devices of the same second light-emitting unit are arranged along the first direction.

25. The light-emitting substrate according to claim 24, wherein, At least one of the driving chips is connected to the light-emitting devices of one of the third lamp zones, one of the target second lamp zones, and one of the central lamp zones.

26. The light-emitting substrate according to claim 24 or 25, wherein, In the first direction, the distance between two adjacent light-emitting devices in the central light area is a first distance, and the distance between two adjacent light-emitting devices in the edge light area is a second distance; the first distance is greater than the second distance. Along the first direction, and from the first wiring segment to the corresponding third light area, the last third light area is the target third light area; in the target third light area, the wiring length of the second wiring segment is the seventh distance, and in the other third light areas, the wiring length of the second wiring segment is the eighth distance. The difference between the first distance and the second distance is the third difference; the difference between the seventh distance and the eighth distance is the fourth difference; the ratio of the third difference to the fourth difference is 1.5 to 2.

27. The light-emitting substrate according to any one of claims 1 to 26, wherein, In the edge light area, in the first direction, the angle between the line connecting the centers of two adjacent light-emitting devices and the first direction is an acute angle; and / or, in the second direction, the angle between the line connecting the centers of two adjacent light-emitting devices and the second direction is an acute angle.

28. The light-emitting substrate according to any one of claims 1 to 27, wherein, The plurality of the driving chips are arranged in multiple rows and columns along the first direction and the second direction; Along the first direction, the plurality of driver chips are divided into a plurality of driver chip groups, and each driver chip group includes two driver chips arranged symmetrically.

29. The light-emitting substrate according to claim 28, further comprising: Multiple grounding signal lines are connected to the bonding part; Along the first direction, the device power signal line and the ground signal line are arranged alternately; The two driver chips in the same driver chip group are connected to the same ground signal line.

30. The light-emitting substrate according to any one of claims 1 to 29, wherein, The driver chip includes two ground pins, and the light-emitting substrate further includes: Multiple grounding signal lines are spaced apart along the first direction and connected to the bonding part; each grounding signal line includes a first main routing segment and a grounding connection line, and the two grounding pins are connected to the first main routing segment through the two grounding connection lines.

31. The light-emitting substrate according to any one of claims 1 to 30, wherein, The plurality of driver chips are arranged in multiple rows and columns along the first direction and the second direction, and the driver chip includes address input pins and data input pins; The light-emitting substrate further includes: Address signal lines, a row of address input pins of the driver chip, are connected to the bonding part through the address signal lines; the address signal lines overlap with the driver chip; A data signal line, a row of data input pins of the driver chip, is connected to the bonding part through the data signal line; the data signal line overlaps with the driver chip.

32. The light-emitting substrate according to claim 31, wherein, The driver chip includes a power input pin and a power output pin, and the light-emitting substrate further includes: The power input pin of the driver chip closest to the bonding area is connected to the bonding part via the power signal line. A cascade line is provided along the second direction, in which the power output pin of the driver chip that is closer to the bonding region in two adjacent driver chips is connected to the power input pin of the driver chip that is farther away from the bonding region through the cascade line; Among them, at least one of the address signal line, the data signal line and the drive power signal line overlaps with the row of lamps closest to the bonding area.

33. The light-emitting substrate according to any one of claims 1 to 32, wherein, Multiple driver chips are arranged in multiple rows and columns along the first direction and the second direction. In the same column, two adjacent driver chips are cascaded, and the row of driver chips closest to the bonding area is connected to the bonding part. The driving chip includes multiple pins, with at least one pin in the row of the driving chip furthest from the bonding area floating. The light-emitting substrate further includes: Redundant traces are connected to the floating pins.

34. The light-emitting substrate according to any one of claims 1 to 33, further comprising: The device connection line connects multiple light-emitting devices in the lamp area in series. The device connection line includes a second main trace segment and a device pad portion. The device pad portion is located at one end of the second main trace segment and is narrower than the second main trace segment.

35. A light-emitting substrate, comprising a light-emitting region and a bonding region, wherein the light-emitting region includes a plurality of lamp regions arranged in multiple rows and columns, a row including at least two lamp regions arranged along a first direction, and a column including at least two lamp regions arranged along a second direction; the second direction intersects the first direction; wherein, Along the second direction, the bonding area is located on one side of the light-emitting area; the light-emitting area includes a central area and an edge area located on at least one side of the central area, the light area located in the central area is the central light area, and the light area located in the edge area is the edge light area; The light-emitting substrate further includes: A binding part is provided in the binding area; The device power signal line is connected to the bonding part; A driver chip is disposed between two adjacent columns of the lamp areas; the driver chip includes driver pins. Multiple light-emitting devices are disposed in the lamp area; and one end of the light-emitting device in one lamp area is coupled to the same driving pin, and the other end is coupled to the device power signal line. The connection method of the multiple light-emitting devices in the central light area is different from the connection method of the multiple light-emitting devices in the edge light area.

36. A display device, comprising: The light-emitting substrate as described in any one of claims 1 to 35; The circuit board is connected to the bonding part of the light-emitting substrate.

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