Semiconductor structure and manufacturing method therefor

Abstract

Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, comprising a device layer, buried power rails, and through-silicon vias, wherein the through-silicon vias are connected to the device layer by means of the buried power rails; a power supply network layer disposed on the substrate, wherein the power supply network layer comprises at least one layer of first power supply arrays and at least one layer of second power supply arrays, and the first power supply arrays are connected to the buried power rails by means of the through-silicon vias; and capacitor structures disposed between the first power supply arrays and the second power supply arrays, and respectively connected to the first power supply arrays and the second power supply arrays by means of lower electrodes and upper electrodes of the capacitor structures.

Description

Semiconductor structure and its preparation method

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202411538521.2, filed on October 30, 2024, entitled "Semiconductor Structure and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0004] In traditional chip manufacturing and advanced 2.5D or 3D packaging, wiring is typically done on the front side of the wafer, with signal lines and power lines vertically stacked and connected to form active electronic components (Semiconductor devices) with multilayer metal interconnect structures. This method results in both signal interconnect networks and power supply networks on the front side of the chip, making it difficult to further reduce the overall package size. Based on this, a back-side power supply network (BSPDN) chip structure was proposed to overcome the shortcomings of the front-side power supply structure. However, this introduces new problems, such as voltage drop due to power conduction path limitations, leading to higher chip power consumption. Therefore, how to further optimize the chip structure and shorten the power conduction path based on back-side power supply technology to improve device performance has become an urgent problem to be solved. Summary of the Invention

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including:

[0006] The substrate includes a device layer, a buried power rail, and a through-silicon via (TSV), wherein the TSV is connected to the device layer through the buried power rail.

[0007] A power network layer is disposed on the substrate, the power network layer including at least one first power array and at least one second power array, the first power array being connected to the buried power rail through the through silicon via;

[0008] A capacitor structure is disposed between the first power array and the second power array, and is connected to the first power array and the second power array respectively through the lower electrode and the upper electrode of the capacitor structure.

[0009] In some embodiments, the first power array extends along a first direction, the second power array extends along a second direction, the first direction and the second direction intersect in a direction parallel to the substrate, and the projections of the first power array and the second power array in a direction perpendicular to the substrate have overlapping portions.

[0010] In some embodiments, both the first power array and the second power array include at least two power lines and at least two ground lines. The at least two power lines and at least two ground lines of the first power array are parallel to each other and staggered along the second direction, and the at least two power lines and at least two ground lines of the second power array are parallel to each other and staggered along the first direction.

[0011] In some embodiments, the projected overlap of the first power array and the second power array in a direction perpendicular to the substrate includes at least one first region and at least one second region. The first region is the projected overlap of the power lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate, and the projected overlap of the ground lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate. The second region is the projected overlap of the ground lines of the first power array and the power lines of the second power array in a direction perpendicular to the substrate, and the projected overlap of the power lines of the first power array and the ground lines of the second power array in a direction perpendicular to the substrate.

[0012] In some embodiments, a contact plug is further provided between the first power array and the second power array. The contact plug is disposed in the first region and is used to connect the power line of the first power array to the power line of the second power array or to connect the ground line of the first power array to the ground line of the second power array.

[0013] In some embodiments, the capacitor structure is disposed in the second region, the lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array.

[0014] In some embodiments, the number of power lines and ground lines in the first power array is the same, and the number of power lines and ground lines in the second power array is the same.

[0015] In some embodiments, the spacing between adjacent power lines and ground lines ranges from 0.1 to 1.5 μm.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure also provides a method for fabricating a semiconductor structure, including:

[0017] A substrate is provided in which a device layer, a buried power rail, and a through-silicon via are formed, wherein the through-silicon via are connected to the device layer through the buried power rail;

[0018] A power network layer and a capacitor structure are formed on the substrate. The power network layer includes at least one first power array and at least one second power array. The first power array is connected to the buried power rail through the through-silicon via. The capacitor structure is formed between the first power array and the second power array and is connected to the first power array and the second power array through the lower electrode and the upper electrode of the capacitor structure, respectively.

[0019] In some embodiments, the step of forming the power network layer and capacitor structure on the substrate includes:

[0020] The substrate has a first surface and a second surface. An isolation layer is formed on the first surface of the substrate. A first power array is formed within the patterned isolation layer. The first power array extends along a first direction and includes at least two power lines and at least two ground lines. An insulating layer is deposited and formed on the isolation layer and the first power array. The insulating layer is patterned, and the patterned insulating layer exposes a portion of the power lines and ground lines of the first power array. A capacitor structure, a contact plug, and a second power array are sequentially formed within the patterned insulating layer. The second power array extends along a second direction and includes at least two power lines and at least two ground lines. The first direction and the second direction intersect in a direction parallel to the substrate. The projection portions of the first power array and the second power array in a direction perpendicular to the substrate coincide. The contact plug and the capacitor structure are connected between the first power array and the second power array.

[0021] In some embodiments, the lower electrode of the capacitor structure is connected to the power line of the first power array, and the upper electrode of the capacitor structure is connected to the ground line of the second power array; or, the lower electrode of the capacitor structure is connected to the ground line of the first power array, and the upper electrode of the capacitor structure is connected to the power line of the second power array.

[0022] In some embodiments, the contact plug is used to connect the power line of the first power array to the power line of the second power array, or to connect the ground line of the first power array to the ground line of the second power array.

[0023] In some embodiments, the insulating layer includes a first barrier layer, a first insulating layer, a second barrier layer, and a second insulating layer. The capacitor structure, the contact plug, and the second power array are sequentially formed within the patterned insulating layer. The method includes: depositing the first barrier layer and the first insulating layer; patterning the first barrier layer and the first insulating layer to form a first trench, the first trench exposing a portion of the power line or ground line of the first power array; sequentially depositing a lower electrode, a dielectric layer, a barrier layer, and an upper electrode within the first trench, the lower electrode, the dielectric layer, the barrier layer, and the upper electrode constituting the capacitor structure; the lower electrode connecting to the power line or ground line of the first power array; depositing the second barrier layer and the second insulating layer; patterning the first barrier layer, the first insulating layer, the second barrier layer, and the second insulating layer to form a second trench, the second trench exposing a portion of the power line or ground line of the first power array and the upper electrode of the capacitor structure; and depositing conductive material within the second trench to form the contact plug and the second power array.

[0024] In some embodiments, the device layer, the buried power rail, and the through-silicon via (TSV) are formed in the substrate, including: forming the TSV in the substrate, the TSV penetrating the first surface and the second surface of the substrate; and sequentially forming the buried power rail and the device layer on the second surface of the substrate.

[0025] In some embodiments, after the device layer is formed in the substrate, a signal interconnect layer is further formed on the device layer.

[0026] The technical solutions provided in this disclosure have at least the following advantages:

[0027] This embodiment integrates the capacitor structure into the power supply network, which improves the voltage regulation effect without the need for additional capacitor structures, thereby reducing the size of the chip. On the other hand, since the power supply network can be directly connected to the capacitor structure internally, the power supply path is shortened, thereby reducing the transmission resistance and further enhancing the stability and reliability of the power supply network. Attached Figure Description

[0028] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 is a top view of a power network layer provided in an embodiment of this disclosure.

[0030] Figure 2 is a cross-sectional view of a partial semiconductor structure along the AA' direction in Figure 1, provided in an embodiment of the present disclosure.

[0031] Figure 3 is a flowchart of a semiconductor fabrication method provided in an embodiment of this disclosure.

[0032] Figure 4 is another flowchart of a semiconductor fabrication method provided in an embodiment of this disclosure.

[0033] Figure 5 is another flowchart of a semiconductor fabrication method provided in an embodiment of this disclosure.

[0034] Figures 6 to 13 are cross-sectional views of a portion of the semiconductor structure along the AA' direction in Figure 1, corresponding to each step of a semiconductor fabrication method provided in an embodiment of this disclosure. Detailed Implementation

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Backside Power Supply Network (BSPDN), as a chip design approach, aims to address the RC (parasitic resistance and capacitance) bottlenecks and wiring congestion caused by signal and power lines sharing interconnect resources in traditional front-side routing by moving power lines to the back of the wafer. This approach not only eliminates the need for front-side power rails but also allows for more economical strategies in interconnect scaling, thus saving costs. However, the introduction of BSPDN also brings some new challenges, the most significant being the voltage drop effect caused by the limitation of power conduction paths, which increases chip power consumption and impacts overall performance.

[0037] To address the aforementioned technical problems, this disclosure provides a semiconductor structure, which will be described below with reference to the accompanying drawings.

[0038] Figure 1 is a top view of a power network layer provided in an embodiment of the present disclosure; Figure 2 is a cross-sectional view of a portion of a semiconductor structure along the AA' direction in Figure 1 provided in an embodiment of the present disclosure. The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0039] Referring to Figures 1 and 2, the semiconductor structure 10 includes: a substrate 101, which includes a device layer 103, a buried power rail (BPR), and a through-silicon via (TSV) 102. The TSV 102 is connected to the device layer 104 via the buried power rail 103; a power network layer 104 disposed on the substrate 101, which includes at least one first power array 1041 and at least one second power array 1042. The first power array 1041 is connected to the buried power rail (BPR) via the TSV 102; and a capacitor structure 108 disposed between the first power array 1041 and the second power array 1042, and connected to the first power array 1041 and the second power array 1042 via the lower electrode 1081 and the upper electrode 1084 of the capacitor structure 108, respectively.

[0040] In some embodiments, the substrate 101 may be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other III-V compounds. The substrate 101 may also include a device layer 103 for forming chip devices. The device layer 103 may include active devices such as transistors or diodes, or passive devices such as capacitors, inductors, resistors, etc. A signal interconnect layer SL may also be disposed below the device layer 103 for connecting the device layer 103 to external control signals or input / output signals. Buried power rails (BPRs) may also be disposed within the substrate 101 as interconnects to which power supply voltage or ground voltage is applied.

[0041] In some embodiments, referring to Figures 1 and 2, a first power array 1041 extends along a first direction Y, and a second power array extends along a second direction X. The first direction Y and the second direction X intersect in a direction parallel to the substrate 101. The projections of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 have an overlapping portion. The intersection of the first direction Y and the second direction X in a direction parallel to the substrate 101 can be perpendicular or, as needed, at other angles, and is not limited here. Exemplarily, the power network layer 104 may include at least one first power array 1041 and at least one second power array 1042. The planes containing the different power arrays are parallel to the substrate 101 and located in different layers. In this embodiment, the second power array 1042 may be disposed above the first power array 1041, and the projections of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 have an intersecting portion.

[0042] In some embodiments, referring to Figures 1 and 2, both the first power array 1041 and the second power array 1042 include at least two power lines Vdd and at least two ground lines Vss. The at least two power lines Vdd and at least two ground lines Vss of the first power array 1041 are parallel to each other and staggered along a second direction X. The at least two power lines Vdd and at least two ground lines Vss of the second power array 1042 are parallel to each other and staggered along a first direction Y. For example, in a direction parallel to the substrate 101, the first power array 1041 includes multiple power lines Vdd. The first power array 1041 includes multiple power lines Vdd and multiple ground lines Vss, wherein each power line Vdd and each ground line Vss is staggered along the second direction X. The second power array 1042 also includes multiple power lines Vdd and multiple ground lines Vss, wherein each power line Vdd and each ground line Vss is staggered along the first direction Y. That is, the multiple power lines Vdd and multiple ground lines Vss in the first power array 1041 and the multiple power lines Vdd and multiple ground lines Vss in the second power array 1042 are all perpendicular to each other, and their projections in the direction perpendicular to the substrate 101 overlap. The power lines Vdd and ground lines Vss in the first power array 1041 and the power lines Vdd and ground lines Vss in the second power array 1042 are arranged in layers, and the power lines Vdd and ground lines Vss in each layer are staggered to reduce the voltage drop and signal interference between the power lines Vdd and ground lines Vss, thereby improving the performance and reliability of the circuit. The first power array 1041 is disposed in the isolation layer 105, and the material of the isolation layer 105 can be silicon oxide (SiO2) to isolate adjacent power lines Vdd and ground lines Vss.

[0043] In some embodiments, the shapes of the power line Vdd and ground line Vss can be rectangular, square, circular, polygonal, serpentine, star-shaped, or other shapes as needed, without limitation. For example, the power line Vdd and ground line Vss are designed as rectangular or square to provide a large-area low-impedance path, which helps reduce voltage drop and electromagnetic interference. They can also be designed as serpentine lines as needed; serpentine lines, by changing the direction of the traces, can increase the trace length, which helps match the length of signal lines and improve signal integrity.

[0044] In some embodiments, continuing to refer to FIG1 and FIG2, the projected overlap portion of the first power array 1041 and the second power array 1042 in a direction perpendicular to the substrate 101 includes at least one first region I and at least one second region II, wherein the first region I is the projected overlap portion of the power line Vdd of the first power array 1041 and the power line Vdd of the second power array 1042 in a direction perpendicular to the substrate 101, and the projected overlap portion of the ground line Vss of the first power array 1041 and the ground line Vss of the second power array 1042 in a direction perpendicular to the substrate 101; the second region II is the projected overlap portion of the ground line Vss of the first power array 1041 and the power line Vdd of the second power array 1042 in a direction perpendicular to the substrate 101, and the projected overlap portion of the power line Vdd of the first power array 1041 and the ground line Vss of the second power array 1042 in a direction perpendicular to the substrate 101. For example, referring to FIG1, the first region I and the second region II are arranged alternately in the first direction Y and the second direction X, that is, the first region I and the second region II are arranged adjacent to each other in the first direction Y and the second direction X, and the areas of the first region I and the second region II in the direction parallel to the substrate 101 may be the same or different.

[0045] In some embodiments, referring to Figures 1 and 2, a contact plug CT is further provided between the first power array 1041 and the second power array 1042. The contact plug CT is located in the first region I and is used to connect the power line Vdd of the first power array 1041 to the power line Vdd of the second power array 1042, or to connect the ground line Vss of the first power array 1041 to the ground line Vss of the second power array 1042.

[0046] In some embodiments, the shape of the contact plug CT can be set as a rectangle, square, circle, polygon, star, or other shape as needed, and is not limited thereto. The number of contact plug CTs can also be set as an integer as needed, for example, 1, 2, 3...10, and is not limited thereto. The materials of the contact plug CTs include, but are not limited to, one or more of copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or alloys thereof.

[0047] In some embodiments, referring to Figures 1 and 2, a capacitor structure 108 is disposed in the second region II, with the lower electrode 1081 of the capacitor structure 108 connected to the power line Vdd of the first power array 1041 and the upper electrode 1084 of the capacitor structure 108 connected to the ground line Vss of the second power array 1042; or, the lower electrode 1081 of the capacitor structure 108 is connected to the ground line Vss of the first power array 1041 and the upper electrode 1084 of the capacitor structure 108 is connected to the power line Vdd of the second power array 1042. For example, the second power array 1042, the capacitor structure 108, and the contact plug CT are all disposed within the insulating layer 106, wherein the insulating layer 106 includes a first barrier layer 1061, a first insulating layer 1062, a second barrier layer 1063, and a second insulating layer 1064, for isolating and supporting the second power array 1042, the capacitor structure 108, and the contact plug CT, wherein the material of the first barrier layer 1061 and the second barrier layer 1063 may include silicon nitride (SiN), and the material of the first insulating layer 1062 and the second insulating layer 1063 may include silicon oxide (SiO2). The capacitor structure 108 includes a lower electrode 1081, a dielectric layer 1082, a barrier layer 1083, and an upper electrode 1084 stacked sequentially from bottom to top. The materials of the lower electrode 1081 and the upper electrode 1084 of the capacitor structure 108 may include cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and molybdenum (Mo), metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tungsten nitride (…). The dielectric layer 1082 may include one or more of the following: WN, and the material of the dielectric layer 1082 may include one or more of the following: metal oxide (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3 and TiO2, and may have a single-layer structure or a multi-layer structure; the barrier layer 1083 may include one or more of the following: titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN) and tungsten nitride (WN)).

[0048] By integrating the capacitor structure 108 into the power supply network layer 104, the voltage regulation effect can be improved without adding an additional capacitor structure, thereby reducing the size of the semiconductor structure. On the other hand, since the power supply network 104 can be directly connected to the capacitor structure 108 internally, the power supply path is shortened, thereby reducing the transmission resistance and further enhancing the stability and reliability of the power supply network.

[0049] In some embodiments, referring to Figures 1 and 2, the number of power lines Vdd and ground lines Vss in the first power array 1041 is the same, and the number of power lines Vdd and ground lines Vss in the second power array 1042 is the same, in order to maintain the balance of the circuit, ensure that the current distribution between the power lines Vdd and ground lines Vss is uniform, thereby reducing voltage drop and signal interference, which is beneficial to maintaining the stability and reliability of the circuit.

[0050] In some embodiments, referring to Figures 1 and 2, the spacing W between adjacent power lines Vdd and ground lines Vss ranges from 0.1 to 1.5 μm, which helps to reduce the size of the circuit and avoid crosstalk between power lines Vdd and ground lines Vss, thereby achieving the best performance and cost balance of the semiconductor structure 10.

[0051] Accordingly, another embodiment of this disclosure provides a method for fabricating a semiconductor structure. Figure 3 is a flowchart of a semiconductor fabrication method provided in one embodiment of this disclosure; Figure 4 is another flowchart of a semiconductor fabrication method provided in one embodiment of this disclosure; Figure 5 is yet another flowchart of a semiconductor fabrication method provided in one embodiment of this disclosure; Figures 6 to 13 are cross-sectional views of a portion of the semiconductor structure along the AA' direction in Figure 1, corresponding to each step of a semiconductor fabrication method provided in one embodiment of this disclosure. The method for fabricating the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0052] Referring to Figure 3, one embodiment of this disclosure provides a method for fabricating a semiconductor structure 10, comprising:

[0053] S100 provides a substrate 101, in which a device layer 103, a buried power rail BPR, and a through-silicon via 102 are formed. The through-silicon via 102 is connected to the device layer 103 through the buried power rail BPR.

[0054] In some embodiments, referring to Figures 6-7, a device layer 103, a buried power rail (BPR), and a through-silicon via (TSV) 102 are formed in the substrate 101, including: forming the TSV 102 in the substrate 101, the TSV 102 penetrating a first surface S1 and a second surface S2 of the substrate 101; and sequentially forming the buried power rail (BPR) and the device layer 103 on the second surface S2 of the substrate 101. Exemplarily, the material of the substrate 101 can be single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V group compounds. A patterned substrate 101 is used to deposit conductive material within the substrate 101 to form a through-silicon via (TSV) 102, which penetrates the first surface S1 and the second surface S2 of the substrate 101. A buried power rail (BPR) and a device layer 103 are then formed on the substrate with the TPV 102. In other embodiments, the device layer 103 and the buried power rail (BPR) may be formed first, followed by the formation of the TPV 102. The formation order is not limited here. Active devices such as transistors or diodes, or passive devices such as capacitors, inductors, and resistors, may be formed within the device layer 103. The buried power rail (BPR) may also be formed within the substrate 101 as an interconnect for applying power or ground voltage. Specifically, after the devices within the device layer 103 are formed, an opening is formed by patterning the device layer 103, and conductive material is deposited within the opening, followed by chemical mechanical polishing.

[0055] In some embodiments, referring to FIG7, after forming a device layer 103 in the substrate 101, a signal interconnect layer SL is further formed on the device layer 103 for connecting the device layer 103 with external control signals or input / output signals. The signal interconnect layer SL can be fabricated by a damascus process to form a signal interconnect layer SL having multiple layers of metal and multiple layers of dielectric material. The material of the signal interconnect layer SL may include one or more of copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn) or alloys thereof.

[0056] In S200, a power network layer 104 and a capacitor structure 108 are formed on a substrate 101. The power network layer 104 includes at least one first power array 1041 and at least one second power array 1042. The first power array 1041 is connected to a buried power rail (BPR) through a through-silicon via (TSV) 102. The capacitor structure 108 is formed between the first power array 1041 and the second power array 1042, and is connected to the first power array 1041 and the second power array 1042 through its lower electrode 1081 and upper electrode 1084, respectively.

[0057] In some embodiments, referring to FIGS. 2-4 and FIG. 8-13, the step of forming a power network layer 104 and a capacitor structure 108 on a substrate 101 includes:

[0058] Substrate 101 has a first surface S1 and a second surface S2. An isolation layer 105 is deposited on the first surface S1 of substrate 101. A first power array 1041 is deposited within the patterned isolation layer 105. The first power array 1041 extends along a first direction Y and includes at least two power lines Vdd and at least two ground lines Vss. The deposition process of the isolation layer 105 includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electrochemical deposition (ECD). The material of the isolation layer 105 can be silicon oxide (SiO2). The formation process of the first power array 1041 includes, but is not limited to, CVD, PVD, ALD, and ECD. The material of the first power array 1041 can include one or more of copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or alloys thereof.

[0059] S220 deposits an insulating layer 106 on the isolation layer 105 and the first power array 1041, and patterns the insulating layer 106. The patterned insulating layer 106 exposes part of the power line Vdd and ground line Vss of the first power array 1041.

[0060] In S230, a capacitor structure 108, a contact plug CT, and a second power array 1042 are sequentially formed within the patterned insulating layer 106. The second power array 1042 extends along the second direction X and includes at least two power lines Vdd and at least two ground lines Vss. The first direction Y intersects the second direction X in a direction parallel to the substrate 101. The intersection of the first direction Y and the second direction X in a direction parallel to the substrate 101 can be perpendicular or set to intersect at other angles as needed, which is not limited here. The projection portions of the first power array 1041 and the second power array 1042 in the direction perpendicular to the substrate 101 overlap. The contact plug CT and the capacitor structure 108 are connected between the first power array 1041 and the second power array 1042. The power network layer 104 can be composed of at least one first power array 1041 and at least one second power array 1042. The planes where the different power arrays are located are parallel to the substrate 101 and located in different layers. The second power array 1042 can be disposed above the first power array 1041, and the projections of the first power array 1041 and the second power array 1042 in the direction perpendicular to the substrate 101 have intersecting portions.

[0061] In some embodiments, referring to Figures 2-5 and 8-13, the insulating layer 106 includes a first barrier layer 1061, a first insulating layer 1062, a second barrier layer 1063, and a second insulating layer 1064. A capacitor structure 108, a contact plug CT, and a second power supply array 1042 are sequentially formed within the patterned insulating layer 106, including:

[0062] S2310 deposits to form a first barrier layer 1061 and a first insulating layer 1062, and patterns the first barrier layer 1061 and the first insulating layer 1062 to form a first trench 107, the first trench 107 exposing a portion of the power line Vdd or ground line Vss of the first power array 1041.

[0063] S2320 deposits in the first trench 107 sequentially from bottom to top to form a lower electrode 1081, a dielectric layer 1082, a barrier layer 1083, and an upper electrode 1084. The lower electrode 1081, dielectric layer 1082, barrier layer 1083, and upper electrode 1084 constitute a capacitor structure 108. The lower electrode 1081 is connected to the power line Vdd or ground line Vss of the first power array 1041.

[0064] S2330 deposits to form a second barrier layer 1063 and a second insulating layer 1064, and patterns the first barrier layer 1061, the first insulating layer 1062, the second barrier layer 1063 and the second insulating layer 1064 to form a second trench 109. The second trench 109 exposes a portion of the power line Vdd or ground line Vss of the first power array 1041 and the upper electrode 1084 of the capacitor structure 108.

[0065] S2340 deposits conductive material within the second trench 109 to form the contact plug CT and the second power array 1042. Exemplarily, the processes for depositing the first barrier layer 1061, the first insulating layer 1062, the second barrier layer 1063, and the second insulating layer 1064 include, but are not limited to, CVD, PVD, and ALD. The processes for depositing the lower electrode 1081, the dielectric layer 1082, the barrier layer 1083, and the upper electrode 1084 include, but are not limited to, CVD, PVD, ALD, and ECD. The patterning process can be dry etching or photomask etching. The material of the first insulating layer 1062 and the second insulating layer 1063 may include silicon oxide (SiO2), and the material of the first barrier layer 1061 and the second barrier layer 1063 may include silicon nitride (SiN). The material of the lower electrode 1081 and the upper electrode 1084 of the capacitor structure 108 may include cobalt. The dielectric layer 1082 may be made of one or more of the following: (Co), titanium (Ti), nickel (Ni), tungsten (W), and molybdenum (Mo); and metal nitrides (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tungsten nitride (WN)). The dielectric layer 1082 may be made of one or more of the following: metal oxides (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, and may have a single-layer or multi-layer structure). The barrier layer 1083 may be made of one or more of the following: titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), and tungsten nitride (WN)).

[0066] In some embodiments, the lower electrode 1081 of the capacitor structure 108 is connected to the power line Vdd of the first power array 1041, and the upper electrode 1084 of the capacitor structure 108 is connected to the ground line Vss of the second power array 1042; or, the lower electrode 1081 of the capacitor structure 108 is connected to the ground line Vss of the first power array 1041, and the upper electrode 1084 of the capacitor structure 108 is connected to the power line Vdd of the second power array 1042.

[0067] In some embodiments, the contact plug CT is used to connect the power line Vdd of the first power array 1041 to the power line Vdd of the second power array 1042, or to connect the ground line Vss of the first power array 1041 to the ground line Vss of the second power array 1042.

[0068] In some embodiments, the semiconductor structure 10 may include a memory device, such as a non-volatile memory device, including at least one of flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and resistive random access memory (RRAM). For example, flash memory includes NAND flash memory or V-NAND flash memory. In some embodiments, the memory device includes a volatile memory device, such as dynamic random access memory (DRAM) or static random access memory (SRAM). The memory semiconductor chip includes a semiconductor device, which includes multiple individual devices of various types. These multiple individual devices include various microelectronic devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) containing CMOS transistors, system-on-a-scale integrated circuits (LSIs), active devices, or passive devices.

[0069] In summary, the embodiments of this disclosure improve voltage regulation by integrating the capacitor structure into the power supply network without the need for additional capacitor structures, thereby reducing the size of the chip. On the other hand, since the power supply network can be directly connected to the capacitor structure internally, the power supply path is shortened, thereby reducing transmission resistance and further enhancing the stability and reliability of the power supply network.

[0070] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: The substrate (101) includes a device layer (103), a buried power rail (BPR), and a through silicon via (102), wherein the through silicon via (102) is connected to the device layer (103) through the buried power rail (BPR); A power network layer (104) is disposed on the substrate (101). The power network layer (104) includes at least one first power array (1041) and at least one second power array (1042). The first power array (1041) is connected to the buried power rail (BPR) through the through silicon via (102). A capacitor structure (108) is disposed between the first power array (1041) and the second power array (1042), and is connected to the first power array (1041) and the second power array (1042) respectively through the lower electrode (1081) and the upper electrode (1084) of the capacitor structure (108).

2. The semiconductor structure of claim 1, wherein, The first power array (1041) extends along a first direction (Y), and the second power array (1042) extends along a second direction (X). The first direction (Y) and the second direction (X) intersect in a direction parallel to the substrate (101). The projections of the first power array (1041) and the second power array (1042) in a direction perpendicular to the substrate (101) have overlapping portions.

3. The semiconductor structure of claim 2, wherein, Both the first power array (1041) and the second power array (1042) include at least two power lines (Vdd) and at least two ground lines (Vss). The at least two power lines (Vdd) and at least two ground lines (Vss) of the first power array (1041) are parallel to each other and staggered along the second direction (X). The at least two power lines (Vdd) and at least two ground lines (Vss) of the second power array (1042) are parallel to each other and staggered along the first direction (Y).

4. The semiconductor structure of claim 3, wherein, The overlapping portion of the projection of the first power array (1041) and the second power array (1042) in a direction perpendicular to the substrate (101) includes at least one first region (I) and at least one second region (II). The first region (I) is the overlapping portion of the projection of the power line (Vdd) of the first power array (1041) and the power line (Vdd) of the second power array (1042) in a direction perpendicular to the substrate (101), and the overlapping portion of the projection of the ground line (Vss) of the first power array (1041) and the ground line (Vss) of the second power array (1042) in a direction perpendicular to the substrate (101). The second region (II) is the portion where the projection of the ground line (Vss) of the first power array (1041) and the power line (Vdd) of the second power array (1042) overlaps in a direction perpendicular to the substrate (101), and the portion where the projection of the power line (Vdd) of the first power array (1041) and the ground line (Vss) of the second power array (1042) overlaps in a direction perpendicular to the substrate (101).

5. The semiconductor structure of claim 4, wherein, A contact plug (CT) is also provided between the first power array (1041) and the second power array (1042). The contact plug (CT) is located in the first region (I) and is used to connect the power line (Vdd) of the first power array (1041) to the power line (Vdd) of the second power array (1042) or to connect the ground line (Vss) of the first power array (1041) to the ground line (Vss) of the second power array (1042).

6. The semiconductor structure of claim 4, wherein, The capacitor structure (108) is disposed in the second region (II). The lower electrode (1081) of the capacitor structure (108) is connected to the power line (Vdd) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the ground line (Vss) of the second power array (1042); or, the lower electrode (1081) of the capacitor structure (108) is connected to the ground line (Vss) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the power line (Vdd) of the second power array (1042).

7. The semiconductor structure of claim 3, wherein, The first power array (1041) has the same number of power lines (Vdd) and ground lines (Vss), and the second power array (1042) has the same number of power lines (Vdd) and ground lines (Vss).

8. The semiconductor structure of claim 7, wherein, The spacing between adjacent power lines (Vdd) and ground lines (Vss) ranges from 0.1 to 1.5 μm.

9. A method for fabricating a semiconductor structure, characterized in that, include: A substrate (101) is provided, wherein a device layer (103), a buried power rail (BPR) and a through silicon via (102) are formed therein, and the through silicon via (102) is connected to the device layer (103) through the buried power rail (BPR). A power network layer (104) and a capacitor structure (108) are formed on the substrate (101). The power network layer (104) includes at least one first power array (1041) and at least one second power array (1042). The first power array (1041) is connected to the buried power rail (BPR) through the through silicon via (102). The capacitor structure (108) is formed between the first power array (1041) and the second power array (1042) and is connected to the first power array (1041) and the second power array (1042) through the lower electrode (1081) and the upper electrode (1084) of the capacitor structure (108), respectively.

10. The preparation method according to claim 9, characterized in that, The step of forming the power network layer (104) and capacitor structure (108) on the substrate (101) includes: The substrate (101) has a first surface (S1) and a second surface (S2). An isolation layer (105) is formed on the first surface (S1) of the substrate (101). A first power array (1041) is formed within the patterned isolation layer (105). The first power array (1041) extends along a first direction (Y) and includes at least two power lines (Vdd) and at least two ground lines (Vss). An insulating layer (106) is deposited on the isolation layer (105) and the first power array (1041), and the insulating layer (106) is patterned. The patterned insulating layer (106) exposes part of the power line (Vdd) and the ground line (Vss) of the first power array (1041). Within the patterned insulating layer (106), the capacitor structure (108), the contact plug (CT), and the second power array (1042) are sequentially formed. The second power array (1042) extends along a second direction (X) and includes at least two power lines (Vdd) and at least two ground lines (Vss). The first direction (Y) and the second direction (X) intersect in a direction parallel to the substrate (101). The projection portions of the first power array (1041) and the second power array (1042) in a direction perpendicular to the substrate (101) coincide. The contact plug (CT) and the capacitor structure (108) are connected between the first power array (1041) and the second power array (1042).

11. The preparation method according to claim 10, characterized in that, The lower electrode (1081) of the capacitor structure (108) is connected to the power line (Vdd) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the ground line (Vss) of the second power array (1042); or, the lower electrode (1081) of the capacitor structure (108) is connected to the ground line (Vss) of the first power array (1041), and the upper electrode (1084) of the capacitor structure (108) is connected to the power line (Vdd) of the second power array (1042).

12. The preparation method according to claim 10, characterized in that, The contact plug (CT) is used to connect the power line (Vdd) of the first power array (1041) to the power line (Vdd) of the second power array (1042), or to connect the ground line (Vss) of the first power array (1041) to the ground line (Vss) of the second power array (1042).

13. The preparation method according to claim 10, characterized in that, The insulating layer (106) includes a first barrier layer (1061), a first insulating layer (1062), a second barrier layer, and a second insulating layer. The capacitor structure (108), the contact plug (CT), and the second power array (1042) are sequentially formed within the patterned insulating layer (106), including: The first barrier layer (1061) and the first insulating layer (1062) are deposited and patterned to form a first trench (107) that exposes a portion of the power line (Vdd) or the ground line (Vss) of the first power array (1041). The lower electrode (1081), dielectric layer (1082), barrier layer (1083) and upper electrode (1084) are sequentially deposited in the first trench (107). The lower electrode (1081), dielectric layer (1082), barrier layer (1083) and upper electrode (1084) constitute the capacitor structure (108). The lower electrode (1081) is connected to the power line (Vdd) or ground line (Vss) of the first power array (1041). The second barrier layer (1063) and the second insulating layer (1064) are deposited and formed. The first barrier layer (1061), the first insulating layer (1062), the second barrier layer (1063) and the second insulating layer (1064) are patterned to form a second trench (109). The second trench (109) exposes a portion of the power line (Vdd) or the ground line (Vss) of the first power array (1041) and the upper electrode (1084) of the capacitor structure (108). Conductive material is deposited in the second trench (109) to form the contact plug (CT) and the second power array (1042).

14. The preparation method according to claim 10, characterized in that, The device layer (103), the buried power rail (BPR), and the through-silicon via (102) are formed within the substrate (101), including: The through-silicon via (102) is formed in the substrate (101), and the through-silicon via (102) penetrates the first surface (S1) and the second surface (S2) of the substrate (101); The buried power rail (BPR) and the device layer (103) are sequentially formed on the second surface (S2) of the substrate (101).

15. The preparation method according to claim 14, characterized in that, After the device layer (103) is formed in the substrate (101), a signal interconnect layer (SL) is also formed on the device layer (103).

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