Chip structure, chip stack structure and preparation method therefor, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a chip structure, a chip stack structure and a preparation method therefor, and an electronic device, used for reducing resistance-capacitance delay. The chip stack structure comprises a first chip structure and a second chip structure which are stacked and electrically connected. The first chip structure comprises a first active layer, a first wiring layer, and a second wiring layer which are sequentially stacked. The second wiring layer is arranged on the side of the first wiring layer close to the second chip structure. The first wiring layer comprises a first dielectric layer and a first metal wiring located in the first dielectric layer; the second wiring layer comprises a second dielectric layer and a second metal wiring located in the second dielectric layer; and the line width of the second metal wiring is greater than that of the first metal wiring. The first chip structure further comprises a first signal line located in the second wiring layer, and the line width of the first signal line is greater than that of the first metal wiring. The second chip structure comprises a second active layer, a third wiring layer, and a fourth wiring layer which are sequentially stacked.

Description

Chip structure, chip stacking structure and its fabrication method, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411540946.7, filed with the State Intellectual Property Office of China on October 30, 2024, entitled “Chip Structure, Chip Stacking Structure and Preparation Method Thereof, Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a chip structure, a chip stacking structure and its fabrication method, and an electronic device. Background Technology

[0003] With the development of electronic technology, the functions of electronic devices are becoming increasingly diverse and comprehensive, leading to a growing demand for the evolution and iteration of high-end chips. The integration of chips continues to increase, with a trend towards integrating chips that perform different functions into electronic devices. This also increases the demand for chip integration on integrated circuits within electronic devices, making multi-chip integration and packaging a trend.

[0004] However, as the integration of chips increases, new challenges arise for the signal transmission rate and the bandwidth density of signal transmission within the chip. Summary of the Invention

[0005] This application provides a chip structure, a chip stacking structure, a method for fabricating the same, and an electronic device.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] A first aspect of this application provides a chip stacking structure, including a first chip structure and a second chip structure stacked and electrically connected. The first chip structure includes a first active layer, a first wiring layer, and a second wiring layer stacked sequentially; the second wiring layer is disposed on the side of the first wiring layer near the second chip structure. The first wiring layer includes a first dielectric layer and a first metal wiring within the first dielectric layer, and the second wiring layer includes a second dielectric layer and a second metal wiring within the second dielectric layer, wherein the linewidth of the second metal wiring is greater than the linewidth of the first metal wiring. The first chip structure also includes a first signal line located on the second wiring layer, wherein the linewidth of the first signal line is greater than the linewidth of the first metal wiring. The second chip structure includes a second active layer, a third wiring layer, and a fourth wiring layer stacked sequentially; the fourth wiring layer is disposed on the side of the third wiring layer near the first chip structure. The fourth wiring layer and the second wiring layer are electrically connected.

[0008] The chip stacking structure provided in this application embodiment is an example where a first chip structure and a second chip structure are electrically connected through a second wiring layer and a fourth wiring layer. The first wiring layer connects the circuit structures within the first chip structure, and the second wiring layer provides power to the circuit structures within the first chip structure. The linewidth of the second metal wiring in the second wiring layer is greater than the linewidth of the first metal wiring in the first wiring layer to meet the power supply requirements of the circuit structures within the first chip structure. As a result, the RC delay of the second metal wiring is lower than that of the first metal wiring. Therefore, placing the first signal line within the second wiring layer can reduce the RC delay during signal transmission in the first signal line, improve the interconnection rate of the chip stacking structure, and thus enhance the performance of the chip stacking structure.

[0009] In one possible implementation, the third wiring layer includes a third dielectric layer and a third metal wiring located within the third dielectric layer, and the fourth wiring layer includes a fourth dielectric layer and a fourth metal wiring located within the fourth dielectric layer, wherein the linewidth of the fourth metal wiring is greater than the linewidth of the third metal wiring. The second chip structure also includes a second signal line located in the fourth wiring layer; the linewidth of the second signal line is greater than the linewidth of the third metal wiring. Thus, the third wiring layer is used to connect the circuit structure within the second chip structure, and the fourth wiring layer is used to provide power to the circuit structure within the second chip structure. The linewidth of the fourth metal wiring in the fourth wiring layer is greater than the linewidth of the third metal wiring in the third wiring layer to meet the power supply requirements of the circuit structure within the second chip structure. Compared to the RC delay of the third metal wiring, the RC delay of the fourth metal wiring is lower. Therefore, placing the second signal line within the fourth wiring layer can reduce the RC delay during signal transmission in the second signal line and improve the interconnection speed of the chip stack structure. Furthermore, the first signal line is distributed in the first chip structure, and the second signal line is distributed in the second chip structure. The signal transmission is now split between two chip structures, instead of being transmitted within a single chip structure. This reduces the linewidth of the signal line transmitted within a single chip structure, thereby reducing the required signal line width. Compared to having the signal line located within a single chip structure, transmitting the signal within one chip structure improves the utilization of the wiring layers in the chip stack structure (utilizing both the second and fourth wiring layers for transmission). Additionally, it reduces the resource consumption of the second or fourth metal wiring layers, minimizes the impact on power signals originally transmitted in those layers, improves power integrity, and ultimately enhances the performance and reliability of the chip stack structure.

[0010] In one possible implementation, the chip stack structure further includes a first connection portion and a second connection portion; the first connection portion and the second connection portion penetrate through the second wiring layer and the fourth wiring layer; a first end of the second signal line is connected to the first connection portion, and a second end of the second signal line is connected to the second connection portion. In this way, the ports of the second signal line and the first signal line are both located within the same chip structure (the first chip structure).

[0011] In one possible implementation, the linewidths of the first signal line and the second signal line are equal. This ensures that the signal is distributed equally across both lines, minimizing the impact on power integrity.

[0012] In one possible implementation, the chip stack structure includes multiple first signal lines and multiple second signal lines; the spacing between adjacent first signal lines is equal to the spacing between adjacent second signal lines. This ensures that the signal transmission distribution is identical in the first and second signal lines, reducing the RC delay between the first and second sub-signal lines, minimizing the impact on power integrity, increasing the interconnect speed of the chip stack structure, and thus improving its performance.

[0013] In one possible implementation, the number of first signal lines is equal to the number of second signal lines. This ensures that the signal transmission distribution is identical across the first and second signal lines, reducing RC delays between the first and second sub-signal lines, minimizing impact on power integrity, increasing the interconnect speed of the chip stack structure, and ultimately improving the performance of the chip stack structure.

[0014] In one possible implementation, the projections of the first signal line onto the first wiring layer and the projections of the second signal line onto the first wiring layer are alternately arranged. This provides one implementation method for the signal line.

[0015] In one possible implementation, the projection of the first signal line onto the first wiring layer is called the first projection, and the projection of the second signal line onto the first wiring layer is called the second projection. There is a first spacing between the second projections on adjacent sides of the first projection, and a second spacing between the second projections on the other side of the first projection. The first spacing and the second spacing are equal. In this way, the signal transmission distribution is the same in the first and second signal lines, resulting in minimal impact on power integrity.

[0016] In one possible implementation, the projection of the first signal line onto the first wiring layer coincides with the projection of the second signal line onto the first wiring layer. This provides one implementation method for the signal line.

[0017] In one possible implementation, the width of the first signal line is less than or equal to the width of the second metal wiring. This way, the first signal line is located within the second wiring layer, minimizing its impact on the signal transmitted through the second metal wiring.

[0018] In one possible implementation, the line width of the second signal line is less than or equal to the line width of the fourth metal wiring. This way, the second signal line is located within the fourth wiring layer, minimizing its impact on the signal transmitted through the fourth metal wiring.

[0019] In one possible implementation, the chip stack structure further includes a transmitter and a receiver; the transmitter and receiver are each electrically connected to a first signal line. Both the transmitter and receiver are located within the first active layer of the first chip structure. This arrangement, with the transmitter and receiver situated within the same chip structure, facilitates signal transmission within the chip stack structure.

[0020] A second aspect of this application provides a chip structure including a first active layer, a first wiring layer, and a second wiring layer stacked sequentially. The first wiring layer includes a first dielectric layer and a first metal wiring located within the first dielectric layer; the second wiring layer includes a second dielectric layer and a second metal wiring located within the second dielectric layer; the linewidth of the second metal wiring is greater than the linewidth of the first metal wiring. The chip structure also includes a first signal line located in the second wiring layer, the linewidth of the first signal line being greater than the linewidth of the first metal wiring.

[0021] The chip structure provided in this application embodiment includes a first wiring layer for connecting circuit structures within the chip structure, and a second wiring layer for providing power to the circuit structures within the chip structure. The linewidth of the second metal wiring in the second wiring layer is greater than the linewidth of the first metal wiring in the first wiring layer to meet the power supply requirements of the circuit structures within the chip structure. As a result, the RC delay of the second metal wiring is lower than that of the first metal wiring. Therefore, placing the first signal line within the second wiring layer can reduce the RC delay during signal transmission in the first signal line, improve the interconnection rate of the chip stack structure, and thus improve the performance of the chip stack structure.

[0022] A third aspect of the embodiments of this application provides an electronic device, including a chip stacking structure of any one of the first aspects or a chip structure of the second aspect and a printed circuit board, wherein the chip stacking structure and the printed circuit board are electrically connected; and the chip structure is electrically connected to the printed circuit board.

[0023] The electronic device provided in the third aspect of the embodiments of this application includes the chip stacking structure of any one of the first aspects or the chip structure of the second aspect. Its beneficial effects are the same as those of the chip stacking structure or the chip structure, and will not be repeated here.

[0024] A fourth aspect of this application provides a method for fabricating a chip stacked structure, comprising: forming a first active layer, a first wiring layer, and a second wiring layer stacked sequentially; the first wiring layer comprising a first dielectric layer and a first metal wiring located within the first dielectric layer; the second wiring layer comprising a second dielectric layer and a second metal wiring located within the second dielectric layer; the linewidth of the second metal wiring being greater than the linewidth of the first metal wiring; forming a first signal line within the second wiring layer, the linewidth of the first signal line being greater than the linewidth of the first metal wiring; forming a second chip structure; the second chip structure comprising a second active layer, a third wiring layer, and a fourth wiring layer stacked sequentially; and electrically connecting the second wiring layer and the fourth wiring layer.

[0025] The chip stacking structure fabrication method provided in this application embodiment involves an electrical connection between a first chip structure and a second chip structure via a second wiring layer and a fourth wiring layer. The first wiring layer connects the circuit structures within the first chip structure, and the second wiring layer provides power to the circuit structures within the first chip structure. The linewidth of the second metal wiring in the second wiring layer is greater than the linewidth of the first metal wiring in the first wiring layer to meet the power supply requirements of the circuit structures within the first chip structure. As a result, the RC delay of the second metal wiring is lower than that of the first metal wiring. Therefore, placing the first signal line within the second wiring layer reduces the RC delay during signal transmission in the first signal line, improves the interconnection rate of the chip stacking structure, and thus enhances the performance of the chip stacking structure.

[0026] In one possible implementation, the third wiring layer of the circuit structure includes a third dielectric layer and a third metal wiring located within the third dielectric layer; the fourth wiring layer of the circuit structure includes a fourth dielectric layer and a fourth metal wiring located within the fourth dielectric layer; the linewidth of the fourth metal wiring is greater than the linewidth of the third metal wiring. Forming the second chip structure further includes forming a second signal line within the fourth wiring layer, the linewidth of which is greater than the linewidth of the third metal wiring. Thus, the third wiring layer is used to connect the circuit structures within the second chip structure, and the fourth wiring layer is used to provide power to the circuit structures within the second chip structure. The linewidth of the fourth metal wiring in the fourth wiring layer is greater than the linewidth of the third metal wiring in the third wiring layer to meet the power supply requirements of the circuit structures within the second chip structure. Compared to the RC delay of the third metal wiring, the RC delay of the fourth metal wiring is lower. Therefore, placing the second signal line within the fourth wiring layer can reduce the RC delay during signal transmission in the second signal line and improve the interconnection rate of the chip stack structure. Furthermore, the first signal line is distributed in the first chip structure, and the second signal line is distributed in the second chip structure. The signal transmission is now split between two chip structures, instead of being transmitted within a single chip structure. This reduces the linewidth of the signal line transmitted within a single chip structure, thereby reducing the required signal line width. Compared to having the signal line located within a single chip structure, transmitting the signal within one chip structure improves the utilization of the wiring layers in the chip stack structure (utilizing both the second and fourth wiring layers for transmission). Additionally, it reduces the resource consumption of the second or fourth metal wiring layers, minimizes the impact on power signals originally transmitted in those layers, improves power integrity, and ultimately enhances the performance and reliability of the chip stack structure.

[0027] A fifth aspect of this application provides a method for fabricating a chip structure, comprising: forming a first active layer, a first wiring layer, and a second wiring layer sequentially stacked; the first wiring layer of the circuit structure includes a first dielectric layer and a first metal wiring located within the first dielectric layer of the circuit structure; the second wiring layer of the circuit structure includes a second dielectric layer and a second metal wiring located within the second dielectric layer of the circuit structure; the linewidth of the second metal wiring of the circuit structure is greater than the linewidth of the first metal wiring of the circuit structure; and forming a first signal line within the second wiring layer of the circuit structure, wherein the linewidth of the first signal line of the circuit structure is greater than the linewidth of the first metal wiring of the circuit structure.

[0028] The chip structure fabrication method provided in this application embodiment includes a first wiring layer for connecting circuit structures within the chip structure and a second wiring layer for providing power to the circuit structures within the chip structure. The linewidth of the second metal wiring in the second wiring layer is greater than the linewidth of the first metal wiring in the first wiring layer to meet the power supply requirements of the circuit structures within the chip structure. As a result, the RC delay of the second metal wiring is lower than that of the first metal wiring. Therefore, placing the first signal line within the second wiring layer can reduce the RC delay during signal transmission in the first signal line, improve the interconnection rate of the chip stack structure, and thus enhance the performance of the chip stack structure. Attached Figure Description

[0029] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0030] Figure 2 is a schematic diagram of a chip structure carried on a PCB according to an embodiment of this application;

[0031] Figure 3 is a schematic diagram of a chip structure provided in an embodiment of this application;

[0032] Figure 4A is a schematic diagram of the structure of a first wiring layer provided in an embodiment of this application;

[0033] Figure 4B is a schematic diagram of a second wiring layer provided in an embodiment of this application;

[0034] Figure 5 is a schematic diagram of a chip stacking structure provided in an embodiment of this application;

[0035] Figure 6 is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0036] Figure 7A is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0037] Figure 7B is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0038] Figure 8A is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0039] Figure 8B is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0040] Figure 9A is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0041] Figure 9B is a schematic diagram of another chip stacking structure provided in an embodiment of this application;

[0042] Figure 10A is a magnified view of a portion of Figure 9BA;

[0043] Figure 10B is a schematic diagram of the first chip structure in Figure 10A;

[0044] Figure 10C is a schematic diagram of the second chip structure in Figure 10A;

[0045] Figure 11A is another enlarged view of part A in Figure 9B;

[0046] Figure 11B is a schematic diagram of the first chip structure in Figure 11A;

[0047] Figure 11C is a schematic diagram of the second chip structure in Figure 11A;

[0048] Figure 12A is another enlarged view of a part of Figure 9B;

[0049] Figure 12B is a top view of Figure 12A;

[0050] Figure 13 is a schematic flowchart of a method for fabricating a chip stacking structure according to an embodiment of this application;

[0051] Figures 14A-14E are schematic diagrams illustrating the process of fabricating a chip stacking structure according to an embodiment of this application;

[0052] Figure 15 is a schematic flowchart of a chip structure fabrication method provided in an embodiment of this application.

[0053] In the attached diagram, 1-electronic device; 2-display module; 3-middle frame; 4-housing; 5-cover plate; 10-chip structure; 11-packaging board; 12-chip; 13-adapter board; 131-Through hole; 21-First chip structure; 22-Second chip structure; 31-Dielectric layer; 100-Chip stack structure; 110-First active layer; 120-Second active layer; 121-Bump; 210-First wiring layer; 220-Second wiring layer; 230-Third wiring layer; 240-Fourth wiring layer; 310-First dielectric layer; 320-Second dielectric layer; 330-Third dielectric layer; 340-Fourth dielectric layer; 410-First metal wiring; 420-Second metal wiring; 430-Third metal wiring; 440-Fourth metal wiring; 510-First signal line; 520-Second signal line; 521-First connector; 522-Second connector; 61-Transmitter; 62-Receiver; 63-Relay. Detailed Implementation

[0054] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0055] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0056] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0057] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0058] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "electrical connection" should be interpreted broadly. For example, "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium (such as an electrical material).

[0059] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0060] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial terminal products include ATMs, self-service terminals, etc. This application does not impose special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following embodiments all use mobile phones as an example for illustration.

[0061] An example of the structure of an electronic device is shown in Figure 1. The electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0062] The display module 2 has a light-emitting side that allows the display image to be seen and a non-light-emitting side that is opposite to the light-emitting side. The back of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0063] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0064] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0065] The aforementioned display module 2 includes a display panel (DP).

[0066] The aforementioned electronic device 1 also includes chip structures disposed on a printed circuit board, such as a processor (CPU) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuit (PMIC), a memory chip (e.g., high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, NAND flash, an image sensor chip, an artificial intelligence (AI) chip, and a gaming graphics card chip. The PCB is used to carry the aforementioned chip structures and to complete signal interaction with the aforementioned chip structures.

[0067] As exemplarily shown in Figure 2, the chip structure 10 is mounted on a printed circuit board. Typically, the chip 12 with functional circuitry is electrically connected to the package board 11, and then electrically connected to the PCB through the package board 11.

[0068] Among them, the packaging board 11 is the carrier of the chip structure 10, and serves as the connector between the chip 12 and the PCB to realize the connection between the chip 12 and the PCB.

[0069] External pins (solder balls or pads) are provided on both the first and second surfaces of the package board 11. External pins on one surface of the package board 11 are connected to the chip 12, and external pins on the other surface are connected to the PCB.

[0070] For example, external pins on the first surface of the package board 11 are connected to the chip 12, and external pins on the second surface of the package board 11 are connected to the PCB.

[0071] The chip 12 is electrically connected to the packaging board 11. The chip 12 can be a bare chip or a packaged chip. This application embodiment does not limit this, and can be reasonably set according to the actual situation.

[0072] For example, at least one transistor is integrated on the chip, which may be a field-effect transistor (FET).

[0073] It is clarified here that field-effect transistors can include planar transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs), and can also include three-dimensional transistors such as fin field-effect transistors (FinFETs), gate all-around field-effect transistors (GAAFETs), or forksheet field-effect transistors (forksheet FETs or FSFETs). This application does not limit the scope of the field-effect transistors.

[0074] With the development of semiconductor technology, the functions of electronic devices 1 are becoming increasingly diverse and comprehensive. This necessitates the integration of chips capable of different functions within the electronic device 1, thus increasing the demand for chip integration on the printed circuit board within the device. While improving the performance of IC dies is necessary, the requirements for chip structures are also becoming increasingly stringent. As the demand for chip computing power increases, the scale of system-on-chip (SoC) is gradually increasing, posing new challenges to the speed, bandwidth density, and latency of network-on-chip (NOC) systems.

[0075] Based on this, this application provides a chip structure, as shown in FIG3. The chip structure 10 includes an active layer 110, a first wiring layer 210 and a second wiring layer 220 stacked sequentially.

[0076] The active layer 110 is used to form the circuit structure of the chip structure 10. The circuit structure may include electronic components such as transistors, resistors, capacitors, or inductors.

[0077] The first wiring layer 210 and the second wiring layer 220 are used to electrically connect electronic components in the circuit structure.

[0078] For example, the first wiring layer 210 includes a first dielectric layer 310 and a first metal wiring 410 located within the first dielectric layer 310. That is, the first wiring layer 210 includes a first dielectric layer 310 and a first metal wiring 410. The first metal wiring 410 is located within the first dielectric layer 310. The second wiring layer 220 includes a second dielectric layer 320 and a second metal wiring 420 located within the second dielectric layer 320. That is, the second wiring layer 220 includes a second dielectric layer 320 and a second metal wiring 420. The second metal wiring 420 is located within the second dielectric layer 320.

[0079] As shown in Figures 4A and 4B, the line width w2 of the second metal wiring 420 is greater than the line width w1 of the first metal wiring 410.

[0080] It is understandable that the dimension of a metal wiring along a direction perpendicular to its extension direction is its linewidth. In other words, the linewidth is the width of the metal wiring. The linewidth is used to indicate the conductivity of the metal wiring.

[0081] For example, the fabrication of chip structure 10 may include two parts: a front-end of line (FEOL) process and a back-end of line (BEOL) process. The front-end process is used to form active or passive devices on the wafer, while the back-end process is used to form metal wiring that connects different devices or layers on the wafer. For instance, the first active layer 110 is formed in the front-end process, while the first wiring layer 210 and the second wiring layer 220 are both formed in the back-end process.

[0082] In this embodiment, the first wiring layer 210 can be regarded as the middle and lower layer metal of the chip structure 10, and the second wiring layer 220 can be regarded as the higher layer metal of the chip structure 10.

[0083] For example, the first wiring layer 210 can be used to connect the circuit structure within the chip structure 10, and the second wiring layer 220 is used to provide power to the circuit structure within the chip structure 10. For example, the device may include at least one of active and passive devices. Active devices may include electronic components such as transistors, vacuum tubes, and integrated circuits. Passive devices may include electronic components such as resistors, capacitors, or inductors. The linewidth of the second metal wiring 420 in the second wiring layer 220 is greater than the linewidth of the first metal wiring 410 in the first wiring layer 210 to meet the power supply requirements of the circuit structure within the chip structure 10. Compared to the RC delay of the first metal wiring 410, the RC delay of the second metal wiring 420 is lower.

[0084] In this embodiment, the second wiring layer 220 further includes a first signal line 510. The line width w0 of the first signal line 510 is greater than the line width w1 of the first metal wiring 410.

[0085] For example, the line width w0 of the first signal line 510 can be equal to the line width w2 of the second metal wiring 420. Alternatively, for example, the line width w0 of the first signal line 510 can also be less than the line width w2 of the second metal wiring 420. This embodiment does not limit this, as long as the line width w0 of the first signal line 510 is greater than the line width w1 of the first metal wiring 410.

[0086] In this way, the first signal line 510 is located within the second wiring layer 220, that is, the first signal line 510 is located within the high-layer metal of the chip structure 10. The signal is transmitted within the second wiring layer 220 of the chip structure 10, and the linewidth of the first signal line 510 is greater than the linewidth of the first metal wiring 410. Therefore, the interconnect RC delay can be reduced, and the performance of the chip structure 10 can be improved.

[0087] As the requirements for chip packaging structures become increasingly stringent, new challenges arise for the development of planar printed circuit boards (PCBs). This drives the evolution of PCB packaging from planar to vertically stacked packaging, thereby enabling 3D IC packaging and 2.5D IC packaging technologies. For example, chips with different functions, such as microelectromechanical system (MEMS) chips, radio frequency communication chips, passive device chips, and processor chips, can all be vertically stacked and integrated using these packaging technologies. This maximizes the utilization of vertical integration space, thereby improving the integration density of the PCB.

[0088] In some embodiments, a 2.5D packaged chip stacking structure is illustrated. As shown in FIG5, the chip stacking structure 100 includes a chip structure 10, an adapter plate 13, and a package plate 11. The adapter plate 13 has a plurality of vias 131, which penetrate the adapter plate 13 along the thickness direction of the adapter plate 13. Exemplarily, the end face of the via 131 is flush with the surface of the adapter plate 13.

[0089] As shown in Figure 5, the chip structure 10 is disposed on the adapter plate 13 (e.g., the first surface a1). Exemplarily, the second wiring layer 220 of the chip structure 10 is disposed facing the adapter plate 13. The chip structure 10 is electrically connected to the first end b1 of the via 131. The package plate 11 is disposed on the side of the adapter plate 13 away from the chip 12.

[0090] Referring again to Figure 5, the chip stack structure 100 also includes a bump 121 connecting the adapter plate 13 and the package plate 11. The bump 121 is disposed on the second surface a2 of the adapter plate 13 opposite to the first surface a1, and is electrically connected to the second end b2 of the via 131.

[0091] The bump 121 may include, for example, a structure made of metal solder such as a solder ball, a bump, a copper pillar, and a controlled collapse chip connection bump (C4 bump).

[0092] This application embodiment does not limit the number of chip structures 10 included in the chip stack structure 100. For example, the chip stack structure 100 includes one chip structure 10. Alternatively, the chip stack structure 100 may also include multiple chip structures 10. For example, multiple chip structures 10 are arranged side by side on the adapter board 13. Alternatively, multiple chip structures 10 are stacked and then arranged on the adapter board 13.

[0093] In other embodiments, a 3D packaged chip stacking structure is illustrated. As shown in FIG6, the chip stacking structure 100 includes a first chip structure 21, a second chip structure 22, and a packaging board 11.

[0094] For example, a first chip structure 21, a second chip structure 22, and a package board 11 are stacked. The first chip structure 21 and the second chip structure 22 are electrically connected and disposed on the package board 11. For example, the first chip structure 21 is disposed on the side of the second chip structure 22 away from the package board 11. Alternatively, the first chip structure 21 is disposed between the second chip structure 22 and the package board 11. This embodiment does not limit this; it is sufficient that the first chip structure 21 and the second chip structure 22 are bonded together and disposed on the package board 11.

[0095] As shown in Figure 6, the first chip structure 21 includes a first active layer 110, a first wiring layer 210, and a second wiring layer 220 stacked sequentially. The second wiring layer 220 is disposed on the side of the first wiring layer 210 near the second chip structure 22.

[0096] The first active layer 110 is used to form the circuit structure of the first chip structure 21. The circuit structure may include electronic components such as transistors, resistors, capacitors, or inductors.

[0097] The first wiring layer 210 and the second wiring layer 220 are used to electrically connect electronic components in the circuit structure.

[0098] For a description of the first wiring layer 210 and the second wiring layer 220 in the above embodiments, please refer to the description of the first wiring layer 210 and the second wiring layer 220, which will not be repeated here.

[0099] Referring again to Figure 6, the second chip structure 22 includes a second active layer 120, a third wiring layer 230 and a fourth wiring layer 240 stacked in sequence.

[0100] For example, the second wiring layer 220 of the first chip structure 21 and the fourth wiring layer 240 of the second chip structure 22 are disposed opposite to each other. The fourth wiring layer 240 is disposed on the side of the third wiring layer 230 near the first chip structure 21, and the second wiring layer 220 is disposed on the side of the first wiring layer 210 near the second chip structure 22. The first chip structure 21 and the second chip structure 22 are electrically connected through the second wiring layer 220 and the fourth wiring layer 240. For example, a dielectric layer 31 is provided between the second wiring layer 220 and the fourth wiring layer 240, and the dielectric layer 31 serves as a bonding layer for hybrid bonding (HB) or fused bonding processes.

[0101] Alternatively, for example, the fourth wiring layer 240 is disposed on the side of the third wiring layer 230 closer to the first chip structure 21, and the second wiring layer 220 is disposed on the side of the first wiring layer 210 away from the second chip structure 22.

[0102] Alternatively, for example, the fourth wiring layer 240 is disposed on the side of the third wiring layer 230 away from the first chip structure 21, and the second wiring layer 220 is disposed on the side of the first wiring layer 210 close to the second chip structure 22.

[0103] Alternatively, for example, the fourth wiring layer 240 is disposed on the side of the third wiring layer 230 away from the first chip structure 21, and the second wiring layer 220 is disposed on the side of the first wiring layer 210 away from the second chip structure 22.

[0104] In this embodiment, the configuration of the first chip structure 21 and the second chip structure 22 is not limited; they can be configured reasonably according to the actual situation.

[0105] The second active layer 120 is used to form the circuit structure of the second chip structure 22. The circuit structure may include electronic components such as transistors, resistors, capacitors, or inductors.

[0106] The third wiring layer 230 and the fourth wiring layer 240 are used to electrically connect electronic components in the circuit structure.

[0107] For example, the third wiring layer 230 includes a third dielectric layer 330 and a third metal wiring 430 located within the third dielectric layer 330. That is, the third wiring layer 230 includes the third dielectric layer 330 and the third metal wiring 430. The third metal wiring 430 is located within the third dielectric layer 330. The fourth wiring layer 240 includes a fourth dielectric layer 340 and a fourth metal wiring 440 located within the fourth dielectric layer 340. That is, the fourth wiring layer 240 includes the fourth dielectric layer 340 and the fourth metal wiring 440. The fourth metal wiring 440 is located within the fourth dielectric layer 340.

[0108] Among them, the line width w2 of the second metal wiring 420 is greater than the line width w1 of the first metal wiring 410, and the line width of the fourth metal wiring 440 is greater than the line width of the third metal wiring 430.

[0109] In this embodiment, the first wiring layer 210 and the third wiring layer 230 can be considered as the middle and lower layers of the chip stack structure 100, and the second wiring layer 220 and the fourth wiring layer 240 can be considered as the higher layers of the chip stack structure 100. For example, the first wiring layer 210 can be considered as the middle and lower layers of the first chip structure 21, and the second wiring layer 220 can be considered as the higher layers of the first chip structure 21. The third wiring layer 230 can be considered as the middle and lower layers of the second chip structure 22, and the fourth wiring layer 240 can be considered as the higher layers of the second chip structure 22. For example, the first wiring layer 210 can be used to connect the circuit structure within the first chip structure 21, and the second wiring layer 220 can be used to provide power to the circuit structure within the first chip structure 21. For example, the device can include at least one of active and passive devices. Active devices can include, for example, electronic components such as transistors, vacuum tubes, and integrated circuits. Passive devices can include, for example, electronic components such as resistors, capacitors, or inductors. The third wiring layer 230 can be used to connect the circuit structure within the second chip structure 22, and the fourth wiring layer 240 is used to provide power to the circuit structure within the first chip structure 21. For example, the devices may include at least one of active and passive devices. Active devices may include, for example, electronic components such as transistors, vacuum tubes, and integrated circuits. Passive devices may include, for example, electronic components such as resistors, capacitors, or inductors.

[0110] The linewidth of the second metal wiring 420 in the second wiring layer 220 is greater than the linewidth of the first metal wiring 410 in the first wiring layer 210 to meet the power supply requirements of the internal circuit structure of the first chip structure 21. Therefore, the RC delay of the second metal wiring 420 is lower than that of the first metal wiring 410. Similarly, the linewidth of the fourth metal wiring 440 in the fourth wiring layer 240 is greater than the linewidth of the third metal wiring 430 in the third wiring layer 230 to meet the power supply requirements of the internal circuit structure of the second chip structure 22. Therefore, the RC delay of the fourth metal wiring 440 is lower than that of the third metal wiring 430.

[0111] As shown in Figure 6, the chip stack structure 100 also includes a first signal line 510. The first signal line 510 is located within the second wiring layer 220.

[0112] At this point, the line width w0 of the first signal line 510 is greater than the line width w1 of the first metal wiring 410. The line width w0 of the first signal line 510 can be equal to the line width w2 of the second metal wiring 420. Alternatively, the line width w0 of the first signal line 510 can also be less than the line width w2 of the second metal wiring 420.

[0113] It is clarified here that the location of the package board 11 is not limited in this embodiment. As shown in FIG6, the package board 11 can be disposed on one side of the first active layer 110 of the first chip structure 21. Alternatively, as shown in FIG7A, the package board 11 can also be disposed on one side of the second active layer 120 of the second chip structure 22. In this way, when the first signal line 510 is disposed in only one chip structure, the first signal line 510 is disposed within the second wiring layer 220 of the first chip structure 21. As shown in FIG6, the first signal line 510 can be disposed in the chip structure (first chip structure 21) away from the package board 11. Alternatively, as shown in FIG7A, the first signal line 510 can also be disposed in the chip structure (first chip structure 21) close to the package board 11.

[0114] In this embodiment of the application, the first signal line 510 included in the chip stack structure 100 can be one or more.

[0115] The first signal line 510 can be located in the second wiring layer 220. Alternatively, the first signal line 510 can also be located within the fourth wiring layer 240, that is, the first signal line 510 is located within the high-layer metal of the first chip structure 21, or the first signal line 510 is located within the high-layer metal of the second chip structure 22. The signal is transmitted within the second wiring layer 220 or the fourth wiring layer 240 of the chip stack structure 100. The linewidth of the first signal line 510 is greater than the linewidth of the first metal wiring 410, and the linewidth of the first signal line 510 is greater than the linewidth of the third metal wiring 430. Therefore, interconnect RC delay can be reduced, and the performance of the chip stack structure 100 can be improved.

[0116] In some embodiments, as shown in FIG7B, the chip stack structure 100 further includes a second signal line 520. The line width of the second signal line 520 is greater than the line width of the third metal wiring 430.

[0117] For example, the line width of the second signal line 520 can be equal to the line width of the fourth metal wiring 440. Alternatively, the line width of the second signal line 520 can also be less than the line width of the fourth metal wiring 440. This embodiment does not limit this, as long as the line width of the second signal line 520 is greater than the line width of the third metal wiring 430.

[0118] In this way, the second signal line 520 is located within the fourth wiring layer 240, that is, within the higher metal layer of the chip structure 10. The signal is transmitted within the fourth wiring layer 240 of the chip structure 10, and the linewidth of the second signal line 520 is greater than the linewidth of the third metal wiring 430. Therefore, interconnect RC delay can be reduced, and the performance of the chip structure 10 can be improved.

[0119] As exemplarily shown in FIG8A, the chip stack structure 100 further includes a first connection portion 521 and a second connection portion 522.

[0120] The first connecting portion 521 and the second connecting portion 522 penetrate the second wiring layer 220 and the fourth wiring layer 240.

[0121] As shown in Figure 8A, the first connection portion 521 and the second connection portion 522 penetrate the dielectric layer 31 along the thickness direction of the first chip structure 21. The two ends of the second signal line 520 are connected to the first connection portion 521 and the second connection portion 522, respectively.

[0122] For example, the first end of the second signal line 520 is connected to the first connection portion 521, and the second end of the second signal line 520 is connected to the second connection portion 522.

[0123] When a signal is transmitted through a signal line, a portion of the signal is transmitted through the first signal line 510, and another portion is transmitted through the second signal line 520. For example, the signal travels from the first chip structure 21 through the first connection portion 521 to the second signal line 520, and then through the second connection portion 522 back to the first chip structure 21. In other words, the signal is transmitted through the second wiring layer 220 of the first chip structure 21 and the fourth wiring layer 240 of the second chip structure 22, respectively.

[0124] In this way, the signal transmission is split from being carried out in only one chip structure to being carried out in two chip structures. This reduces the linewidth of the signal line transmitted in one chip structure, thereby reducing the area width of the first signal line 510 required for signal transmission. Compared to the first signal line 510 being located in one chip structure, signal transmission within one chip structure improves the utilization rate of the wiring layers in the chip stack structure 100 (which utilizes both the second wiring layer 220 and the fourth wiring layer 240 for transmission). Furthermore, it reduces the resource consumption of the second metal wiring 420 or the fourth metal wiring 440, reduces the impact on the power signals originally transmitted in the second wiring layer 220 or the fourth wiring layer 240, improves power integrity, and ultimately enhances the performance of the chip stack structure 100.

[0125] As shown in Figure 8A, the signals transmitted by the signal lines are transmitted in the first signal line 510 and the second signal line 520, respectively.

[0126] For example, the line width of the first signal line 510 is equal to the line width of the second signal line 520.

[0127] In this way, signal transmission can be evenly distributed within the first signal line 510 and the second signal line 520, reducing the impact on the transmission of other signals.

[0128] Referring again to Figure 8A, the chip stack structure 100 also includes a transmitter 61 and a receiver 62. The first signal line 510 and the second signal line 520 are electrically connected to the transmitter 61 and the receiver 62, respectively.

[0129] For example, the transmitting end 61 and the receiving end 62 can be circuit structures composed of electronic components such as transistors, resistors, capacitors or inductors.

[0130] For example, as shown in FIG8B, the transmitting end 61 and the receiving end 62 are located within the same chip structure. For instance, the transmitting end 61 and the receiving end 62 are located in the first active layer 110 of the first chip structure 21. Alternatively, the transmitting end 61 and the receiving end 62 are located in the second active layer 120 of the second chip structure 22.

[0131] It should be noted that, for the sake of illustrating the distribution of the first signal line 510 and the second signal line 520, Figure 8B does not show the specific structure of the first chip structure 21 and the second chip structure 22, nor does it show the dielectric layer 31.

[0132] In some embodiments, the chip stack structure 100 further includes at least one relay terminal 63. The relay terminal 63 is located on the transmission path of the first signal line 510 or the second signal line 520. Exemplarily, the relay terminal 63 may be located within the same chip structure as the transmitting terminal 61 and the receiving terminal 62. As shown in FIG8B, the relay terminal 63 may also be located in the second chip structure 22.

[0133] For example, the relay terminal 63 can be a circuit structure composed of electronic components such as transistors, resistors, capacitors or inductors.

[0134] In this embodiment, the number of relay terminals 63 is not limited, and can be reasonably set according to the length of the first signal line 510 or the second signal line 520.

[0135] In some embodiments, as shown in Figures 9A and 9B, the chip stack structure 100 includes a plurality of first signal lines 510 and a plurality of second signal lines 520. The plurality of first signal lines 510 and the plurality of second signal lines 520 are connected to the transmitting end 61 and the receiving end 62.

[0136] For example, signals from multiple first signal lines 510 are output from the transmitting end 61 and transmitted to the receiving end 62.

[0137] For example, as shown in FIG9B, the first chip structure 21 includes a plurality of first signal lines 510, and the second chip structure 22 includes a plurality of second signal lines 520. The chip stack structure 100 also includes a plurality of first connection portions 521 and a plurality of second connection portions 522. For example, the number of first connection portions 521 and the number of second connection portions 522 correspond to the number of second signal lines 520.

[0138] In some embodiments, the chip stack structure 100 includes a plurality of first signal lines 510 and a plurality of second signal lines 520. The number of first signal lines 510 and the number of second signal lines 520 are the same.

[0139] For example, the distance between adjacent first signal lines 510 is equal to the distance between adjacent second signal lines 520. That is, the spacing between the first signal lines 510 is equal to the spacing between the second signal lines 520. It is clarified here that the spacing is the distance between two adjacent signal lines.

[0140] In this embodiment, the line width and spacing of the first signal line 510 and the second signal line 520 can be adjusted to change the area width of the signal lines, thereby changing the resource occupation of the transmitted signal on the second metal wiring 420 and the fourth metal wiring 440, improving the power integrity problem, and enhancing the performance of the chip stacking structure 100.

[0141] The following examples illustrate the line width and spacing of the first signal line 510 and the second signal line 520, respectively.

[0142] In some embodiments, as shown in FIG10A, which is a partial enlarged view of A in FIG9B, the projection of the first signal line 510 on the first wiring layer 210 and the projection of the second signal line 520 on the first wiring layer 210 coincide. For example, the first signal line 510 has a line spacing d1 and a line width w01, and the second signal line 520 has a line spacing d2 and a line width w02.

[0143] For example, as shown in Figures 10B and 10C, the line spacing d1 of the first signal line 510 is equal to the line spacing d2 of the second signal line 520, and the line width w01 of the first signal line 510 is equal to the line width w02 of the second signal line 520. For ease of explanation, the line spacing d1 of the first signal line 510 and the line spacing d2 of the second signal line 520 are referred to as the first line spacing, and the line width w01 of the first signal line 510 and the line width w02 of the second signal line 520 are referred to as the first line width.

[0144] As shown in Figure 10A, taking four first signal lines 510 and four second signal lines 520 as an example, the width of the signal lines is 4w01+3d1.

[0145] Compared to the case where multiple signal lines are located within the same chip structure, there should be 8 signal lines with a line spacing of d1 and a line width of w01, resulting in a surface width of 8w01 + 7d1. The solution provided in this application embodiment can reduce the surface width of the signal lines by approximately 50%. Therefore, in this application embodiment, while maintaining the line width and line spacing of the signal lines, distributing the signal lines within the first chip structure 21 and the second chip structure 22 can reduce the surface width compared to distributing the signal lines within the same chip structure.

[0146] In other embodiments, as shown in FIG11A, the projection of the first signal line 510 on the first wiring layer 210 coincides with the projection of the second signal line 520 on the first wiring layer 210. For example, the first signal line 510 has a line spacing d3 and a line width w03, and the second signal line 520 has a line spacing d4 and a line width w04.

[0147] For example, as shown in Figures 11B and 11C, the linewidth w03 of the first signal line 510 is equal to the linewidth w04 of the second signal line 520. For ease of explanation, the linewidths w03 of the first signal line 510 and w04 of the second signal line 520 are referred to as the second linewidth. In this case, compared to the previous embodiment, the second linewidth is twice the first linewidth, i.e., w03 = w04 = 2w01 = 2w02.

[0148] Increasing the linewidth of the signal lines can improve the signal transmission quality and thus increase the interconnection rate.

[0149] For example, as shown in Figures 11B and 11C, the third spacing d3 of the first signal line 510 is equal to the fourth spacing d4 of the second signal line 520. For ease of explanation, the spacing d3 of the first signal line 510 and the spacing d4 of the second signal line 520 are referred to as the second spacing. In this case, compared to the previous embodiment, the second spacing is twice the first spacing, that is, d3 = d4 = 2d1 = 2d2.

[0150] In this way, increasing the spacing between signal lines can reduce the impact of signal transmission on other signals and alleviate power integrity issues in signal transmission.

[0151] In some other embodiments, as shown in FIG12A, the projections of the first signal line 510 on the first wiring layer 210 and the projections of the second signal line 520 on the first wiring layer 210 are alternately arranged.

[0152] In other words, the projections of the first signal line 510 onto the first wiring layer 210 and the second signal line 520 onto the first wiring layer 210 are spaced apart. That is, the projections of the first signal line 510 onto the first wiring layer 210 and the second signal line 520 onto the first wiring layer 210 do not coincide. For example, the first signal line 510 has a line spacing d5 and a line width w05, and the second signal line 520 has a line spacing d6 and a line width w06.

[0153] For example, the projection of the first signal line 510 onto the first wiring layer 210 is a first projection, and the projection of the second signal line 520 onto the first wiring layer 210 is a second projection. There is a first spacing between the second projections on the adjacent side of the first projection, and there is a second spacing between the second projections on the adjacent side of the first projection; the first spacing and the second spacing are equal.

[0154] As shown in Figure 12B, the line spacing d5 of the first signal line 510 is the sum of twice the gap size and the line width w06 of the second signal line 520, i.e., d5 = 2m1 + w06. The line spacing d6 of the second signal line 520 is the sum of twice the gap size and the line width w05 of the first signal line 510, i.e., d6 = 2m1 + w05.

[0155] For example, as shown in Figure 12B, the line width w05 of the first signal line 510 is equal to the line width w06 of the second signal line 520. In this case, the line width w05 of the first signal line 510 is equal to the aforementioned first line width, that is, w05 = w06 = w01 = w02.

[0156] Increasing the spacing between signal lines reduces the impact of signal transmission on other signals, alleviates power integrity issues in signal transmission, and thus improves the quality of signal transmission.

[0157] The chip stack structure 100 provided in this application embodiment has a first chip structure 21 and a second chip structure 22 electrically connected through a second wiring layer 220 and a fourth wiring layer 240. In the first chip structure 21, the first wiring layer 210 connects the circuit structures within the first chip structure 21, and the second wiring layer 220 provides power to the circuit structures within the first chip structure 21. The linewidth of the second metal wiring 420 in the second wiring layer 220 is greater than the linewidth of the first metal wiring 410 in the first wiring layer 210 to meet the power supply requirements of the circuit structures within the first chip structure 21. As a result, the RC delay of the second metal wiring 420 is lower than that of the first metal wiring 410. Therefore, the first signal line 510 is disposed within the second wiring layer 220, which can reduce the RC delay, improve the interconnection rate of the chip stack structure 100, and thus improve the performance of the chip stack structure 100. In the second chip structure 22, the third wiring layer 230 connects the circuit structures within the second chip structure 22, and the fourth wiring layer 240 provides power to the circuit structures within the second chip structure 22. The linewidth of the fourth metal wiring 440 in the fourth wiring layer 240 is greater than that of the third metal wiring 430 in the third wiring layer 230 to meet the power supply requirements of the circuit structure within the second chip structure 22. As a result, the RC delay of the fourth metal wiring 440 is lower than that of the third metal wiring 430. Therefore, placing the second signal line 520 within the fourth wiring layer 240 reduces RC delay, increases the interconnection rate of the chip stack structure 100, and thus improves the performance of the chip stack structure 100. Furthermore, with signal lines distributed across the first chip structure 21 and the second chip structure 22, the signal transmission is split between two chip structures instead of being confined to a single chip structure. This reduces the linewidth of the signal line transmitted within a single chip structure, thereby reducing the required signal line width. Compared to a signal line located within a single chip structure, signal transmission within a single chip structure improves the utilization rate of the wiring layers in the chip stack structure 100 (simultaneously utilizing the second wiring layer 220 and the fourth wiring layer 240 for transmission). In addition, it can reduce the resource consumption of the second metal wiring 420 or the fourth metal wiring 440, reduce the impact on the power signals originally transmitted in the second wiring layer 220 or the fourth wiring layer 240, improve power integrity issues, and thus improve the performance and reliability of the chip stack structure 100.

[0158] Based on this, this application also provides a method for fabricating a chip stacking structure, which can be used to form the chip stacking structure in the above embodiments. As shown in Figure 13, the method for fabricating the chip stacking structure includes:

[0159] S11, as shown in Figure 14A, a first active layer 110, a first wiring layer 210, and a second wiring layer 220 are formed in sequence.

[0160] As shown in Figure 14A, the first wiring layer 210 includes a first dielectric layer 310 and a first metal wiring 410 located within the first dielectric layer 310. The second wiring layer 220 includes a second dielectric layer 320 and a second metal wiring 420 located within the second dielectric layer 320. The linewidth of the second metal wiring 420 is greater than the linewidth of the first metal wiring 410.

[0161] For example, the first metal wiring 410 can be formed in the first dielectric layer 310 using the damascus process, and the second metal wiring 420 can be formed in the second dielectric layer 320 using the damascus process.

[0162] For a description of the first active layer 110, the first wiring layer 210, and the second wiring layer 220, please refer to the description of the first active layer 110, the first wiring layer 210, and the second wiring layer 220 in the first chip structure 21 in the above embodiments, which will not be repeated here.

[0163] S12. As shown in Figure 14B, a first signal line 510 is formed in the second wiring layer 220.

[0164] The line width of the first signal line 510 is greater than the line width of the first metal wiring 410.

[0165] In this way, the first signal line 510 is formed within the second wiring layer 220, which can reduce interconnect resistance and capacitance delay and improve the performance of the chip stack structure 100.

[0166] In some embodiments, the first signal line 510 and the second metal wiring 420 can be formed in the same process step or in different process steps. This application does not limit this; any reasonable configuration can be made according to the actual situation.

[0167] It is clarified here that the first active layer 110, the first wiring layer 210 and the second wiring layer 220 can constitute the first chip structure 21.

[0168] S13, as shown in Figure 14C, forms the second chip structure 22.

[0169] As shown in Figure 14C, the second chip structure 22 includes a second active layer 120, a third wiring layer 230 and a fourth wiring layer 240 stacked in sequence.

[0170] The third wiring layer 230 includes a third dielectric layer 330 and a third metallic wiring 430 located within the third dielectric layer 330. The fourth wiring layer 240 includes a fourth dielectric layer 340 and a fourth metallic wiring 440 located within the fourth dielectric layer 340. The line width of the fourth metallic wiring 440 is greater than the line width of the third metallic wiring 430.

[0171] For example, a third metal wiring 430 can be formed in the third dielectric layer 330 using a damascus process, and a fourth metal wiring 440 can be formed in the fourth dielectric layer 340 using a damascus process.

[0172] For an introduction to the second chip structure 22, please refer to the description of the second chip structure 22 in the above embodiments, which will not be repeated here.

[0173] S14. As shown in Figure 14D, a second signal line 520 is formed in the fourth wiring layer 240.

[0174] The line width of the second signal line 520 is greater than that of the third metal wiring 430.

[0175] In this way, the second signal line 520 is formed within the fourth wiring layer 240, which can reduce interconnect resistance and capacitance delay and improve the performance of the chip stack structure 100.

[0176] In some embodiments, the second signal line 520 and the fourth metal wiring 440 can be formed in the same process step or in different process steps. This application does not limit this; any appropriate configuration can be made according to the actual situation.

[0177] S15. As shown in Figure 14E, the second wiring layer 220 and the fourth wiring layer 240 are electrically connected.

[0178] In this way, the first chip structure 21 and the second chip structure 22 are electrically connected.

[0179] In some embodiments, after the first chip structure 21 and the second chip structure 22 are electrically connected, the fabrication method further includes: placing the first chip structure 21 and the second chip structure 22 on a packaging board (not shown in FIG14E) and bonding them to the packaging board.

[0180] This application also provides a method for fabricating a chip structure, which can be used to form the chip structure in the above embodiments. As shown in Figure 15, the method for fabricating the chip structure includes:

[0181] S21, forming a first active layer 110, a first wiring layer 210 and a second wiring layer 220 that are stacked sequentially.

[0182] The materials and formation methods of the first active layer 110, the first wiring layer 210 and the second wiring layer 220 in step S21 are the same as those in step S1, and can be referred to the relevant description of S11 above.

[0183] S22. As shown in Figure 14B, a first signal line 510 is formed in the second wiring layer 220.

[0184] The method for forming the first signal line 510 in step S22 is the same as in step S1, and you can refer to the relevant description of S12 above.

[0185] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip stacking structure, characterized in that, include: A first chip structure and a second chip structure are stacked together; the first chip structure and the second chip structure are electrically connected. The first chip structure includes a first active layer, a first wiring layer, and a second wiring layer stacked sequentially; the second wiring layer is disposed on the side of the first wiring layer close to the second chip structure; the first wiring layer includes a first dielectric layer and a first metal wiring located within the first dielectric layer; the second wiring layer includes a second dielectric layer and a second metal wiring located within the second dielectric layer; the linewidth of the second metal wiring is greater than the linewidth of the first metal wiring. The first chip structure further includes a first signal line; the first signal line is located in the second wiring layer; the line width of the first signal line is greater than the line width of the first metal wiring. The second chip structure includes a second active layer, a third wiring layer, and a fourth wiring layer stacked sequentially; the fourth wiring layer is disposed on the side of the third wiring layer close to the first chip structure; the fourth wiring layer and the second wiring layer are electrically connected.

2. The chip stacking structure according to claim 1, characterized in that, The third wiring layer includes a third dielectric layer and a third metal wiring located within the third dielectric layer; the fourth wiring layer includes a fourth dielectric layer and a fourth metal wiring located within the fourth dielectric layer; the line width of the fourth metal wiring is greater than the line width of the third metal wiring; The second chip structure further includes a second signal line; the second signal line is located in the fourth wiring layer; the line width of the second signal line is greater than the line width of the third metal wiring.

3. The chip stacking structure according to claim 2, characterized in that, The chip stack structure further includes a first connection portion and a second connection portion; both the first connection portion and the second connection portion penetrate the second wiring layer and the fourth wiring layer; the first end of the second signal line is connected to the first connection portion, and the second end of the second signal line is connected to the second connection portion.

4. The chip stacking structure according to claim 2 or 3, characterized in that, The line width of the first signal line is equal to the line width of the second signal line.

5. The chip stacking structure according to any one of claims 2-4, characterized in that, The chip stack structure includes a plurality of first signal lines and a plurality of second signal lines; the spacing between adjacent first signal lines is equal to the spacing between adjacent second signal lines.

6. The chip stacking structure according to claim 5, characterized in that, The number of the first signal lines is equal to the number of the second signal lines.

7. The chip stacking structure according to any one of claims 2-6, characterized in that, The projections of the first signal line onto the first wiring layer and the projections of the second signal line onto the first wiring layer are alternately arranged.

8. The chip stacking structure according to claim 7, characterized in that, The projection of the first signal line on the first wiring layer is the first projection, and the projection of the second signal line on the first wiring layer is the second projection; there is a first spacing between the second projections on the side adjacent to the first projection, and there is a second spacing between the second projections on the other side adjacent to the first projection; the first spacing and the second spacing are equal.

9. The chip stacking structure according to any one of claims 2-6, characterized in that, The projection of the first signal line onto the first wiring layer coincides with the projection of the second signal line onto the first wiring layer.

10. The chip stacking structure according to any one of claims 1-9, characterized in that, The width of the first signal line is less than or equal to the width of the second metal wiring.

11. The chip stacking structure according to any one of claims 1-10, characterized in that, The chip stack structure further includes a transmitter and a receiver; the transmitter and the receiver are electrically connected to the first signal line respectively, and both the transmitter and the receiver are located within the first active layer of the first chip structure.

12. A chip structure, characterized in that, include: The first active layer, the first wiring layer, and the second wiring layer are stacked sequentially. The first wiring layer includes a first dielectric layer and a first metal wiring located within the first dielectric layer; the second wiring layer includes a second dielectric layer and a second metal wiring located within the second dielectric layer; the line width of the second metal wiring is greater than the line width of the first metal wiring; A first signal line is located in the second wiring layer, and the line width of the first signal line is greater than the line width of the first metal wiring.

13. An electronic device, characterized in that, It includes the chip stacking structure according to any one of claims 1-11 or the chip structure and printed circuit board according to claim 12; the chip structure or the chip stacking structure and the printed circuit board are electrically connected.

14. A method for fabricating a chip stacking structure, characterized in that, include: A first active layer, a first wiring layer, and a second wiring layer are formed and stacked sequentially; the first wiring layer includes a first dielectric layer and a first metal wiring located within the first dielectric layer; the second wiring layer includes a second dielectric layer and a second metal wiring located within the second dielectric layer; the line width of the second metal wiring is greater than the line width of the first metal wiring; A first signal line is formed within the second wiring layer, and the line width of the first signal line is greater than the line width of the first metal wiring. A second chip structure is formed; the second chip structure includes a second active layer, a third wiring layer and a fourth wiring layer stacked sequentially. The second wiring layer and the fourth wiring layer are electrically connected.

15. The method for fabricating a chip stacking structure according to claim 14, characterized in that, The third wiring layer includes a third dielectric layer and a third metal wiring located within the third dielectric layer; the fourth wiring layer includes a fourth dielectric layer and a fourth metal wiring located within the fourth dielectric layer; The line width of the fourth metal wiring is greater than the line width of the third metal wiring; The formation of the second chip structure also includes: A second signal line is formed within the fourth wiring layer, and the line width of the second signal line is greater than the line width of the third metal wiring.

16. A method for fabricating a chip structure, characterized in that, include: A first active layer, a first wiring layer, and a second wiring layer are formed and stacked sequentially; the first wiring layer includes a first dielectric layer and a first metal wiring located within the first dielectric layer; the second wiring layer includes a second dielectric layer and a second metal wiring located within the second dielectric layer; the line width of the second metal wiring is greater than the line width of the first metal wiring; A first signal line is formed within the second wiring layer, the line width of the first signal line being greater than the line width of the first metal wiring.

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