Shielded-gate trench power device and preparation method therefor

Abstract

The present invention relates to the technical field of semiconductors, and more specifically, relates to a shielded-gate trench power device and a preparation method therefor. The method comprises: preparing a semiconductor wafer to be processed; depositing gate polysilicon on the upper surface of an epitaxial layer and a trench structure of the semiconductor wafer, such that a recess is formed above the trench structure; etching the gate polysilicon in the recess until an oxide layer above source polysilicon is reached, so as to form two sub-gates, wherein an inter-gate trench is formed between the two sub-gates; planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed; forming an oxide-film dielectric layer, which covers the oxide layer covering the upper surface of the epitaxial layer, and the gate polysilicon; and planarizing the oxide-film dielectric layer, so as to obtain a flat surface of the oxide-film dielectric layer. The shielded-gate trench power device and the preparation method therefor provided by the present invention enable the adjustment of the gate-source overlap area, thereby reducing the gate-source capacitance, and increasing the degree of freedom in device preparation.

Description

A shielded gate trench power device and its fabrication method Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a shielded gate trench power device and its fabrication method. Background Technology

[0002] Shielded gate trench (SGT) MOSFETs are advanced field-effect transistors that combine the advantages of trench MOSFETs and shielded gates. They are widely used in electric vehicles, renewable energy conversion, and high-efficiency motor drives, demonstrating their importance in modern electronic devices.

[0003] Compared to traditional trench MOSFETs, shielded gate trench MOSFETs achieve lower on-resistance and switching losses by introducing shielded gate technology. To further reduce the switching losses of SGT power devices, the structure of the gate and shielded gate can be optimized to reduce the impact of various parasitic capacitances.

[0004] In SGT power devices, parasitic capacitance mainly consists of three parts: gate-source capacitance Cgs, gate-drain capacitance Cgd, and drain-source capacitance Cds. The presence of these parasitic capacitances directly affects the switching losses, speed, and efficiency of the device. Therefore, how to effectively reduce these parasitic capacitances has become an important issue in SGT device design.

[0005] In the prior art, although some progress has been made in reducing parasitic capacitance in SGT power devices, no effective solution has yet been found for reducing parasitic capacitance, especially gate-source capacitance Cgs, in shielded gate trench (SGT) devices, which can be flexibly adjusted according to design requirements. Summary of the Invention

[0006] The purpose of this invention is to provide a shielded gate trench power device and its fabrication method, which solves the problem of high switching power consumption of existing SGT power devices.

[0007] Another objective of this invention is to provide a shielded gate trench power device and its fabrication method, which solves the problem of high parasitic capacitance in existing SGT power devices.

[0008] Another objective of this invention is to provide a shielded gate trench power device and its fabrication method, which solves the problem of high gate-source capacitance Cgs in existing SGT power devices.

[0009] To achieve the above objectives, the present invention provides a method for fabricating a shielded gate trench power device, comprising the following steps:

[0010] A semiconductor wafer is prepared for processing. The semiconductor wafer includes at least a substrate layer, an epitaxial layer, and a trench structure. The epitaxial layer is on the upper surface of the substrate layer, the trench structure is inside the epitaxial layer, the trench structure is filled with source polysilicon, and the trench structure is covered with an oxide layer above and around the source polysilicon and on the upper surface of the epitaxial layer.

[0011] Gate polysilicon deposition is performed on the upper surface of the epitaxial layer and the trench structure of the semiconductor wafer, so that a groove is formed above the trench structure;

[0012] The gate polysilicon within the groove is etched until the oxide layer above the source polysilicon is reached to form two sub-gates, with an inter-gate trench formed between the two sub-gates.

[0013] The gate polysilicon is planarized until the oxide layer on the surface of the epitaxial layer is exposed;

[0014] An oxide film dielectric layer is formed, covering the oxide layer on the upper surface of the epitaxial layer and the gate polysilicon;

[0015] The oxide film dielectric layer is planarized to obtain a smooth surface of the oxide film dielectric layer.

[0016] In some embodiments, the step of etching the gate polysilicon within the trench until reaching the oxide layer above the source polysilicon to form two sub-gates further includes:

[0017] The gate polysilicon within the groove is etched using a dry anisotropic etching process until the oxide layer above the source polysilicon is reached to form two sub-gates, and / or

[0018] The gate polysilicon in the inter-gate trench is laterally etched using an isotropic etching process to adjust the lateral structure of the inter-gate trench.

[0019] In some embodiments, the polysilicon etching selectivity ranges from 50:1 to 100:1, and / or

[0020] The isotropic selection ratio is 1:1.

[0021] In some embodiments, the preparation of the semiconductor wafer to be processed further includes:

[0022] Provides a substrate layer for a semiconductor wafer and an epitaxial layer on the surface of the substrate layer;

[0023] The etched trench structure is in the epitaxial layer;

[0024] An oxide layer is formed at the edge of the trench structure;

[0025] The source polysilicon is filled in the middle of the trench structure;

[0026] An oxide layer is formed, covering the source polysilicon above and around it, as well as the upper surface of the epitaxial layer.

[0027] In some embodiments, in the step of preparing the semiconductor wafer to be processed, a high-density plasma deposition process for forming an inter-gate oxide layer or a thermal oxidation growth process for forming an inter-gate oxide layer is used to form an oxide layer.

[0028] In some embodiments, after the step of depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure to form a groove above the trench structure, the method further includes: forming a sacrificial layer above the gate polysilicon; and etching the sacrificial layer until the gate polysilicon in the groove is exposed.

[0029] After the step of etching the gate polysilicon within the groove until reaching the oxide layer above the source polysilicon, the method further includes: removing the sacrificial layer.

[0030] In some embodiments, the step of etching the sacrificial layer until the gate polysilicon within the trench is exposed further includes:

[0031] The sacrificial layer is etched using a dry anisotropic etching process until the gate polysilicon in the trench is exposed.

[0032] In some embodiments, the sacrificial layer is a deposited film generated by chemical vapor deposition, and the sacrificial layer is removed by dry etching or wet etching.

[0033] In some embodiments, the sacrificial layer includes a nitride film and an oxide film;

[0034] When the sacrificial layer is a nitride film, the sacrificial layer is removed by wet etching with hot phosphoric acid.

[0035] When the sacrificial layer is an oxide film, it is removed by wet etching with hydrofluoric acid.

[0036] In some embodiments, after the step of planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed, the method further includes:

[0037] An inter-gate oxide layer is formed on the surface of the gate polysilicon, wherein the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer.

[0038] In some embodiments, a chemical mechanical polishing process is used for planarization.

[0039] In some embodiments, an oxide film dielectric layer is formed using a chemical vapor deposition process.

[0040] In some embodiments, an oxide film dielectric layer is formed using a sub-pressure vapor phase deposition process, so that a cavity is formed in the middle of the inter-gate trench.

[0041] In some embodiments, after the step of planarizing the oxide film dielectric layer to obtain a flat surface of the oxide film dielectric layer, the method further includes:

[0042] A double contact hole is formed at the sub-gate location, and the double contact hole connects to an electrode to bring out the external circuitry of the power device.

[0043] To achieve the above objectives, the present invention provides a shielded gate trench type power device, which is prepared by the above-described method for preparing a shielded gate trench type power device.

[0044] This invention proposes a shielded gate trench power device and its fabrication method. After depositing polysilicon gate, the groove formed above the trench structure is used as a self-aligned etching window to perform anisotropic etching on the polysilicon gate to form two sub-gates. An isotropic etching process is then used to laterally etch the trench between the gates. According to different design requirements, the amount of isotropic etching can be selectively adjusted to change the overlap area between the gate and the source and the shielded gate, thereby obtaining an SGT power device with low gate-source capacitance Cgs in an adjustable manner. Attached Figure Description

[0045] The above and other features, properties and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings and embodiments, in which the same reference numerals always denote the same features, wherein:

[0046] Figure 1 illustrates the steps of a method for fabricating a shielded gate trench power device according to an embodiment of the present invention;

[0047] Figure 2a shows a schematic cross-sectional structure of the device after step S1 is completed in the embodiment shown in Figure 1;

[0048] Figure 2b shows a schematic cross-sectional structure of the device after step S2 is completed in the embodiment shown in Figure 1;

[0049] Figure 2c shows a schematic cross-sectional structure of the device after step S3 is completed in the embodiment shown in Figure 1;

[0050] Figure 2d shows a schematic cross-sectional structure of the device after step S4 is completed in the embodiment shown in Figure 1;

[0051] Figure 2e shows a schematic cross-sectional structure of the device after step S5 in the embodiment shown in Figure 1.

[0052] Figure 2f shows a schematic cross-sectional structure of the device after step S6 is completed in the embodiment shown in Figure 1;

[0053] Figure 2g shows a schematic cross-sectional structure of the device after step S7 in the embodiment shown in Figure 1.

[0054] Figure 2h shows a schematic cross-sectional structure of the device after step S8 in the embodiment shown in Figure 1;

[0055] Figure 2i shows a schematic cross-sectional structure of the device after step S9 is completed in the embodiment shown in Figure 1;

[0056] Figure 2j shows a schematic cross-sectional structure of the device after step S10 is completed in the embodiment shown in Figure 1;

[0057] Figure 2k shows a schematic cross-sectional structure of the device after step S11 is completed in the embodiment shown in Figure 1;

[0058] Figure 21 shows a schematic cross-sectional view of the device after step S12 is completed in the embodiment shown in Figure 1.

[0059] The meanings of the labels in the figures are as follows: 11 Epitaxial layer; 12 Substrate layer; 13 Trench structure; 14 Source polysilicon; 15 Oxide layer; 21 Gate polysilicon; 211 Trench; 212 Sub-gate; 213 Inter-gate trench; 22 Sacrificial layer; 23 Inter-gate oxide layer; 24 Oxide dielectric layer; 25 Cavity; 26 Double contact hole; 31 Source metal layer. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0061] Existing technologies have proposed an unetched shielding gate that can reduce gate-source capacitance (Cgs). This is fabricated by completely oxidizing the exposed shielding gate during wet etching, followed by filling it with gate polysilicon. However, this technique is only applicable to processes where a thermal IPO (inter-gate oxide layer) is formed. Furthermore, the width of the polysilicon in this technique is limited and difficult to adjust flexibly, and the inter-gate oxide layer may be too thin, leading to increased gate-source leakage current.

[0062] SGT parasitic capacitance can be further divided into input capacitance Ciss and output capacitance Coss. Among them, the gate-source capacitance Cgs is an important component of the input capacitance Ciss (the input capacitance Ciss equals the gate-source capacitance Cgs plus the gate-drain capacitance Cgd), and affects the turn-on speed of the SGT power device.

[0063] The gate-source capacitance Cgs can be subdivided into four parts: Cgs1 between the gate and the source electrode, Cgs2 between the gate and the N+ source region, Cgs3 between the gate and the P-type body region, and Cgs4 between the gate and the shield gate (which shares a common terminal with the source).

[0064] The present invention proposes a method for fabricating a shielded gate trench power device. By adjusting the device structure, the gate polysilicon is etched to form two sub-gates, and an inter-gate trench is formed between the two sub-gates to reduce the overlap area between the gate and the source and the shielded gate, thereby reducing the gate-source capacitance Cgs. This results in the fabrication of a low gate-source capacitance Cgs SGT power device with other parasitic capacitances remaining unchanged.

[0065] The present invention proposes a method for fabricating a shielded gate trench power device, comprising the following steps:

[0066] A semiconductor wafer is prepared for processing. The semiconductor wafer includes at least a substrate layer, an epitaxial layer, and a trench structure. The epitaxial layer is on the upper surface of the substrate layer, the trench structure is inside the epitaxial layer, the trench structure is filled with source polysilicon, and the trench structure is covered with an oxide layer above and around the source polysilicon and on the upper surface of the epitaxial layer.

[0067] Gate polysilicon deposition is performed on the upper surface of the epitaxial layer and the trench structure of the semiconductor wafer, so that a groove is formed above the trench structure;

[0068] The gate polysilicon within the groove is etched until the oxide layer above the source polysilicon is reached to form two sub-gates, with an inter-gate trench formed between the two sub-gates.

[0069] The gate polysilicon is planarized until the oxide layer on the surface of the epitaxial layer is exposed;

[0070] An oxide film dielectric layer is formed, covering the oxide layer on the upper surface of the epitaxial layer and the gate polysilicon;

[0071] The oxide film dielectric layer is planarized to obtain a smooth surface of the oxide film dielectric layer.

[0072] This invention proposes a method for fabricating a shielded gate trench power device. After depositing polysilicon gate, anisotropic etching is performed on the polysilicon gate using a groove formed above the trench structure as a self-aligned etching window to form two sub-gates. Isotropic etching is then used to laterally etch the inter-gate trench. The amount of isotropic etching is selectively adjusted according to different design requirements to change the overlap area between the gate and source and the shielded gate, thereby allowing for the tunable acquisition of a shielded gate trench power device with low gate-source capacitance Cgs.

[0073] Figure 1 illustrates the steps of a method for fabricating a shielded trench power device according to an embodiment of the present invention. As shown in Figure 1, the method for fabricating a shielded trench power device proposed in this invention includes the following steps:

[0074] Step S1: Prepare the semiconductor wafer to be processed;

[0075] Step S2: Deposit gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure to form a groove above the trench structure;

[0076] Step S3: Form a sacrificial layer over the gate polysilicon;

[0077] Step S4: Etch the sacrificial layer until the gate polysilicon in the trench is exposed;

[0078] Step S5: Use a dry anisotropic etching process to etch the gate polysilicon in the trench until the oxide layer above the source polysilicon is reached to form two sub-gates, and an inter-gate trench is formed between the two sub-gates.

[0079] Step S6: Use an isotropic etching process to perform lateral etching on the gate polysilicon in the inter-gate trench to adjust the lateral structure of the inter-gate trench.

[0080] Step S7: Remove the sacrificial layer;

[0081] Step S8: Planarize the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed;

[0082] Step S9: Form an inter-gate oxide layer on the surface of the gate polysilicon, wherein the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer;

[0083] Step S10: Form an oxide film dielectric layer, which covers the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon;

[0084] Step S11: Planarize the oxide film medium layer to obtain a smooth surface of the oxide film medium layer.

[0085] Step S6 is an optional, preferred step.

[0086] Furthermore, after step S11, the method further includes:

[0087] Step S12: Complete the remaining process according to the standard process flow.

[0088] Figures 2a to 2l show the cross-sectional structure of the device after each step in the embodiment shown in Figure 1. The following describes in detail each step of the fabrication method of the shielded gate trench power device provided in this embodiment with reference to Figures 2a to 2l.

[0089] Step S1: Prepare the semiconductor wafer to be processed;

[0090] Please refer to Figure 2a. The semiconductor wafer to be processed in step S1 includes at least an epitaxial layer 11, a substrate layer 12, and a trench structure 13.

[0091] The epitaxial layer 11 is located in the region above the device structure, on the upper surface of the substrate layer 12. The epitaxial layer 11 is typically made of high-quality silicon and is used to support current transport in the device while ensuring the electrical characteristics of the channel region. It typically has low defect density and high conductivity.

[0092] The substrate layer 12, located at the bottom of the device structure, serves to support the entire device. The substrate layer 12 is typically doped silicon, which determines the overall mechanical strength and conductivity of the device. According to the design requirements of power devices, the substrate layer has a high doping concentration to enhance its current carrying capacity.

[0093] The trench structure 13 consists of multiple vertical trenches etched in the epitaxial layer 11. These trenches are prepared for the subsequent filling of the gate and shielding gate materials, allowing the gate to be deeply embedded in the substrate, improving the control capability of the electric field, and reducing parasitic capacitance.

[0094] In this embodiment, the trench structure 13 is filled with source polysilicon 14, and the trench structure 13 is covered with an oxide layer 15 above and around the source polysilicon 14 and on the upper surface of the epitaxial layer 11.

[0095] The aforementioned characteristics provide a solid foundation for the semiconductor wafer to be processed, ensuring efficient current control and low-loss switching performance in subsequent process steps.

[0096] More specifically, preparing the aforementioned semiconductor wafer to be processed includes the following steps:

[0097] A substrate layer 12 and an epitaxial layer 11 on the surface of the substrate layer 12 are provided for the semiconductor wafer;

[0098] The etched trench structure 13 is in the epitaxial layer 11;

[0099] An oxide layer 15 is formed at the edge of the trench structure 13;

[0100] The source polysilicon 14 is filled in the middle of the trench structure 13;

[0101] An oxide layer 15 is formed, covering the source polysilicon 14 above and around it, as well as the upper surface of the epitaxial layer 11.

[0102] In this embodiment, an oxide layer 15 is formed by a high-density plasma deposition (HDP IPO) molding process or a thermal oxidation growth process for forming an inter-gate oxide layer (Thermal IPO).

[0103] HDP IPO is a molding method that uses high-density plasma deposition to deposit inter-gate oxide layers, resulting in high-quality inter-gate oxide layers and high process flexibility.

[0104] Thermal IPO is an inter-gate oxide layer formed by thermal oxidation growth, and is commonly used as an oxide film for isolating the gate polysilicon and source polysilicon of SGT.

[0105] Step S2: Deposit gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure to form a groove above the trench structure;

[0106] Please refer to Figure 2b. In step S2, gate polysilicon 21 is deposited on the upper surface of the epitaxial layer 11 of the semiconductor wafer and the trench structure 13. During the deposition process, a groove 211 is formed above the trench structure 13. This groove 211 is a structural feature that is naturally formed during the deposition of polysilicon.

[0107] Gate polysilicon deposition can generally be performed using chemical vapor deposition (CVD), direct thermal oxidation growth, a combination of both (thermal oxidation followed by CVD), or furnace tube deposition.

[0108] Step S3: Form a sacrificial layer over the gate polysilicon;

[0109] Please refer to Figure 2c. In step S3, the sacrificial layer 22 refers to a material layer that is temporarily set during the manufacturing process and eventually needs to be removed. It is formed on the gate polysilicon 21.

[0110] In this embodiment, the sacrificial layer 22 is a deposited film generated by chemical vapor deposition (CVD); the deposited film may be a nitride film, an oxide film, or other material layers that can be used as sacrificial layers to block deposition.

[0111] The thickness of the deposited film is related to the structure itself, and the thickness of the deposited film is usually between 500 Å and 2000 Å.

[0112] The size of the etching window can be adjusted by changing the thickness of the deposited film. The etching window refers to the opening used for subsequent etching. When filling the grooves, the deposited film is often relatively thin, with the thickness at the bottom of the groove being only about 50% to 70% of that at the top.

[0113] In step S3, the thickness of the sacrificial layer 22 at the bottom, sidewall, and top of the groove is inconsistent, with the bottom sacrificial layer 22 being thinner than the top layer, approximately 50% to 70% of the top layer thickness.

[0114] Step S4: Etch the sacrificial layer until the gate polysilicon in the trench is exposed;

[0115] Please refer to Figure 2d. Through the dry anisotropic etching process, the thinner sacrificial layer 22 at the bottom of the groove 211 can be completely etched away, while the sacrificial layer 22 on the sidewalls and top of the groove 211 still has a certain thickness, thus forming a specific self-aligned etching window.

[0116] The formation of this etched window is based on the shape and position of the groove itself, without the need for a photomask for positioning. This naturally formed method is called "self-alignment". Since no additional photolithography steps are required, it can improve production efficiency and reduce costs.

[0117] Anisotropic etching refers to the process where the material removal rate is different in different directions during the etching process. In dry anisotropic etching, by selecting appropriate gases and controlling reaction conditions, preferential etching in specific directions can be achieved, thereby forming a structure with vertical sidewalls.

[0118] In this embodiment, the polysilicon etching selectivity ratio is between 50:1 and 100:1, which means that in this step, polysilicon is etched away much faster than other materials. This ensures that the etching process has high selectivity, that is, it effectively etches only the target material while having little impact on other materials.

[0119] Step S5: Etch the gate polysilicon in the groove until the oxide layer above the source polysilicon is reached to form two sub-gates, and an inter-gate trench is formed between the two sub-gates.

[0120] Referring to Figure 2e, in step S5, an anisotropic etching process is used to etch the gate polysilicon 21 in the vertical direction to form two sub-gates 212. A gate trench 213 of a specific depth is formed between the two sub-gates 212. This invention reduces the overlap area between the gate, the shield gate, and the source by using the structure of the two sub-gates and the gate trench between them, thereby reducing the gate-source capacitance Cgs.

[0121] In this embodiment, the polysilicon etching selectivity ratio is between 50:1 and 100:1.

[0122] Step S6: Use an isotropic etching process to perform lateral etching on the gate polysilicon in the inter-gate trench to adjust the lateral structure of the inter-gate trench.

[0123] Please refer to Figure 2f. In step S6, the gate polysilicon 21 on both sides of the gate trench 213 is etched laterally using an isotropic etching process. The etching amount of the lateral etching can be selected according to the structural design requirements, thereby further adjusting the overlap area between the gate, the shield gate, and the source.

[0124] This step primarily involves precisely controlling the isotropic etching process to etch the gate polysilicon, thereby controlling the geometry of the inter-gate trenches. By selectively controlling the etching amount of the isotropic etching, the shape of the sub-gate 212 and the width of the inter-gate trench 213 can be further adjusted to optimize the electrode overlap area.

[0125] Furthermore, in step S6, the isotropic selectivity ratio is 1:1. The polysilicon etching selectivity ratio is between 50:1 and 100:1.

[0126] Isotropic etching refers to etching at the same rate in all directions. This etching method does not distinguish between materials, so the selection ratio is 1:1, which means that the etching rate is the same for all materials.

[0127] Steps S5 and S6 involve operations related to the trench etching process. Based on the analysis of Figures 2e, 2f and 2l, if the etching amount of the inter-gate trench 213 in the horizontal direction increases, the corresponding facing areas of the upper gate polysilicon (sub-gate 212), the lower source polysilicon 214, and subsequently the upper source metal plate will decrease accordingly, resulting in a reduction in the overlap area.

[0128] As shown in Figure 2e, in step S5, the inter-gate trench 213 has been etched, thus forming a small overlapping area. If step S6 is not performed, the overlapping area formed after step S5 will be fixed and cannot be adjusted further.

[0129] In step S6, as shown in Figure 2f, the overlap area between the two sub-gates 212 and the source polysilicon 14 can be further reduced by etching. The shielding gate refers to the source polysilicon 14 below.

[0130] As shown in Figure 21, the area of ​​the source (the upper source metal layer 31 and the lower source polysilicon 14) facing the two sub-gates 212 is greatly reduced.

[0131] Therefore, step S6 is an optional but preferred step because it provides the possibility of further optimizing the overlap area, thereby having a positive impact on the final semiconductor device performance.

[0132] Step S7: Remove the sacrificial layer;

[0133] Referring to Figure 2g, in step S7, the sacrificial layer is removed using either dry etching or wet etching to expose the gate polysilicon 21. Both dry etching and wet etching are techniques used to remove materials during semiconductor manufacturing.

[0134] When the sacrificial layer is a nitride film, it can be removed by wet etching with hot phosphoric acid.

[0135] When the sacrificial layer is an oxide film, it is removed by wet etching with hydrofluoric acid.

[0136] Step S8: Planarize the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed;

[0137] Please refer to Figure 2h. In step S8, a planarization process is performed using chemical mechanical polishing.

[0138] In this step, the gate polysilicon is surface-polished and etched back to remove excess polysilicon, ensuring the flatness of the gate region and preparing it for subsequent processes.

[0139] In this embodiment, the chemical mechanical polishing process stops on the oxide layer 15 on the surface of the epitaxial layer 11. All the gate polysilicon on the surface of the epitaxial layer 11 is removed, while the gate polysilicon (two sub-gates 212) within the trench structure 13 is retained.

[0140] The etch depth range is generally between 500A and 1000A. The etch depth refers to the depth reached during the etching process, and this depth needs to be precisely controlled to meet the requirements of chip design.

[0141] The specific depth of the etch is determined by the design requirements, which means that the grinding depth needs to be precisely controlled according to the actual chip design and manufacturing standards.

[0142] Step S9: Form an inter-gate oxide layer on the surface of the gate polysilicon, wherein the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer;

[0143] Please refer to Figure 2i. In step S9, the gate polysilicon (two sub-gates 212) in the trench structure 13 is oxidized using a high-temperature oxidation process to form an oxide film protective layer on the surface of the gate polysilicon, ensuring electrical isolation in subsequent processes.

[0144] In this embodiment, the protective oxide film layer is the inter-gate oxide layer 23, with a thickness of 200 Å to 500 Å.

[0145] Step S10: Form an oxide film dielectric layer, which covers the oxide layer covering the upper surface of the epitaxial layer and the gate polysilicon;

[0146] Please refer to Figure 2j. In step S10, an oxide film dielectric layer 24 is formed by sub-pressure chemical vapor deposition so that a cavity 25 is formed in the middle of the inter-gate trench 213.

[0147] In this embodiment, sub-pressure vapor deposition technology is used to cover the entire structure surface with a uniform oxide film medium layer as a protective layer for the subsequent mechanical polishing. In other embodiments, other vapor deposition processes can also be used to form the oxide film medium layer 24.

[0148] Sub-pressure chemical vapor deposition is a chemical vapor deposition technique performed under low pressure conditions that can produce uniform and high-quality oxide films.

[0149] Because of the high aspect ratio of this oxide film, meaning its thickness is relatively large compared to its width, an airgap structure can be formed in the middle of the gate polysilicon, between the two sub-gates. This airgap structure helps to release and buffer stress generated within the structure, thereby improving the stability and reliability of the material.

[0150] Step S11: Planarize the oxide film medium layer to obtain a smooth surface of the oxide film medium layer.

[0151] Please refer to Figure 2k. In step S11, the oxide film dielectric layer 24 is subjected to chemical mechanical polishing.

[0152] The purpose of this step is to make the surface of the oxide film dielectric layer 24 smooth, especially the grooved area, so as to facilitate the subsequent preparation of contact holes.

[0153] By precisely controlling the grinding time, it is possible to ensure that the oxide film medium layer maintains a certain thickness after grinding, and this remaining thickness range is set between 500A and 800A.

[0154] Step S12: Complete the remaining process according to the standard process flow.

[0155] Please refer to Figure 2l. In step S12, the subsequent processes are carried out according to the normal process flow to complete the connection of the entire SGT power device structure.

[0156] Furthermore, dual contact holes 26 are formed on the gate bus region, with the positions of the dual contact holes corresponding to the positions of the two sub-gates 212. The dual contact holes 26 are connected to electrodes to connect other external circuits of the power device, ensuring that the device can operate normally.

[0157] The method for fabricating a shielded gate trench power device proposed in this invention adjusts the overlap area between the gate and source electrodes and the shielded gate through fine anisotropic and isotropic etching processes, effectively reducing the gate-source capacitance Cgs and thus improving the device performance.

[0158] Based on the above-mentioned method for fabricating shielded trench power devices, this invention also proposes a shielded trench power device obtained by the above-mentioned method.

[0159] Since the specific structure of the shielded gate trench power device has been described in detail in the preparation method, it will not be described again here.

[0160] The shielded gate trench power device proposed in this invention reduces the overlap area between the gate and source through a shielded gate trench design, thereby lowering the parasitic capacitance Cgs. This optimization is crucial for improving switching speed and reducing power consumption, because a smaller gate-source capacitance results in a faster switching speed, making it perform better in high-frequency applications.

[0161] Furthermore, it is worth emphasizing that the shielded gate trench power device can encompass shielded gate trench MOSFETs, demonstrating the broad application potential of this technology.

[0162] The shielded gate trench power device and its fabrication method provided by this invention have the following beneficial effects:

[0163] 1) This method does not require the use of additional masks and is applicable to two different process routes: medium and high voltage SGT HDP IPO and thermal IPO with larger pitch.

[0164] 2) By adjusting the isotropic etching amount within a certain range, the gate-source overlap area can be adjusted, thereby increasing the degree of freedom in device fabrication;

[0165] 3) It will not affect other parasitic capacitances, thus maintaining the performance of the device;

[0166] 4) A cavity is formed in the middle of the device, which helps to buffer and reduce the stress inside the device.

[0167] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0168] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0169] The above embodiments are provided for those skilled in the art to implement or use the present invention. Those skilled in the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the protection scope of the present invention is not limited to the above embodiments, but should be the maximum scope that conforms to the innovative features mentioned in the claims.

Claims

1. A method for fabricating a shielded gate trench type power device, characterized in that, Includes the following steps: A semiconductor wafer is prepared for processing. The semiconductor wafer includes at least a substrate layer, an epitaxial layer, and a trench structure. The epitaxial layer is on the upper surface of the substrate layer, the trench structure is inside the epitaxial layer, the trench structure is filled with source polysilicon, and the trench structure is covered with an oxide layer above and around the source polysilicon and on the upper surface of the epitaxial layer. Gate polysilicon deposition is performed on the upper surface of the epitaxial layer and the trench structure of the semiconductor wafer, so that a groove is formed above the trench structure; The gate polysilicon within the groove is etched until the oxide layer above the source polysilicon is reached to form two sub-gates, with an inter-gate trench formed between the two sub-gates. The gate polysilicon is planarized until the oxide layer on the surface of the epitaxial layer is exposed; An oxide film dielectric layer is formed, covering the oxide layer on the upper surface of the epitaxial layer and the gate polysilicon; The oxide film dielectric layer is planarized to obtain a smooth surface of the oxide film dielectric layer.

2. The method for fabricating a shielded trench power device according to claim 1, characterized in that, The step of etching the gate polysilicon within the groove until reaching the oxide layer above the source polysilicon to form two sub-gates further includes: The gate polysilicon within the groove is etched using a dry anisotropic etching process until the oxide layer above the source polysilicon is reached to form two sub-gates, and / or The gate polysilicon in the inter-gate trench is laterally etched using an isotropic etching process to adjust the lateral structure of the inter-gate trench.

3. The method for fabricating a shielded trench power device according to claim 2, characterized in that, The polysilicon etching selectivity ranges from 50:1 to 100:1, and / or The isotropic selection ratio is 1:

1.

4. The method for fabricating a shielded trench power device according to claim 1, characterized in that, The semiconductor wafer to be processed further includes: Provides a substrate layer for a semiconductor wafer and an epitaxial layer on the surface of the substrate layer; The etched trench structure is in the epitaxial layer; An oxide layer is formed at the edge of the trench structure; The source polysilicon is filled in the middle of the trench structure; An oxide layer is formed, covering the source polysilicon above and around it, as well as the upper surface of the epitaxial layer.

5. The method for fabricating a shielded gate trench power device according to claim 4, characterized in that, In the step of preparing the semiconductor wafer to be processed, a high-density plasma deposition process for forming an inter-gate oxide layer or a thermal oxidation growth process for forming an inter-gate oxide layer is used to form an oxide layer.

6. The method for fabricating a shielded gate trench power device according to claim 1, characterized in that, After the step of depositing gate polysilicon on the upper surface of the epitaxial layer of the semiconductor wafer and the trench structure to form a groove above the trench structure, the method further includes: forming a sacrificial layer above the gate polysilicon; etching the sacrificial layer until the gate polysilicon in the groove is exposed. After the step of etching the gate polysilicon within the groove until reaching the oxide layer above the source polysilicon, the method further includes: removing the sacrificial layer.

7. The method for fabricating a shielded gate trench type power device according to claim 6, characterized in that, The step of etching the sacrificial layer until the gate polysilicon within the trench is exposed further includes: The sacrificial layer is etched using a dry anisotropic etching process until the gate polysilicon in the trench is exposed.

8. The method for fabricating a shielded gate trench power device according to claim 6, characterized in that, The sacrificial layer is a deposited film generated by chemical vapor deposition, and is removed by dry etching or wet etching.

9. The method for fabricating a shielded gate trench power device according to claim 6, characterized in that, The sacrificial layer includes a nitride film and an oxide film; When the sacrificial layer is a nitride film, the sacrificial layer is removed by wet etching with hot phosphoric acid. When the sacrificial layer is an oxide film, it is removed by wet etching with hydrofluoric acid.

10. The method for fabricating a shielded gate trench power device according to claim 1, characterized in that, After the step of planarizing the gate polysilicon until the oxide layer on the surface of the epitaxial layer is exposed, the method further includes: An inter-gate oxide layer is formed on the surface of the gate polysilicon, wherein the inter-gate oxide layer is not higher than the oxide layer on the surface of the epitaxial layer.

11. The method for fabricating a shielded gate trench power device according to claim 1, characterized in that, Planarization is performed using a chemical mechanical grinding process.

12. The method for fabricating a shielded gate trench power device according to claim 1, characterized in that, An oxide film dielectric layer is formed using a chemical vapor deposition process.

13. The method for fabricating a shielded gate trench power device according to claim 12, characterized in that, An oxide film dielectric layer is formed using a sub-pressure vapor phase deposition process, so that a cavity is formed in the middle of the inter-gate trench.

14. The method for fabricating a shielded gate trench power device according to claim 1, characterized in that, After the step of planarizing the oxide film dielectric layer to obtain a smooth surface of the oxide film dielectric layer, the method further includes: A double contact hole is formed at the sub-gate location, and the double contact hole connects to an electrode to bring out the external circuitry of the power device.

15. A shielded grid trench type power device, characterized in that, It is prepared by the method of any one of claims 1 to 14 for the preparation of a shielded gate trench power device.

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