Matrix data processing method, processor and computer device

Abstract

The embodiments disclosed in the present application relate to the technical field of computers, and particularly relate to a matrix data processing method. The method is applied to a processor configured with a matrix operation unit and a vector operation unit, and comprises: acquiring a first matrix and a second matrix to be subjected to a matrix multiplication operation; determining a first order for rearranging the first matrix, and on the basis of the first order, determining a third matrix corresponding to the first matrix, wherein the third matrix comprises a first matrix block and a second matrix block, the proportion of non-zero elements in the first matrix block is greater than a second threshold value, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold value; and using a matrix operation unit to execute a matrix operation on data of the first matrix block and data of the second matrix, so as to obtain a first operation result, and using a vector operation unit to execute a vector operation on data of the second matrix block and the data of the second matrix, so as to obtain a second operation result. By means of using the present application, the efficiency of executing an SPMM operation can be improved.

Description

Matrix data processing methods, processors, and computer equipment

[0001] This application claims priority to Chinese Patent Application No. 202411550673.4, filed on October 31, 2024, entitled "Method for Processing Matrix Data, Processor and Computer Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computer technology, and in particular to a method for processing matrix data, a processor, and a computer device. Background Technology

[0003] Sparse-Dense Matrix Multiplication (SPMM) is a matrix multiplication operation between sparse and dense matrices, which has wide applications in artificial intelligence (AI), high-performance computing (HPC), and other scenarios.

[0004] Currently, SPMM operations are mainly implemented through matrix operation units. However, since sparse matrices contain a large number of zero elements, the matrix operation units will involve a large number of invalid calculations on zero elements during the execution of SPMM operations, which will result in low execution efficiency of SPMM operations. Summary of the Invention

[0005] This application provides a method for processing matrix data, a processor, and a computer device, which can improve the efficiency of the processor in performing SPMM operations. The corresponding technical solution is as follows:

[0006] Firstly, a method for processing matrix data is provided, applied to a processor. The processor is configured with a matrix operation unit and a vector operation unit. The method involves: acquiring a first matrix and a second matrix to be multiplied; wherein the proportion of non-zero elements in the first matrix is ​​less than a first threshold, and the proportion of non-zero elements in the second matrix is ​​greater than or equal to the first threshold; determining a first order for rearranging the elements in the first matrix; and determining a third matrix corresponding to the first matrix based on the first order, wherein the third matrix includes a first matrix block and a second matrix block; wherein the proportion of non-zero elements in the first matrix block is greater than a second threshold, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold; performing matrix operations on the data of the first matrix block and the data of the second matrix using the matrix operation unit to obtain a first operation result; and performing vector operations on the data of the second matrix block and the data of the second matrix using the vector operation unit to obtain a second operation result; and processing the first operation result and the second operation result according to the first order to obtain the result of performing matrix multiplication on the first and second matrices.

[0007] The first threshold can be used to distinguish between sparse and dense matrices; that is, the first matrix can be a sparse matrix, and the second matrix can be a dense matrix. The second threshold can be determined based on the efficiency of the matrix operation unit and the vector operation unit in performing operations, respectively.

[0008] In the scheme shown in this application, if the processor needs to perform SPMM operations, the elements in the sparse matrix can be rearranged so that non-zero elements cluster in at least one direction, thereby dividing the sparse matrix into a first matrix block and a second matrix block. In this way, the SPMM operation can be broken down into operations between the first matrix block and the dense matrix, and operations between the first matrix block and the dense matrix. Since the first matrix block contains more non-zero elements, a higher-performance matrix operation unit can be used to accelerate the operation between the first matrix block and the dense matrix, thereby reducing invalid calculations of zero elements by the matrix operation unit. Since the second matrix block contains fewer non-zero elements, and the proportion of non-zero elements is smaller than that of the first matrix, a vector operation unit can be used to perform operations between the non-zero elements in the second matrix block and the dense matrix, thereby skipping invalid calculations involving zero elements. By utilizing the hardware characteristics of the matrix operation unit and the vector operation unit respectively, accelerated processing of SPMM operations can be achieved, and the matrix operation unit and the vector operation unit can operate in parallel, further improving the efficiency of the processor in performing SPMM operations.

[0009] In one possible approach, determining a first order for rearranging the elements included in the first matrix includes: determining a first order for rearranging the row vectors in the first matrix based on the number of non-zero elements included in each row vector of the first matrix; or, determining a first order for rearranging the column vectors in the first matrix based on the number of non-zero elements included in each column vector of the first matrix.

[0010] In the scheme shown in this application, the order in which the elements included in the first matrix are rearranged can be either the order in which the row vectors are rearranged or the order in which the column vectors are rearranged. In this way, by rearranging only the row vectors or the column vectors, the non-zero elements can be aggregated, which can improve the efficiency of determining the first order and improve the efficiency of rearranging the first matrix.

[0011] In one possible implementation, a second order for rearranging the row vectors in the first matrix is ​​determined based on the number of non-zero elements in each row vector of the first matrix, and a third order for rearranging the column vectors in the first matrix is ​​determined based on the number of non-zero elements in each column vector of the first matrix, wherein the first order includes the second order and the third order.

[0012] By rearranging the non-zero elements in both the row and column directions, the non-zero elements can be clustered in both directions, which can further increase the density of the first matrix block and the sparsity of the second matrix block, thereby improving the efficiency of matrix operation units and vector operation units in performing operations.

[0013] In one feasible approach, the data of the second matrix is ​​adjusted to the data of the fourth matrix according to a first order. A matrix operation unit performs matrix multiplication on the data of the first matrix block and the data of the second matrix to obtain a first operation result. A vector operation unit performs vector multiplication on the data of the second matrix block and the data of the second matrix to obtain a second operation result, which includes the first operation result obtained by performing matrix multiplication on the data of the first matrix block and the data of the fourth matrix using the matrix operation unit, and the second operation result obtained by performing vector multiplication on the data of the second matrix block and the data of the fourth matrix using the vector operation unit.

[0014] In the scheme shown in this application, the data of the second matrix is ​​rearranged according to the order in which the first matrix is ​​rearranged, resulting in the data of the fourth matrix. The data in the second matrix and the fourth matrix contain the same content, but in a different order. This means that the second matrix can be adaptively rearranged according to the order in which the first matrix is ​​rearranged, thus ensuring normal operations between the second and first matrices.

[0015] In one possible implementation, the fourth matrix is ​​recorded using the second matrix and the first sequence, and the first matrix block is recorded using the first matrix and the fourth sequence, with the fourth sequence derived from the first sequence. A matrix operation unit is used to perform matrix multiplication on the first matrix block and the fourth matrix to obtain a first operation result, including: obtaining data from the first matrix block in the fourth sequence from the first matrix; obtaining data from the fourth matrix in the first sequence from the second matrix; and performing matrix multiplication on the obtained data from the first matrix block and the fourth matrix using the matrix operation unit to obtain the first operation result.

[0016] In the scheme shown in this application, the processor can record the third matrix using a first order and a first matrix, without needing to rearrange the first matrix according to the first order before storing the third matrix. Furthermore, the first matrix blocks included in the third matrix can also be recorded using a fourth order and a first matrix. The fourth order is the arrangement order of the first matrix blocks in the first matrix, which can be determined based on the first order and the position of the first matrix blocks in the third matrix. Thus, by recording the first matrix blocks using a fourth order in this application, the data of the first matrix blocks can be retrieved from the first matrix according to the fourth order for computation, thereby avoiding the step of rearranging the first matrix to store the third matrix, and improving the efficiency of retrieving and computing the first matrix blocks.

[0017] In one possible implementation, the fourth matrix is ​​recorded using the second matrix and a first order, and the second matrix block is recorded using the first matrix and a fifth order, with the fifth order derived from the first order. The second operation result, obtained by performing a vector multiplication operation on the second matrix block and the fourth matrix using a vector operation unit, includes: obtaining data from the second matrix block from the first matrix according to the fifth order; obtaining data from the fourth matrix from the second matrix according to the first order; and performing a vector multiplication operation on the obtained data from the second matrix block and the fourth matrix using the vector operation unit to obtain the second operation result.

[0018] In the scheme shown in this application, the processor can record the third matrix using a first order and a first matrix, eliminating the need to rearrange the first matrix according to the first order before storing the third matrix. Furthermore, the second matrix blocks included in the third matrix can also be recorded using a fifth order and a first matrix. The fifth order is the arrangement order of the second matrix blocks in the first matrix, which can be determined based on the first order and the positions of the second matrix blocks in the third matrix. Thus, by recording the second matrix blocks using the fifth order in this application, the data of the second matrix blocks can be retrieved from the first matrix according to the fifth order for computation, thereby avoiding the step of rearranging the first matrix to store the third matrix, and improving the efficiency of retrieving and computing the second matrix blocks.

[0019] In one feasible approach, the results of the first operation and the second calculation are processed according to a first order to obtain the result of matrix multiplication of the first matrix and the second matrix, including: obtaining the result matrix of matrix multiplication of the third matrix and the fourth matrix from the first operation result and the second operation result; and adjusting the result matrix according to the first order to obtain the result matrix of matrix multiplication of the first matrix and the second matrix.

[0020] In the scheme shown in this application, in order to accelerate the SPMM operation, the SPMM operation is split into the operation between the first matrix block and the second matrix, and the operation between the second matrix block and the second matrix. Furthermore, the first matrix and the second matrix are rearranged according to a first order, so the first operation result and the second operation result can be adjusted according to the first order to obtain the result matrix of the matrix multiplication operation between the first matrix and the second matrix.

[0021] Secondly, a processor is provided, which is configured with a matrix operation unit and a vector operation unit, and the processor is used for:

[0022] Obtain the first and second matrices to be multiplied. The proportion of non-zero elements in the first matrix is ​​less than a first threshold, and the proportion of non-zero elements in the second matrix is ​​greater than or equal to the first threshold.

[0023] Determine a first order for rearranging the elements included in the first matrix, and determine a third matrix corresponding to the first matrix based on the first order. The third matrix includes a first matrix block and a second matrix block. The proportion of non-zero elements in the first matrix block is greater than a second threshold, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold.

[0024] The matrix operation unit performs matrix operations on the data of the first matrix block and the data of the second matrix to obtain the first operation result, and the vector operation unit performs vector operations on the data of the second matrix block and the data of the second matrix to obtain the second operation result;

[0025] The first operation result and the second calculation result are processed according to the first order to obtain the result of matrix multiplication of the first matrix and the second matrix.

[0026] In one possible implementation, the processor is configured to: determine a first order for rearranging the row vectors in the first matrix based on the number of non-zero elements in each row vector of the first matrix; or, determine a first order for rearranging the column vectors in the first matrix based on the number of non-zero elements in each column vector of the first matrix.

[0027] In one possible implementation, the processor is configured to: determine a second order for rearranging the row vectors in the first matrix based on the number of non-zero elements in each row vector of the first matrix, and determine a third order for rearranging the column vectors in the first matrix based on the number of non-zero elements in each column vector of the first matrix, wherein the first order includes the second order and the third order.

[0028] In one possible implementation, the processor is further configured to: adjust the data of the second matrix to the data of the fourth matrix according to a first order. The processor is also configured to: perform matrix multiplication on the data of the first matrix block and the data of the fourth matrix using a matrix operation unit to obtain a first operation result, and perform vector multiplication on the data of the second matrix block and the data of the fourth matrix using a vector operation unit to obtain a second operation result.

[0029] In one possible implementation, the fourth matrix is ​​recorded through the second matrix and the first sequence, and the first matrix block is recorded through the first matrix and the fourth sequence, with the fourth sequence derived from the first sequence. The processor is configured to: obtain data of the first matrix block from the first matrix according to the fourth sequence; obtain data of the fourth matrix from the second matrix according to the first sequence; and perform matrix multiplication on the obtained data of the first matrix block and the data of the fourth matrix using a matrix operation unit to obtain a first operation result.

[0030] In one possible implementation, the fourth matrix is ​​recorded through the second matrix and the first order, and the second matrix block is recorded through the first matrix and the fifth order, the fifth order being derived from the first order. The processor is used to: obtain the data of the second matrix block from the first matrix according to the fifth order; obtain the data of the fourth matrix from the second matrix according to the first order; and perform vector multiplication on the obtained data of the second matrix block and the data of the fourth matrix using a vector operation unit to obtain a second operation result.

[0031] In one possible implementation, the processor is configured to: obtain a matrix by performing matrix multiplication on a third matrix and a fourth matrix from the first operation result and the second operation result; and adjust the result matrix by a first order to obtain a matrix by performing matrix multiplication on a first matrix and a second matrix.

[0032] Thirdly, a computer device is provided, the computer device including a memory and a processor as described in the second aspect or any of the possible implementations of the second aspect above.

[0033] Fourthly, a computer program product containing instructions is provided, which, when executed by a computer device, cause the computer device to perform the method as described in the first aspect or any of the implementable methods in the first aspect.

[0034] Fifthly, a computer-readable storage medium is provided, including computer program instructions that, when executed by a computer device, cause the computer device to perform the method as described in the first aspect or any of the implementable methods in the first aspect. Attached Figure Description

[0035] Figure 1 is a schematic diagram of the structure of a processor provided in an embodiment of this application;

[0036] Figure 2 is a schematic diagram of the structure of a computer device provided in an embodiment of this application;

[0037] Figure 3 is a flowchart of a matrix data processing method provided in an embodiment of this application;

[0038] Figure 4 is a schematic diagram of rearranging the row vectors of a first matrix according to an embodiment of this application;

[0039] Figure 5 is a schematic diagram of rearranging the column vectors of a first matrix according to an embodiment of this application;

[0040] Figure 6 is a schematic diagram of a method for processing matrix data provided in an embodiment of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] Matrix multiplication is widely used in various scientific computing scenarios. The density of matrices involved varies across different computing scenarios, leading to the main classification of matrix multiplication into dense matrix multiplication and sparse matrix multiplication. Dense matrix multiplication is generally used in traditional machine learning and neural network model computations, while sparse matrix multiplication is more commonly used in graph computing, graph neural networks, and multigrid solutions.

[0043] Dense matrix multiplication refers to the multiplication of matrices in which the matrices are dense, while sparse matrix multiplication refers to the multiplication of matrices in which the matrices are sparse. A sparse matrix is ​​a matrix where the percentage of non-zero elements is very small (e.g., less than 5%), while a dense matrix is ​​a matrix where the percentage of non-zero elements is relatively large.

[0044] Sparse matrix multiplication also includes the SPMM operation, which is the matrix multiplication of a sparse matrix with a dense matrix. SPMM has wide applications, such as in AI computing and HPC computing. Currently, SPMM is mainly implemented through a matrix operation unit, which performs out-of-vector accumulation on column vectors in a sparse matrix and row vectors in a dense matrix, thus achieving matrix multiplication. However, because sparse matrices contain a large number of zero elements, the matrix operation unit performs ineffective calculations on many zero elements during the SPMM operation, leading to reduced efficiency.

[0045] This application provides a method for processing matrix data, which combines the characteristics of SPMM operations with the advantages of vector operation units and matrix operation units to improve the computational efficiency of SPMM. Figure 1 is a schematic diagram of a processor structure provided in this application embodiment. As shown in Figure 1, the processor 100 includes a processor core 110 and is equipped with a matrix operation unit 120 and a vector operation unit 130. The processor core 110 can process matrix data according to the matrix processing method provided in this application embodiment, and control the matrix operation unit 120 to perform operations on the processed matrix data, thereby realizing SPMM operations.

[0046] In one example, the processor 100 described above can be a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or the like. The matrix operation unit 120 and the vector operation unit 130 configured in the processor 100 can be integrated into the operation units inside the processor 100, or they can be operation units located outside the processor 100.

[0047] Figure 2 is a schematic diagram of a computer device according to an embodiment of this application. As shown in Figure 2, the computer device 200 includes a bus 202, a processor 204, a memory 206, and a communication interface 208. The processor 204, the memory 206, and the communication interface 208 communicate with each other via the bus 202. The computer device 200 can be a server or a terminal device. It should be understood that this application does not limit the number of processors and memories in the computer device 200.

[0048] Bus 202 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one line is used in Figure 2, but this does not imply that there is only one bus or one type of bus. Bus 202 can include pathways for transmitting information between various components of computer device 200 (e.g., memory 206, processor 204, communication interface 208).

[0049] Processor 204 can be processor 100 as shown in Figure 1 above, such as a CPU, NPU, GPU, etc. Processor 204 may also include multiple vector registers for storing input matrices, result matrices, etc., involved in SPMM operations.

[0050] Memory 206 may include volatile memory, such as random access memory (RAM). Memory 206 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0051] The memory 206 stores executable program code, and the processor 204 executes the executable program code to implement the matrix data processing method provided in this application embodiment. That is, the memory 206 stores instructions for the matrix data processing method.

[0052] The communication interface 208 uses transceiver modules such as, but not limited to, network interface cards and transceivers to enable communication between the computer device 200 and other devices or communication networks.

[0053] Figure 3 is a flowchart of a matrix data processing method provided in an embodiment of this application. The processing method shown in Figure 3 can be executed by the computer device described in Figure 2, specifically by the processor included in the computer device as shown in Figure 1. As shown in Figure 3, the matrix data processing method provided in an embodiment of this application includes:

[0054] Step 301: The processor obtains the first matrix and the second matrix to be performed in the matrix multiplication operation, wherein the proportion of non-zero elements in the first matrix is ​​less than a first threshold, and the proportion of non-zero elements in the second matrix is ​​greater than or equal to the first threshold.

[0055] The first threshold can be used to distinguish between dense and sparse matrices. The first matrix can be a sparse matrix where the proportion of non-zero elements is less than the first threshold, and the second matrix can be a dense matrix where the proportion of non-zero elements is greater than or equal to the first threshold. The specific value of the first threshold can be determined by a person skilled in the art, and will not be elaborated further in this embodiment.

[0056] In implementation, the computer device can run applications involving SPMM operations, such as high-performance computing (HPC) applications, artificial intelligence (AI) applications, graph computing applications, etc. During runtime, when an application needs to perform an SPMM operation, it can send an SPMM operation request to the processor. In response to the SPMM operation request, the processor can read the first and second matrices to be performed from the computer device's memory or storage (such as a hard disk), and then read the first and second matrices into the vector registers configured in the processor, respectively.

[0057] Step 302: The processor determines the first order for rearranging the elements included in the first matrix, and determines the third matrix corresponding to the first matrix based on the first order. The third matrix includes a first matrix block and a second matrix block. The proportion of non-zero elements in the first matrix block is greater than a second threshold, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold.

[0058] In implementation, the processor can determine the first order for rearranging the row vectors and / or column vectors in the first matrix based on the position of the non-zero elements in the first matrix, so that the non-zero elements in the rearranged first matrix (i.e., the third matrix) are clustered in one direction. Thus, the third matrix can include first matrix blocks and second matrix blocks, wherein the proportion of non-zero elements in the first matrix block is greater than a second threshold, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold. The number of first matrix blocks and second matrix blocks can be one or more.

[0059] In one example, the second threshold can be a threshold used to distinguish between dense and sparse matrices, and can be the same as the first threshold mentioned above, so that the first matrix block can be a dense matrix and the second matrix can be a sparse matrix.

[0060] In another example, in this embodiment of the application, the operation between the first matrix and the second matrix can be split into the operation between the first matrix block and the second matrix, and the operation between the second matrix block and the second matrix. The operation between the first matrix block and the second matrix can be performed by a matrix operation unit, and the operation between the second matrix block and the second matrix can be performed by a vector operation unit. Therefore, the second threshold can also be determined by the efficiency of the matrix operation unit and the vector operation unit performing the operations respectively. For example, if the proportion of non-zero elements in the first matrix block is greater than the second threshold, the efficiency of performing the operation between the first matrix block and the second matrix by the matrix operation unit is greater than the efficiency of performing the operation between the first matrix block and the second matrix by the vector operation unit. Similarly, if the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold, the efficiency of performing the operation between the second matrix block and the second matrix by the vector operation unit is greater than the efficiency of performing the operation between the second matrix block and the second matrix by the matrix operation unit. In this case, the value of the second threshold can be set by a technician based on experimental data, and its specific value is not limited in this embodiment of the application; for example, it can be 1 / 2.

[0061] In implementation, the processor can determine the regions containing the first and second matrix blocks in the third matrix based on the proportion of non-zero elements. For example, an engineer can set a second threshold for the proportion of non-zero elements. The processor can determine that the region in the third matrix where the proportion of corresponding non-zero elements is greater than the second threshold is the region containing the first matrix block, and the region in the third matrix where the proportion of corresponding non-zero elements is less than or equal to the second threshold is the region containing the second matrix block.

[0062] In one example, since the non-zero elements in the third matrix are mainly concentrated in one direction, such as at the top of the third matrix, the processor can determine, based on the second order, starting from the first row of the third matrix, whether the proportion of non-zero elements in the first X rows of the third matrix is ​​greater than a second threshold. If the proportion of non-zero elements in the first Y rows is less than or equal to the second threshold, then the first Y-1 rows can be determined as the first matrix block, and the remaining rows as the second matrix block.

[0063] Step 303: The processor uses the matrix operation unit to perform matrix operations on the data of the first matrix block and the data of the second matrix to obtain the first operation result, and uses the vector operation unit to perform vector operations on the data of the second matrix block and the data of the second matrix to obtain the second operation result.

[0064] In one example, in step 302, after the processor determines the first order, it can rearrange the first matrix according to the first order to obtain a third matrix. Then, in the third matrix, a first matrix block and a second matrix block can be determined respectively according to a second threshold. After determining the first matrix block and the second matrix block, the first operation result of performing matrix multiplication on the first matrix block and the second matrix block can be calculated, and the second operation result of performing matrix multiplication on the second matrix block and the second matrix block can be calculated. Here, the data in the first matrix block refers to the elements included in the first matrix block, and the data in the second matrix block is the same as the elements included in the second matrix block, and the data in the second matrix is ​​the same as the elements included in the second matrix.

[0065] For the first matrix block, since both the first matrix block and the second matrix contain a large number of non-zero elements, a higher-performance matrix operation unit can be used in this embodiment to accelerate the operation of the first matrix block and the second matrix. Specifically, the matrix operation unit can be controlled to perform vector-outside accumulation and addition operations on the first matrix block and the second matrix to obtain the first result of matrix multiplication. Because both the first matrix block and the second matrix contain a large number of non-zero elements, the matrix operation unit will not perform invalid calculations on a large number of zero elements during the operation of the first matrix block and the second matrix, thus fully utilizing the performance of the matrix operation unit to accelerate the operation of the first matrix block and the second matrix.

[0066] For the second matrix block, since it is a sparse matrix with even higher sparsity than the first matrix, it contains only a few non-zero elements, with a large number of rows or columns being zero elements, and sometimes even a zero matrix. Therefore, in this embodiment, a vector operation unit can be used to accelerate the operations on the second matrix block and the second matrix. Specifically, the vector operation unit can be controlled to skip the operation corresponding to a row of zero elements if it determines that all elements in that row are zero. This reduces the computational load of the vector operation unit and improves its efficiency in performing inner product operations on the second matrix block and the second matrix.

[0067] It should be noted that since the first and second matrix blocks are matrix blocks included in the third matrix, and the third matrix is ​​a matrix obtained by rearranging the first matrix blocks according to the first order, when the first and second matrix blocks are operated on with the second matrix, it may be necessary to rearrange the elements in the second matrix. The matrix resulting from rearranging the second matrix can be called the fourth matrix. Alternatively, the first and second matrix blocks may also be obtained directly from the first matrix according to the first order, meaning the processor may not need to store the third matrix in actual processing. The rearrangement of the second matrix and the acquisition of the first and second matrix blocks will not be discussed here; please refer to Figures 4 to 6 below for details.

[0068] Step 304: The processor processes the first calculation result and the second calculation result according to the first order to obtain the result of matrix multiplication of the first matrix and the second matrix.

[0069] In step 302 above, the first matrix is ​​rearranged according to a first order. The first order can be the order in which the row vectors in the first matrix are rearranged, the order in which the column vectors in the first matrix are rearranged, or the order in which both the row vectors and column vectors in the first matrix are rearranged.

[0070] Based on the calculation process of matrix multiplication using the outer product, if the first order only rearranges the column vectors of the first matrix, and the row vectors of the second matrix are adaptively rearranged, then the matrix resulting from the matrix multiplication of the first and second matrices is the same as the matrix resulting from the matrix multiplication of the rearranged first and second matrices. In this case, the results of the first and second calculations can be directly concatenated according to the positions of the first and second matrix blocks in the third matrix to obtain the result of the matrix multiplication of the first and second matrices.

[0071] Based on the calculation process of matrix multiplication using the inner product, if the first order includes the rearrangement of the row vectors of the first matrix, then the resulting matrix from performing matrix multiplication on the first and second matrices contains the same row vectors, but in a different order, as does the resulting matrix from performing matrix multiplication on the rearranged first and second matrices. In this case, we can directly rearrange the row order in the first and second calculation results according to the rearrangement of the row vectors of the first matrix to obtain the result of performing matrix multiplication on the first and second matrices.

[0072] In this embodiment, the row and column positions of the sparse matrix in the SPMM operation can be adjusted first, so that a first matrix block belonging to the dense matrix and a second matrix block belonging to the sparse matrix appear in the sparse matrix. Thus, matrix multiplication of the first matrix block and the second matrix can be performed separately by the matrix operation unit, and matrix multiplication of the second matrix block and the second matrix can be performed by the vector operation unit. In other words, the more efficient computing power of the matrix operation unit can be utilized, while the characteristics of the sparse matrix can be used to reduce the computational load, thereby improving the efficiency of the processor in performing SPMM operations. Furthermore, the matrix operation unit and the vector operation unit can execute operations in parallel, further improving the efficiency of the processor in performing SPMM operations.

[0073] The method for determining the first order of rearranging the first matrix in step 302 above will be described in detail below:

[0074] Method 1: The first order is the order in which the row vectors in the first matrix are rearranged.

[0075] In this embodiment, the processor can determine the number of non-zero elements in each row vector of the first matrix. After determining the number of non-zero elements in each row vector of the first matrix, a first order for rearranging the row vectors of the first matrix can be determined according to the order of the number of non-zero elements from most to least (or from least to most).

[0076] For each row vector in the first matrix, after determining the non-zero elements included in each row vector, the processor can determine the first order for rearranging the rows based on the order of the non-zero elements from most to least. Figure 4 is a schematic diagram of rearranging the row vectors of the first matrix according to an embodiment of this application. In Figure 4, matrix A1 is the first matrix, which includes 8 row vectors with row numbers "0", "1", "2", "3", "4", "5", "6", and "7" respectively, and the non-zero elements included in each row from top to bottom are 3, 2, 1, 0, 1, 2, 4, and 1 respectively. According to the order of the non-zero elements from most to least, the first order corresponding to the 8 row vectors included in matrix A2 can be determined as "6", "0", "1", "5", "2", "4", "7", and "3" (for row vectors with the same number of non-zero elements, they can be arranged according to the order of the row vectors in the unrearranged first matrix).

[0077] As shown in Figure 4, if the row vectors of the first matrix are rearranged according to the first order, the non-zero elements of the first matrix are mainly concentrated above the third matrix. In one example, the first X row vectors of the third matrix that contain more non-zero elements can be defined as the first matrix block, and the remaining row vectors can be defined as the second matrix block. For example, the first 4 row vectors are the first matrix block, and the last 4 row vectors are the second matrix block.

[0078] Method 2: The first order is the order in which the column vectors in the first matrix are rearranged.

[0079] In this embodiment, the processor can determine the number of non-zero elements in each column vector of the first matrix. After determining the number of non-zero elements in each column vector of the first matrix, a first order for rearranging the column vectors of the first matrix can be determined according to the order of the number of non-zero elements from most to least (or from least to most).

[0080] For each column vector in the first matrix, after determining the non-zero elements included in each column vector, the processor can determine the first order for rearranging the column vectors according to the order of the non-zero elements from most to least. Figure 5 is a schematic diagram of rearranging the column vectors of the first matrix provided by an embodiment of this application. As shown in Figure 5, matrix A1 is the first matrix, which includes 4 column vectors with column numbers "0", "1", "2", and "3" respectively, and the number of non-zero elements in each column from left to right is 4, 3, 4, and 3 respectively. According to the order of the non-zero elements from most to least, the first order corresponding to the 4 vectors included in matrix A1 can be determined as "0", "2", "1", and "3" (for column vectors with the same number of non-zero elements, they can be arranged according to their order in the first matrix).

[0081] As shown in Figure 5, if the column vectors of the first matrix are rearranged according to the first order, the non-zero elements of the first matrix are mainly concentrated on the left side of the third matrix. In one example, the matrix block located on the left side of the third matrix can be defined as the first matrix block, and the remaining matrix blocks can be defined as the second matrix block. The size of the first matrix block can be determined based on the proportion of non-zero elements located on the left side of the third matrix.

[0082] Method 3: The first order includes a second order that rearranges the row vectors in the first matrix and a third order that rearranges the column vectors in the first matrix.

[0083] In this embodiment, the processor can determine the number of non-zero elements in each row vector and each column vector of the first matrix. After determining the number of non-zero elements in each row vector and column vector of the first matrix, a second order for rearranging the row vectors of the first matrix and a third order for rearranging the column vectors of the first matrix can be determined according to the order of non-zero elements from most to least (or from least to most).

[0084] For each row vector and column vector in the first matrix, after determining the non-zero elements included in each row vector, the processor can determine a second order for rearranging the row vectors and a third order for rearranging the column vectors based on the order of the non-zero elements from most to least. The methods for determining the second and third orders have been explained in "Method 1" and "Method 2" of the above embodiments and will not be repeated here.

[0085] If the row and column vectors of the first matrix are rearranged according to the second and third orders, the non-zero elements of the first matrix are mainly concentrated in the upper left corner of the third matrix. In one example, the matrix block located in the upper left corner of the third matrix can be defined as the first matrix block, and the remaining matrix blocks can be defined as the second matrix block. The size of the first matrix block can be determined based on the proportion of the non-zero elements located in the upper left corner of the third matrix.

[0086] In one example, the first matrix is ​​a sparse matrix and can be stored in various compressed formats, such as Coordinate Format (COO), Compressed Sparse Column Format (CSC), and Compressed Sparse Row Format (CSR). The processor can determine the number of non-zero elements in each row and column of the first matrix based on its storage format. Alternatively, the processor can determine the number of non-zero elements in each row and column of the first matrix by iterating through its elements.

[0087] In this embodiment, the first order can be used to indicate the order in which the columns and rows of the first matrix are rearranged. After rearranging the column vectors and / or row vectors of the first matrix according to the first order, the non-zero elements in the first matrix will cluster in one direction. For example, in Figure 4, after rearranging the row vectors of matrix A1 according to the second order (i.e., the second sequence), the non-zero elements in the resulting matrix A2 will cluster upwards. Thus, for a sparse matrix, by adjusting the positions of the row vectors and / or column vectors of the sparse matrix, the non-zero elements in the sparse matrix can be concentrated in one region. In this way, at least one matrix block with dense characteristics (the first matrix block) can be formed inside the sparse matrix, that is, the first matrix block includes more non-zero elements. In addition, the other matrix blocks (the second matrix blocks) in the sparse matrix besides the first matrix block are matrix blocks with sparse characteristics, and since the non-zero elements in the sparse matrix are mainly concentrated in the first matrix block, the remaining second matrix blocks are sparser than the first matrix.

[0088] The following is a detailed explanation of the method for rearranging the first matrix according to the first order:

[0089] When the first order is the order in which the row vectors in the first matrix are rearranged, the rearrangement of the row vectors in the first matrix according to the first order includes:

[0090] In step 301 above, the processor can sequentially read each row vector included in the first matrix and store each row vector in each vector register. The vector register storing each row vector has corresponding row index information, which can be used to indicate the position of the stored row vector in the first matrix. For example, column index information can indicate the row number of the column vector stored in each register in the first matrix. When the processor inputs the first matrix to the vector operation unit or matrix operation unit for operation, it can sequentially obtain each row vector included in the first matrix according to the row index information.

[0091] In step 303 above, the processor can modify the row index information corresponding to the vector register storing each row vector in a first order. Thus, the modified row index information can be used to indicate the position of each row vector in the third matrix. For example, the modified row index information can be used to indicate the row number corresponding to each row vector in the third matrix. In this way, the row vectors obtained by the processor according to the modified row index information are the row vectors in the third matrix.

[0092] Taking Figure 4 above as an example, the row index information before modification is "0", "1", "2", "3", "4", "5", "6", "7", which indicates that the row vectors stored in the eight vector registers are the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th row vectors in the first matrix, respectively. The modified row index information can be "6", "0", "1", "5", "2", "4", "7", "3", which indicates that the row vectors stored in the eight vector registers are the 6th, 0th, 1st, 5th, 2nd, 4th, 7th, and 3rd row vectors in the first matrix, respectively. Thus, by simply modifying the row index information, the row vectors in the first matrix can be rearranged, avoiding the need to reread each row vector from the vector registers and store them in the first order, thereby improving the efficiency of rearranging the row vectors of the first matrix.

[0093] In this scenario, the third matrix can be recorded using the first order (or row index information) and the first matrix, without needing to rearrange the first matrix. Furthermore, the first and second matrix blocks included in the third matrix can also be recorded using the first order and the first matrix. The order in which the row vectors of the first matrix block are recorded can be called the fourth order, and the order in which the row vectors of the second matrix block are recorded can be called the fifth order. Taking Figure 4 as an example, if the first matrix block consists of the first four row vectors in the third matrix, then the corresponding fourth order can be "6", "0", "1", and "5". If the second matrix block consists of the last four row vectors in the third matrix, then the corresponding fifth order can be "6", "0", "1", and "5". It is evident that the fourth and fifth orders can be obtained by dividing the first order according to the size of the first matrix block (or the second matrix block). In actual calculations, data from the first matrix block can be obtained from the first matrix according to the fourth order and input into the matrix operation unit for calculation, and data from the second matrix block can be obtained from the first matrix according to the fifth order and input into the matrix operation unit for calculation. In this way, the storage of the third matrix can be avoided, and the data of the first matrix block and the second matrix block can be obtained, thereby improving the efficiency of the matrix operation unit in performing operations.

[0094] When the first order is the order in which the column vectors in the first matrix are rearranged, the rearrangement of the column vectors of the first matrix according to the first order includes:

[0095] In step 301 above, the processor can sequentially read each column vector included in the first matrix and store each column vector into each vector register. Each vector register storing a column vector has corresponding column index information, which can be used to indicate the position of the stored column vector in the first matrix. For example, the column index information can indicate the column number of the column vector stored in each register within the first matrix. The processor can sequentially retrieve each column vector included in the first matrix according to the column index information.

[0096] In step 303 above, the processor can modify the column index information corresponding to the vector register storing each column vector in a first order. Thus, the modified column index information can be used to indicate the position of each column vector in the third matrix. For example, the modified column index information can be used to indicate the column number corresponding to each column vector in the third matrix. In this way, the column vectors obtained by the processor according to the modified column index information are the column vectors in the third matrix.

[0097] Taking Figure 5 above as an example, the column index information before modification is "0", "1", "2", and "3", which indicates that the column vectors stored in the four vector registers are the 0th, 1st, 2nd, and 3rd column vectors in the first matrix, respectively. The modified column index information can be "0", "2", "1", and "3", indicating that the column vectors stored in the four vector registers are the 0th, 2nd, 1st, and 3rd column vectors in the first matrix, respectively. Thus, by simply modifying the column index information, the column vectors in the first matrix can be rearranged, avoiding the need to reread each column vector from the vector registers and store them in the first order, thereby improving the efficiency of rearranging the column vectors of the first matrix.

[0098] In this scenario, the third matrix can be recorded using the first order (or column index information) and the first matrix, without needing to rearrange the first matrix. Furthermore, the first and second matrix blocks included in the third matrix can also be recorded using the first order and the first matrix. The order in which the row vectors of the first matrix block are recorded can be called the fourth order, and the order in which the row vectors of the second matrix block are recorded can be called the fifth order. Taking Figure 5 as an example, if the first matrix block consists of the first two column vectors in the third matrix, the corresponding fourth order can be "0" and "2"; if the second matrix block consists of the last two column vectors in the third matrix, the corresponding fifth order can be "1" and "3". It is evident that the fourth and fifth orders can be obtained by dividing the first order according to the size of the first matrix block (or the second matrix block). In actual calculations, data from the first matrix block can be obtained from the first matrix according to the fourth order and input into the matrix operation unit for computation, and data from the second matrix block can be obtained from the first matrix according to the fifth order and input into the matrix operation unit for computation. This avoids storing the third matrix, allowing the acquisition of data from the first and second matrix blocks, thereby improving the efficiency of the matrix operation unit.

[0099] For rearranging the row and column vectors of the first matrix according to the second and third orders:

[0100] In this embodiment, if it is necessary to rearrange both the column vectors and row vectors of the first matrix, the column vectors of the first matrix can be rearranged according to the third order in the above embodiment (that is, the column index information can be modified), and then the row vectors of the first matrix can be rearranged.

[0101] Before rearranging the row vectors of the first matrix, we can first determine the first region of the first matrix block in the third matrix, and the second region of the second matrix block in the third matrix. The third matrix refers to the matrix after rearranging according to the first and second orders. The first region includes the row and column positions of the first matrix block in the third matrix, and the second region includes the row and column positions of the second matrix block in the third matrix.

[0102] The third order (or the aforementioned column index information) indicates the column order of the column vectors stored sequentially in the vector register within the third matrix, while the second order indicates the row order corresponding to each element in each column vector. Thus, the processor can sequentially retrieve each column element located in the first region of the third matrix according to the second order, i.e., retrieve the column vector of the first matrix block, and then input the retrieved column vector of the first matrix block into the matrix operation unit for computation. Similarly, it can sequentially retrieve each row element located in the second region of the third matrix according to the second order, i.e., retrieve the row vector of the second matrix block, and then input the retrieved row vector of the second matrix block into the vector operation unit for computation.

[0103] Taking Figures 4 and 5 above as examples, the modified column index information is "0", "2", "1", "3", and the second order is "6", "0", "1", "5", "2", "4", "7", "3". Taking the first matrix block located in the first four rows of the third matrix and the second matrix block located in the last four rows of the third matrix as an example, the processor can sequentially obtain each column vector of the first matrix block based on the column index information "0", "2", "1", "3" and the second order including "6", "0", "1", "5" (i.e., the fourth order). The processor can sequentially obtain each row vector of the second matrix block based on the column index information "0", "2", "1", "3" and the second order including "2", "4", "7", "3" (i.e., the fifth order).

[0104] In other words, in this embodiment, after modifying the column index information corresponding to the column vectors of the first matrix according to the third order, the column vectors of the first matrix block or the row vectors of the second matrix block can be directly obtained according to the fourth and fifth orders and input into the matrix operation unit or the vector operation unit. This is equivalent to rearranging the row vectors and column vectors in the first matrix while inputting the first and second matrix blocks into the matrix operation unit or the vector operation unit, respectively. This avoids rereading each row vector in the vector register and then storing the first and second matrix blocks in the vector register according to the fourth and fifth orders, thus improving the efficiency of rearranging the row vectors of the first matrix.

[0105] The above embodiments illustrate the process of first modifying the column index information according to the third order, and then obtaining the first matrix block and the second matrix block according to the second order. Alternatively, the row index information can be modified according to the second order, and then the first matrix block and the second matrix block can be obtained according to the third order; the specific process is similar to the above embodiments and will not be repeated here.

[0106] It should be reiterated that the third matrix mentioned in the above embodiments is a concept used for ease of description and understanding of the scheme. Although it exists mathematically, it is not actually stored in the processor's processing. Instead, the first matrix stored in the vector register can be converted into column vectors of the first matrix block and row vectors of the second matrix block included in the third matrix, according to the first order. Therefore, the embodiments of this application improve the efficiency of rearranging the first matrix to obtain the first and second matrix blocks, further improving the efficiency of the processor in performing SPMM operations.

[0107] Furthermore, since the row or column vectors included in the first matrix have been rearranged, the second matrix may also need to be adaptively rearranged to ensure that it can be operated on with the first matrix.

[0108] The following section details the method for rearranging the second matrix based on the rearrangement of the first matrix:

[0109] For the case where only the row vectors included in the first matrix are rearranged

[0110] Based on the calculation process of matrix multiplication using the inner product, it is known that even if the row vectors in the first matrix are rearranged, each row vector in the first matrix can still be multiplied by each column vector in the second matrix. In this case, only the positions of the elements in the third result (the result matrix) are changed. Therefore, the row or column vectors in the second matrix do not need to be rearranged. Subsequently, by adjusting the positions of the row or column vectors in the result matrix, the result of matrix multiplication of the first and second matrices can be obtained.

[0111] The case of rearranging the column vectors included in the first matrix.

[0112] Because the column vectors in the first matrix have been rearranged, the order of elements in each row vector of the first matrix has changed; that is, the elements in the row vectors have been rearranged according to the first order. Following the calculation process of matrix multiplication using the outer product, the elements in each column vector of the second matrix need to be rearranged according to the first order to ensure that the row vectors of the first matrix and the column vectors of the second matrix can be used for the inner product operation. Therefore, in this case, the row vectors in the second matrix can be rearranged according to the first order, so that the elements in each column vector are rearranged according to the first order. The rearranged matrix can become the fourth matrix; the rearrangement method can refer to the above-described rearrangement method for the first matrix, and will not be repeated in this embodiment. Similar to the third matrix, the fourth matrix is ​​a concept mentioned for ease of description and understanding of the scheme. Although it exists mathematically, the processor does not actually need to store the fourth matrix during processing. Instead, according to the first order, the second matrix (including row vectors or column vectors) stored in the vector register is input to the matrix operation unit or vector operation unit, thereby achieving the effect of inputting the row vectors or column vectors of the fourth matrix to the matrix operation unit or vector operation unit. This avoids storing the fourth matrix and further improves the efficiency of the processor in performing SPMM operations.

[0113] Furthermore, in this case, since both the first and second matrices have been rearranged, the resulting matrix formed by the first and second operation results is the matrix resulting from performing matrix multiplication on the rearranged third and fourth matrices. Therefore, the positions of the elements in the resulting matrix can be further rearranged to obtain the result of performing matrix multiplication on the first and second matrices.

[0114] The following describes the method for rearranging the elements in the result of the third operation:

[0115] As we know from the calculation process of matrix multiplication using the outer product, rearranging the column vectors in the first matrix does not affect the position of the elements in the resulting matrix. The factor that affects the position of the elements in the resulting matrix is ​​the order in which the row vectors are arranged. Therefore, after rearranging the row vectors of the first matrix according to the second order, the resulting matrix can be rearranged according to the second order.

[0116] In one example, the row vectors included in the first operation result and the second operation result can be stored according to the order in which the row vectors in the first matrix are arranged, so as to obtain the result matrix after adjusting the order of the row vectors, which is the result matrix of matrix multiplication of the first matrix and the second matrix.

[0117] Figure 6 is a schematic diagram of a matrix processing method provided in an embodiment of this application. As shown in Figure 6, after arranging the first matrix A1 according to the second and third orders, a first matrix A3 can be obtained. Correspondingly, after arranging the second matrix B1 according to the second order, a second matrix B2 can be obtained. The first matrix A3 can be divided into a first matrix block A31 and a second matrix block A32. The processor can control the matrix operation unit to perform operations on the first matrix block A31 and the second matrix B2 to obtain a first operation result (matrix C1), and control the vector operation unit to perform operations on the second matrix block A33 and the second matrix B2 to obtain a second operation result (matrix C2). Matrix C1 and matrix C2 are concatenated in the column direction to obtain a third operation result. However, since the first matrix A1 has been rearranged according to the second order, the third operation result needs to be rearranged according to the second order to obtain the result matrix of matrix multiplication of the first and second matrices.

[0118] Referring again to Figure 6, during the calculation of the first operation result by the matrix operation unit, each row vector included in the first operation result can be stored in multiple vector registers according to the second order. Similarly, during the calculation of the second operation result by the vector operation unit, each row vector included in the second operation result can be stored in multiple vector registers according to the second order. In this way, the third operation result can be stored in multiple vector registers according to the second order, which is to obtain the matrix resulting from the matrix multiplication operation between the first and second matrices.

[0119] In this embodiment, the SPMM operation can be broken down into matrix operations performed by the matrix operation unit and vector operations performed by the vector operation unit. After obtaining the operation result, the result can be further adjusted to be the result of the SPMM operation. In this way, during the implementation of the SPMM operation, the high performance of the matrix operation unit can be used to perform operations on a large number of non-zero elements, and the operation of zero elements can be skipped by the vector operation unit, thereby improving the efficiency of the processor in performing the SPMM operation.

[0120] Based on the same inventive concept, this application also provides a processor, which may be the processor shown in FIG1, including a matrix operation unit and a vector operation unit, capable of executing the matrix data processing method provided in this application embodiment, thereby improving the execution efficiency of SPMM operations. The matrix data processing method implemented by the processor provided in this application embodiment can be referred to the content described in the above embodiments, and will not be repeated here.

[0121] This application also provides a computer device, which may be the computer device shown in FIG2, including a memory and a processor configured with matrix operation units, vector operation units, and other components, capable of executing the matrix data processing method provided in this application embodiment, thereby improving the execution efficiency of SPMM operations. The matrix data processing method implemented by the computer device provided in this application embodiment can be referred to the content described in the above embodiments, and will not be repeated here.

[0122] This application also provides a computer program product containing instructions. The computer program product may be software or program products containing instructions, capable of running on a computer device or stored on any usable medium. When the computer program product is run on at least one computer device, it causes the at least one computer device to perform the matrix data processing method provided in this application embodiment.

[0123] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to execute the matrix data processing method provided in this application embodiment.

[0124] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have substantially the same function and purpose. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of various examples, a first data matrix can be referred to as a second data matrix, and similarly, a second data matrix can be referred to as a first data matrix. Both the first and second data matrices can be collectively referred to as data matrices, and in some cases, they can be separate and distinct data matrices.

[0125] In this application, the term "at least one" means one or more, and the term "multiple" means two or more.

[0126] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for processing matrix data, characterized in that, The method is applied to a processor, the processor being configured with a matrix operation unit and a vector operation unit, the method comprising: Obtain the first matrix and the second matrix to be multiplied, wherein the proportion of non-zero elements in the first matrix is ​​less than a first threshold, and the proportion of non-zero elements in the second matrix is ​​greater than or equal to the first threshold. A first order for rearranging the elements included in the first matrix is ​​determined, and a third matrix corresponding to the first matrix is ​​determined according to the first order. The third matrix includes a first matrix block and a second matrix block. The proportion of non-zero elements in the first matrix block is greater than a second threshold, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold. The matrix operation unit performs matrix operations on the data of the first matrix block and the data of the second matrix to obtain a first operation result, and the vector operation unit performs vector operations on the data of the second matrix block and the data of the second matrix to obtain a second operation result. The first calculation result and the second calculation result are processed according to the first order to obtain the result of the matrix multiplication operation performed on the first matrix and the second matrix.

2. The method according to claim 1, characterized in that, Determining the first order for rearranging the elements in the first matrix includes: The first order for rearranging the row vectors in the first matrix is ​​determined based on the number of non-zero elements in each row vector of the first matrix; or, The first order for rearranging the column vectors in the first matrix is ​​determined based on the number of non-zero elements in each column vector of the first matrix.

3. The method according to claim 1, characterized in that, Determining the first order for rearranging the elements in the first matrix includes: A second order for rearranging the row vectors in the first matrix is ​​determined based on the number of non-zero elements in each row vector of the first matrix, and a third order for rearranging the column vectors in the first matrix is ​​determined based on the number of non-zero elements in each column vector of the first matrix, wherein the first order includes the second order and the third order.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: adjusting the data of the second matrix to the data of the fourth matrix according to the first order; The step of performing matrix multiplication on the data of the first matrix block and the data of the second matrix using the matrix operation unit to obtain a first operation result, and performing vector multiplication on the data of the second matrix block and the data of the second matrix using the vector operation unit to obtain a second operation result, includes: The matrix operation unit performs matrix multiplication on the data of the first matrix block and the data of the fourth matrix to obtain a first operation result, and the vector operation unit performs vector multiplication on the data of the second matrix block and the data of the fourth matrix to obtain a second operation result.

5. The method according to claim 4, characterized in that, The fourth matrix is ​​recorded through the second matrix and the first sequence, and the first matrix block is recorded through the first matrix and the fourth sequence, wherein the fourth sequence comes from the first sequence; The step of using the matrix operation unit to perform matrix multiplication on the data of the first matrix block and the data of the fourth matrix to obtain the first operation result includes: According to the fourth order, the data of the first matrix block is obtained from the first matrix; Following the first order, the data of the fourth matrix is ​​obtained from the second matrix; The matrix operation unit performs matrix multiplication on the acquired data of the first matrix block and the data of the fourth matrix to obtain the first operation result.

6. The method according to claim 4, characterized in that, The fourth matrix is ​​recorded through the second matrix and the first sequence, and the second matrix block is recorded through the first matrix and the fifth sequence, wherein the fifth sequence comes from the first sequence; The second operation result of performing a vector multiplication operation on the data of the second matrix block and the data of the fourth matrix using the vector operation unit includes: According to the fifth order, the data of the second matrix block is obtained from the first matrix; Following the first order, the data of the fourth matrix is ​​obtained from the second matrix; The vector operation unit performs a vector multiplication operation on the data of the second matrix block and the data of the fourth matrix to obtain the second operation result.

7. The method according to any one of claims 4 to 6, characterized in that, The step of processing the first calculation result and the second calculation result according to the first order to obtain the result of performing the matrix multiplication operation on the first matrix and the second matrix includes: The matrix obtained by performing matrix multiplication on the third matrix and the fourth matrix is ​​obtained from the first operation result and the second operation result; The result matrix is ​​adjusted by the first order to obtain the matrix result of the matrix multiplication operation between the first matrix and the second matrix.

8. A processor, characterized in that, The processor is configured with a matrix operation unit and a vector operation unit, and the processor is used for: Obtain the first matrix and the second matrix to be multiplied, wherein the proportion of non-zero elements in the first matrix is ​​less than a first threshold, and the proportion of non-zero elements in the second matrix is ​​greater than or equal to the first threshold. A first order for rearranging the elements included in the first matrix is ​​determined, and a third matrix corresponding to the first matrix is ​​determined according to the first order. The third matrix includes a first matrix block and a second matrix block. The proportion of non-zero elements in the first matrix block is greater than a second threshold, and the proportion of non-zero elements in the second matrix block is less than or equal to the second threshold. The matrix operation unit performs matrix operations on the data of the first matrix block and the data of the second matrix to obtain a first operation result, and the vector operation unit performs vector operations on the data of the second matrix block and the data of the second matrix to obtain a second operation result. The first calculation result and the second calculation result are processed according to the first order to obtain the result of the matrix multiplication operation performed on the first matrix and the second matrix.

9. The processor according to claim 8, characterized in that, The processor is used for: The first order for rearranging the row vectors in the first matrix is ​​determined based on the number of non-zero elements in each row vector of the first matrix; or, The first order for rearranging the column vectors in the first matrix is ​​determined based on the number of non-zero elements in each column vector of the first matrix.

10. The processor according to claim 8, characterized in that, The processor is configured to: determine a second order for rearranging the row vectors in the first matrix based on the number of non-zero elements in each row vector of the first matrix, and determine a third order for rearranging the column vectors in the first matrix based on the number of non-zero elements in each column vector of the first matrix, wherein the first order includes the second order and the third order.

11. The processor according to any one of claims 8 to 10, characterized in that, The processor is further configured to: adjust the data of the second matrix to the data of the fourth matrix according to the first order; The processor is configured to: use the matrix operation unit to perform matrix multiplication on the data of the first matrix block and the data of the fourth matrix to obtain a first operation result, and use the vector operation unit to perform vector multiplication on the data of the second matrix block and the data of the fourth matrix to obtain a second operation result.

12. The processor according to claim 11, characterized in that, The fourth matrix is ​​recorded through the second matrix and the first sequence, the first matrix block is recorded through the first matrix and the fourth sequence, the fourth sequence comes from the first sequence, and the processor is used to: According to the fourth order, the data of the first matrix block is obtained from the first matrix; Following the first order, the data of the fourth matrix is ​​obtained from the second matrix; The matrix operation unit performs matrix multiplication on the acquired data of the first matrix block and the data of the fourth matrix to obtain the first operation result.

13. The processor according to claim 11, characterized in that, The fourth matrix is ​​recorded through the second matrix and the first sequence, the second matrix block is recorded through the first matrix and the fifth sequence, the fifth sequence being derived from the first sequence, and the processor is used to: According to the fifth order, the data of the second matrix block is obtained from the first matrix; Following the first order, the data of the fourth matrix is ​​obtained from the second matrix; The vector operation unit performs a vector multiplication operation on the data of the second matrix block and the data of the fourth matrix to obtain the second operation result.

14. The processor according to any one of claims 11 to 13, characterized in that, The processor is used for: The matrix obtained by performing matrix multiplication on the third matrix and the fourth matrix is ​​obtained from the first operation result and the second operation result; The result matrix is ​​adjusted by the first order to obtain the matrix result of the matrix multiplication operation between the first matrix and the second matrix.

15. A computer device, characterized in that, The computer device includes a memory and a processor as described in claims 9 to 14 above.

16. A computer program product containing instructions, characterized in that, When the instructions are executed by a computer device, the computer device performs the method as described in any one of claims 1 to 7.

17. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computer device, cause the computer device to perform the method as described in any one of claims 1 to 7.

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