Semiconductor device and method for fabricating semiconductor device

Abstract

The present invention addresses the problem of raising the breakdown voltage of a semiconductor device. This semiconductor device comprises a semiconductor substrate having an element region and an outer peripheral region. The semiconductor substrate comprises: an element p-type layer disposed in the element region; an outer peripheral p-type layer disposed in the outer peripheral region so as to surround the element region; an outer peripheral n-type layer disposed on the outer peripheral side of the outer peripheral p-type layer so as to be spaced apart from the outer peripheral p-type layer; and a breakdown voltage p-type layer located between the outer peripheral p-type layer and the outer peripheral n-type layer. The semiconductor device comprises: an interlayer insulating film disposed on a substrate upper surface; an upper electrode disposed in the element region; a specific electrode disposed in the outer peripheral region; a semi-insulating film disposed in a range from the upper electrode to the specific electrode; and a protective insulating film disposed on a surface of the semi-insulating film. The semi-insulating film is disposed continuously from the upper electrode to the specific electrode and covers a specific electrode corner part.

Description

Semiconductor Device and Method of Manufacturing the Same

[0001] (Cross - reference to related applications) This application is a related application of Japanese Patent Application No. 2024 - 189160 filed on October 28, 2024, claims priority based on this Japanese patent application, and incorporates all the contents described in this Japanese patent application as constituting this specification.

[0002] The technology disclosed in this specification relates to a semiconductor device and a method of manufacturing the semiconductor device.

[0003] The semiconductor device disclosed in JP - A - 2014 - 33108 has an element region provided with semiconductor elements and an outer peripheral region provided around the element region. In the outer peripheral region, a breakdown voltage structure such as a RESURF layer and a guard ring is provided. An n - type semiconductor region is provided on the outer peripheral side of the breakdown voltage structure. Also, electrodes are disposed on the upper surface on the inner peripheral side of the breakdown voltage structure and on the upper surface of the n - type semiconductor region. The upper surfaces of the electrodes and the breakdown voltage structure are covered with a semi - insulating film. Further, the upper surface of the semi - insulating film is sealed with a protective insulating film (e.g., resin). Since the charges arriving from the outside are released to the electrodes by the semi - insulating film, no charges are accumulated in the vicinity of the breakdown voltage structure. It is possible to increase the breakdown voltage of the semiconductor device because the bias of the electric field distribution in the vicinity of the breakdown voltage structure can be suppressed.

[0004] In the form sealed with the protective insulating film, expansion and contraction occur at the interface between the electrode and the semi - insulating film due to thermal stress. As a result, if cracks occur in the semi - insulating film in the vicinity of the breakdown voltage structure, it becomes difficult to release the charges in the vicinity of the breakdown voltage structure to the electrodes. There is a risk that charges will accumulate in the vicinity of the breakdown voltage structure and the breakdown voltage of the semiconductor device will decrease.

[0005] The semiconductor device disclosed herein comprises a semiconductor substrate having an element region and an outer peripheral region arranged to surround the outer periphery of the element region. The semiconductor substrate comprises an element p-type layer disposed within the element region and in a region including the upper surface of the semiconductor substrate, an outer peripheral p-type layer disposed within the outer peripheral region to surround the element region and in a region including the upper surface of the substrate, and adjacent to the element p-type layer, and a breakdown voltage p-type layer disposed within the outer peripheral region, located further outward than the outer peripheral p-type layer, and in a region including the upper surface of the substrate. The semiconductor device comprises an interlayer insulating film disposed on the upper surface of the substrate in the element region and the outer peripheral region, an upper electrode disposed on the surface of the interlayer insulating film within the element region, a specific electrode disposed on the surface of the interlayer insulating film within the outer peripheral region, a semi-insulating film disposed in the range from the upper electrode to the specific electrode, covering a part of the upper electrode, at least a part of the specific electrode, and the breakdown voltage p-type layer, and a protective insulating film disposed on the surface of the semi-insulating film within the region of the semi-insulating film. The specific electrode has a specific electrode upper surface parallel to the substrate upper surface, a specific electrode side surface connecting the specific electrode upper surface and the surface of the interlayer insulating film, and a specific electrode corner connecting the specific electrode upper surface and the specific electrode side surface. The semi-insulating film is arranged continuously from the upper electrode to the specific electrode and covers the specific electrode corner.

[0006] In this semiconductor device, a semi-insulating film is continuously arranged from the upper electrode to a specific electrode and also covers the corner of the specific electrode. The semi-insulating film covering the corner of the specific electrode is more prone to stress concentration than the semi-insulating film covering the breakdown p-type layer. Therefore, the corner of the specific electrode can be designated as a crack initiation point where cracks can preferentially occur in the semi-insulating film. As a result, when thermal stress occurs in the semiconductor device, cracks can be generated in the semi-insulating film at the corner of the specific electrode. Consequently, the stress on the semi-insulating film near the breakdown p-type layer can be relieved, making it possible to suppress the occurrence of cracks in the semi-insulating film near the breakdown p-type layer. A conductive path can be secured to allow charge to escape from the vicinity of the breakdown p-type layer to the specific electrode, so charge does not accumulate near the breakdown p-type layer. This makes it possible to increase the breakdown voltage of the semiconductor device.

[0007] In this specification, the outer periphery may refer to the side closer to the outer edge of the semiconductor substrate. Furthermore, the breakdown voltage p-type layer may be a resurfacing layer, a guard ring, or both.

[0008] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later.

[0009] This is a top view of semiconductor device 1. This is a cross-sectional view taken along line II-II in Figure 1. This is a flowchart illustrating the manufacturing method of semiconductor device 1. This is a cross-sectional view illustrating the manufacturing method of semiconductor device 1. This is a cross-sectional view illustrating semiconductor device 201 of Example 2.

[0010] (Structure of Semiconductor Device 1) Figure 1 shows a top view of the semiconductor device 1. The semiconductor device 1 has a semiconductor substrate 12. An upper electrode 14, a first electrode 51, and a second electrode 52 are provided on the upper part of the semiconductor substrate 12. Figure 1 shows these electrodes in an exposed state. These electrodes are also shown as solid gray. These electrodes are made of AlSi or the like.

[0011] The semiconductor substrate 12 comprises an element region 20 and an outer peripheral region 40. The element region 20 is the region on which various semiconductor elements (e.g., IGBTs (insulated gate bipolar transistors), FETs (field effect transistors), diodes) are formed. In this embodiment, the case in which IGBTs are formed in the element region 20 will be described. In Figure 1, the element region 20 is shown by a dotted line. The outer peripheral region 40 is the semiconductor region of the semiconductor substrate 12 surrounding the element region 20. That is, the outer peripheral region 40 is the region between the element region 20 and the outer peripheral end face 12c of the semiconductor substrate 12.

[0012] Figure 2 shows a cross-sectional view along the line II-II in Figure 1. Figure 2 is a cross-section that passes through the center of the element region 20 and is perpendicular to the upper surface 12u of the semiconductor substrate 12.

[0013] The structure of the element region 20 will now be described. The element region 20 is the region where the IGBT is formed. An upper electrode 14 is placed on the upper surface 12u of the semiconductor substrate 12 within the element region 20, via an interlayer insulating film 50. Multiple gate trenches 30 are provided on the upper surface 12u at regular intervals. The inner surface of each gate trench 30 is covered with a gate insulating film 32. A gate electrode 34 is placed within each gate trench 30. The upper surface of the gate electrode 34 is insulated from the upper electrode 14 by the interlayer insulating film 50.

[0014] An emitter region 35, an upper body region 36, a barrier region 37, and a lower body region 38 are provided within the area sandwiched between adjacent gate trenches 30. The emitter region 35 is an n-type region with a high n-type impurity concentration. The emitter region 35 is in ohmic contact with the upper electrode 14. The upper body region 36 is a p-type region. The upper body region 36 is located in an area that includes the upper surface 12u of the semiconductor substrate 12. The upper body region 36 has a contact region 36a and a low-concentration region 36b. The contact region 36a has a higher p-type impurity concentration than the low-concentration region 36b. The contact region 36a is in ohmic contact with the upper electrode 14. The low-concentration region 36b is located below the contact region 36a and the emitter region 35. The barrier region 37 is an n-type region with a low n-type impurity concentration and is located below the low-concentration region 36b. The lower body region 38 is a p-type region and is located below the barrier region 37. Since the configuration of the IGBT is known, a detailed explanation is omitted.

[0015] The structure of the outer peripheral region 40 will now be described. The semiconductor substrate 12 within the outer peripheral region 40 is provided with an outer peripheral p-type layer 42, a breakdown voltage p-type layer 44, and an outer peripheral n-type layer 46. Furthermore, an interlayer insulating film 50, a first electrode 51, a second electrode 52, a protective electrode 53, a semi-insulating film 56, and a protective insulating film 58 are arranged on the upper surface 12u within the outer peripheral region 40.

[0016] The outer peripheral region 40 further comprises three regions: a p-type region 40r1, a pressure-resistant structure region 40r2, and an EQR region 40r3. The p-type region 40r1 is the region where the outer peripheral p-type layer 42 is formed. The EQR region 40r3 is the region where the outer peripheral n-type layer 46 is formed. The pressure-resistant structure region 40r2 is the region between the p-type region 40r1 and the EQR region 40r3, and is the region where the pressure-resistant p-type layer 44 is formed.

[0017] The p-type region 40r1 will now be described. The outer p-type layer 42 is arranged to surround the element region 20 and is located in a range that includes the upper surface 12u of the semiconductor substrate 12, and is adjacent to the upper body region 36. The outer p-type layer 42 is distributed from the upper surface 12u of the semiconductor substrate 12 to a position below the lower end of each gate trench 30. The outer p-type layer 42 includes a plurality of gate trenches 30, including the end gate trench 30a located on the outermost (+x direction) side.

[0018] The first electrode 51 is positioned on the surface of the interlayer insulating film 50 within the region of the outer p-type layer 42. As shown in Figure 1, the first electrode 51 extends in an annular shape along the outer circumference of the element region 20. Therefore, the first electrode 51 surrounds the upper electrode 14. The first electrode 51 is made of AlSi or the like.

[0019] The first electrode 51 has a first electrode upper surface 51u, a first electrode side surface 51s, and a first electrode corner portion 51c. The first electrode upper surface 51u is a surface parallel to the upper surface 12u. The first electrode side surface 51s is a surface that connects the first electrode upper surface 51u to the surface of the interlayer insulating film 50. The first electrode corner portion 51c is a portion that connects the first electrode upper surface 51u to the first electrode side surface 51s.

[0020] The protective electrode 53 is located within the region of the outer p-type layer 42. The protective electrode 53 is separated from the outer p-type layer 42 by the interlayer insulating film 50. The protective electrode 53 extends in an annular shape to surround the upper electrode 14, similar to the first electrode 51. The protective electrode 53 is made of AlSi or the like.

[0021] The first electrode 51 is connected to the protective electrode 53 via a contact hole provided in the interlayer insulating film 50.

[0022] The breakdown structure region 40r2 will now be described. The breakdown structure region 40r2 includes a breakdown p-type layer 44. The breakdown p-type layer 44 is located between the outer peripheral p-type layer 42 and the outer peripheral n-type layer 46, and is adjacent to the outer peripheral p-type layer 42 on the outer peripheral side (+x direction side). The breakdown p-type layer 44 is arranged in a range that includes the upper surface 12u of the semiconductor substrate 12. The breakdown p-type layer 44 is distributed from the upper surface 12u to a position shallower than the lower end of the outer peripheral p-type layer 42. That is, the breakdown p-type layer 44 is distributed in a range shallower than the outer peripheral p-type layer 42. When the semiconductor substrate 12 is viewed from above in a plan view, the breakdown p-type layer 44 surrounds the periphery of the element region 20. The breakdown p-type layer 44 has a lower p-type impurity concentration than the outer peripheral p-type layer 42. In this embodiment, the breakdown p-type layer 44 is a resurf layer.

[0023] The EQR region 40r3 will now be described. The outer n-type layer 46 is spaced apart from the outer p-type layer 42 and the pressure-resistant p-type layer 44, and is located further outward (towards the +x direction) than the outer p-type layer 42 and the pressure-resistant p-type layer 44. The outer n-type layer 46 is located in a region that includes the upper surface 12u. The outer n-type layer 46 is separated from the pressure-resistant p-type layer 44 by the drift n-type layer 24. The outer n-type layer 46 has a higher n-type impurity concentration than the drift n-type layer 24.

[0024] The second electrode 52 is positioned on the surface of the interlayer insulating film 50 within the region of the outer n-type layer 46. The second electrode 52 is connected to the outer n-type layer 46 via a contact hole provided in the interlayer insulating film 50. As shown in Figure 1, the second electrode 52 extends in an annular shape along the outer edge of the semiconductor substrate 12. Therefore, the second electrode 52 surrounds the first electrode 51. This forms a so-called equipotential ring (EQR) structure. The second electrode 52 is made of AlSi or the like.

[0025] The second electrode 52 has a second electrode upper surface 52u, a second electrode side surface 52s, and a second electrode corner portion 52c. The second electrode upper surface 52u is a surface parallel to the upper surface 12u. The second electrode side surface 52s is a surface that connects the second electrode upper surface 52u to the surface of the interlayer insulating film 50. The second electrode corner portion 52c is a portion that connects the second electrode upper surface 52u to the second electrode side surface 52s.

[0026] The structure common to the element region 20 and the outer peripheral region 40 will now be described. The drift n-type layer 24 is distributed across the element region 20 and the outer peripheral region 40. The drift n-type layer 24 is in contact with the lower body region 38, the outer peripheral p-type layer 42, the breakdown p-type layer 44, and the outer peripheral n-type layer 46 from below. The drift n-type layer 24 also extends to the upper surface 12u at a position between the breakdown p-type layer 44 and the outer peripheral n-type layer 46. A lower n-type layer 26 is located below the drift n-type layer 24. The lower n-type layer 26 is a region with a higher n-type impurity concentration than the drift n-type layer 24. A lower electrode 16 is provided on the lower surface 12b of the semiconductor substrate 12.

[0027] (Structure of the semi-insulating film 56 and protective insulating film 58) The semi-insulating film 56 is arranged in the range from the upper electrode 14 to the second electrode 52. The semi-insulating film 56 is arranged continuously from the upper electrode 14 to the second electrode 52. The semi-insulating film 56 covers a part of the upper electrode 14, the entire first electrode 51, and at least a part of the second electrode 52. The semi-insulating film 56 also covers the corner portion 51c of the first electrode and the corner portion 52c of the second electrode. The semi-insulating film 56 has a semi-insulating film end portion 56e. The semi-insulating film end portion 56e is the end portion on the center side (-x direction side) of the element region 20. The semi-insulating film end portion 56e is located within the region of the upper electrode 14.

[0028] The semi-insulating film 56 has a laminated structure comprising a first layer 56_1 and a second layer 56_2 disposed on the upper surface of the first layer 56_1. The first layer 56_1 is a semi-insulating film. The semi-insulating film has a thickness of, for example, 1 × 10⁻¹⁶ at 25°C. ８ Ωcm or more and 1 × 10⁻⁶ １４This film has a resistivity of Ωcm or less. Various types of films can be used for the first layer 56_1. In this example, the first layer 56_1 is SInSiN (Semi-insulating Silicon Nitride). By adjusting the concentration of impurities added during film formation, semi-insulating properties can be obtained for SInSiN.

[0029] The second layer 56_2 is an insulating film. That is, the electrical resistance of the second layer 56_2 is higher than that of the first layer 56_1. Various types of films can be used for the second layer 56_2. In this embodiment, the second layer 56_2 is made of insulating silicon nitride.

[0030] The effect of the semi-insulating film 56 is explained below. The upper surface of the breakdown structure region 40r2 is covered by the semi-insulating first layer 56_1. Charges arriving from the outside are released by the first layer 56_1 to the first electrode 51 and the second electrode 52, so that charge does not accumulate in the vicinity of the breakdown structure region 40r2 (see region A1). Since the bias in the electric field distribution in the vicinity of the breakdown structure region 40r2 can be suppressed, it is possible to increase the breakdown voltage of the semiconductor device 1. In addition, the insulating second layer 56_2 can suppress ions in the protective insulating film 58 from penetrating into the semiconductor substrate 12.

[0031] The protective insulating film 58 is located within the region of the semi-insulating film 56 and on the surface of the semi-insulating film 56. Various types of films can be used for the protective insulating film 58. In this embodiment, the protective insulating film 58 is made of polyimide.

[0032] The protective insulating film 58 has a protective insulating film end 58e. The protective insulating film end 58e is the end on the central side (-x direction side) of the element region 20. The protective insulating film end 58e is located within the region of the upper electrode 14 and within the region of the semi-insulating film 56. The semi-insulating film end 56e protrudes more toward the central side (-x direction side) of the element region 20 than the protective insulating film end 58e.

[0033] The protective insulating film 58 has a protective insulating film upper surface 58u and a protective insulating film side surface 58s. The protective insulating film upper surface 58u is a surface parallel to the upper surface 12u of the semiconductor substrate 12. The protective insulating film side surface 58s is a surface connecting the protective insulating film upper surface 58u and the surface of the semi-insulating film 56. The protective insulating film side surface 58s has a curved surface that is convex on the downward side.

[0034] (Effect) The problem is explained. In the configuration sealed with a protective insulating film 58, expansion and contraction occur at the interface between the electrodes (upper electrode 14, first electrode 51, second electrode 52) and the semi-insulating film 56 due to thermal stress. As a result, if a crack occurs in the semi-insulating film 56 near the breakdown structure region 40r2, it becomes difficult to release the charge near the breakdown structure region 40r2 to the electrodes (see region A1). Charge may accumulate near the breakdown structure region 40r2, potentially reducing the breakdown voltage of the semiconductor device 1. Therefore, in the technology described herein, the semi-insulating film 56 is arranged continuously from the upper electrode 14 to the second electrode 52 and also covers the first electrode corner 51c and the second electrode corner 52c. The semi-insulating film 56 covering the first electrode corner 51c and the second electrode corner 52c is more prone to stress concentration than the semi-insulating film 56 covering the breakdown p-type layer 44 (region A1). Therefore, the first electrode corner 51c and the second electrode corner 52c can be designated as crack initiation points that can preferentially cause cracks to occur in the semi-insulating film 56 (see region A2). In other words, a structure can be realized in which the withstand voltage structure region 40r2 is positioned between the two crack initiation points. As a result, when thermal stress occurs in the semiconductor device 1, cracks can be generated in the semi-insulating film 56 at the first electrode corner 51c and the second electrode corner 52c. Therefore, the stress on the semi-insulating film 56 of the withstand voltage structure region 40r2 can be relieved, and the occurrence of cracks in the semi-insulating film 56 of the withstand voltage structure region 40r2 can be suppressed. Conductive paths can be secured to allow charge to escape from the withstand voltage structure region 40r2 to the first electrode 51 and the second electrode 52, so that charge does not accumulate in the withstand voltage structure region 40r2. This makes it possible to increase the withstand voltage of the semiconductor device 1.

[0035] Furthermore, the inventors have found that even if cracks occur in the semi-insulating film 56 on the first electrode 51 or the second electrode 52, the breakdown voltage and reliability of the semiconductor device 1 do not decrease. This is because, due to the conductivity of the electrodes, the charge is discharged through the electrodes. Therefore, it is possible to actively form crack initiation points on the first electrode 51 or the second electrode 52.

[0036] If the protective insulating film 58 and the upper surface 14u of the upper electrode 14 are in direct contact, stress strain will increase, and there is a risk of cracking in the upper electrode 14. Therefore, in the technology described herein, the semi-insulating film end 56e is structured to protrude further towards the center of the element region than the protective insulating film end 58e. This ensures that the semi-insulating film end 56e reliably isolates the protective insulating film end 58e from the upper surface 14u of the upper electrode 14. This makes it possible to suppress the occurrence of cracks in the upper electrode 14.

[0037] In the technology described herein, the protective insulating film side surface 58s has a curved surface that is convex downwards. This makes it possible to smooth the stress distribution near the protective insulating film side surface 58s compared to the case where the protective insulating film side surface 58s is perpendicular to the upper surface 12u of the semiconductor substrate 12. This makes it possible to suppress the occurrence of cracks in the upper electrode 14.

[0038] (Manufacturing Method) Using the flowchart in Figure 3, the steps related to the semi-insulating film 56 and the protective insulating film 58 among the steps included in the manufacturing method of the semiconductor device 1 will be explained. For the other steps, known manufacturing methods can be appropriately adopted.

[0039] In step S1, a metal film is formed on the entire upper surface of the interlayer insulating film 50 in which contact holes are formed. The thickness of the metal film is not particularly limited, but may be, for example, 5 to 6 μm. In step S2, an electrode processing mask (not shown) is formed on the surface of the metal film. The electrode processing mask is a mask in which the areas other than the upper electrode 14, the first electrode 51, and the second electrode 52 are open. In step S3, the metal film is patterned by anisotropic etching using the electrode processing mask. This forms the upper electrode 14, the first electrode 51, and the second electrode 52.

[0040] In step S4, a semi-insulating film 56 is formed on the entire surface of the semiconductor substrate 12 on which these electrodes are formed. Specifically, by adjusting the impurity concentration during film formation, a semi-insulating first layer 56_1 and an insulating second layer 56_2 are laminated in sequence to form the film. The film thickness of the semi-insulating film 56 is not particularly limited, but may be, for example, about 1 μm.

[0041] In step S5, a protective insulating film 58 is formed on the entire surface of the semi-insulating film 56. Specifically, after applying a polyimide film, curing for imidization is performed. The film thickness of the protective insulating film 58 is not particularly limited, but may be, for example, about 10 μm.

[0042] In step S6, a mask 60 having an opening OP corresponding to the element region 20 is formed (see FIG. 4). The mask 60 may be, for example, a photoresist. In step S7, using the mask 60, an opening 58o is patterned in the protective insulating film 58. The processing of the opening 60o may use, for example, anisotropic etching. As a result, as shown in FIG. 4, a structure is formed in which the semi-insulating film 56 is exposed at the bottom surface of the opening 58o.

[0043] In step S8, the semi-insulating film 56 is isotropically etched through the opening 58o of the protective insulating film 58. In this embodiment, as the isotropic etching, dry etching using a gas such as O ２ or CF ４ is used. Note that wet etching may be used as the isotropic etching. As a result, by making the protective insulating film 58 function as a mask, the semi-insulating film 56 within the opening 58o can be removed. As a result, the structure shown in FIG. 2 can be formed.

[0044] The etching rate of the isotropic etching is higher for the protective insulating film 58 than for the semi-insulating film 56. Therefore, the etching is performed such that the end portion 58e of the protective insulating film is at a position recessed more than the end portion 56e of the semi-insulating film (i.e., a position on the +x direction side). Also, the processing can be performed such that the side surface 58s of the protective insulating film has a downwardly convex curved surface. By adjusting the manufacturing conditions of the isotropic etching, the protruding amount PA of the end portion 56e of the semi-insulating film from the end portion 58e of the protective insulating film and the cross-sectional shape of the side surface 58s of the protective insulating film can be controlled.

[0045] According to the above manufacturing method, the protective insulating film 58 can be made to function as a mask for processing the semi-insulating film 56. Since a dedicated mask for processing the semi-insulating film 56 can be omitted, it becomes possible to reduce the manufacturing cost of the semiconductor device 1.

[0046] (Structure of Semiconductor Device 201) The semiconductor device 201 (FIG. 5) of Example 2 is different from the semiconductor device 1 of Example 1 in that recesses are formed in the first electrode 51 and the second electrode 52. The same reference numerals are given to the parts common to Example 2 and Example 1, and the description thereof is omitted.

[0047] A recess 51r is formed on the upper surface 51u of the first electrode. The recess 51r has a rectangular cross-sectional shape. When viewed from a direction perpendicular to the upper surface 12u of the semiconductor substrate 12 (i.e., the +z direction), the recess 51r is formed in a groove shape so as to surround the element region 20. The semi-insulating film 56 is disposed so as to be embedded in the recess 51r.

[0048] Similarly, a recess 52r is formed on the upper surface 52u of the second electrode. The recess 52r has the same groove shape as the recess 51r described above. The semi-insulating film 56 is disposed so as to be embedded in the recess 52r.

[0049] (Effect) Stress can be concentrated in the semi-insulating film 56 covering the recesses 51r and 52r, allowing the recesses 51r and 52r to function as crack initiation points. When thermal stress is generated in the semiconductor device 1, the stress on the semi-insulating film 56 of the pressure-resistant structural region 40r2 can be relieved by causing cracks to form in the recesses 51r and 52r. This makes it possible to suppress the formation of cracks in the semi-insulating film 56 of the pressure-resistant structural region 40r2.

[0050] The recesses 51r and 52r are configured to surround the element region 20. This makes it possible to relieve the stress on the semi-insulating film 56 of the pressure-resistant structure region 40r2 around the entire circumference of the outer edge of the element region 20.

[0051] (Manufacturing Method) An example of a manufacturing method for recesses 51r and 52r is described. The electrode processing mask of Example 2 (see Figure 3, step S2) further includes recess openings for processing recesses 51r and 52r, in addition to separation openings for separating electrodes. By making the width of the recess openings sufficiently narrow compared to the width of the separation openings, the processing rate of recesses 51r and 52r can be reduced compared to the processing rate of electrodes. As a result, recesses 51r and 52r can be formed at the same time as patterning the upper electrode 14, the first electrode 51, and the second electrode 52 by anisotropic etching in step S3. Recesses 51r and 52r can be formed simply by modifying the mask pattern of the electrode processing mask. Since no additional steps are required to form recesses 51r and 52r, an increase in manufacturing costs can be suppressed.

[0052] (Modification of Example 2) The cross-sections of the recesses 51r and 52r are not limited to a rectangular shape and may be various. For example, they may be triangular, semicircular, tapered, curved, etc. Also, the number of recesses 51r and 52r may vary.

[0053] The recesses 51r and 52r are not limited to groove shapes and may be of various types. For example, they may have a shape in which many dots are arranged.

[0054] Although the examples have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

[0055] (Modified form) Although a form comprising both the first electrode 51 and the second electrode 52 has been described, the invention is not limited to this form. Even in a form comprising only one of the first electrode 51 and the second electrode 52, the effect of relieving the stress on the semi-insulating film 56 can be obtained.

[0056] The semi-insulating film 56 can have various configurations as long as it has a predetermined semi-insulating property. For example, it does not need to have an insulating second layer 56_2.

[0057] The structure of the first electrode 51 is not limited to the structure of this embodiment and may vary. For example, the first electrode 51 may be connected to the outer p-type layer 42 via a contact hole provided in the interlayer insulating film 50.

[0058] The configurations of the technology disclosed herein are listed below. [Configuration 1] A semiconductor device (1) comprising a semiconductor substrate (12) having an element region (20) and an outer peripheral region (40) arranged to surround the outer periphery of the element region, wherein the semiconductor substrate comprises: an element p-type layer (36) disposed within the element region and in a range including the upper surface (12u) of the semiconductor substrate; an outer peripheral p-type layer (42) disposed within the outer peripheral region to surround the element region and in a range including the upper surface of the substrate, and adjacent to the element p-type layer; a breakdown voltage p-type layer (44) disposed within the outer peripheral region, located on the outer peripheral side of the outer peripheral p-type layer, and in a range including the upper surface of the substrate, wherein the semiconductor device comprises: an interlayer insulating film (50) disposed on the upper surface of the substrate in the element region and the outer peripheral region; an upper electrode (14) disposed on the surface of the interlayer insulating film within the element region; and specific electrodes (51, 52) disposed on the surface of the interlayer insulating film within the outer peripheral region. A semiconductor device comprising: a semi-insulating film (56) disposed in the range from the upper electrode to the specific electrode, the semi-insulating film covering a part of the upper electrode, at least a part of the specific electrode, and the voltage-resistant p-type layer; and a protective insulating film (58) disposed on the surface of the semi-insulating film within the region of the semi-insulating film, wherein the specific electrode has a specific electrode upper surface (51u, 52u) parallel to the upper surface of the substrate, a specific electrode side surface (51s, 52s) connecting the specific electrode upper surface and the surface of the interlayer insulating film, and a specific electrode corner portion (51c, 52c) connecting the specific electrode upper surface and the specific electrode side surface, and the semi-insulating film is disposed continuously from the upper electrode to the specific electrode and covers the specific electrode corner portion.[Configuration 2] The semiconductor device according to Configuration 1, wherein the specific electrode is a first electrode (51) disposed on the surface of the interlayer insulating film within the region of the outer peripheral p-type layer and surrounding the upper electrode, the upper surface of the specific electrode is the upper surface of the first electrode (51u), the side surface of the specific electrode is the side surface of the first electrode (51s) connecting the upper surface of the first electrode and the surface of the interlayer insulating film, the corner portion of the specific electrode is the corner portion of the first electrode (51c) connecting the upper surface of the first electrode and the side surface of the first electrode, and the semi-insulating film is continuously disposed from the upper electrode to the first electrode and covers the corner portion of the first electrode. [Configuration 3] The semiconductor device according to Configuration 2, further comprising a recess (51r) formed on the upper surface of the first electrode, wherein the semi-insulating film is disposed within the recess. [Configuration 4] The semiconductor device according to Configuration 3, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region. [Configuration 5] The semiconductor device according to Configuration 1, wherein the semiconductor substrate is arranged within the outer peripheral region, in a range including the upper surface of the substrate, and further comprises an outer peripheral n-type layer (46) that is spaced apart from the outer peripheral p-type layer and located further outward than the outer peripheral p-type layer, the breakdown voltage p-type layer (44) is located between the outer peripheral p-type layer and the outer peripheral n-type layer, the specific electrode is a second electrode (52) arranged on the surface of the interlayer insulating film within the region of the outer peripheral n-type layer and surrounding the upper electrode, the upper surface of the specific electrode is the upper surface of the second electrode (52u), the side surface of the specific electrode is a second electrode side surface (52s) connecting the upper surface of the second electrode and the surface of the interlayer insulating film, the corner of the specific electrode is a second electrode corner (52c) connecting the upper surface of the second electrode and the side surface of the second electrode, and the semi-insulating film is arranged continuously from the upper electrode to the second electrode and covers the corner of the second electrode. [Configuration 6] The semiconductor device according to Configuration 5, further comprising a recess (52r) formed on the upper surface of the second electrode, wherein the semi-insulating film is disposed within the recess. [Configuration 7] The semiconductor device according to Configuration 6, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.[Configuration 8] The semiconductor substrate is arranged within the outer peripheral region, in a range including the upper surface of the substrate, and further comprises an outer peripheral n-type layer (46) that is spaced apart from the outer peripheral p-type layer and located further outward than the outer peripheral p-type layer, The breakdown voltage p-type layer (44) is located between the outer peripheral p-type layer and the outer peripheral n-type layer, The specific electrode is a first electrode (51) arranged on the surface of the interlayer insulating film within the region of the outer peripheral p-type layer and surrounding the upper electrode, and a second electrode (52) arranged on the surface of the interlayer insulating film within the region of the outer peripheral n-type layer and surrounding the first electrode, The upper surface of the specific electrode is the upper surface of the first electrode (51u) and the upper surface of the second electrode (52u), The side surface of the specific electrode is a first electrode side surface (51s) connecting the upper surface of the first electrode and the surface of the interlayer insulating film, and a second electrode side surface (52s) connecting the upper surface of the second electrode and the surface of the interlayer insulating film, The semiconductor device according to Configuration 1, wherein the specific electrode corners are a first electrode corner (51c) connecting the upper surface of the first electrode and the side surface of the first electrode, and a second electrode corner (52c) connecting the upper surface of the second electrode and the side surface of the second electrode, and the semi-insulating film is continuously arranged from the upper electrode to the second electrode and covers the first electrode corner and the second electrode corner. [Configuration 9] The semiconductor device according to Configuration 8, further comprising a recess (52r) formed on at least one of the upper surface of the first electrode and the upper surface of the second electrode, wherein the semi-insulating film is disposed within the recess. [Configuration 10] The semiconductor device according to Configuration 9, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region. [Configuration 11] The semiconductor device according to any one of Configurations 1-10, wherein the semi-insulating film end (56e), which is the central end of the semi-insulating film of the element region, is located within the region of the upper electrode, the protective insulating film end (58e), which is the central end of the protective insulating film of the element region, is located within the region of the upper electrode and within the region of the semi-insulating film, and the semi-insulating film end protrudes further toward the center of the element region than the protective insulating film end.[Configuration 12] The protective insulating film has a protective insulating film upper surface (58u) parallel to the upper surface of the substrate and a protective insulating film side surface (58s) connecting the protective insulating film upper surface and the surface of the semi-insulating film, and in a cross section passing through the center of the element region and perpendicular to the upper surface of the substrate, the protective insulating film side surface has a curved surface that is convex downward, as described in any one of Configurations 1-11. [Configuration 13] The semi-insulating film has a laminated structure comprising a first layer (56_1) and a second layer (56_2) disposed on the upper surface of the first layer, and the electrical resistance of the first layer is lower than the electrical resistance of the second layer, as described in any one of Configurations 1-12.[Configuration 14] A method for manufacturing a semiconductor device (1), wherein the semiconductor device comprises a semiconductor substrate (12) having an element region (20) and an outer peripheral region (40) arranged to surround the outer periphery of the element region, the semiconductor substrate comprising: an element p-type layer (36) arranged within the element region and in a range including the upper surface of the semiconductor substrate; an outer peripheral p-type layer (42) arranged within the outer peripheral region to surround the element region and in a range including the upper surface of the substrate, and in contact with the element p-type layer; a breakdown voltage p-type layer (44) arranged within the outer peripheral region and located on the outer peripheral side of the outer peripheral p-type layer, and in a range including the upper surface of the substrate, the semiconductor device comprising: an interlayer insulating film (50) arranged on the upper surface of the substrate in the element region and on the upper surface of the substrate in the outer peripheral region; an upper electrode (14) arranged on the surface of the interlayer insulating film within the element region; and specific electrodes (51, 52) arranged on the surface of the interlayer insulating film within the outer peripheral region. A semiconductor device comprising: a semi-insulating film (56) disposed in the range from the upper electrode to the specific electrode; and a protective insulating film (58) disposed on the surface of the semi-insulating film within the region of the semi-insulating film, wherein the manufacturing method comprises: a step (S4) of depositing the semi-insulating film on the entire surface of the semiconductor substrate on which the upper electrode, the specific electrode, and the breakdown p-type layer are formed; a step (S5) of depositing the protective insulating film on the entire surface of the semi-insulating film; a step (S6) of forming a mask having an opening corresponding to the element region; a step (S7) of forming an opening in the protective insulating film using the mask; and a step (S8) of isotropically etching the semi-insulating film through the opening in the protective insulating film.

[0059] According to the above configurations 2, 5, and 8, the semi-insulating film at the corners of the first and second electrodes can be used as a crack initiation point. This makes it possible to suppress the occurrence of cracks in the semi-insulating film near the pressure-resistant p-type layer.

[0060] According to the above configurations 3, 6, and 9, by inducing cracks in the recesses of the first and second electrodes, it becomes possible to relieve the stress on the semi-insulating film near the pressure-resistant p-type layer.

[0061] According to the above configurations 4, 7, and 10, it is possible to relieve the stress on the semi-insulating film around the entire circumference of the outer edge of the element region.

[0062] If the protective insulating film and the upper surface of the upper electrode are in direct contact, stress and strain will increase, potentially causing cracks in the upper electrode. According to the above configuration 11, the semi-insulating film end reliably isolates the protective insulating film end from the upper surface of the upper electrode. This makes it possible to suppress the occurrence of cracks in the upper electrode.

[0063] According to the above configuration 12, since the side surface of the protective insulating film has a curved surface that is convex downwards, the stress distribution near the side surface of the protective insulating film can be made smoother compared to the case where the side surface of the protective insulating film is perpendicular to the upper surface of the substrate. This makes it possible to suppress the occurrence of cracks in the upper electrode.

Claims

1. A semiconductor device (1) comprising a semiconductor substrate (12) having an element region (20) and an outer peripheral region (40) arranged to surround the outer periphery of the element region, wherein the semiconductor substrate comprises: an element p-type layer (36) disposed within the element region and in a range including the upper surface (12u) of the semiconductor substrate; an outer peripheral p-type layer (42) disposed within the outer peripheral region to surround the element region and in a range including the upper surface of the substrate, and adjacent to the element p-type layer; a breakdown voltage p-type layer (44) disposed within the outer peripheral region, located on the outer peripheral side of the outer peripheral p-type layer, and in a range including the upper surface of the substrate, wherein the semiconductor device comprises: an interlayer insulating film (50) disposed on the upper surface of the substrate in the element region and the outer peripheral region; an upper electrode (14) disposed on the surface of the interlayer insulating film within the element region; and specific electrodes (51, 52) disposed on the surface of the interlayer insulating film within the outer peripheral region. A semiconductor device comprising: a semi-insulating film (56) disposed in the range from the upper electrode to the specific electrode, the semi-insulating film covering a part of the upper electrode, at least a part of the specific electrode, and the voltage-resistant p-type layer; and a protective insulating film (58) disposed on the surface of the semi-insulating film within the region of the semi-insulating film, wherein the specific electrode has a specific electrode upper surface (51u, 52u) parallel to the upper surface of the substrate, a specific electrode side surface (51s, 52s) connecting the specific electrode upper surface and the surface of the interlayer insulating film, and a specific electrode corner portion (51c, 52c) connecting the specific electrode upper surface and the specific electrode side surface, and the semi-insulating film is disposed continuously from the upper electrode to the specific electrode and covers the specific electrode corner portion.

2. The semiconductor device according to claim 1, wherein the specified electrode is a first electrode (51) disposed on the surface of the interlayer insulating film within the region of the outer peripheral p-type layer and surrounding the upper electrode, the upper surface of the specified electrode is the upper surface of the first electrode (51u), the side surface of the specified electrode is the side surface of the first electrode (51s) connecting the upper surface of the first electrode and the surface of the interlayer insulating film, the corner portion of the specified electrode is the corner portion of the first electrode (51c) connecting the upper surface of the first electrode and the side surface of the first electrode, and the semi-insulating film is continuously arranged from the upper electrode to the first electrode and covers the corner portion of the first electrode.

3. The semiconductor device according to claim 2, further comprising a recess (51r) formed on the upper surface of the first electrode, wherein the semi-insulating film is disposed within the recess.

4. The semiconductor device according to claim 3, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.

5. The semiconductor device according to claim 1, wherein the semiconductor substrate is disposed within the outer peripheral region, is disposed in a range including the upper surface of the substrate, and further comprises an outer peripheral n-type layer (46) that is spaced apart from the outer peripheral p-type layer and located further outward than the outer peripheral p-type layer, the breakdown voltage p-type layer (44) is located between the outer peripheral p-type layer and the outer peripheral n-type layer, the specific electrode is a second electrode (52) disposed on the surface of the interlayer insulating film within the region of the outer peripheral n-type layer and surrounding the upper electrode, the upper surface of the specific electrode is the upper surface of the second electrode (52u), the side surface of the specific electrode is a second electrode side surface (52s) connecting the upper surface of the second electrode and the surface of the interlayer insulating film, the corner of the specific electrode is a second electrode corner (52c) connecting the upper surface of the second electrode and the side surface of the second electrode, and the semi-insulating film is continuously disposed from the upper electrode to the second electrode and covers the corner of the second electrode.

6. The semiconductor device according to claim 5, further comprising a recess (52r) formed on the upper surface of the second electrode, wherein the semi-insulating film is disposed within the recess.

7. The semiconductor device according to claim 6, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.

8. The semiconductor substrate is located within the outer peripheral region, and further comprises an outer peripheral n-type layer (46) located within the region including the upper surface of the substrate, spaced apart from the outer peripheral p-type layer and located further outward than the outer peripheral p-type layer, the breakdown voltage p-type layer (44) is located between the outer peripheral p-type layer and the outer peripheral n-type layer, the specific electrode is a first electrode (51) located on the surface of the interlayer insulating film within the region of the outer peripheral p-type layer and surrounding the upper electrode, and a second electrode (52) located on the surface of the interlayer insulating film within the region of the outer peripheral n-type layer and surrounding the first electrode, the upper surface of the specific electrode is the upper surface of the first electrode (51u) and the upper surface of the second electrode (52u), the side surface of the specific electrode is a first electrode side surface (51s) connecting the upper surface of the first electrode and the surface of the interlayer insulating film, and a second electrode side surface (52s) connecting the upper surface of the second electrode and the surface of the interlayer insulating film. The semiconductor device according to claim 1, wherein the specific electrode corners are a first electrode corner (51c) connecting the upper surface of the first electrode and the side surface of the first electrode, and a second electrode corner (52c) connecting the upper surface of the second electrode and the side surface of the second electrode, and the semi-insulating film is arranged continuously from the upper electrode to the second electrode and covers the first electrode corner and the second electrode corner.

9. The semiconductor device according to claim 8, further comprising a recess (52r) formed on at least one of the upper surface of the first electrode and the upper surface of the second electrode, wherein the semi-insulating film is disposed within the recess.

10. The semiconductor device according to claim 9, wherein, in a vertical upward view of the upper surface of the substrate, the recess is formed in a groove shape so as to surround the element region.

11. The semiconductor device according to claim 1, wherein the semi-insulating film end (56e), which is the end of the semi-insulating film on the central side of the element region, is located within the region of the upper electrode, the protective insulating film end (58e), which is the end of the protective insulating film on the central side of the element region, is located within the region of the upper electrode and within the region of the semi-insulating film, and the semi-insulating film end protrudes more toward the center of the element region than the protective insulating film end.

12. The semiconductor device according to claim 11, wherein the protective insulating film has a protective insulating film upper surface (58u) parallel to the upper surface of the substrate and a protective insulating film side surface (58s) connecting the protective insulating film upper surface and the surface of the semi-insulating film, and in a cross section passing through the center of the element region and perpendicular to the upper surface of the substrate, the protective insulating film side surface has a curved surface that is convex downward.

13. The semiconductor device according to claim 1, wherein the semi-insulating film has a laminated structure comprising a first layer (56_1) and a second layer (56_2) disposed on the upper surface of the first layer, and the electrical resistance of the first layer is lower than that of the second layer.

14. A method for manufacturing a semiconductor device (1), wherein the semiconductor device comprises a semiconductor substrate (12) having an element region (20) and an outer peripheral region (40) arranged to surround the outer periphery of the element region, the semiconductor substrate comprising: an element p-type layer (36) arranged within the element region and in a range including the upper surface of the semiconductor substrate; an outer peripheral p-type layer (42) arranged within the outer peripheral region to surround the element region and in a range including the upper surface of the substrate, and in contact with the element p-type layer; a breakdown voltage p-type layer (44) arranged within the outer peripheral region and located on the outer peripheral side of the outer peripheral p-type layer, and in a range including the upper surface of the substrate, the semiconductor device comprising: an interlayer insulating film (50) arranged on the upper surface of the substrate in the element region and on the upper surface of the substrate in the outer peripheral region; an upper electrode (14) arranged on the surface of the interlayer insulating film within the element region; and specific electrodes (51, 52) arranged on the surface of the interlayer insulating film within the outer peripheral region. A semiconductor device comprising: a semi-insulating film (56) disposed in the range from the upper electrode to the specific electrode; and a protective insulating film (58) disposed on the surface of the semi-insulating film within the region of the semi-insulating film, wherein the manufacturing method comprises: a step (S4) of depositing the semi-insulating film on the entire surface of the semiconductor substrate on which the upper electrode, the specific electrode, and the breakdown p-type layer are formed; a step (S5) of depositing the protective insulating film on the entire surface of the semi-insulating film; a step (S6) of forming a mask having an opening corresponding to the element region; a step (S7) of forming an opening in the protective insulating film using the mask; and a step (S8) of isotropically etching the semi-insulating film through the opening in the protective insulating film.

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