Semiconductor wafer and semiconductor apparatus

Abstract

The present invention reduces the on-resistance of a vertical device of a semiconductor apparatus that comprises an SiC substrate and an AlGaN layer and includes a vertical device. A contact layer 20 that is formed from an AlxGa1-xN layer that has an Al composition of x at which the electron affinity of AlxGa1-xN and the electron affinity of SiC are substantially the same is formed on an SiC substrate 10 without an AlN layer therebetween.

Description

Semiconductor wafers and semiconductor devices

[0001] This disclosure relates to semiconductor wafers and semiconductor devices, and more particularly to technologies effective for use in semiconductor wafers and semiconductor devices having, for example, a silicon carbide substrate and an AlGaN layer.

[0002] Japanese Patent Publication No. 2007-214515 (Patent Document 1) describes a technique for increasing the breakdown voltage of a nitride semiconductor device by using an AlGaN layer instead of a GaN layer as the voltage-holding layer. Specifically, an AlGaN layer is formed on an n-type SiC substrate via an AlGaN buffer layer. The Al composition of the AlGaN layer is greater than or equal to the Al composition of the AlGaN buffer layer. This makes it possible to increase the breakdown voltage while suppressing crystal defects.

[0003] Japanese Patent Publication No. 2007-59719 (Patent Document 2) describes a technique for sequentially forming an AlGaN layer with a high impurity concentration (Al composition > 0) and an AlBGaN layer with a low impurity concentration (Al composition ≥ 0, B composition ≥ 0) on a SiC substrate.

[0004] Japanese Patent Publication No. 2000-40858 (Patent Document 3) describes a structure formed on a SiC substrate, 3 × 10 １８ ( / cm ３ ) ~ 1 x 10 ２０ ( / cm ３ Al having n-type carrier concentration ｘ Ga １－ｘ The N layers (0 < x < 0.4) are described.

[0005] Japanese Patent Publication No. 2007-214515, Japanese Patent Publication No. 2007-59719, Japanese Patent Publication No. 2000-40858

[0006] Silicon carbide (SiC) and gallium nitride (GaN) are known as wide-bandgap semiconductor materials (hereinafter referred to as WBG materials) with a larger bandgap than silicon. Because WBG materials have a high dielectric breakdown voltage, the breakdown voltage can be maintained even with a thin drift layer. For this reason, WBG materials are useful in that they can improve the trade-off relationship between improving breakdown voltage and reducing on-resistance.

[0007] In this regard, AlGaN has a larger bandgap than SiC or GaN. Therefore, AlGaN is an ultra-wide bandgap semiconductor material with a higher dielectric breakdown voltage than SiC or GaN. Consequently, AlGaN holds great potential for achieving both improved breakdown voltage and reduced on-resistance, which are typically in a trade-off relationship. For this reason, AlGaN is expected to be a semiconductor material for next-generation power devices.

[0008] AlGaN layers are used, for example, as drift layers. In this case, the AlGaN layer is often formed on a GaN or AlN substrate using an epitaxial growth method. However, when an AlGaN layer is formed on a GaN substrate, tensile strain is introduced, and cracks easily occur, making it impossible to form a thick film. When an AlGaN layer is formed on an AlN substrate, compressive strain is introduced into the AlGaN layer, which somewhat suppresses crack occurrence. However, since the AlN substrate is an insulator, it is difficult to configure it as a vertical device that carries current in the thickness direction of the semiconductor wafer (sometimes referred to as the longitudinal direction in this specification) from the back surface of the substrate.

[0009] In this regard, SiC substrates have a conductive substrate and a higher thermal conductivity than GaN or AlN substrates. Focusing on this point, from the viewpoint of improving the heat dissipation of semiconductor devices, it is being considered to form an AlGaN layer on a SiC substrate instead of a GaN or AlN substrate.

[0010] When forming an AlGaN layer on a SiC substrate using epitaxial growth, it is considered necessary to interpose a buffer layer between the AlGaN layer and the SiC substrate to mitigate lattice mismatch between SiC and AlGaN, and AlN is generally used as the buffer layer.

[0011] The inventor of the present invention is considering manufacturing a vertical device that allows current to flow in the vertical direction of a semiconductor wafer by using a semiconductor wafer provided with an AlGaN layer on a SiC substrate. When current flows in the vertical direction, the on-resistance becomes extremely high due to the AlN buffer layer. Therefore, it is necessary to use a semiconductor wafer provided with an AlGaN layer without an AlN buffer layer on the SiC substrate.

[0012] Therefore, in order to manufacture a semiconductor device including a vertical device with a low on-resistance using a semiconductor wafer including a SiC substrate and an AlGaN layer, a device is desired.

[0013] A semiconductor wafer according to one embodiment includes a silicon carbide substrate of a first conductivity type, and a first nitride semiconductor layer provided on the silicon carbide substrate, having the first conductivity type, and being Al ｘ Ga １－ｘ N (0.25 < x ≤ 0.5), and a second nitride semiconductor layer provided on the first nitride semiconductor layer, having the first conductivity type, and being Al ｙ Ga １－ｙ N (0 ≤ y ≤ 1).

[0014] According to one embodiment, in a semiconductor device including a SiC substrate and an AlGaN layer and including a vertical device, the on-resistance of the vertical device can be reduced.

[0015] It is a cross-sectional view showing the configuration of the semiconductor wafer in Embodiment 1. The SiC substrate and Al ｘ Ga １－ｘThis graph shows the dependence of the conduction band gap formed at the interface with the N layer on the Al composition x. This graph shows the relationship between the current density flowing in the first direction and the Al composition x. This graph shows the relationship between the current density flowing in the second direction and the Al composition x. This graph shows the relationship between the thickness of the contact layer and the impurity concentration. This is a cross-sectional view showing the configuration of a semiconductor device including a Schottky diode. This graph shows the relationship between the voltage between the upper electrode and the lower electrode and the current density flowing through the Schottky diode. This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 2. This is a cross-sectional view showing the manufacturing process of a semiconductor device following Figure 8. This is a cross-sectional view showing the manufacturing process of a semiconductor device following Figure 9. This graph shows the relationship between the voltage between the upper electrode and the lower electrode and the current density flowing through the Schottky diode. This is a cross-sectional view showing the configuration of a semiconductor device including a pn junction diode. This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 3. This is a cross-sectional view showing the manufacturing process of a semiconductor device following Figure 13. This is a cross-sectional view showing the manufacturing process of a semiconductor device following Figure 14.

[0016] The following disclosures of embodiments or examples refer to the accompanying drawings. Identical reference symbols (e.g., numbers and / or letters) in different drawings may indicate the same or similar elements.

[0017] When used in this disclosure, terms indicating that one element (e.g., a layer, region, and / or substrate) is “on” or “over” another element may indicate that the element may be “directly on” or “indirectly above” another element, with or without intervening elements. Furthermore, when used in this disclosure, terms indicating that one element is “directly on” or “directly over” another element may indicate that there are no intervening elements between them.

[0018] In this disclosure, impurities can generally be referred to as having the following conductivity types: “First conductivity type” corresponds to n-type, and “Second conductivity type” corresponds to p-type. However, this definition can be reversed as appropriate.

[0019] <Novel findings discovered by the inventors> When manufacturing a vertical device using a semiconductor wafer in which an AlGaN layer is provided on a SiC substrate via an AlN buffer layer, the inventors have discovered, as a novel finding, that the on-resistance becomes very high due to the AlN buffer layer (AlN layer).

[0020] The following explains why the on-resistance becomes very high due to the AlN layer.

[0021] First, let's explain electron affinity. Electron affinity is the difference between the vacuum energy level and the energy level at the conduction band edge. That is, if we let electron affinity be "χ", the vacuum energy level be "Evac", and the energy level at the conduction band edge be "Ec", then χ = Evac - Ec.

[0022] The electron affinity of SiC and AlN differs significantly. That is, the energy levels at the conduction band edge of SiC and AlN differ greatly. Therefore, a discontinuity occurs at the interface where a SiC substrate and an AlN layer are in contact. As a result, a potential barrier is generated at the interface due to this discontinuity.

[0023] In vertical devices, current flows across the aforementioned interface. Therefore, the electrons constituting the current must overcome the potential barrier. As a result, the on-resistance (parasitic resistance) when the current flows becomes high.

[0024] For the reasons stated above, when manufacturing vertical devices using a semiconductor wafer in which an AlGaN layer is provided on a SiC substrate via an AlN layer, the on-resistance becomes high due to the AlN layer.

[0025] Therefore, there is a need for innovations to manufacture semiconductor devices, including vertical devices with low on-resistance, using semiconductor wafers comprising a SiC substrate and an AlGaN layer.

[0026] The following explains the technical concept behind this disclosure.

[0027] <Basic Idea> First, let's focus on the following facts.

[0028] The electron affinity of SiC lies between that of GaN and that of AlN (Fact 1). ｘ Ga １－ｘ The electron affinity of N is the same as that of GaN when x = 0, and the electron affinity of AlN is the same as that of AlN when x = 1. Therefore, when 0 < x < 1, Al ｘ Ga １－ｘ The electron affinity of N lies between the electron affinity of GaN and the electron affinity of AlN (Fact 2). That is, Al ｘ Ga １－ｘ The electron affinity of N varies between the electron affinity of GaN and the electron affinity of AlN, depending on the Al composition x. Therefore, considering facts 1 and 2 above, Al ｘ Ga １－ｘ There must always exist an Al composition x where the electron affinity of N matches the electron affinity of SiC. ｘ Ga １－ｘ The fact that the electron affinity of N matches that of SiC means that the SiC substrate and Al ｘ Ga １－ｘ This means that the discontinuity at the conduction band edge can be reduced at the interface where N is in contact. As a result, the height of the potential barrier generated at the interface due to the discontinuity at the conduction band edge can be reduced. This makes it easier for electrons constituting the current to overcome the potential barrier in a vertical device where current flows across the aforementioned interface. In other words, the on-resistance (parasitic resistance) when current flows can be reduced.

[0029] Considering the above, the basic idea is to use Al without the intermediary of an AlN layer. ｘ Ga １－ｘ Al has an Al composition x in which the electron affinity of N and the electron affinity of SiC are approximately equal. ｘ Ga １－ｘ This concept involves manufacturing vertical devices using a semiconductor wafer with an N-layer formed on a SiC substrate.

[0030] Specifically, the basic concept is to use a semiconductor wafer having the following configuration:

[0031] The semiconductor wafer comprises a first conductivity type SiC substrate, a first conductivity type contact layer provided on the SiC substrate, and a first conductivity type drift layer provided on the contact layer. The contact layer is made of Al ｘ Ga １－ｘ It is an N-layer (0.25 < x ≤ 0.5), and the drift layer is Al ｙ Ga １－ｙ It is an N-layer (0 ≤ y ≤ 1). In particular, the basic idea is Al ｘ Ga １－ｘ Al has an Al composition x in which the electron affinity of N and the electron affinity of SiC are almost the same. ｘ Ga １－ｘ As the N layer, Al ｘ Ga １－ｘ A distinctive feature is that it uses an N-layer structure (0.25 < x ≤ 0.5).

[0032] According to the basic concept, on a SiC substrate and Al ｘ Ga １－ｘ No AlN layer is interposed between the N layer and the AlGaN layer. This suppresses the extremely high on-resistance of vertical devices caused by the AlN layer. In other words, according to the basic idea, (1) high heat dissipation due to the SiC substrate, (2) high breakdown voltage due to the AlGaN layer which is an ultra-wide bandgap semiconductor material, (3) reduction of parasitic resistance by not interposing an AlN layer at the interface between the SiC substrate and the AlGaN layer, and (4) Al on the SiC substrate ｘ Ga １－ｘ By reducing parasitic resistance through the provision of an N layer (0.25 < x ≤ 0.5), the performance of semiconductor devices, including vertical devices, can be improved.

[0033] In the following, we will describe an embodiment that embodies the basic concept, with the first conductivity type being n-type.

[0034] <Embodiment 1> <<Semiconductor Wafer Configuration>> Figure 1 is a cross-sectional view showing the configuration of a semiconductor wafer WF in Embodiment 1.

[0035] In Figure 1, the semiconductor wafer WF has a SiC substrate 10, a contact layer (first nitride semiconductor layer) 20, and a drift layer (second nitride semiconductor layer) 30. The semiconductor wafer WF is a wafer for forming a vertical device that conducts current in the thickness direction (Z direction).

[0036] The SiC substrate 10 is, for example, a 4H-SiC substrate having an upper surface and a lower surface. An n-type impurity (donor) is introduced into the SiC substrate 10. The n-type impurity is, for example, nitrogen (N). The impurity concentration of the SiC substrate 10 is, for example, 2 × 10⁻¹⁶. １８ ( / cm ３ ) is approximately the extent of this. In this specification, "impurity concentration" refers to the concentration of impurities that determine the conductivity type and conductivity of the semiconductor, and can also be referred to as dopant concentration.

[0037] A contact layer 20 is provided on the upper surface of the SiC substrate 10. The contact layer 20 is made of Al ｘ Ga １－ｘ The N layer (0.25 < x ≤ 0.5) contains n-type impurities. The n-type impurities are, for example, silicon (Si). The contact layer 20 has an impurity concentration of, for example, 5 × 10⁻¹⁰. １８ ( / cm ３ ) is of a certain degree, and the thickness is, for example, about 15 nm. In Embodiment 1, the thickness of the contact layer 20 (cm) and the impurity concentration of the contact layer 20 ( / cm) are ３ The product of ) is 4.5 × 10 １４ ( / cm ２ The following applies: The contact layer 20 is provided so as to be in direct contact with the SiC substrate 10, and consists of silicon carbide and Al ｘ Ga １－ｘ It forms a heterointerface of N.

[0038] A drift layer 30 is provided on top of the contact layer 20. The drift layer 30 is made of Al ｙ Ga １－ｙ The layer is an N-layer (0 ≤ y ≤ 1) and contains n-type impurities. The n-type impurities are, for example, silicon (Si). The drift layer 30 has an impurity concentration of, for example, 5 × 10⁻¹⁶. １７ ( / cm ３ The impurity concentration is approximately 0.5 μm (500 nm), and the thickness is, for example, approximately 0.5 μm (500 nm). Here, the combination of impurity concentration and thickness of the drift layer 30 can be designed to minimize the drift layer resistance according to the target breakdown voltage. For example, the impurity concentration is 1 × 10⁻⁶. １６ ~5 x 10１７ ( / cm ３ The thickness can be approximately 0.5 to 10 μm.

[0039] The drift layer 30 may contain carbon (C) and oxygen (O) incorporated during crystal growth. The carbon concentration within the drift layer 30 is 10 １６ ( / cm ３ It is below the order of ). The oxygen concentration in the drift layer 30 is 10 １６ ( / cm ３ It is below the order of )

[0040] <<Method of Manufacturing Semiconductor Wafers>> Next, the method of manufacturing semiconductor wafers (WF) will be explained with reference to Figure 1.

[0041] First, for example, a SiC substrate 10 made of 4H-SiC single crystal is prepared. Nitrogen, an n-type impurity, is introduced into the SiC substrate 10, and the impurity concentration of the SiC substrate 10 is, for example, 2 × 10 １８ ( / cm ３ ) is the extent of it. The SiC substrate 10 is cut from a SiC ingot. To enable the growth of good AlGaN crystals on the upper surface, the SiC substrate 10 is an off-surface substrate cut with the substrate surface orientation tilted by 0.4 degrees from the silicon surface (Si surface) in the "a-plane direction" {11-20}. The silicon surface on which crystal growth is performed is mirror polished.

[0042] Next, a contact layer 20 is formed on the SiC substrate 10. Specifically, AlGaN crystals are grown on the SiC substrate 10 by using the epitaxial growth method in the chamber of a reduced-pressure MOCVD (Metal Organic Chemical Vapor Deposition) apparatus. For example, "trimethylaluminum (TMAl)" is used as the raw material for Al. For example, "trimethylgallium (TMGa)" is used as the raw material for Ga. For example, "ammonia (NH4)" is used as the raw material for N. ３ ) is used. In addition, as a raw material for the n-type impurity Si, "silane (SiH)" is used. ４ ) is used, and hydrogen (H) is used as the carrier gas. ２) is used. The substrate temperature in this process is set to 1100 degrees Celsius, and the chamber pressure is adjusted to 50 to 150 Torr (50 to 150 × 133.32 Pa). SiH ４ The gas flow rate is calculated based on the concentration of Si, an n-type impurity, which is 5 × 10⁻⁶. １８ ( / cm ３ ) are adjusted to be the case. Also, TMAl, TMGa and NH ３ The gas flow rate ratio is adjusted so that the Al composition x is 0.25 < x ≤ 0.5. In this way, an Al layer with a thickness of about 15 nm is formed. ｘ Ga １－ｘ A contact layer 20, which is an N layer (0.25 < x ≤ 0.5), is provided.

[0043] Subsequently, a drift layer 30 is provided on the contact layer 20. The drift layer 30 is made of TML, TMGa, and NH ３ The gas flow rate ratio was changed, and the Si concentration was increased to 5 × 10 １７ ( / cm ３ ) so that SiH ４ The gas flow rate is adjusted. Under these conditions, an epitaxial growth method is used to grow an Al layer approximately 0.5 μm thick. ｙ Ga １－ｙ A drift layer 30 with N layers (0 ≤ y ≤ 1) is provided.

[0044] As described above, semiconductor wafers (WF) can be manufactured.

[0045] The Al that constitutes the resulting contact layer 20 ｘ Ga １－ｘ Analysis of the N layer (0.25 < x ≤ 0.5) using X-ray reciprocal lattice mapping (RSM) confirmed that the lattice strain was almost 100% relaxed. Surface morphology observation of the contact layer 20 using atomic force microscopy (AFM) revealed that there were no cracks and the Al layer was atomically flat. ｘ Ga １－ｘIt was confirmed that the N layer (0.25 < x ≤ 0.5) was obtained. Further, as a result of lattice image observation by cross-sectional TEM, it was confirmed that the interface between the SiC substrate 10 and the contact layer 20 is steep at the atomic level and an interface close to ideal without an intervening interface transition layer is formed. From the above results, it is verified that the semiconductor wafer in Embodiment 1 is excellent in quality.

[0046] <<First Feature Point in Embodiment 1>> Next, the first feature point in Embodiment 1 will be described.

[0047] The first feature point is, for example, as shown in FIG. 1, in the semiconductor wafer WF for forming a vertical device that conducts current in the thickness direction (Z direction), Al is provided on the SiC substrate 10 ｘ Ga １－ｘ N layer (0.25 < x ≤ 0.5). That is, the first feature point is that without intervening an AlN layer, Al ｘ Ga １－ｘ N having an Al composition x in which the electron affinity of AlGaN and the electron affinity of SiC are substantially the same is provided on the SiC substrate 10. ｘ Ga １－ｘ N layer is provided on the SiC substrate 10.

[0048] Thereby, the potential barrier at the interface between the SiC substrate 10 and the contact layer 20 can be reduced. As a result, according to Embodiment 1, the on-resistance when current flows through the vertical device manufactured using the semiconductor wafer can be reduced.

[0049] Hereinafter, the technical significance of setting the upper limit value of the Al composition x to "0.5" will be described.

[0050] FIG. 2 is a graph showing the dependence of the conduction band gap ΔEc formed at the heterointerface between the SiC substrate and the Al ｘ Ga １－ｘ N layer on the Al composition x.

[0051] In FIG. 2, the vertical axis represents the conduction band gap ΔEc. The horizontal axis represents the Al composition x. The conduction band gap ΔEc corresponds to the potential barrier. The Al composition x is represented by x = [Al] / ([Al] + [Ga]). The Al composition x is in the range of 0 ≤ x ≤ 1.

[0052] In FIG. 2, first, focus on point A. Point A corresponds to an Al composition x = 0. That is, when the Al ｘ Ga １－ｘ N layer becomes a GaN layer. On the left side of FIG. 2, a band diagram near the interface between the SiC substrate and the GaN layer is shown.

[0053] As shown in this band diagram, when taking the conduction band edge of SiC as a reference, the conduction band gap ΔEc existing at the interface between SiC and GaN is ΔEc = -0.70 eV.

[0054] Next, focus on point B. Point B corresponds to an Al composition x = 1. That is, when the Al ｘ Ga １－ｘ N layer becomes an AlN layer. On the right side of FIG. 2, a band diagram near the interface between the SiC substrate and the AlN layer is shown.

[0055] As shown in this band diagram, when taking the conduction band edge of SiC as a reference, the conduction band gap ΔEc existing at the interface between SiC and AlN is ΔEc = +0.78 eV.

[0056] As shown in FIG. 2, the value of the conduction band gap ΔEc changes along the straight line connecting point A and point B. Therefore, as can be seen from FIG. 2, ΔEc ≒ 0 near the Al composition x = 0.5. This means that when the Al composition x = 0.5, the potential barrier almost disappears. That is, it can be seen that the Al composition x at which the electron affinity of Al ｘ Ga １－ｘ N and the electron affinity of SiC are substantially the same is x = 0.5. Therefore, from the viewpoint of approaching the conduction band gap ΔEc to "0", it is desirable to set the Al composition x = 0.5.

[0057] Next, in the diode described in Embodiment 2 or Embodiment 3, a cathode electrode is provided on the lower surface of the SiC substrate 10, and an anode electrode is provided above the SiC substrate 10. Therefore, in the diode, current flows in the first direction (-Z direction) from the anode electrode toward the cathode electrode. Therefore, when assuming a diode as a vertical device manufactured using the semiconductor wafer WF, it is desirable that current flows with low resistance in the first direction.

[0058] In contrast, when considering a power transistor as a vertical device manufactured using a semiconductor wafer (WF), the drain electrode is generally placed on the underside of the semiconductor substrate, and the source electrode is placed on the upper side of the semiconductor substrate. Therefore, in a power transistor, current flows in a second direction (+Z direction) from the drain electrode to the source electrode. Consequently, when considering a power transistor as a vertical device manufactured using a semiconductor wafer (WF), it is desirable for the current to flow in the second direction with low resistance.

[0059] Based on the above, if we consider both diodes and power transistors as vertical devices manufactured using semiconductor wafers (WF), then Al ｘ Ga １－ｘ The first direction (-Z direction) from the N layer toward the SiC substrate 10, and from the SiC substrate 10 toward Al ｘ Ga １－ｘ It is desirable for current to flow with low resistance in both directions, including the second direction toward the N layer (+Z direction).

[0060] Therefore, we evaluated how the parasitic resistance changes depending on the Al composition x when current flows in the first direction, and how the parasitic resistance changes depending on the Al composition x when current flows in the second direction. The following conditions were used for the evaluation.

[0061] (Conditions) SiC substrate 10 (impurity concentration = 2×10 １８ / cm ３ ) Al ｘ Ga １－ｘ N layer (impurity concentration = 5×10 １８ / cm ３ ) Al ｘ Ga １－ｘ Under the conditions described above, when current flows in the first direction, a positive voltage is applied to the first ohmic electrode while the second ohmic electrode is grounded. When current flows in the second direction, the first ohmic electrode is grounded while a positive voltage is applied to the second ohmic electrode.

[0062] Figure 3 is a graph showing the relationship between the current density flowing in the first direction and the Al composition x.

[0063] In Figure 3, the vertical axis represents the current density (A / cm²) flowing in the first direction. ２ The horizontal axis represents the voltage (V) applied to the first ohmic electrode.

[0064] As shown in Figure 3, in the range of Al composition x = 0.3 to x = 0.5, parasitic resistance (corresponding to on-resistance) decreases as Al composition x increases. On the other hand, when Al composition x exceeds x = 0.5 and reaches x = 0.6 and x = 0.7, parasitic resistance increases sharply. Therefore, when current flows in the first direction, it is desirable that x ≤ 0.5 in order to reduce parasitic resistance. For the above reasons, the upper limit of Al composition x is set to "0.5".

[0065] Next, we will explain the technical significance of setting the lower limit of Al composition x to "0.25".

[0066] Figure 4 is a graph showing the relationship between the current density flowing in the second direction and the Al composition x.

[0067] In Figure 4, the vertical axis represents the current density (A / cm²) flowing in the second direction. ２ The horizontal axis represents the voltage (V) applied to the first ohmic electrode.

[0068] As shown in Figure 4, when the Al composition x decreases to x = 0.25, the parasitic resistance increases sharply. Therefore, when current flows in the second direction, it is desirable that 0.25 < x in order to reduce the parasitic resistance. For this reason, the lower limit of the Al composition x is set to "0.25". Also, reducing the Al composition x reduces the band gap. A smaller band gap means a lower dielectric breakdown voltage. For this reason, from the standpoint of ensuring withstand voltage, it is advisable to avoid making the Al composition x too small. From this standpoint as well, it is desirable to set the lower limit of the Al composition x to "0.25".

[0069] <<Second characteristic feature in Embodiment 1>> Next, the second characteristic feature in Embodiment 1 will be explained.

[0070] The second characteristic feature is the thickness (cm) of the contact layer 20 and the impurity concentration ( / cm) of the contact layer 20. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ The key point is that it is less than or equal to ). That is, if the thickness of the contact layer 20 is d1 (cm), then the impurity concentration of the contact layer 20 is n1 ( / cm²). ３ If so, the second feature point is n1 × d1 ≤ 4.5 × 10 １４ ( / cm ２ )

[0071] The technical significance of the second feature point will be explained below.

[0072] For example, cracks may occur on the upper surface of the contact layer 20. In this case, it is known that the leakage current increases when the vertical device is turned off due to the cracks. Also, surface roughness may occur on the upper surface of the contact layer 20. In this case, there is concern that the manufacturing yield of semiconductor devices including vertical devices will decrease.

[0073] Therefore, it is desirable to suppress the occurrence of cracks on the upper surface of the contact layer 20 and to suppress surface roughness on the upper surface of the contact layer 20.

[0074] In this regard, according to the inventors' findings, the cause of cracks and surface roughness is the contact layer 20, Al ｘ Ga １－ｘ It was found that the result does not depend on the Al composition x of the N layer, but on the thickness and impurity concentration of the contact layer 20. Furthermore, as a result of further investigation, the inventors found that the thickness (cm) of the contact layer 20 and the impurity concentration ( / cm) of the contact layer 20 are related. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ The inventors have discovered, as a novel finding, that cracks and surface roughness can be suppressed if the following conditions are met. Therefore, the second characteristic point serves as an important guideline for realizing a contact layer 20 that can suppress the occurrence of cracks and surface roughness.

[0075] Figure 5 shows the thickness d1 (nm) and impurity concentration n1 ( / cm³) in the contact layer 20. ３This graph shows the relationship between the two. In Figure 5, the vertical axis represents the thickness d1 (nm). The horizontal axis represents the impurity concentration n1 ( / cm³). ３ This indicates that...

[0076] The dashed line represents n1 ( / cm ３ )×d1(cm)=4.5×10 １４ ( / cm ２ This shows the curve represented by ). Therefore, the area to the left of the dashed line is n1 ( / cm ３ )×d1(cm)<4.5×10 １４ ( / cm ２ This is the region represented by ). On the other hand, the region to the right of the dashed line is n1 ( / cm ３ ) x d1 (cm) > 4.5 x 10 １４ ( / cm ２ This is the region represented by ).

[0077] In Figure 5, the circles indicate combinations of thickness and impurity concentration corresponding to contact layer 20 without cracks or surface roughness. In contrast, the crosses indicate combinations of thickness and impurity concentration corresponding to contact layer 20 with cracks or surface roughness. The circles are located in the area to the left of the dashed line, and the crosses are located in the area to the right of the wavy line. This means that the wavy line functions as a boundary line to distinguish between the presence or absence of cracks and surface roughness. That is, the thickness (cm) of the contact layer 20 and the impurity concentration ( / cm) of the contact layer 20. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ Figure 5 supports the idea that cracks and surface roughness can be suppressed if the following conditions are met.

[0078] Based on the above, the second characteristic feature has technical significance in that it provides useful guidelines for realizing a contact layer 20 that can suppress the occurrence of cracks and surface roughness.

[0079] The thickness of the contact layer 20 is preferably 95 nm or less, more preferably 60 nm or less, and even more preferably 40 nm or less. This further reduces the parasitic resistance of the contact layer 20.

[0080] <<Third Feature Point in Embodiment 1>> Next, the third feature point in Embodiment 1 will be explained.

[0081] The third characteristic is that, regarding the carbon and oxygen that may be incorporated into the drift layer 30 during growth, the carbon concentration within the drift layer 30 is 10 １６ ( / cm ３ ) is below the order of 10, and the oxygen concentration in the drift layer 30 is 10 １６ ( / cm ３ The key point is that it is below the order of ).

[0082] The technical significance of the third feature point will be explained below.

[0083] Al constituting the drift layer 30 ｙ Ga １－ｙ The N layer (0 ≤ y ≤ 1) is formed, for example, by the MOCVD method. In the MOCVD method, carbon and oxygen inevitably become mixed into the drift layer 30. Carbon and oxygen are known to exhibit acceptor and donor behavior in AlGaN crystals, and are factors that affect the control of conductive impurities. Therefore, if the amount of carbon and oxygen mixed into the drift layer 30 increases, it may lead to effects such as a decrease in conductivity in AlGaN, a decrease in the controllability of carrier concentration, or a decrease in the activation rate of conductive impurities. For this reason, it is desirable to reduce the amount of carbon and oxygen mixed into the drift layer 30.

[0084] In this regard, in Embodiment 1, in order to reduce the amount of carbon and oxygen mixed into the drift layer 30, Al is prepared by the MOCVD method. ｙ Ga １－ｙ The conditions for forming the N layer (0 ≤ y ≤ 1) are being improved. Specifically, the chamber pressure in the MOCVD method is being increased. This improves the Al ｙ Ga １－ｙ The carbon and oxygen concentrations in the N layer (0 ≤ y ≤ 1) can be reduced. However, increasing the chamber pressure in the MOCVD method will also decrease the Al concentration.

[0085] Therefore, the carrier gas is T ２The flow rate is increased. In other words, in Embodiment 1, the chamber pressure in the MOCVD method is increased, and the carrier gas H ２ The flow rate is increased. As a result, according to Embodiment 1, the carbon concentration and oxygen concentration in the drift layer 30 can be reduced without lowering the Al concentration. Specifically, according to Embodiment 1, the carbon concentration in the drift layer 30 is reduced to 10 １７ ( / cm ３ ) Reduce from the order to 10 １６ ( / cm ３ ) can be reduced to the order of 10, and the oxygen concentration in the drift layer 30 can be reduced to 10 １７ ( / cm ３ ) Reduce from the order to 10 １６ ( / cm ３ This can be reduced to the order of ) or less. According to Embodiment 1, this makes it possible to improve the activation rate and controllability of Si in the drift layer 30. In other words, by realizing the third feature point, Al ｙ Ga １－ｙ This can improve the activation rate and controllability of Si within the N layer (0 ≤ y ≤ 1).

[0086] <<Modification of Embodiment 1>> Generally, the conductivity of a semiconductor increases with the concentration of impurity doping.

[0087] For example, to improve the conductivity of an n-type semiconductor, an n-type impurity (donor) having a donor level near the conduction band is introduced into the semiconductor. This excites electrons from the donor level to the conduction band, thereby increasing the conductivity of the n-type semiconductor.

[0088] While Si is known as an n-type impurity in AlGaN, the band gap widens rapidly as the Al composition increases, resulting in an ultrawide-band gap semiconductor. This increases the activation energy required to excite electrons from the Si donor level to the conduction band. Consequently, the activation rate of n-type impurities decreases. This means that it is difficult to improve the conductivity of n-type AlGaN through impurity doping alone. Therefore, it is difficult to reduce the on-resistance of the drift layer 30.

[0089] Therefore, in the modified version, not only impurity doping but also polarization doping, which in principle results in zero activation energy, is used.

[0090] In polarization doping, for example, Al is used along the thickness direction (Z direction). ｙ Ga １－ｙ By changing the Al composition y of the N layer, ｙ Ga １－ｙ Polarization occurs within the N layer based on changes in Al composition, and carriers are attracted to the fixed charge corresponding to the difference in polarization, ｙ Ga １－ｙ This increases the carrier concentration in the N layer. As a result, Al ｙ Ga １－ｙ The conductivity of the N layer can be improved.

[0091] For example, n-type Al ｙ Ga １－ｙ To increase the conductivity of the N layer, the Al composition y is increased along the +Z direction. In other words, the Al composition in the drift layer 30 is changed so that it increases from the interface between the drift layer 30 and the contact layer 20 toward the upper surface of the drift layer 30. This makes it possible to increase the conductivity of the drift layer 30. That is, in the modified example, by combining impurity doping and polarization doping, Al ｙ Ga １－ｙ The parasitic resistance of the drift layer 30 having a composition of N (0 ≤ y ≤ 1) can be reduced. In a modified example, the on-resistance of a vertical device manufactured using a semiconductor wafer can be further reduced by combining the first feature point in Embodiment 1 with the use of polarization doping.

[0092] <Embodiment 2> Embodiment 2 describes an example of a vertical device manufactured using the semiconductor wafer WF described in Embodiment 1. Examples of vertical devices include power transistors and diodes. Embodiment 2 uses a Schottky barrier diode as the vertical device. The Schottky barrier diode may be abbreviated as SBD or Schottky diode below. The SBD is applied, for example, to regenerative diodes used in DC / DC converters that perform high-frequency operation. The SBD described in Embodiment 2 can be applied to power conversion devices such as automotive inverters, automotive converters, industrial inverters, and industrial converters. Furthermore, the SBD in Embodiment 2 is expected to be used in high-voltage power supplies used in medical equipment, for example, by taking advantage of the high voltage resistance of AlGaN, an ultra-wide bandgap semiconductor material.

[0093] <<Configuration of a semiconductor device including a Schottky barrier diode (SBD)>> Figure 6 is a cross-sectional view showing the configuration of a semiconductor device 100 including an SBD.

[0094] The semiconductor device 100 includes a SiC substrate 10, a contact layer 20, a drift layer 30, a lower electrode 40, an insulating portion 50A, an insulating portion 50B, an insulating film 60, and an upper electrode 70.

[0095] The SiC substrate 10 has nitrogen, an n-type impurity, introduced into it. Therefore, the SiC substrate 10 is an n-type semiconductor substrate. The SiC substrate 10 has an upper surface and a lower surface.

[0096] A contact layer 20 is provided on the upper surface of the SiC substrate 10. The contact layer 20 is made of Al ｘ Ga １－ｘ The N layer is (0.25 < x ≤ 0.5). The contact layer 20 is an n-type semiconductor layer into which the n-type impurity Si is introduced. In addition, in the contact layer 20, the thickness (cm) and impurity concentration ( / cm) are specified. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ ) The following:

[0097] A lower electrode 40 is provided on the lower surface of the SiC substrate 10. The lower electrode 40 is, for example, a NiSi film.

[0098] A drift layer 30 is provided on the contact layer 20. The drift layer 30 is made of Al ｙ Ga １－ｙ It is an N-layer (0 ≤ y ≤ 1). The drift layer 30 is an n-type semiconductor layer into which the n-type impurity Si is introduced. The impurity concentration of the drift layer 30 is lower than the impurity concentration of the contact layer 20. The drift layer 30 may contain carbon and oxygen, and the carbon concentration within the drift layer 30 is 10 １６ ( / cm ３ It is below the order of ). The oxygen concentration in the drift layer 30 is 10 １６ ( / cm ３ It is below the order of )

[0099] Insulating portions 50A and 50B are formed in the X direction, separated from each other. Each of insulating portions 50A and 50B is formed to penetrate the drift layer 30 and the contact layer 20 and reach into the SiC substrate. The contact layer 20 and the drift layer 30 are formed in the portion sandwiched between insulating portions 50A and 50B.

[0100] An insulating film 60 is provided on the insulating portion 50A and the insulating portion 50B. The insulating film 60 is, for example, a silicon oxide film. An opening OP is formed in the insulating film 60. The upper surface of the drift layer 30 is exposed through the opening OP.

[0101] An upper electrode 70 is provided on the upper surface of the drift layer 30 exposed from the opening OP. The upper electrode 70 is also provided so as to overlap a portion of the insulating film 60. The upper electrode 70 is, for example, a Ni film. The drift layer 30 and the upper electrode 70 are in Schottky contact. In this way, the semiconductor device 100 including the SBD is constructed.

[0102] An SBD consists of a SiC substrate 10, a contact layer 20, a drift layer 30, a lower electrode 40, and an upper electrode 70. The lower electrode 40 is the cathode electrode, while the upper electrode 70 is the anode electrode. The combined region of the SiC substrate 10, contact layer 20, and drift layer 30 constitutes the cathode region. The cathode region is electrically connected to the lower electrode 40, which is the cathode electrode.

[0103] In the SBD, when a positive voltage is applied to the upper electrode 70 and a negative voltage is applied to the lower electrode 40, the Schottky barrier formed at the interface between the drift layer 30 and the upper electrode 70 collapses, and a forward current flows. The forward current flows through the path upper electrode 70 → drift layer 30 → contact layer 20 → SiC substrate 10 → lower electrode 40. In contrast, in the SBD, when a negative voltage is applied to the upper electrode 70 and a positive voltage is applied to the lower electrode 40, the Schottky barrier becomes higher and almost no current flows. The SBD in Embodiment 2 is a vertical device in which current flows in the thickness direction (-Z direction).

[0104] The SBD in Embodiment 2 has the same characteristics as in Embodiment 1, and can reduce the potential barrier at the interface between the SiC substrate 10 and the contact layer 20. As a result, the SBD in Embodiment 2 can reduce the on-resistance when forward current flows.

[0105] Thickness (cm) and impurity concentration ( / cm) of the contact layer 20 of the SBD in Embodiment 2 ３ The product of ) is 4.5 × 10 １４ ( / cm ２ ) The following applies. Therefore, the occurrence of cracks and surface roughness can be suppressed in the contact layer 20.

[0106] Therefore, according to the SBD in Embodiment 2, the increase in leakage current when off can be suppressed, and the decrease in the manufacturing yield of the semiconductor device 100 including the SBD can be suppressed.

[0107] <<Verification of the effect of the third feature point>> The third feature point in Embodiment 1 is adopted in Embodiment 2. Below, the effect of applying the third feature point to the Schottky barrier diode (SBD) in Embodiment 2 will be explained.

[0108] To verify this effect, a test element was fabricated in which the contact layer 20 and the drift layer 30 were combined into a single layer in the SBD structure shown in Figure 6. Although the single drift layer 30 also served as the contact layer 20, the test element effectively functioned as an SBD.

[0109] Table 1 shows the main parameters of the prototype test element, the carbon and oxygen concentrations in the drift layer, and the evaluation results of the effective donor concentration Nd(efff). The carbon and oxygen concentrations were measured using SIMS (Secondary Ion Mass Spectrometry). The effective donor concentration was calculated from the C-V characteristics (capacitance-voltage characteristics) of the test element as 1 / C. ２ - A V-plot was created, and the slope of the plot was used to determine the relative permittivity of AlGaN (εr = 10.2).

[0110] Two test elements were prepared: Sample 1 as a comparative example and Sample 2 as an embodiment 2. Both Sample 1 and Sample 2 shared the same characteristics: the Al composition of the drift layer was y = 0.3, and the film thickness was 0.5 μm. The concentration of Si impurities added to the drift layer was approximately the same for both samples.

[0111] On the other hand, in Sample 2, in order to verify the third characteristic point in Embodiment 1, the epitaxial crystal growth conditions of the drift layer by MOCVD were adjusted as described in Embodiment 1. As a result, the concentrations of carbon and oxygen in Sample 2 were reduced to about 1 / 10 of those in Sample 1. Consequently, the effective donor concentration Nd(eff) of the drift layer in Sample 2 was improved to about five times that of Sample 1. In other words, the Si activation rate was significantly improved in Sample 2.

[0112] Figure 7 shows the voltage (V) between the upper electrode 70 and the lower electrode 40 and the current density (A / cm²) flowing through the SBD. ２ This graph shows the J-V characteristic (current density-voltage characteristic), which is the relationship between the two. It can be seen that the forward current of the SBD in Sample 2 (S2) is about an order of magnitude higher in current density than the forward current of the SBD in Sample 1 (S1).

[0113] From the above, it is confirmed that applying the third characteristic point described in Embodiment 1 to the SBD can significantly improve the activation rate of Si introduced in the drift layer 30. As a result, it is also shown that the third characteristic point contributes to improving the conductivity of the drift layer 30 and increasing the current density of the SBD.

[0114] <<Manufacturing Method for Semiconductor Device Including Schottky Barrier Diodes (SBDs)>> Next, an example of a manufacturing method for semiconductor device 100 will be described.

[0115] First, as shown in Figure 8, a semiconductor wafer is prepared in which a contact layer 20 is provided on the upper surface of a SiC substrate 10, and a drift layer 30 is provided on the contact layer 20. In Embodiment 2, the Al composition of the contact layer 20 and the drift layer 30 is set to "0.3".

[0116] The semiconductor wafer used is the semiconductor wafer WF from Embodiment 1. The thickness and impurity concentration of the drift layer 30 are designed considering the breakdown voltage and on-resistance of the SBD to be manufactured, and the growth conditions are controlled to adjust them to the desired design values. The thickness of the SiC substrate 10 is adjusted to the target design value as appropriate by using a chemical mechanical polishing method (CMP method) or a polishing method.

[0117] Next, as shown in Figure 9, an insulating film 51 is provided on the drift layer 30, for example, by using the CVD (Chemical Vapor Deposition) method. The insulating film 51 is, for example, a silicon oxide film, and its thickness is, for example, about 50 nm.

[0118] Subsequently, a resist film 52 is applied onto the insulating film 51. Then, the resist film 52 is patterned using photolithography technology. The patterning of the resist film 52 is performed in such a way that the regions for forming the insulating portions 50A and 50B are opened. The thickness of the resist film 52 is, for example, about 3 μm.

[0119] Next, boron (B) is introduced into the semiconductor wafer by ion implantation using the patterned resist film 52 as a mask. The ion implantation conditions for boron are, for example, 7-stage implantation with a maximum implantation energy of 400 keV and a total dose of 8.1 × 10⁻¹⁶ １４ ( / cm ２ ) Then, after removing the patterned resist film 52, annealing is performed in a nitrogen atmosphere at 800 degrees Celsius for 30 minutes. This forms insulating portions 50A and 50B. Each of insulating portions 50A and 50B penetrates the drift layer 30 and the contact layer 20 and reaches into the SiC substrate 10.

[0120] Next, as shown in Figure 10, insulating films 60 are formed on the drift layer 30, on the insulating portion 50A, and on the insulating portion 50B, for example, by using the CVD method. The insulating film 60 is, for example, a silicon oxide film, and its thickness is, for example, about 300 nm. Then, after forming a laminated film of nickel and silicon on the lower surface of the SiC substrate 10, annealing is performed at 900 degrees Celsius. This causes a silicide reaction between the nickel and silicon films. As a result, a lower electrode 40 of the nickel silicide film is formed on the lower surface of the SiC substrate 10. The lower electrode 40 and the SiC substrate 10 are in ohmic contact.

[0121] Subsequently, as shown in Figure 6, a resist film is coated onto the insulating film 60, and then the resist film is patterned using photolithography. The resist film is patterned in such a way that areas of the insulating film 60 are left open. Next, the insulating film 60 is etched using the patterned resist film as a mask. Hydrofluoric acid, for example, is used for etching. This forms an opening OP in the insulating film 60. The drift layer 30 is exposed at the bottom of the opening OP. Next, a nickel film is provided on the drift layer 30 and the resist film exposed at the bottom of the opening OP, for example, by a vapor deposition method. Then, the resist film is lifted off. This provides the upper electrode 70 on the drift layer 30. The drift layer 30 and the upper electrode 70 are in Schottky contact.

[0122] As described above, a semiconductor device 100 including an SBD can be manufactured.

[0123] <<Evaluation Results of the Electrical Characteristics of the Schottky Diode>> Next, we will explain the evaluation results of the electrical characteristics of the SBD fabricated under the conditions of the manufacturing method described above. The main parameters of the fabricated SBD are as follows: The contact layer has an Al composition of x = 0.3, a film thickness of 15 nm, and an impurity concentration of added Si of 5 × 10⁻⁶. １８ ( / cm ３ The drift layer had an Al composition of y = 0.3, a film thickness of 0.5 μm, and an impurity concentration of added Si of 5 × 10⁻⁶. １７ ( / cm ３ )

[0124] After measuring the C-V characteristics (capacitance-voltage characteristics) of a circular diode with a diameter of 424 μm at 100 kHz, 1 / C ２ - A V-plot was performed, and the linearity of the graph was good. The effective donor concentration, which can be calculated from the slope of the plot and the relative permittivity of AlGaN (εr = 10.2), is ND (donor concentration) - NA (acceptor concentration) = 4 × 10⁻¹⁰ １７ ( / cm ３ This value was determined to be the Si impurity concentration (5 × 10). １７ ( / cm ３ It is close to ))

[0125] 1 / C ２ - The built-in potential obtained by extrapolating the V-plot to the voltage axis is Vbi = 1.8V, and Ni and Al ｙ Ga １－ｙ This value is close to ΦB = 1.6 eV, which is assumed to be the height of the Schottky barrier present at the interface of N (y = 0.3).

[0126] In the J-V characteristics measured for a circular diode with a diameter of 424 μm, clear rectification was confirmed, and the on / off ratio was 10. ９ That concludes the analysis. The differential resistance obtained by differentiating the forward J-V waveform is 1 mΩ·cm for forward voltages of 4V or higher. ２ The following results were obtained, confirming that the parasitic resistance was as low as that of a vertical diode on a GaN substrate.

[0127] <<Modified Version of Embodiment 2>> In the modified version, in addition to impurity doping, polarization doping is also used for the drift layer 30 shown in Figure 6. For example, n-type Al ｙ Ga １－ｙ To increase the conductivity of the N layer, the Al composition y is increased along the +Z direction. In other words, the Al composition in the drift layer 30 is changed so that it increases from the interface between the drift layer 30 and the contact layer 20 toward the upper electrode 70. This makes it possible to increase the conductivity of the drift layer 30.

[0128] The verification results are described below. For this verification, two samples were prepared under the conditions shown in Table 2.

[0129] Sample 4 is an SBD fabricated as a modification of Embodiment 2, in which the Al composition of the drift layer 30 is increased from 0.3 to 0.5 (y = 0.3 ⇒ 0.5) from the interface between the drift layer 30 and the contact layer 20 toward the upper electrode 70. In contrast, the SBD of the reference sample 3 has the Al composition of the drift layer 30 kept constant at the intermediate value y = 0.4. Other specifications include a contact layer thickness of 15 nm and a Si impurity concentration of 5 × 10⁻¹⁶ in the contact layer. １８ ( / cm ３ ), the thickness of the drift layer is 0.5 μm, and the Si impurity concentration in the drift layer is 3 × 10 １７ ( / cm ３ The point that was stated is common to both Sample 3 and Sample 4.

[0130] Figure 11 shows the voltage (V) between the upper electrode 70 and the lower electrode 40 and the current density (A / cm²) flowing through the SBD for sample 3 (S3) and sample 4 (S4). ２ This is a graph showing the relationship between ).

[0131] In Figure 11, the forward current of the SBD (S4) in the modified example using both impurity doping and polarization doping is significantly higher than the forward current of the SBD (S3) using only impurity doping. This confirms that the parasitic resistance of the drift layer 30 can be reduced by using both impurity doping and polarization doping.

[0132] <Embodiment 3> In Embodiment 3, a pn junction diode will be described as a vertical device manufactured using the semiconductor wafer WF described in Embodiment 1.

[0133] <<Configuration of a semiconductor device including a pn junction diode>> Figure 12 is a cross-sectional view showing the configuration of a semiconductor device 200 including a pn junction diode.

[0134] The semiconductor device 200 includes a SiC substrate 10, a contact layer 20, a drift layer 30, a lower electrode 40, an insulating film 60A, an upper electrode 70, a semiconductor layer 80 (third nitride semiconductor layer), and a semiconductor layer 90 (fourth nitride semiconductor layer).

[0135] The SiC substrate 10 has nitrogen, an n-type impurity, introduced into it. Therefore, the SiC substrate 10 is an n-type semiconductor substrate. The SiC substrate 10 has an upper surface and a lower surface. A mesa structure MS is formed on the upper surface of the SiC substrate 10.

[0136] The mesa structure MS is provided with a contact layer 20, a drift layer 30, a semiconductor layer 80, and a semiconductor layer 90. An insulating film 60A is provided so as to cover the mesa structure MS. An opening OP2 is formed in the insulating film 60A. An upper electrode 70 is provided on a part of the insulating film 60A, including the area within the opening OP2.

[0137] The contact layer 20 provided on the SiC substrate 10 is made of Al ｘ Ga １－ｘ The N layer is (0.25 < x ≤ 0.5). The contact layer 20 is an n-type semiconductor layer into which the n-type impurity Si is introduced. In addition, in the contact layer 20, the thickness (cm) and impurity concentration ( / cm) are specified. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ ) The following:

[0138] A lower electrode 40 is provided on the lower surface of the SiC substrate 10. The lower electrode 40 is, for example, a NiSi film. The SiC substrate 10 and the lower electrode 40 are in ohmic contact.

[0139] A drift layer 30 is provided on the contact layer 20. The drift layer 30 is made of Al ｙ Ga １－ｙ It is an N-layer (0 ≤ y ≤ 1). The drift layer 30 is an n-type semiconductor layer into which the n-type impurity Si is introduced. The impurity concentration of the drift layer 30 is lower than that of the contact layer 20. The drift layer 30 may contain carbon and oxygen. The carbon concentration in the drift layer 30 is 10 １６ ( / cm ３ It is below the order of ). The oxygen concentration in the drift layer 30 is 10 １６ ( / cm ３ It is below the order of )

[0140] A semiconductor layer 80 is provided on the drift layer 30. The semiconductor layer 80 is made of Al ｚ Ga １－ｚ It is an N-layer (0 ≤ z ≤ 1). Polarization doping is used for the semiconductor layer 80. For example, the semiconductor layer 80 is p-type Al ｚ Ga １－ｚ To construct an N-layer, the Al composition z is decreased along the +Z direction. In other words, the Al composition within semiconductor layer 80 changes such that it decreases as it approaches the interface between semiconductor layer 80 and semiconductor layer 90 from the bottom surface of semiconductor layer 80. For example, the Al composition z within semiconductor layer 80 is changed from z = 0.5 to z = 0. As a result, semiconductor layer 80 becomes essentially a p-type semiconductor layer.

[0141] The drift layer 30 is an n-type semiconductor layer, and the semiconductor layer 80 is a p-type semiconductor layer. Therefore, a pn junction is formed at the interface between the drift layer 30 and the semiconductor layer 80.

[0142] A semiconductor layer 90 is provided on the semiconductor layer 80. The semiconductor layer 90 is a GaN layer. The semiconductor layer 90 has a high concentration (1 × 10⁻¹⁶) of Mg, which is a p-type impurity. ２０ ( / cm ３ This is a p-type semiconductor layer introduced into the )).

[0143] An insulating film 60A is provided so as to cover the mesa structure MS. The insulating film 60A is, for example, a silicon nitride film. An opening OP2 is formed in the insulating film 60A. A part of the upper surface of the semiconductor layer 90 is exposed through the opening OP2.

[0144] An upper electrode 70 is provided on the upper surface of the semiconductor layer 90 exposed through the opening OP2. The upper electrode 70 is also provided so as to overlap a portion of the insulating film 60A. The upper electrode 70 is, for example, a laminated film formed by stacking a Ni film and an Au film. The semiconductor layer 90 and the upper electrode 70 are in ohmic contact.

[0145] In this way, a semiconductor device 200 including a pn junction diode is constructed.

[0146] A pn junction diode consists of a SiC substrate 10, a contact layer 20, a drift layer 30, a lower electrode 40, an upper electrode 70, a semiconductor layer 80, and a semiconductor layer 90. The lower electrode 40 is the cathode electrode, while the upper electrode 70 is the anode electrode. The region comprising the SiC substrate 10, the contact layer 20, and the drift layer 30 constitutes the cathode region. The cathode region is electrically connected to the lower electrode 40, which is the cathode electrode. The region comprising the semiconductor layer 80 and the semiconductor layer 90 constitutes the anode region. The anode region is electrically connected to the upper electrode 70, which is the anode electrode. A pn ​​junction is formed at the interface between the anode region and the cathode region.

[0147] In a pn junction diode, when a positive voltage is applied to the upper electrode 70 and a negative voltage is applied to the lower electrode 40, the pn junction formed at the interface between the drift layer 30 and the semiconductor layer 80 is forward-biased, and a forward current flows. The forward current flows through the path upper electrode 70 → semiconductor layer 90 → semiconductor layer 80 → drift layer 30 → contact layer 20 → SiC substrate 10 → lower electrode 40. On the other hand, in a pn junction diode, when a negative voltage is applied to the upper electrode 70 and a positive voltage is applied to the lower electrode 40, the pn junction is reverse-biased, and almost no current flows. The pn junction diode in Embodiment 3 is a vertical device in which current flows in the thickness direction (-Z direction).

[0148] The pn junction diode in Embodiment 3 has the characteristics of Embodiment 1, and the potential barrier at the interface between the SiC substrate 10 and the contact layer 20 can be reduced. As a result, the on-resistance when forward current flows can be reduced with the pn junction diode in Embodiment 3. Thickness (cm) of the contact layer 20 and impurity concentration ( / cm) of the pn junction diode in Embodiment 3 ３ The product of ) is 4.5 × 10 １４ ( / cm ２ ) The following applies. Therefore, the occurrence of cracks and surface roughness in the contact layer 20 can be suppressed. Accordingly, the pn junction diode in Embodiment 3 can suppress the increase in leakage current when off, and suppress the decrease in manufacturing yield.

[0149] Furthermore, similar to Embodiment 1, the activation rate of Si in the drift layer 30 can be improved by reducing the concentrations of carbon and oxygen. That is, Al ｙ Ga １－ｙ The activation rate of Si in the N layer (0 ≤ y ≤ 1) can be improved.

[0150] In Embodiment 3, polarization doping is used to realize a p-type semiconductor layer 80. Specifically, p-type Al z Ga １－ｚ To realize an N-layer, the Al composition z is decreased along the +Z direction. In other words, the Al composition within semiconductor layer 80 is changed so that it decreases as it approaches the interface between semiconductor layer 80 and semiconductor layer 90 from the bottom surface of semiconductor layer 80. This makes semiconductor layer 80 substantially a p-type semiconductor.

[0151] <<Manufacturing Method for Semiconductor Device Including a pn Junction Diode>> Next, an example of a manufacturing method for the semiconductor device 200 will be described.

[0152] First, as shown in Figure 13, a semiconductor wafer is prepared by sequentially providing a contact layer 20, a drift layer 30, a semiconductor layer 80, and a semiconductor layer 90 on a SiC substrate 10. In the manufacturing process of this semiconductor wafer, in addition to the raw materials Al, Ga, N, and Si, Mg, which is a p-type impurity that acts as an acceptor, is introduced, hence the term "Cp ２Use Mg (biscyclopentadienylmagnesium).

[0153] First, in the epitaxial growth method, under conditions where the Al composition x is 0.5, the Si impurity concentration (donor concentration) is 5 × 10⁻⁶. １８ ( / cm ３ By setting the gas flow rate ratio to such a state, an Al layer with a thickness of approximately 15 nm is formed on the SiC substrate 10. ｘ Ga １－ｘ A contact layer 20, which is an N-layer (x = 0.5), is provided.

[0154] Next, the Si impurity concentration (donor concentration) is 1 × 10⁻⁶ １７ ( / cm ３ By changing the gas flow rate ratio to such a state, the Al composition x is maintained at 0.5, and an Al thickness of approximately 2 μm corresponding to a withstand voltage of 1 kV is obtained. ｙ Ga １－ｙ A drift layer 30, which is an N-layer (y = 0.5), is provided.

[0155] Next, by reducing the gas flow rate ratio of the Al raw material while supplying only Al, Ga, and N raw materials so that the Al composition decreases at a constant rate along the growth direction (z = 0.5 → z = 0), epitaxial growth is continued, resulting in an Al material with a thickness of approximately 0.5 μm. ｚ Ga １－ｚ A semiconductor layer 80, which is an N-layer, is provided. This semiconductor layer 80 can be considered a p-type semiconductor layer by the principle of polarization doping. The equivalent acceptor concentration of the semiconductor layer 80 is 7 × 10⁻¹⁶. １７ ( / cm ３ ) Subsequently, Mg is added to the semiconductor layer 80 in a high concentration (1 × 10⁻¹⁶). ２０ ( / cm ３ A semiconductor layer 90, which is a GaN layer, is provided in the )). The semiconductor wafer shown in Figure 13, manufactured in this manner, contains a pn junction. The following describes the process for manufacturing a semiconductor device 200 containing a pn junction diode using a semiconductor wafer containing a pn junction.

[0156] As shown in Figure 14, a mesa structure MS is formed on a semiconductor wafer using photolithography and etching techniques.

[0157] The drift layer 30 is electrically isolated by forming a mesa structure MS. The mesa structure is formed to alleviate electric field concentration at the termination of the pn junction diode (both ends of the mesa structure MS in the X direction) and to bring the breakdown voltage of the pn junction diode closer to the theoretical value.

[0158] Next, as shown in Figure 15, an insulating film 60A is provided to cover the mesa structure MS and the upper surface of the exposed SiC substrate 10, for example, by using a plasma CVD method. The insulating film 60A is, for example, a silicon nitride film, and its thickness is about 100 nm.

[0159] Next, a laminated film consisting of a nickel film and a silicon film is formed on the lower surface of the SiC substrate 10, and then annealing is performed at 900 degrees Celsius. As a result, the nickel film and silicon film undergo a silicide reaction, and a nickel silicide film is formed on the lower surface of the SiC substrate 10. This forms a lower electrode 40 composed of the nickel silicide film.

[0160] Next, as shown in Figure 12, an opening OP2 is formed in the insulating film 60A using photolithography and etching techniques. A portion of the upper surface of the semiconductor layer 90 is exposed from the bottom of the opening OP2.

[0161] Then, with the resist film used to form the opening OP2 remaining, a laminated film is formed by laminating a nickel film and a gold film on the resist film, including the area within the opening OP2. The nickel film is formed, for example, by vapor deposition, and has a thickness of about 20 nm. The gold film is formed, for example, by vapor deposition, and has a thickness of about 200 nm.

[0162] Next, after lifting off the resist film, annealing is performed, for example, at 550 degrees Celsius for 10 minutes. This provides the upper electrode 70 on the semiconductor layer 90 exposed through the opening OP2. The upper electrode 70 is composed of a laminated film of nickel and gold. The semiconductor layer 90 and the upper electrode 70 are in ohmic contact.

[0163] As described above, a semiconductor device 200 including a pn junction diode can be manufactured.

[0164] <<Features of the manufacturing process>> The key feature of the manufacturing process is that the insulating film 60A is made from a silicon nitride film.

[0165] The semiconductor layer 90 is a p-type GaN layer. When annealing is performed at temperatures exceeding 800 degrees Celsius, high-density defects tend to form near the surface of the GaN layer. When high-density defects form near the surface of the GaN layer, the p-type conductivity decreases.

[0166] Therefore, for example, as shown in Figure 15, in order to protect the semiconductor layer 90 from annealing at temperatures exceeding 800 degrees Celsius, the semiconductor layer 90 is covered with an insulating film 60A while annealing at temperatures exceeding 800 degrees Celsius is performed. In other words, the insulating film 60A has the function of protecting the semiconductor layer 90 when annealing at temperatures exceeding 800 degrees Celsius is performed in order to provide the lower electrode 40, which is made of a nickel silicide film, on the lower surface of the SiC substrate 10.

[0167] In this regard, in Embodiment 3, the insulating film 60A is made of a silicon nitride film. The silicon nitride film is a film with high heat resistance. The silicon nitride film has the effect of suppressing the generation of high-density defects near the surface of the GaN layer and the resulting decrease in p-type conductivity due to annealing at temperatures exceeding 800 degrees Celsius. As a result, according to Embodiment 3, the decrease in conductivity of the semiconductor layer 90, which is a p-type GaN layer, can be suppressed.

[0168] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0169] The above embodiment includes the following form: (Note 1) A silicon carbide substrate of the first conductivity type, and provided on the silicon carbide substrate, which is of the first conductivity type, Al ｘ Ga １－ｘ A first nitride semiconductor layer of N (0.25 < x ≤ 0.5), and a first conductivity type Al, provided on the first nitride semiconductor layer. ｙ Ga １－ｙA semiconductor wafer comprising a second nitride semiconductor layer of N (0 ≤ y ≤ 1), and (Note 2) In the semiconductor wafer described in Note 1, the thickness (cm) of the first nitride semiconductor layer and the impurity concentration ( / cm) of the first nitride semiconductor layer. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ ) is less than or equal to: (Note 3) In the semiconductor wafer described in Note 1 or 2, the carbon concentration in the second nitride semiconductor layer is 10 １６ ( / cm ３ ) is on the order of less than or equal to 10, and the oxygen concentration in the second nitride semiconductor layer is 10 １６ ( / cm ３ ) is of an order of less than or equal to. (Note 4) In the semiconductor wafer described in any one of Notes 1 to 3, the Al composition in the second nitride semiconductor layer increases from the interface between the second nitride semiconductor layer and the first nitride semiconductor layer toward the upper surface of the second nitride semiconductor layer. (Note 5) In the semiconductor wafer described in any one of Notes 1 to 4, the semiconductor wafer is a wafer for forming a device that conducts current in the thickness direction. (Note 6) In the semiconductor wafer described in any one of Notes 1 to 5, the silicon carbide substrate and the first nitride semiconductor layer are composed of silicon carbide and Al ｘ Ga １－ｘForms an N heterointerface. (Note 7) In the semiconductor wafer described in any one of Notes 1 to 6, the impurity concentration of the first nitride semiconductor layer is greater than the impurity concentration of the second nitride semiconductor layer. (Note 8) A semiconductor device using the semiconductor wafer described in any one of Notes 1 to 7, comprising: a first electrode provided on the second nitride semiconductor layer; and a second electrode provided on the lower surface of the silicon carbide substrate. (Note 9) In the semiconductor device described in Note 8, the second nitride semiconductor layer and the first electrode are in Schottky contact to form a Schottky barrier diode. (Note 10) In the semiconductor device described in Note 8, the semiconductor device further comprises: a third nitride semiconductor layer and a fourth nitride semiconductor layer inserted between the second nitride semiconductor layer and the first electrode, wherein the third nitride semiconductor layer is provided on the second nitride semiconductor layer and comprises Al of the second conductivity type which is the opposite conductivity type to the first conductivity type. ｚ Ga １－ｚ N is (0 ≤ z ≤ 1), the fourth nitride semiconductor layer is provided on the third nitride semiconductor layer and is GaN of the second conductivity type, and the semiconductor device is a pn junction diode. (Note 11) In the semiconductor device described in Note 10, the Al composition in the third nitride semiconductor layer decreases as it approaches the interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer from the lower surface of the third nitride semiconductor layer.

[0170] 10 SiC substrate 20 Contact layer (first nitride semiconductor layer) 30 Drift layer (second nitride semiconductor layer) 40 Lower electrode 50A Insulating part 50B Insulating part 51 Insulating film 52 Resist film 60 Insulating film 60A Insulating film 70 Upper electrode 80 Semiconductor layer (third nitride semiconductor layer) 90 Semiconductor layer (fourth nitride semiconductor layer) 100 Semiconductor device 200 Semiconductor device MS Mesa structure OP Aperture OP2 Aperture WF Semiconductor wafer

Claims

1. A silicon carbide substrate of the first conductivity type, and a material provided on the silicon carbide substrate, which is of the first conductivity type, Al ｘ Ga １－ｘ A first nitride semiconductor layer of N (0.25 < x ≤ 0.5), and a first conductivity type Al, provided on the first nitride semiconductor layer. ｙ Ga １－ｙ A semiconductor wafer comprising a second nitride semiconductor layer of type N (0 ≤ y ≤ 1).

2. In the semiconductor wafer according to claim 1, the thickness (cm) of the first nitride semiconductor layer and the impurity concentration ( / cm) of the first nitride semiconductor layer. ３ The product of ) is 4.5 × 10 １４ ( / cm ２ ) The following:

3. In the semiconductor wafer according to claim 1, the carbon concentration in the second nitride semiconductor layer is 10 １６ ( / cm ３ ), and the oxygen concentration in the second nitride semiconductor layer is 10 １６ ( / cm ３ ).

4. In the semiconductor wafer according to claim 1, the Al composition in the second nitride semiconductor layer increases from the interface between the second nitride semiconductor layer and the first nitride semiconductor layer toward the upper surface of the second nitride semiconductor layer.

5. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is a wafer for forming a device that conducts electric current in the thickness direction.

6. In the semiconductor wafer according to claim 1, the silicon carbide substrate and the first nitride semiconductor layer are composed of silicon carbide and Al ｘ Ga １－ｘ It forms a heterointerface of N.

7. In the semiconductor wafer according to claim 1, the impurity concentration of the first nitride semiconductor layer is greater than the impurity concentration of the second nitride semiconductor layer.

8. A semiconductor device using a semiconductor wafer according to any one of claims 1 to 7, comprising: a first electrode provided on the second nitride semiconductor layer; and a second electrode provided on the lower surface of the silicon carbide substrate.

9. In the semiconductor device according to claim 8, the second nitride semiconductor layer and the first electrode are in Schottky contact to form a Schottky barrier diode.

10. The semiconductor device according to claim 8, wherein the semiconductor device further comprises a third nitride semiconductor layer and a fourth nitride semiconductor layer inserted between the second nitride semiconductor layer and the first electrode, the third nitride semiconductor layer being provided on the second nitride semiconductor layer and comprising Al of the second conductivity type which is the opposite conductivity type to the first conductivity type. ｚ Ga １－ｚ N is (0 ≤ z ≤ 1), the fourth nitride semiconductor layer is provided on the third nitride semiconductor layer and is GaN of the second conductivity type, and the semiconductor device is a pn junction diode.

11. In the semiconductor device according to claim 10, the Al composition in the third nitride semiconductor layer decreases as it approaches the interface between the third nitride semiconductor layer and the fourth nitride semiconductor layer from the lower surface of the third nitride semiconductor layer.

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