Interposer and electronic component module

Abstract

The present disclosure addresses the problem of maintaining the insulation reliability of an insulation layer while maintaining the conduction reliability between an electrode and a via conductor part, when providing an electrode and a via conductor part to an insulation layer of an interposer. An interposer (1) comprises: an insulation layer (202) that has a first main surface (221) and a second main surface (222) on the reverse side from the first main surface (221); an electrode (32) that is embedded in the insulation layer (202) and that is exposed to the outside of the insulation layer (202) at the first main surface (221); a via conductor part (33) that passes through the insulation layer (202) from the second main surface (222) to the electrode (32); and a barrier layer (81) that covers the electrode (32). The barrier layer (81) is interposed between the electrode (32) and the insulation layer (202) but is not interposed between the electrode (32) and the via conductor part (33).

Description

Interposer and Electronic Component Module

[0001] The present disclosure relates to an interposer and an electronic component module, and more particularly to an interposer including electrodes and via conductor portions connected to the electrodes, and an electronic component module including the interposer.

[0002] As an interposer, a wiring board on which electronic components such as semiconductor chips are mounted is known (Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2012-94734

[0004] Due to the miniaturization of conductors in the interposer, the insulation reliability of the insulating layer becomes a problem. In order to improve the insulation reliability, when a barrier layer is interposed between the insulating layer and a conductor such as an electrode, the conduction reliability between the electrode and the via conductor portion may decrease when connecting the via conductor portion to the electrode in the interposer.

[0005] An object of the present disclosure is to provide an interposer capable of maintaining the conduction reliability between an electrode and a via conductor portion while maintaining the insulation reliability of an insulating layer when the electrode and the via conductor portion are provided in the insulating layer of the interposer, and an electronic component module including this interposer.

[0006] An interposer according to one aspect of the present disclosure includes an insulating layer having a first main surface and a second main surface opposite to the first main surface, an electrode embedded in the insulating layer and exposed outside the insulating layer at the first main surface, a via conductor portion penetrating the insulating layer from the second main surface to the electrode, and a barrier layer covering the electrode. The barrier layer is interposed between the electrode and the insulating layer and is not interposed between the electrode and the via conductor portion.

[0007] An electronic component module according to one aspect of the present disclosure includes the interposer and an electronic component connected to the electrode of the interposer.

[0008] Figure 1 is a cross-sectional view of an interposer and an electronic component module according to an embodiment. Figure 2 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 3 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 4 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 5 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 6 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 7 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 8 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 9 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 10 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 11 is a cross-sectional view of the process for explaining the manufacturing method of the interposer, structure and electronic component module according to the same embodiment. Figure 12 is a cross-sectional view illustrating the manufacturing method of the interposer, structure, and electronic component module according to the above embodiment. Figure 13 is a cross-sectional view illustrating the manufacturing method of the interposer, structure, and electronic component module according to the above embodiment. Figure 14 is a cross-sectional view illustrating the manufacturing method of the interposer, structure, and electronic component module according to the above embodiment. Figure 15 is an enlarged view of the main part of Figure 14. Figure 16 is a cross-sectional view illustrating the manufacturing method of the interposer, structure, and electronic component module according to the above embodiment. Figure 17 is a cross-sectional view of the interposer and electronic component module according to the first modified example. Figure 18 is a cross-sectional view of the interposer and structure according to the second modified example. Figure 19 is a cross-sectional view of the interposer according to the third modified example.

[0009] Embodiments of this disclosure will be described below with reference to the drawings. The drawings referenced in the following embodiments are schematic diagrams, and the size and thickness of the components shown in the drawings do not necessarily reflect the actual dimensions, nor do the size ratios and thickness ratios between components necessarily reflect the actual dimensional ratios.

[0010] 1. Outline Figure 1 shows an interposer 1 and an electronic component module 100 equipped with the interposer 1, and Figure 14 shows a structure 110 equipped with the interposer 1.

[0011] The interposer 1 comprises an insulating layer (first insulating layer 202), an electrode (first electrode 32), a via conductor portion (first via conductor portion 33), and a barrier layer (first barrier layer 81). The first insulating layer 202 has a first main surface 221 and a second main surface 222 opposite to the first main surface 221. The first electrode 32 is embedded in the first insulating layer 202 and is exposed to the outside of the first insulating layer 202 at the first main surface 221. The first via conductor portion 33 penetrates the first insulating layer 202 from the second main surface 222 to the first electrode 32. The first barrier layer 81 is interposed between the first electrode 32 and the first insulating layer 202, but not between the first electrode 32 and the first via conductor portion 33.

[0012] The electronic component module 100 comprises an interposer 1 and an electronic component 19 connected to the first electrode 32 of the interposer 1.

[0013] According to the embodiment, the first barrier layer 81 suppresses insulation defects in the first insulating layer 202, and the first barrier layer 81 is not interposed between the first electrode 32 and the first via conductor portion 33, thereby continuously maintaining conductivity reliability between the first electrode 32 and the first via conductor portion 33.

[0014] 2. Details (1) Interposer and Structure Equipped Therewith The interposer 1 according to the embodiment comprises a first insulating layer 202 and a plurality of first via conductor portions 33, as shown in Figures 1 and 14. The interposer 1 according to the embodiment further comprises a plurality of wiring portions 6, a second insulating layer 201, a plurality of second via conductor portions 31, a plurality of second electrodes 4, a plurality of first electrodes 32, a plurality of third electrodes 7, and a plurality of solder bumps 18. The interposer 1 shown in Figure 14, together with the temporary adhesive layer 15 and the carrier substrate 16, constitutes a structure 110. That is, the structure 110 comprises the interposer 1, the temporary adhesive layer 15, and the carrier substrate 16.

[0015] The first insulating layer 202 has a first main surface 221 and a second main surface 222 opposite to the first main surface 221.

[0016] Multiple first electrodes 32 are embedded in the first insulating layer 202. The first electrodes 32 are exposed to the outside of the first insulating layer 202 on the first main surface 221.

[0017] Multiple wiring sections 6 are embedded in the first insulating layer 202. The first electrode 32 is exposed to the outside of the first insulating layer 202 on the first main surface 221.

[0018] In this embodiment, a plurality of first via conductor portions 33 correspond one-to-one with a plurality of first electrodes 32. The first via conductor portions 33 penetrate from the second main surface 222 to the corresponding first electrode 32. The first via conductor portions 33 and the first electrodes 32 are electrically connected. The first insulating layer 202 has through holes (first through holes 223) that penetrate from the second main surface 222 to the first electrode 32, and the first via conductor portions 33 are filled into the first through holes 223.

[0019] Multiple third electrodes 7 correspond one-to-one with multiple first via conductor portions 33. The third electrodes 7 are arranged on the second main surface 222 of the first insulating layer 202. The third electrodes 7 are positioned to block the first via conductor portions 33 and are electrically connected to the first via conductor portions 33.

[0020] Multiple solder bumps 18 correspond one-to-one with multiple third electrodes 7. The solder bumps 18 and their corresponding third electrodes 7 are arranged on the main surface 701 opposite to the first insulating layer 202 side.

[0021] The second insulating layer 201 has a third main surface 211 and a fourth main surface 212 opposite to the third main surface 211. The first insulating layer 202 and the second insulating layer 201 are laminated such that the first main surface 221 of the first insulating layer 202 and the fourth main surface 212 of the second insulating layer 201 are in contact. The first insulating layer 202 and the second insulating layer 201 constitute the insulating substrate 2 in the interposer 1. That is, the interposer 1 includes an insulating substrate 2, and the insulating substrate 2 includes the first insulating layer 202 and the second insulating layer 201.

[0022] Each of the first electrode 32 and the wiring portion 6 is in contact with the fourth main surface 212 of the second insulating layer 201. It can also be said that each of the first electrode 32 and the wiring portion 6 is arranged on the fourth main surface 212 of the second insulating layer 201.

[0023] In this embodiment, there is a one-to-one correspondence between the multiple second via conductor portions 31 and the multiple first electrodes 32. The second via conductor portions 31 penetrate the second insulating layer 201 from the third main surface 211 to the fourth main surface 212. Through holes (second through holes 213) are formed in the second insulating layer 201, penetrating from the third main surface 211 to the fourth main surface 212, and the second via conductor portions 31 are filled into these second through holes 213. The first electrodes 32 are positioned to block the corresponding second via conductor portions 31. Therefore, the second via conductor portions 31 are electrically connected to the first electrodes 32 by directly contacting the corresponding first electrodes 32.

[0024] In this embodiment, there is a one-to-one correspondence between the multiple second electrodes 4 and the multiple second via conductor portions 31. The second electrodes 4 are arranged on the third main surface 211 of the second insulating layer 201. The second electrodes 4 are positioned to block the corresponding second via conductor portion 31. Therefore, the second via conductor portion 31 is electrically connected to the second electrode 4 by contacting the corresponding second electrode 4.

[0025] Therefore, the second via conductor portion 31 penetrates the second insulating layer 201 from the third main surface 211 to the fourth main surface 212, and electrically connects the corresponding first electrode 32 to the corresponding second electrode 4.

[0026] In this embodiment, the first barrier layer 81 covers the first electrode 32. The first barrier layer 81 is interposed between the first electrode 32 and the first insulating layer 202, but not between the first electrode 32 and the first via conductor portion 33. That is, the first electrode 32 and the first via conductor portion 33 are in direct contact without the first barrier layer 81 in between.

[0027] In this embodiment, the second barrier layer 82 covers the wiring portion 6. The second barrier layer 82 is interposed between the wiring portion 6 and the first insulating layer 202.

[0028] In this embodiment, the second via conductor portion 31, the first electrode 32, and the first via conductor portion 33, which overlap in the thickness direction D1 of the second insulating layer 201, constitute a through-wiring portion 3 that penetrates the insulating substrate 2. Therefore, the interposer 1 according to this embodiment comprises a plurality of through-wiring portions 3. The plurality of third electrodes 7 correspond one-to-one with the plurality of through-wiring portions 3 and one-to-one with the plurality of second electrodes 4. The plurality of third electrodes 7 are connected to the corresponding through-wiring portions 3 among the plurality of through-wiring portions 3. In addition, each of the plurality of third electrodes 7 is connected to the corresponding second electrode 4 among the plurality of second electrodes 4 via the through-wiring portion 3.

[0029] In the interposer 1 according to this embodiment, a plurality of second electrodes 4 constitute a plurality of first pad electrodes for BGA (Ball Grid Array) connection, and a plurality of third electrodes 7 constitute a plurality of second pad electrodes for connecting electronic components 19.

[0030] As shown in Figure 15, the structure 110 comprising the interposer 1 according to the embodiment includes the interposer 1, a temporary adhesive layer 15, and a carrier substrate 16. To make the interposer 1 capable of performing its function, the carrier substrate 16 is peeled off from the temporary adhesive layer 15, and the temporary adhesive layer 15 is peeled off from the interposer 1.

[0031] The interposer 1 according to Embodiment 1 is, for example, placed between an electronic component 19 and a SiP (System in Package) package substrate. The electronic component 19 includes, for example, a processor, a logic IC (Integrated Circuit), or memory (e.g., HBM: High Bandwidth Memory).

[0032] (2) Interposer The components of the interposer 1 according to this embodiment will be described in more detail below.

[0033] The insulating substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21.

[0034] The insulating substrate 2 includes a first insulating layer 202 and a second insulating layer 201. The first insulating layer 202 and the second insulating layer 201 are laminated together. The thickness direction of the insulating substrate 2 is the same as the thickness direction D1 of the first insulating layer 202.

[0035] The second insulating layer 201 has a third main surface 211 and a fourth main surface 212 opposite to the third main surface 211.

[0036] The first insulating layer 202 has a first main surface 221 that is in contact with the fourth main surface 212 of the second insulating layer 201, and a second main surface 222 that is on the opposite side of the first main surface 221.

[0037] The material of the first insulating layer 202 includes an organic material. More specifically, the material of the first insulating layer 202 includes, as a main component, an imide-based resin (e.g., polyimide, bismaleimide, etc.), a fluororesin (e.g., polytetrafluoroethylene, etc.), or an epoxy-based resin.

[0038] The material of the second insulating layer 201 includes an organic material. More specifically, the material of the second insulating layer 201 includes, as a main component, an imide-based resin (e.g., polyimide, bismaleimide, etc.), a fluororesin (e.g., polytetrafluoroethylene, etc.), or an epoxy-based resin.

[0039] The material of the first insulating layer 202 and the material of the second insulating layer 201 may be the same or they may be different.

[0040] The first electrode 32 is smaller than the corresponding second electrode 4 in a plan view from the thickness direction D1, and is located inside the outer edge 402 of the corresponding second electrode 4.

[0041] As shown in FIG. 15, the first electrode 32 has a first surface 321 and a second surface 322 opposite to the first surface 321. The first surface 321 of the first electrode 32 is exposed on the first main surface 221 of the first insulating layer 202 and contacts the corresponding second via conductor portion 31. In a plan view from the thickness direction D1, the outer edge shape of the first electrode 32 is, for example, circular or rectangular, but is not limited thereto. The shape of the first electrode 32 is frustum-shaped. In the first electrode 32, the first outer diameter R1 of the first surface 321 is larger than the second outer diameter R2 of the second surface 322. The outer diameter of the first electrode 32 gradually decreases as it moves away from the second via conductor portion 31 in the thickness direction D1 of the second insulating layer 201. The side peripheral surface 324 connecting the first surface 321 and the second surface 322 of the first electrode 32 is inclined according to the difference between the first outer diameter R1 of the first surface 321 and the second outer diameter R2 of the second surface 322 (see FIG. 15).

[0042] In the present disclosure, the outer diameter refers to the minimum distance among the distances between two points where an arbitrary straight line passing through the centroid of a figure showing the planar shape of an object intersects the outer periphery of the figure. For example, if the figure is a perfect circle, the outer diameter coincides with the diameter of the perfect circle; if the figure is an ellipse, the outer diameter coincides with the minor axis of the ellipse; if the figure is a rectangle, the outer diameter coincides with the length of the shorter side of the rectangle.

[0043] In the first electrode 32 of the embodiment, for example, the first outer diameter R1 is 25 μm and the second outer diameter R2 is 20 μm, but the dimensions of the first electrode 32 are not limited thereto.

[0044] The first barrier layer 81 covers the entire side peripheral surface 324 of the first electrode 32 and the entire portion of the second surface 322 that does not contact the first via conductor portion 33 (see FIG. 15). Therefore, the first barrier layer 81 is interposed between the first electrode 32 and the first insulating layer 202, and the first electrode 32 does not directly contact the first insulating layer 202.

[0045] The thickness of the first barrier layer 81 is, for example, 10 nm or more and 50 nm or less, but is not limited thereto.

[0046] The material of the first electrode 32 is, for example, copper or a copper alloy. The material of the first barrier layer 81 is preferably a material with lower diffusibility into the first insulating layer 202 than the material of the first electrode 32. The material of the first barrier layer 81 is, for example, at least one selected from the group consisting of tantalum, titanium, tantalum nitride, and titanium nitride.

[0047] The wiring portion 6 is embedded in the first insulating layer 202 and exposed from the first main surface 221 of the first insulating layer 202. The wiring portion 6 is connected to at least one of the plurality of first electrodes 32.

[0048] As shown in FIG. 15, in the embodiment, the wiring portion 6 has a strip-shaped surface (third surface 61) that is exposed on the first main surface 221 of the first insulating layer 202 and contacts the third main surface 211 of the second insulating layer 201, a strip-shaped surface (fourth surface 62) on the opposite side of the third surface 61, and a surface (side surface 63) connecting the third surface 61 and the fourth surface 62. The width (second width H2) of the fourth surface 62 is smaller than the width (first width H1) of the third surface 61. The first width H1 of the wiring portion 6 is smaller than the first outer diameter R1 of the first electrode 32. The second width H2 of the wiring portion 6 is smaller than the second outer diameter R2 of the first electrode 32. The side surface 63 is inclined according to the difference between the first width H1 of the third surface 61 and the second width H2 of the fourth surface 62. The thickness of the wiring portion 6 is the same as the thickness of the first electrode 32.

[0049] The second barrier layer 82 covers the entire side surface 63 and the entire fourth surface 62 of the wiring portion 6. Therefore, the second barrier layer 82 is interposed between the wiring portion 6 and the first insulating layer 202, and the wiring portion 6 does not directly contact the first insulating layer 202.

[0050] The thickness of the second barrier layer 82 is, for example, 10 nm or more and 50 nm or less, but is not limited thereto.

[0051] The material of the wiring portion 6 is, for example, copper or a copper alloy. The material of the second barrier layer 82 is preferably a material with lower diffusibility into the first insulating layer 202 than the material of the wiring portion 6. The material of the second barrier layer 82 is, for example, at least one selected from the group consisting of tantalum, titanium, tantalum nitride, and titanium nitride. The material of the wiring portion 6 is, for example, the same as the material of the first electrode 32. The material of the second barrier layer 82 is, for example, the same as the material of the first barrier layer 81.

[0052] The outer edge shape of the first via conductor portion 33 is circular in plan view from the thickness direction D1, but is not limited to this. The first via conductor portion 33 is frustoconical. The fifth outer diameter R5 (see Figure 15) of the first via conductor portion 33 at the second surface 322 of the first electrode 32 is smaller than the sixth outer diameter R6 (see Figure 15) at the second main surface 222 of the first insulating layer 202. The outer diameter of each of the multiple first via conductor portions 33 gradually decreases in the thickness direction D1 of the second insulating layer 201 as it moves away from the third electrode 7 and approaches the first electrode 32. The fifth outer diameter R5 of the first via conductor portion 33 is smaller than the second outer diameter R2 of the first electrode 32.

[0053] The material of the first via conductor portion 33 is, for example, copper or a copper alloy.

[0054] The second electrode 4 is circular or rectangular in shape when viewed from the thickness direction D1, but is not limited to these shapes. When viewed from the thickness direction D1, the second electrode 4 is larger than both the through-wiring portion 3 and the third electrode 7. When viewed from the thickness direction D1, the outer edge 402 of the second electrode 4 encloses the outer edge of the second via conductor portion 31 connected to the second electrode 4. Also, when viewed from the thickness direction D1, the outer edge 402 of the second electrode 4 encloses the outer edge 323 of the first electrode 32 which overlaps the second electrode 4. Also, when viewed from the thickness direction D1, the outer edge 402 of the second electrode 4 encloses the outer edge 702 of the third electrode 7 which overlaps the second electrode 4. The second electrode 4 protrudes from the third main surface 211 of the second insulating layer 201. The second electrode 4 has a main surface 401 on the opposite side from the second insulating layer 201.

[0055] The material of the second electrode 4 is, for example, copper or a copper alloy.

[0056] The thickness of the second electrode 4 is, for example, 10 μm, but is not limited to this.

[0057] The second electrode 4 is circular or rectangular in shape when viewed from the thickness direction D1, but is not limited to these. The second electrode 4 is, for example, a pad electrode for a BGA. The outer diameter R0 (see Figure 15) of the main surface 401 of the second electrode 4 is, for example, 200 μm, but is not limited to this. The distance between the centers of two adjacent second electrodes 4 is, for example, 400 μm, but is not limited to this.

[0058] The outer edge shape of the second via conductor portion 31 in a plan view from the thickness direction D1 is circular, but is not limited to this. The shape of the second via conductor portion 31 is frustum-shaped. In the second via conductor portion 31, the fourth outer diameter R4 (see Figure 15) at the fourth main surface 212 of the second insulating layer 201 is smaller than the third outer diameter R3 (see Figure 15) at the third main surface 211 of the second insulating layer 201. The outer diameter of the second via conductor portion 31 gradually decreases in the thickness direction D1 as it moves away from the second electrode 4 and approaches the first electrode 32.

[0059] In the second via conductor portion 31, for example, the third outer diameter R3 is 15 μm and the fourth outer diameter R4 is 10 μm, but it is not limited to this.

[0060] The material of the second via conductor portion 31 is, for example, copper or a copper alloy.

[0061] The through-wiring section 3 includes a second via conductor section 31, a first electrode 32, and a first via conductor section 33. In the through-wiring section 3, the second via conductor section 31, the first electrode 32, and the first via conductor section 33 are arranged in this order from the first main surface 21 side of the insulating substrate 2. In the through-wiring section 3, the second via conductor section 31 and the first electrode 32 are directly connected, and the first electrode 32 and the first via conductor section 33 are directly connected, so the second via conductor section 31, the first electrode 32, and the first via conductor section 33 are electrically connected. In the through-wiring section 3, the second via conductor section 31 penetrates the second insulating layer 201. Also, in the through-wiring section 3, the first electrode 32 and the first via conductor section 33 are embedded in the first insulating layer 202.

[0062] In a plan view from the thickness direction D1, the third electrode 7 is smaller than the corresponding second electrode 4 and is located inside the outer edge 402 of the corresponding second electrode 4.

[0063] In a plan view from the thickness direction D1, the third electrode 7 is circular or rectangular, but is not limited to these shapes. In a plan view from the thickness direction D1, the third electrode 7 is smaller than the second electrode 4. In a plan view from the thickness direction D1, the outer edge 702 of the third electrode 7 encloses the outer edge 323 of the first via conductor portion 33 connected to the third electrode 7. In a plan view from the thickness direction D1, the outer edge 702 of the third electrode 7 is enclosed by the outer edge 323 of the corresponding first electrode 32. In a plan view from the thickness direction D1, the outer edge 702 of the third electrode 7 is enclosed by the outer edge 402 of the second electrode 4 connected to the third electrode 7. The third electrode 7 protrudes from the second main surface 222 of the first insulating layer 202. The third electrode 7 has a main surface 701 opposite to the first insulating layer 202.

[0064] The material of the third electrode 7 includes, for example, copper or a copper alloy.

[0065] The thickness of the third electrode 7 is, for example, 5 μm, but is not limited to this.

[0066] The solder bumps 18 are positioned on the main surface 701 of the corresponding third electrode 7. The material of the solder bumps 18 is a suitable solder alloy.

[0067] (3) As shown in the structural diagram 14, the structure 110 comprises an interposer 1, a temporary adhesive layer 15, and a carrier substrate 16.

[0068] The temporary adhesive layer 15 is directly laminated onto the third main surface 211 of the second insulating layer 201. It covers the first main surface 21 of the insulating substrate 2. The temporary adhesive layer 15 covers the plurality of second electrodes 4 and the third main surface 211 of the second insulating layer 201. The temporary adhesive layer 15 is peelable from the interposer 1. The material of the temporary adhesive layer 15 includes, for example, an acrylic resin. The thickness of the temporary adhesive layer 15 is, for example, 20 μm, but is not limited to this.

[0069] The carrier substrate 16 includes, for example, a glass substrate 161 and a release layer 162 laminated on the glass substrate 161. The carrier substrate 16 is temporarily fixed to the temporary adhesive layer 15, but is peelable from the temporary adhesive layer 15.

[0070] (4) Method of manufacturing the interposer The method of manufacturing the interposer 1 according to the embodiment will be described.

[0071] First, a laminate 10 is prepared in which a first insulating layer 202 is laminated on a carrier substrate 9 (hereinafter referred to as the first carrier substrate 9) (see Figure 2).

[0072] The first carrier substrate 9 has a first main surface 91 and a second main surface 92 opposite to the first main surface 91. The first carrier substrate 9 is, for example, a metal substrate. In this embodiment, the material of the metal substrate is stainless steel, but other materials may be used. The first carrier substrate 9 may also include, for example, an organic substrate, a silicon substrate, or a glass substrate instead of a metal substrate. As an organic substrate, for example, an LCP (Liquid Crystal Polymer) substrate, a PET (Polyethyleneterephthalate) substrate, or a PTFE (Polytetrafluoroethylene) substrate can be used. The first insulating layer 202 is laminated on the first main surface 91 of the first carrier substrate 9.

[0073] Next, the first electrode 32, the first barrier layer 81, the wiring section 6, and the second barrier layer 82 are fabricated. First, a plurality of recesses (first recesses 224) opening on the first main surface 221 for the placement of the first electrode 32 and the first barrier layer 81, and a plurality of recesses (second recesses 225) opening on the first main surface 221 for the placement of the wiring section 6 and the second barrier layer 82 are formed in the first insulating layer 202 by laser processing or the like (see Figure 3).

[0074] The materials for the first barrier layer 81 and the second barrier layer 82 are deposited on the first main surface 221 and on the inner surfaces of the recesses 224 and 225 by sputtering or the like to produce a raw barrier layer 80 made of the materials for the first barrier layer 81 and the second barrier layer 82 (see Figure 4).

[0075] A base conductor layer 30 consisting of the materials for the first electrode 32 and the wiring section 6 is fabricated by depositing the materials for the first electrode 32 and the wiring section 6 onto the base barrier layer 80 using electroplating or the like (see Figure 5).

[0076] Unnecessary portions on the first main surface 221 of the original barrier layer 80 and the original conductor layer 30 are removed by CMP polishing or the like. This creates the first electrode 32 and wiring portion 6 derived from the original conductor layer 30, and the first barrier layer 81 and second barrier layer 82 derived from the original barrier layer 80. At this point, the first barrier layer 81 covers the entire first surface 321 and the entire side surface 324 of the first electrode 32 (see Figure 6).

[0077] Next, a second insulating layer 201 is formed to cover the first main surface 221 of the first insulating layer 202, the plurality of first electrodes 32, and the plurality of wiring portions 6 (see Figure 7). For example, the second insulating layer 201 is formed by applying a solution containing the organic material of the second insulating layer 201 onto the laminate 10 using a coater (e.g., a spin coater) or dispenser and performing pre-baking. Alternatively, the second insulating layer 201 may be formed by laminating a resin film that will become the second insulating layer 201 onto the laminate 10.

[0078] Next, multiple second through-holes 213 are formed in the second insulating layer 201 by laser processing or the like (see Figure 8). The second through-holes 213 are formed in the second insulating layer 201 at the locations where the second via conductor portion 31 is to be formed. There is a one-to-one correspondence between the multiple second through-holes 213 and the multiple second via conductor portions 31.

[0079] Next, the second via conductor portion 31 and the second electrode 4 are fabricated by a semi-additive method or the like (see Figure 9). Specifically, a seed layer is fabricated on the third main surface 211 of the second insulating layer 201 and on the inner surface of the second through hole 213 by, for example, electroless plating or sputtering, and the material for the second via conductor portion 31 and the second electrode 4 is deposited by pattern plating using a plating resist on the seed layer. Subsequently, after removing the plating resist, the unnecessary portions of the seed layer are removed by etching. This fabricates the second via conductor portion 31 and the second electrode 4.

[0080] Next, a temporary adhesive layer 15 is prepared to cover the multiple second electrodes 4 and the third main surface 211 of the second insulating layer 201 (see Figure 10). For example, the temporary adhesive layer 15 is prepared by applying a varnish containing an organic material (e.g., acrylic resin), which is the material for the temporary adhesive layer 15, and drying it. The thickness of the temporary adhesive layer 15 is, for example, 20 μm, but is not limited to this.

[0081] Next, the carrier substrate 16 (hereinafter also referred to as the second carrier substrate 16) is bonded to the temporary adhesive layer 15 (see Figure 11). The second carrier substrate 16 includes, for example, a glass substrate 161 and a release layer 162 laminated on the glass substrate 161. For example, the release layer 162 of the second carrier substrate 16 is bonded to the temporary adhesive layer 15.

[0082] Next, the first carrier substrate 9 is peeled off from the first insulating layer 202 (see Figure 12).

[0083] Next, multiple first through-holes 223 are formed in the first insulating layer 202 by laser processing or the like (see Figure 13). The multiple first through-holes 223 are formed in the areas where each of the multiple first via conductor portions 33 in the first insulating layer 202 is to be formed.

[0084] When forming the first through-hole 223, the portion of the first barrier layer 81 that is exposed to the first through-hole 223 is removed. For example, when forming the first through-hole 223 by laser processing, the laser processing conditions are adjusted so that the portion of the first barrier layer 81 that is exposed to the first through-hole 223 is removed by the laser processing. As a result, the first barrier layer 81 is not exposed to the first through-hole 223, and a portion of the second surface 322 of the first electrode 32 is directly exposed.

[0085] Next, multiple first via conductors 33, multiple third electrodes 7, and multiple solder bumps 18 are fabricated (see Figure 14). For example, the first via conductors 33 and the third electrodes 7 are fabricated by a semi-additive method or the like. That is, for example, a seed layer is fabricated on the second main surface 222 of the first insulating layer 202 and on the inner surface of the first through hole 223 by an electroless plating method or a sputtering method, and the material for the first via conductors 33 and the third electrodes 7 is deposited by pattern plating using a plating resist on the seed layer. Subsequently, after removing the plating resist, unnecessary parts of the seed layer are removed by etching. This fabricates the first via conductors 33 and the third electrodes 7. Subsequently, the solder bumps 18 are fabricated by placing the material for the solder bumps 18 on the main surface 701 of the third electrodes 7.

[0086] Based on the above, a structure 110 equipped with the interposer 1 is manufactured.

[0087] The interposer 1 is obtained by peeling the second carrier substrate 16 from the temporary adhesive layer 15, and then peeling the temporary adhesive layer 15 from the interposer 1.

[0088] (5) An electronic component module 100 equipped with an electronic component module interposer 1 will be described with reference to Figure 1.

[0089] The electronic component module 100 comprises an interposer 1, an electronic component 19, and a sealing portion 20.

[0090] The electronic component 19 is a chip component such as an IC chip. The electronic component 19 is mounted on the interposer 1. More specifically, the electronic component 19 is flip-chip mounted on the interposer 1. The electronic component 19 has a plurality of external connection electrodes 191, and the plurality of external connection electrodes 191 are connected to each of the plurality of third electrodes 7 of the interposer 1 via solder bumps 18.

[0091] The sealing portion 20 seals and protects the electronic component 19. The sealing portion 20 has an underfill portion 24 that fills the gap between the electronic component 19 and the second main surface 222 of the first insulating layer 202, and an outer enclosure portion 25 that is arranged to cover the portion of the electronic component 19 other than the portion covered by the underfill portion 24. The sealing portion 20 is made from, for example, a reaction-curable resin material (for example, an epoxy resin composition). The resin material and the sealing portion 20 may further contain fillers.

[0092] (6) Method for manufacturing an electronic component module First, a structure 110 equipped with an interposer 1 is manufactured by the method described in item (4) above (see Figures 14 and 15).

[0093] Next, the electronic component 19 is flip-chip mounted on the interposer 1 so that the external connection electrode 191 of the electronic component 19 and the third electrode 7 of the interposer 1 are connected via solder bumps 18, and then the sealing portion 20 is manufactured by molding the resin material (see Figure 16). For example, the underfill portion 24 can be manufactured by injecting the resin material into the gap between the electronic component 19 and the second main surface 222 of the first insulating layer 202 and then curing it, and then the outer casing portion 25 can be manufactured by molding the resin material using a mold. Alternatively, the underfill portion 24 and the outer casing portion 25 may be manufactured simultaneously by molding the resin material using a mold.

[0094] Next, the second carrier substrate 16 is peeled off from the temporary adhesive layer 15, and then the temporary adhesive layer 15 is removed to obtain an electronic component module 100 equipped with the interposer 1 (see Figure 1).

[0095] (7) Advantages In the interposer 1 according to this embodiment, the first barrier layer 81 suppresses the migration of the material of the first electrode 32 (such as copper) from the first electrode 32 to the first insulating layer 202. Therefore, insulation failure of the first insulating layer 202 due to migration can be suppressed.

[0096] Furthermore, since the first barrier layer 81 is not interposed between the first electrode 32 and the first via conductor portion 33, the electrical conductivity between the first electrode 32 and the first via conductor portion 33 is not hindered by the first barrier layer 81. Therefore, good conductivity reliability between the first electrode 32 and the first via conductor portion 33 can be maintained. In addition, since there is no portion with high electrical resistance between the first electrode 32 and the first via conductor portion 33, the occurrence of electromigration when current flows between the first electrode 32 and the first via conductor portion 33 can be suppressed. Therefore, conductivity reliability between the first electrode 32 and the first via conductor portion 33 can be continuously maintained.

[0097] In this embodiment, the interposer 1 includes a wiring portion 6 embedded in the first insulating layer 202 and exposed to the outside of the first insulating layer 202 on its first main surface 221. The wiring portion 6 has a third surface 61 in contact with the fourth main surface 212 of the second insulating layer 201 and a fourth surface 62 opposite to the third surface 61. In the wiring portion 6, the first width H1 of the third surface 61 is greater than the second width H2 of the fourth surface 62. The first width H1 of the wiring portion 6 is smaller than the first outer diameter R1 of the first electrode 32, and the second width H2 of the wiring portion 6 is smaller than the second outer diameter R2 of the first electrode 32. The wiring portion 6 is covered by the first insulating layer 202.

[0098] With the above configuration, it is possible to narrow the width of the wiring section 6 while improving the reliability of the wiring section 6.

[0099] In this embodiment, the interposer 1 further includes a second barrier layer 82 that covers the wiring section 6, and the second barrier layer 82 is interposed between the wiring section 6 and the first insulating layer 202. As a result, the second barrier layer 82 suppresses the migration of the wiring section material (such as copper) from the wiring section 6 to the first insulating layer 202. Therefore, insulation failure of the first insulating layer 202 due to migration can be further suppressed.

[0100] In this embodiment, the interposer 1 further comprises a second insulating layer 201, a second via conductor portion 31, and a second electrode 4. The second insulating layer 201 has a third main surface 211 and a fourth main surface 212 opposite to the third main surface 211. The second via conductor portion 31 penetrates the second insulating layer 201. The second electrode 4 is circular or rectangular, but is not limited to these shapes. The second electrode 4 is positioned across the third main surface 211 of the second insulating layer 201 and the second via conductor portion 31. The second electrode 4 is connected to the second via conductor portion 31. The first electrode 32 is positioned across the fourth main surface 212 of the second insulating layer 201 and the second via conductor portion 31. The first electrode 32 is circular or rectangular, but is not limited to these shapes. The first electrode 32 is connected to the second via conductor portion 31. In a plan view from the thickness direction D1 of the first insulating layer 202, the first electrode 32 is smaller than the second electrode 4 and is located inside the outer edge 402 of the second electrode 4. The first electrode 32 has a first surface 321 that is in contact with the second via conductor portion 31 and a second surface 322 opposite to the first surface 321. In the first electrode 32, the first outer diameter R1 of the first surface 321 is larger than the second outer diameter R2 of the second surface 322.

[0101] With the above configuration, it is possible to improve the manufacturing yield. With the above configuration, since the first outer diameter R1 of the first surface 321 of the first electrode 32 is larger than the second outer diameter R2 of the second surface 322, the alignment margin between the first surface 321 of the first electrode 32 and the second via conductor portion 31 can be increased, making it possible to improve the manufacturing yield.

[0102] Furthermore, in the interposer 1 according to this embodiment, the second via conductor portion 31 is frustum-shaped, and the fourth outer diameter R4 on the fourth main surface 212 of the second insulating layer 201 is smaller than the third outer diameter R3 on the third main surface 211 of the second insulating layer 201.

[0103] With the above configuration, the alignment margin between the first surface 321 of the first electrode 32 and the second via conductor portion 31 can be further increased, making it possible to further improve the manufacturing yield.

[0104] Furthermore, the interposer 1 according to Embodiment 1 further comprises a third electrode 7. The first insulating layer 202 has a first main surface 221 that is in contact with the fourth main surface 212 of the second insulating layer 201, which is the second insulating layer 201, and a second main surface 222 that is opposite to the first main surface 221. The first insulating layer 202 covers the first electrode 32. The first via conductor portion 33 penetrates the first insulating layer 202 and is connected to the first electrode 32. The third electrode 7 is positioned across the second main surface 222 of the first insulating layer 202 and the first via conductor portion 33 and is connected to the first via conductor portion 33. The first via conductor portion 33 is frustum-shaped, and the fifth outer diameter R5 at the second surface 322 of the first electrode 32 is smaller than the sixth outer diameter R6 at the second main surface 222 of the first insulating layer 202.

[0105] The above configuration makes it possible to further improve manufacturing yield. Furthermore, the above configuration makes it possible to improve mounting reliability.

[0106] 3. Modified Examples Modified examples of the present disclosure will now be described. In the following modified examples, components similar to those in the interposer 1 and electronic component module 100 according to the embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0107] (1) Figure 17 of the first modified example shows the interposer 1 of the first modified example and an electronic component module 100 equipped with the interposer 1.

[0108] The interposer 1 and electronic component module 100 of the first modified example further include a third barrier layer 83 covering the first via conductor portion 33. Otherwise, the first modified example has the same configuration as the embodiment.

[0109] The third barrier layer 83 is interposed between the first via conductor portion 33 and the first insulating layer 202. In the first modified example, the third barrier layer 83 is also interposed between the third electrode 7 and the first insulating layer 202 (specifically, its second main surface 222). The third barrier layer 83 is not interposed between the first via conductor portion 33 and the first electrode 32, and, as in the embodiment, the first via conductor portion 33 and the first electrode 32 are in direct contact.

[0110] The material of the third barrier layer 83 is preferably a material with lower diffusion to the first insulating layer 202 than the material of the first via conductor portion 33. The material of the third barrier layer 83 is, for example, at least one selected from the group consisting of titanium, tantalum, titanium nitride, and tantalum nitride.

[0111] The interposer 1 and electronic component module 100 of the first modified example can be manufactured by adding a step for manufacturing the third barrier layer 83 to the manufacturing method in the embodiment. That is, for example, in the manufacturing method of the embodiment, after forming a plurality of first through holes 223 in the first insulating layer 202, a step for manufacturing the third barrier layer 83 is added before manufacturing the first via conductor portion 33 and the third electrode 7.

[0112] Specifically, the third barrier layer 83 is fabricated by depositing the material for the third barrier layer 83 on the inner surface of the first through-hole 223 in the first insulating layer 202 and on the area of ​​the second main surface 222 where the third electrode 7 is positioned, using a sputtering method or the like. At this point, the third barrier layer 83 is also present on the portion of the second surface 322 of the first electrode 32 that is exposed to the first through-hole 223. Subsequently, the portion of the third barrier layer 83 on the second surface 322 of the first electrode 32 that is exposed to the first through-hole 223 is removed using an Ar reverse sputtering method or the like.

[0113] Next, the first via conductor portion 33 and the third electrode 7 are fabricated in the same manner as in the embodiment.

[0114] In the first modified example, the third barrier layer 83 suppresses the migration of the material (such as copper) of the first via conductor 33 from the first via conductor 33 to the first insulating layer 202. As a result, insulation failure of the first insulating layer 202 due to migration can be further suppressed.

[0115] Furthermore, since the third barrier layer 83 is not interposed between the first electrode 32 and the first via conductor portion 33, the conductivity reliability between the first electrode 32 and the first via conductor portion 33 is maintained well, as in the embodiment, and the occurrence of electromigration when current flows between the first electrode 32 and the first via conductor portion 33 can be suppressed. For this reason, the conductivity reliability between the first electrode 32 and the first via conductor portion 33 can be continuously maintained.

[0116] (2) Figure 18 of the second modified example shows the interposer 1 and the structure 110 equipped with the interposer 1 of the second modified example.

[0117] In the second embodiment, the plurality of first electrodes 32 include a first conductive electrode 320 connected to a first via conductor portion 33 and a second conductive electrode 329 connected to a second via conductor portion 31. In the second modified example, the first conductive electrode 320 is not connected to the second via conductor portion 31, and the second conductive electrode 329 is not connected to the first via conductor portion 33.

[0118] Thus, in this disclosure, the first electrode 32 is not necessarily connected to both the first via conductor portion 33 and the second via conductor portion 31.

[0119] (3) Figure 19 shows the third modified example of the interposer 1.

[0120] In the third modification, the material of the first via conductor portion 33 is a solder alloy. Also, the interposer 1 does not have a third electrode 7, and the solder bump 18 is directly connected to and integrated with the first via conductor portion 33.

[0121] In the third modified example, when manufacturing the first via conductor portion 33, for example, molten solder alloy is filled into the first through-hole 223, and further molded so that the solder alloy overflows from the first through-hole 223 and rises onto the second main surface 222 of the first insulating layer 202. This allows the first electrode 32 to be manufactured from the portion of the solder alloy that is filled into the first through-hole 223, and solder bumps 18 to be manufactured from the portion that rises onto the second main surface 222 of the first insulating layer 202.

[0122] In the third modified example, the solder bump 18 can be directly connected to the first electrode 32, and the portion of the solder bump 18 that is filled into the first through hole 223 can be considered to be the first via conductor portion 33.

[0123] 4. As shown in the embodiments and modifications, the present disclosure includes the following embodiments:

[0124] An interposer (1) in a first embodiment comprises a first insulating layer (202), a first electrode (32), a first via conductor (33), and a first barrier layer (81). The first insulating layer (202) has a first main surface (221) and a second main surface (222) opposite to the first main surface (221). The first electrode (32) is embedded in the first insulating layer (202) and is exposed to the outside of the first insulating layer (202) at the first main surface (221). The first via conductor (33) penetrates the first insulating layer (202) from the second main surface (222) to the first electrode (32). The first barrier layer (81) covers the first electrode (32). The first barrier layer (81) is interposed between the first electrode (32) and the first insulating layer (202), but not between the first electrode (32) and the first via conductor portion (33).

[0125] According to this embodiment, insulation defects in the first insulating layer (202) are suppressed, and the conductivity reliability between the first electrode (32) and the first via conductor portion (33) can be continuously maintained.

[0126] In a second embodiment, the interposer (1) further comprises a wiring portion (6) which is embedded in the first insulating layer (202) and exposed to the outside of the first insulating layer (202) on the first main surface (221).

[0127] In a third embodiment, the interposer (1) further comprises a second barrier layer (82) covering the wiring section (6) as in the second embodiment. The second barrier layer (82) is interposed between the wiring section (6) and the first insulating layer (202).

[0128] In this embodiment, even if the interposer (1) is equipped with a wiring section (6), insulation defects in the first insulating layer (202) can be further suppressed.

[0129] In a fourth embodiment, in any one of the first to third embodiments, the interposer (1) further comprises a third barrier layer (83) covering the first via conductor portion (33). The third barrier layer (83) is interposed between the first via conductor portion (33) and the first insulating layer (202).

[0130] In this embodiment, insulation defects in the first insulating layer (202) can be further suppressed.

[0131] In the fifth embodiment, in any one of the first to fourth embodiments, the material of the first insulating layer (202) includes an organic material.

[0132] According to this embodiment, it is possible to improve the high-frequency characteristics of the interposer (1).

[0133] In the sixth embodiment, in any one of the first to fifth embodiments, the first electrode (32) has a first surface (321) in contact with the first via conductor portion (33) and a second surface (322) opposite to the first surface (321). The outer diameter (R1) of the first surface (321) of the first electrode (32) is greater than the outer diameter (R2) of the second surface (322).

[0134] According to this embodiment, it is possible to improve the manufacturing yield of the interposer (1).

[0135] In the seventh aspect, as in the sixth aspect, the outer diameter (R5) of the second surface (322) of the electrode (32) in the first via conductor portion (33) is smaller than the outer diameter (R6) of the second main surface (222) of the first insulating layer (202).

[0136] According to this embodiment, it is possible to improve the manufacturing yield of the interposer (1).

[0137] In the eighth aspect, in any one of the first to seventh aspects, the interposer (1) further comprises a second insulating layer (201), a second electrode (4), and a second via conductor (31). The second insulating layer (201) has a third main surface (211) and a fourth main surface (212) opposite to the third main surface (211). The first insulating layer (202) and the second insulating layer (201) are laminated such that the first main surface (221) and the fourth main surface (212) are in contact. The second electrode (4) is positioned on the third main surface (211) of the second insulating layer (201). The second via conductor (31) penetrates the second insulating layer (201) from the third main surface (211) to the fourth main surface (212) and is electrically connected to the second electrode (4).

[0138] In the ninth embodiment, in any one of the first to eighth embodiments, the first electrode (32) is a pad electrode for connecting an electronic component (19).

[0139] An electronic component module (100) according to the tenth embodiment comprises an interposer (1) according to any one of the first to ninth embodiments, and an electronic component (19) connected to a first electrode (32) of the interposer (1).

[0140] 1 Interposer 100 Electronic component module 19 Electronic component 201 Second insulating layer 202 First insulating layer (insulating layer) 211 Third main surface 212 Fourth main surface 221 First main surface 222 Second main surface 31 Second via conductor section 32 First electrode 321 First surface 322 Second surface 33 First via conductor section (via conductor section) 6 Wiring section 81 First barrier layer (barrier layer) 82 Second barrier layer 83 Third barrier layer R1 First outer diameter (outer diameter) R2 Second outer diameter (outer diameter) R3 Third outer diameter (outer diameter) R4 Fourth outer diameter (outer diameter)

Claims

1. An interposer comprising: an insulating layer having a first main surface and a second main surface opposite to the first main surface; an electrode embedded in the insulating layer and exposed to the outside of the insulating layer at the first main surface; a via conductor portion penetrating the insulating layer from the second main surface to the electrode; and a barrier layer covering the electrode, wherein the barrier layer is interposed between the electrode and the insulating layer, and not between the electrode and the via conductor portion.

2. The interposer according to claim 1, further comprising a wiring portion embedded in the insulating layer and exposed to the outside of the insulating layer on the first main surface.

3. The interposer according to claim 2, further comprising a second barrier layer covering the wiring portion, wherein the second barrier layer is interposed between the wiring portion and the insulating layer.

4. The interposer according to claim 1, further comprising a third barrier layer covering the via conductor portion, wherein the third barrier layer is interposed between the via conductor portion and the insulating layer.

5. The interposer according to claim 1, wherein the material of the insulating layer includes an organic material.

6. The interposer according to claim 1, wherein the electrode has a first surface in contact with the via conductor and a second surface opposite to the first surface, and the outer diameter of the first surface of the electrode is larger than the outer diameter of the second surface.

7. In the via conductor portion, the outer diameter of the electrode on the second surface is smaller than the outer diameter of the insulating layer on the second main surface. The interposer according to claim 6.

8. The interposer according to claim 1, further comprising a second insulating layer, a second electrode, and a second via conductor portion, wherein the second insulating layer has a third main surface and a fourth main surface opposite to the third main surface, the insulating layer and the second insulating layer are laminated such that the first main surface and the fourth main surface are in contact, the second electrode is disposed on the third main surface of the second insulating layer, and the second via conductor portion penetrates the second insulating layer from the third main surface to the fourth main surface and is electrically connected to the second electrode.

9. The interposer according to claim 1, wherein the electrode is a pad electrode for connecting electronic components.

10. An electronic component module comprising an interposer according to any one of claims 1 to 9, and an electronic component connected to the electrodes of the interposer.

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