Field-effect transistor (FET)-based sensing chip with integrated reference electrode and manufacturing method of an integrated reference electrode

Abstract

A field-effect transistor (FET)-based sensing chip with an integrated reference electrode and a manufacturing method for an integrated reference electrode of an FET-based sensing chip are disclosed. The FET-based sensing chip with an integrated reference electrode provides a multi-layer reference electrode easily formed by common metal process of the semiconductor manufacturing process including sputtering. No rear material or chemical solvents are required. Therefore, practical quantification of the FET-based sensing chip with an integrated reference electrode of the present invention is easily achieved.

Description

[0001] FIELD-EFFECT TRANSISTOR (FET)-BASED SENSING CHIP WITH INTEGRATED REFERENCE ELECTRODE AND MANUFACTURING METHOD OF AN INTEGRATED REFERENCE ELECTRODE CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of United States provisional application filed on November 01, 2024 and having application Ser No. 63 / 715,382 and the benefit of United States provisional application filed on February 14, 2025 and having application Ser. No. 63 / 758,740, the entire contents of which are hereby incorporated herein by reference.

[0003] BACKGROUND OF THE INVENTION

[0004] 1. Field of the Invention

[0005] This present invention is related to a field-effect transistor (FET)-based sensing chip, and more particularly to a field-effect transistor (FET)-based sensing chip with an integrated reference electrode.

[0006] 2. Description of the Prior Arts

[0007] Both the EGFET and ISFET require a reference electrode to provide a reference potential. An Ag / AgCl electrode has been commonly used as an external reference electrode for EGFET and ISFET due to its chemical stability and ease of manufacture. With reference to Fig. 6, the EGFET or ISFET may be used as an FET-based pH sensor 70 or a biosensor. The Ag / AgCl electrode 80 consists of a glass tube 81 containing a chloride solution 82 (e.g., KC1), a silver wire 83 coated with AgCl, and a porous membrane for an electrical interaction. With further reference to Fig. 7, a PH sensing curve is measured by the FET-based pH sensor 70 with the external Ag / AgCl electrode 80. Despite the popularity and durability, the external Ag / AgCl electrode 80 has several disadvantages when constructing the FET-based pH sensor or biosensor. First, the bulky configuration makes it difficult to miniaturize the sensing chip. Second, the large volume of the external reference electrode may interfere with the analyte when the sample volume is small.

[0008] With reference to Fig. 8D, a biosensor 90 with an integrated Ag / AgCl electrode 93 is proposed. A manufacturing method of the biosensor 90 has steps (a) to (g). With further reference to Fig. 8A, an FET device 91 and an external lead 92 of a reference electrode 93 are partially covered by a passivation layer 900. An Ag metal layer 93a is formed on an exposed area 921 of the external lead 92 and protrudes from the passivation layer 900. As shown in Fig. 8B, an AgCl layer 93b on a surface of the Ag metal layer 93a is formed by chlorinating the Ag metal layer using a 0.1 mol / L FeCE solution for minutes. As shown in Fig. 8C, an agar solution 94 containing KC1 is dropped onto the AgCl layer 93b to form a KC1 hydrogel layer to complete an integrated Ag / AgCl electrode 93. As shown in Fig. 8D, a polymer coating 95 composed of Nafion and polyurethane may be further applied over the formed KC1 hydrogel layer 94 to extend the lifespan of the integrated Ag / AgCl electrode 93. Since the aforementioned steps of the manufacturing method are not standard semiconductor fabrication procedures, such as chlorinating and rare materials, such as FeCh solution, KCL hydrogel, etc., are used, practical quantification of the biosensor with an integrated Ag / AgCl electrode remains challenging.

[0009] To overcome the shortcomings, the present invention provides a new Field-effect transistorbased sensing chip to mitigate or to obviate the aforementioned problems.

[0010] SUMMARY

[0011] An objective of the present invention is to provide a field-effect transistor (FET)-based sensing chip with an integrated reference electrode.

[0012] The field-effect transistor (FET)-based sensing chip with an integrated reference electrode includes:

[0013] a semiconductor substrate having a contact surface;

[0014] a plurality of I / O pads formed on the semiconductor substrate and not located on the contact surface;

[0015] a plurality of FETs formed on the semiconductor substrate, not located on the contact surface and electrically connected to the plurality of I / O pads, wherein each of the plurality of FETs;

[0016] a plurality of sensing metal layers formed on the semiconductor substrate, located on the contact surface and electrically connected to the corresponding gates of the plurality of FETs to form a plurality of EGFETs; and

[0017] a multi-layer reference electrode formed on the semiconductor substrate, located on the contact surface, electrically connected to the I / O pad, and from bottom to top having:

[0018] a base metal layer, wherein the base metal layer and the lurality of sensing metal layers are made by the same material;

[0019] an intermediary metal layer formed on the base layer; and

[0020] a top metal layer formed on the intermediary metal layer by sputtering, wherein the top metal layer exhibits a low reactivity with a solution to be sensed.

[0021] Based on the foregoing description, the FET-based sensing chip with an integrated reference electrode in accordance with the present invention mainly provides a multi-layer reference electrode easily formed by common metal process of the semiconductor manufacturing process including sputtering. No rear material or chemical solvents are required. Therefore, practical quantification of the FET-based sensing chip with an integrated reference electrode of the present invention is easily achieved.

[0022] Another objective of the present invention is to provide a manufacturing method for an integrated reference electrode of an FET-based sensing chip.

[0023] The manufacturing method includes steps of: (a) providing a semiconductor substrate is provided, wherein the semiconductor substrate has a contact surface;

[0024] (b) in the contact surface, downwardly defining a plurality of slots on the semiconductor substrate to separate multiple regions;

[0025] (c) respectively forming a plurality of first metal layers on the regions of the semiconductor substrate layer at the same time;

[0026] (d) forming a second metal layer on one of the first metal layers, wherein the rest of the first metal layers are used as an extended gate of EGFETs formed on the sensing integrated circuit area; and

[0027] (e) forming a third metal layer by sputtering on the second metal layer, wherein the third metal layer exhibits a low reactivity w ith a solution to be sensed.

[0028] Based on the foregoing description, the manufacturing method of an integrated reference electrode of FET-based sensing chip in accordance with the present invention mainly uses common metal process of the semiconductor manufacturing process including sputtering to form each metal layer of the multi-layer reference electrode. No rear material or chemical solvents are required. Therefore, practical quantification of the FET-based sensing chip with an integrated reference electrode of the present invention is easily achieved.

[0029] Other objectives, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Fig. 1 is a top plan view of a field-effect transistor (FET)-based sensing chip in accordance with the present invention;

[0032] Fig. 2 is a cross-sectional view of Fig. 1 taken along with line A-A;

[0033] Fig. 3 is an enlarged view of B region in Fig. 2;

[0034] Figs. 4Ato 4E are cross-sectional views of the FET-based sensing chip in different steps of a manufacturing method in accordance with the present invention;

[0035] Fig. 5 A is a diagram including responses of drain current to gate voltage under different pH values for an integrated Au electrode of Fig. 1;

[0036] Fig. 5B is a response curve of gate voltage under different pH values for the integrated Au electrode of Fig. 1;

[0037] Fig. 6 is an FET-based pH sensor with an external Ag / AgCl electrode in accordance w ith the prior art;

[0038] Fig. 7A is a diagram including responses of drain current to gate voltage under different pH values for an external Ag / AgCl electrode of Fig. 6;

[0039] Fig. 7B is a response curve of gate voltage under different pH values for the external Ag / AgCl electrode of Fig. 6; and

[0040] Figs. 8Ato 8D are cross-sectional views of a biosensor with an integrated Ag / AgCl electrode in different steps of a manufacturing method in accordance with the prior art.

[0041] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] With reference to Figs. 1 and 2, a field-effect transistor (FET)-based sensing chip with an integrated reference electrode in accordance with the present invention is shown. The FET-based sensing chip with an integrated reference electrode includes a semiconductor substrate 10, a liquidisolation element 14, a plurality of I / O pads 20, a plurality of field-effect transistors (FETs) 30, a plurality of sensing metal layers 40, and a multi-layer reference electrode 50.

[0043] The semiconductor substrate 10 has a contact surface area 11.

[0044] The liquid-isolation element 14 is formed around the contact surface 11 and is higher than the contact surface 11 to define a liquid storage space. Therefore, a solution to be sensed 60 is applied to the liquid storage space, as shown in Fig. 2. In one embodiment, the liquid-isolation element 14 may be a molding compound, and further encapsulates the semiconductor substrate 10 except for the contact surface 11.

[0045] The plurality of I / O pads 20 are formed on the semiconductor substrate 10 and not located on the contact surface 11. The I / O pads 20 may be arranged along one periphery, two or four peripheries of the semiconductor substrate 10.

[0046] The plurality of FETs 30 are formed on the semiconductor substrate 10 by a semiconductor process and not located on the contact surface 11. The sensing integrated circuit 30 is electrically connected to the plurality of I / O pads 20. In Fig. 1, the FETs are formed around the contact surface 11. In Fig. 2, the FETs 30 or a part of the FETs may be formed under the contact surface 11. Therefore, the FETs 30 are not exposed to the contact surface 11. Each FET 31 has a drain D, a source S, and a gate G.

[0047] The plurality of sensing metal layers 40 are formed on the contact surface 11 and respectively and electrically connected to the corresponding gates G of the plurality of FETs 31. In particular, each sensing metal layer 40 is electrically connected to the gate G of the corresponding FET 31 or the gates G of the corresponding FETs 31. The sensing metal layer 40 is regarded as an extended gate of the corresponding FET 31, so a plurality of EGFETs are formed. In the present embodiment, with further reference to Fig. 3, a SiCh layer 100 is formed on the contact surface 11 and the sensing metal layers 40 are formed on the SiCh layer 100 of the semiconductor substrate 10 and made of aluminum (Al) used in the metal process of the semiconductor manufacturing process. The metal process includes deposition and patterning.

[0048] With reference to Figs. 1 and 3, the multi-layer reference electrode 50 is formed on the contact surface 11 by common metal process of the semiconductor manufacturing process and is electrically connected to one of the I / O pads 20. In one embodiment, the plurality of the sensing metal layers 40 are arranged around the multi-layer reference electrode 50. Particularly, the plurality of the sensing metal layers 40 and the multi-layer reference electrode 50 are arranged in a matrix.

[0049] The multi-layer reference electrode 50 from bottom to top has a base metal layer 51, an intermediary metal layer 52, and a top metal layer 53.

[0050] The base metal layer 5 land the sensing metal layer 40 are made by the same material. For example, the base metal layer 51 is made of aluminum (Al). In one embodiment, with further reference to Fig. 3, the base metal layer 51 and the sensing metal layers 40 are formed on the same SiO2 layer 100 of the semiconductor substrate 10 in the same metal process, such as deposition and patterning. Since the intermediary metal layer 52 is formed on the base metal layer 51 and the top metal layer 53 is formed on the intermediary metal layer 52, the top metal layer 53 is higher than the sensing metal layers 40.

[0051] In the present embodiment, the top metal layer 53 exhibits low reactivity with the solution to be sensed 60. Gold (Au) or platinum (Pt) may be selected to form the top metal layer 53 and Gold (Au) has better conductivity. If the base metal layer 51 is made of Al and the top metal layer is made of Au, a proper metal material for the intermediary metal layer 52 is titanium (Ti) or nickel (Ni). The intermediary metal layer 52 stably binds between the base metal layer 51 and the top metal layer 53. In one embodiment, the base metal layer 51 is thicker than the intermediary metal layer 52 and the top metal layer 53. The intermediary metal layer 52 is thicker than the top metal layer 53.

[0052] With reference to Fig. 5 A, four solutions to be sensed with different pH values are respectively sensed by the FET-based sensing chip with Au top metal layer 53 and four responses of drain current to gate voltage under different pH values are obtained. With reference to Fig. 5B, a response curve is derived from the linear regression across the four responses of Fig. 7A. The same solutions to be sensed are sensed by the FET-based pH sensor 70 with the external Ag / AgCl electrode 80 as shown in Fig. 6. With further reference to Fig. 7A, the four solutions to be sensed with different pH values are respectively sensed by the FET-based pH sensor 70 with the external Ag / AgCl electrode 80 as shown in Fig. 6 and four responses of drain current to gate voltage under different pH values are obtained. With reference to Fig. 7B, a response curve is derived from the linear regression across the four responses of Fig. 7A. With reference to Figs. 5B and 7B, square labels indicate averages, with error bars indicating standard errors. The FET-based sensing chip with Au top metal layer 53 shows a pH sensing performance which is similar to that of the FET-based pH sensor 70 with the external Ag / AgCl electrode 80 as shown in Fig. 6. Furthermore, the stability of the FET-based sensing chip with Au top metal layer 53 is better than that of the FET-based pH sensor 70 with the external Ag / AgCl electrode 80.

[0053] A manufacturing method for the integrated reference electrode of the FET-based sensing chip has steps (a) to (d).

[0054] With reference to Figs. 1 and 4A, in the step (a), a semiconductor substrate 10 is provided. The semiconductor substrate 10 has a contact surface 1. In the present embodiment, an SiO2 layer 100 is formed on the contact surface 11 of the semiconductor substrate 10.

[0055] With reference to Figs. 1 and 4B, in the step (b), a plurality of slots 101 are defined downwardly on the SiCh layer 100 of the semiconductor substrate 10 to separate multiple regions 102. In the present embodiment, four slots 101 are defined to separate nine regions 102, and nine regions 102 are arranged in a matrix.

[0056] With reference to Figs. 1 and 4C, in the step (c), a plurality of first metal layers 51’, 40’ are respectively formed on the regions 102 of the S1O2 layer 100 in the contact surface 11 at the same time. In the present embodiment, the first metal layers 51’, 40’ are also arranged in a matrix and formed by deposition and patterning.

[0057] With reference to Figs. 1 and 4D, in the step (d), a second metal layer 52’ is formed on one of the first metal layers 51’. In the present embodiment, the second metal layer 52’ is formed on a middle one 51’ of the first metal layers. The rest of the first metal layers 40’ are used as an extended gate of EGFETs formed on the sensing integrated circuit area 12.

[0058] With reference to Figs. 1 and 4E, in the step (e), a third metal layer 53 ’ is formed on the second metal layer 52’ by sputtering. In the present embodiment, the top metal layer 53’ exhibits low reactivity with the solution to be sensed 60 as shown in Fig.2. Particularly, aluminum (Al) used in the metal process of the semiconductor process, may be selected to form the first metal layer 51’, 40’. Gold (Au) or platinum (Pt) exhibiting the low reactivity with the solution to be sensed may be selected to form the third metal layer 53’. The second metal layer 52’ stably binds the first metal layer 51 ’ and the third metal layer 53’. If the first metal layer 51’ is made of Al and the third metal layer 53’ is made of Au, a proper metal material for the second metal layer 52’ is titanium (Ti) or nickel (Ni). When the SiCh layer 100 is flat, the third metal layer 53’ is higher than the others of the first metal layers 40’. In one embodiment, the first metal layer 51’ is thicker than the second metal layer 52’ and the third metal layer 53’. The second metal layer 52’ is thicker than the third metal layer 53’. Therefore, the integrated reference electrode is a multi-layer reference electrode consisting of the first, second and third layers 51’, 52’, 53’.

[0059] Based on the foregoing description, the FET-based sensing chip with an integrated reference electrode in accordance with the present invention mainly provides the multi-layer reference electrode easily formed by common metal process of the semiconductor manufacturing process including sputtering. No rear material or chemical solvents are required. Therefore, practical quantification of the FET-based sensing chip with an integrated reference electrode of the present invention is easily achieved. Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and features of the invention, the disclosure is illustrative only. Changes may be made in the details, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Claims

WHAT IS CLAIMED IS:

1. A field-effect transistor (FET)-based sensing chip with an integrated reference electrode, comprising:a semiconductor substrate having a contact surface;a plurality of I / O pads formed on the semiconductor substrate and not located on the contact surface;a plurality of FETs formed on the semiconductor substrate, not located on the contact surface and electrically connected to the plurality of I / O pads, wherein each of the plurality of FETs has a drain, a source, and a gate;a plurality of sensing metal layers formed on the semiconductor substrate, located on the contact surface and electrically connected to the corresponding gates of the plurality of FETs to form a plurality of EGFETs; anda multi-layer reference electrode formed on the semiconductor substrate, located on the contact surface, electrically connected to the I / O pad, and from bottom to top having:a base metal layer, wherein the base metal layer and the plurality of sensing metal layers are made by the same material;an intermediary metal layer formed on the base layer; anda top metal layer formed on the intermediary metal layer by sputtering, wherein the top metal layer exhibits a low reactivity with a solution to be sensed.

2. The FET-based sensing chip with an integrated reference electrode as claimed in claim 1, whereinthe base metal layer is made of aluminum (Al);the intermediary metal layer is made of titanium (Ti) or nickel (Ni); andthe top metal layer is made of gold (Au).

3. The FET-based sensing chip with an integrated reference electrode as claimed in claim 1, whereinthe base metal layer is made of aluminum (Al); andthe intermediary metal layer is made of titanium (Ti) or nickel (Ni); andthe top metal layer is made of platinum (Pt).

4. The FET-based sensing chip with an integrated reference electrode as claimed in claim 1, whereina SiO2 layer is formed on the contact surface of the semiconductor substrate and is flat; the base metal layer and the plurality of sensing metal layers are formed on the SiO2 layer at the same time; andthe top metal layer is higher than the sensing metal layers.

5. The FET-based sensing chip with an integrated reference electrode as claimed in claim 1, whereinthe base metal layer is thicker than the intermediary metal layer and the top metal layer; and the intermediary metal layer is thicker than the top metal layer.

6. The FET-based sensing chip with an integrated reference electrode as claimed in claim 1, wherein the plurality of the sensing metal layers are arranged around the multi-layer reference electrode.

7. The FET-based sensing chip with an integrated reference electrode as claimed in claim 6, wherein the plurality of the sensing metal layers and the multi-layer reference electrode are arranged in a matrix.

8. The FET-based sensing chip with an integrated reference electrode as claimed in claim 1, further comprising a liquid-isolation element formed around the contact surface to define a liquid storage space.

9. The FET-based sensing chip with an integrated reference electrode as claimed in claim 8, wherein the liquid-isolation element is a molding compound and further encapsulates the semiconductor substrate except for the contact surface.

10. A manufacturing method of an integrated reference electrode of an FET-based sensing chip, comprising steps of:(a) providing a semiconductor substrate is provided, wherein the semiconductor substrate has a contact surface;(b) in the contact surface, downwardly defining a plurality of slots on the semiconductor substrate to separate multiple regions;(c) respectively forming a plurality of first metal layers on the regions of the semiconductor substrate at the same time;(d) forming a second metal layer on one of the first metal layers, wherein the rest of the first metal layers are used as an extended gate of EGFETs formed on the sensing integrated circuit area; and(e) forming a third metal layer by sputtering on the second metal layer, wherein the third metal layer exhibits a low reactivity with a solution to be sensed.

11. The manufacturing method as claimed in claim 10, whereinthe first metal layer is made of aluminum (Al);the second metal layer is made of titanium (Ti) or nickel (Ni); andthe third metal layer is made of gold (Au).

12. The manufacturing method as claimed in claim 10, whereinthe base metal layer is made of aluminum (Al);the second metal layer is made of titanium (Ti) or nickel (Ni); andthe top metal layer is made of platinum (Pt).

13. The manufacturing method as claimed in claim 10, wherein in the step (b), the multiple regions and the first metal layers are arranged in a matrix.

14. The manufacturing method as claimed in claim 13, wherein in the step (d), the second metal layer is formed on a middle one of the first metal layers.

15. The manufacturing method as claimed in claim 10, whereinin the step (a), a SiO2layer is further formed on the contact surface and is flat; and in the step (e), the third metal layer is higher than the others of the first metal layers.

16. The manufacturing method as claimed in claim 10, whereinthe first metal layer is thicker than the second metal layer and the third metal layer; and the second metal layer is thicker than the third metal layer.

17. The manufacturing method as claimed in claim 10, wherein in the step (c) the plurality of first metal layers are formed by deposition and patterning.

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