High speed switching radio frequency switch

Abstract

Embodiments described herein include radio frequency (RF) switches. Generally, embodiments described herein selectively bias an output of one or more switch transistors in the RF switch. Such coupling can provide a bias that significantly reduces gate lag effects. In one embodiment, the RF switch includes an antenna node, a first input / output (I / O) node, a second I / O node, a field effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment, the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the one or more output terminals.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to radio frequency (RF) switches, and more specifically to RF switches for high-speed switching and high-power handling. Background Technology

[0002] Radio frequency (RF) switches are widely used in a variety of RF applications, including RF power amplification, RF signal transmission, and RF signal reception. In these applications, RF switches require both high-speed switching and high power handling. To facilitate high power handling, many RF switches use one or more stacks of field-effect transistors (FETs), where each stack includes several FETs arranged in series. In such devices, each FET can be a monolithic transistor device including a variable conductivity channel between the drain and source terminals and one or more gates positioned above the channel. An electrical signal supplied to the gate controls the conductivity of the channel during FET operation. Therefore, RF switches implemented with stacks of such FETs offer relatively high power handling capabilities.

[0003] However, one challenge with these RF switches is the ability to provide improved switching speeds while still maintaining high power handling capability. For example, the switching speed of some RF switches can be limited by a phenomenon known as "gate hysteresis" in some FETs, which can lead to "slow tail" switching. Generally, gate hysteresis is a delay in drain current caused by electron trapping under the gate of the transistor. For instance, in some FETs formed from III-V type materials (such as gallium arsenide (GaAs) and gallium nitride (GaN) FETs), undesirable surface trapping can cause significant gate hysteresis. This gate hysteresis can lead to slow steady-state stabilization, which reduces the high-speed switching capability of the RF switch. Therefore, there remains a continued need for improved RF switches that offer both high power handling and high-speed switching. Summary of the Invention

[0004] According to a first aspect of the present invention, a radio frequency (RF) switch is provided, comprising:

[0005] Antenna node;

[0006] First input / output (I / O) node;

[0007] Second I / O node;

[0008] A first field-effect transistor (FET) coupled between the antenna node and the first I / O node, the first FET having a first gate terminal;

[0009] A first FET stack coupled between the antenna node and the second I / O node, the first FET stack having a first plurality of output terminals; and

[0010] A first bias coupling circuit electrically couples the first gate terminal to one or more of the first plurality of output terminals.

[0011] According to one or more embodiments, the first bias coupling circuit includes a first plurality of impedance elements, each of the first plurality of impedance elements being coupled to one of the first plurality of outputs.

[0012] According to one or more embodiments, the first bias coupling circuit includes a first plurality of resistors, each of the first plurality of resistors being electrically coupled to one of the first plurality of output terminals.

[0013] According to one or more embodiments, the resistance of each of the first plurality of resistors is greater than 10K ohms.

[0014] According to one or more embodiments, the RF switch further includes:

[0015] A second FET stack coupled between the first I / O node and the first reference node, the second FET stack having a second plurality of outputs; and

[0016] A second bias coupling circuit electrically couples the first gate terminal to the second plurality of output terminals.

[0017] According to one or more embodiments, the second bias coupling circuit includes a second plurality of resistors, each of the second plurality of resistors being electrically coupled to one of the second plurality of output terminals.

[0018] According to one or more embodiments, the first FET and each of the first FET stack are formed on a gallium arsenide (GaAs)-based substrate or a gallium nitride (GaN)-based substrate.

[0019] According to one or more embodiments, each of the first plurality of output terminals includes a source terminal or a drain terminal.

[0020] According to a second aspect of the present invention, a radio frequency (RF) switch is provided, comprising:

[0021] Antenna node;

[0022] Launch node;

[0023] Receive node;

[0024] First reference node;

[0025] Second reference node;

[0026] A first field-effect transistor (FET) stack coupled between the antenna node and the transmitter node, the first FET stack comprising a first series-coupled plurality of FETs, each of the first series-coupled plurality of FETs having a first plurality of output terminals, the first FET stack having a first gate terminal;

[0027] A second FET stack coupled between the antenna node and the receiving node, the second FET stack comprising a second series-coupled plurality of FETs, each of the second series-coupled plurality of FETs having a second plurality of output terminals, and the second FET stack having a second gate terminal;

[0028] A third FET stack coupled between the emitter node and the first reference node, the third FET stack comprising a third series-coupled plurality of FETs, each of the third series-coupled plurality of FETs having a third plurality of output terminals, the third FET stack having a third gate terminal;

[0029] A fourth FET stack coupled between the receiving node and the second reference node, the fourth FET stack comprising a fourth series-coupled plurality of FETs, each of the fourth series-coupled plurality of FETs having a fourth plurality of output terminals, the fourth FET stack having a fourth gate terminal;

[0030] A first bias coupling circuit electrically couples the first gate terminal to the second plurality of output terminals; and

[0031] A second bias coupling circuit electrically couples the first gate terminal to the third plurality of output terminals.

[0032] According to one or more embodiments, the first bias coupling circuit includes a first plurality of resistors, each of the first plurality of resistors being coupled to one of the second plurality of output terminals.

[0033] The second bias coupling circuit includes a second plurality of resistors, each of which is electrically coupled to one of the third plurality of output terminals.

[0034] According to one or more embodiments, the resistance of each of the first plurality of resistors and the second plurality of resistors is greater than 10K ohms.

[0035] According to one or more embodiments, each of the first FET stack, the second FET stack, the third FET stack, and the fourth FET stack is formed on a gallium arsenide (GaAs)-based substrate or a gallium nitride (GaN)-based substrate.

[0036] According to a third aspect of the present invention, a method for controlling a radio frequency (RF) switch, characterized in that the RF switch comprises a first field-effect transistor (FET) stack between an antenna node and a first I / O node and a second FET stack between the antenna node and a second I / O node, the method comprising the following steps:

[0037] A first control signal at the gate terminal of the FET in the first FET stack is provided to at least one output terminal of at least one FET in the second FET stack; and

[0038] Simultaneously with providing the first control signal, a second control signal is provided to the gate of the FET in the second FET stack, the second control signal being the inverse of the first control signal.

[0039] According to one or more embodiments, providing the first control signal to at least one output of the at least one FET in the second FET stack includes providing the first control signal through at least one impedance element coupled to the at least one output.

[0040] According to one or more embodiments, providing the first control signal to at least one output of the at least one FET in the second FET stack includes providing the first control signal through at least one resistor coupled to the at least one output.

[0041] According to one or more embodiments, the resistance of each of the at least one resistor is greater than 10K ohms.

[0042] According to one or more embodiments, each of the first FET and the second FET stack is formed on a gallium arsenide (GaAs)-based substrate or a gallium nitride (GaN)-based substrate.

[0043] According to one or more embodiments, the RF switch further includes a third FET stack between the first I / O node and the first reference node, and the method further includes the following steps:

[0044] The first control signal at the gate terminal of the FET in the first FET stack is provided to at least one output terminal of at least one FET in the third FET stack.

[0045] According to one or more embodiments, providing the first control signal to at least one output of at least one FET in the third FET stack includes providing the first control signal through at least one impedance element coupled to the at least one output.

[0046] According to one or more embodiments, providing the first control signal to at least one output of at least one FET in the third FET stack includes providing the first control signal through at least one resistor coupled to the at least one output. Attached Figure Description

[0047] A more complete understanding of the subject matter can be obtained by referring to the detailed embodiments and claims when considered in conjunction with the following figures, wherein similar reference numerals in the figures refer to similar elements.

[0048] Figure 1 This is a schematic diagram of a radio frequency (RF) switch according to an exemplary embodiment;

[0049] Figure 2 This is a circuit diagram of an RF switch according to an exemplary embodiment;

[0050] Figure 3 This is a circuit diagram of an RF switch according to an exemplary embodiment;

[0051] Figure 4 A graphical representation of a signal according to an exemplary embodiment;

[0052] Figure 5A and Figure 5B A graphical representation of an RF signal according to an exemplary embodiment;

[0053] Figure 6 This is a circuit diagram of an RF switch according to an exemplary embodiment;

[0054] Figure 7 This is a circuit diagram of a bias coupling circuit according to an exemplary embodiment;

[0055] Figure 8 A simplified block diagram of an RF transceiver system;

[0056] Figure 9 To illustrate according to the embodiments Figure 8 A top view of a module that is part of an RF transceiver system; and

[0057] Figure 10 A flowchart illustrating a method for fabricating an IC having one or more bias coupling circuits electrically coupled to one or more FETs, according to an embodiment. Detailed Implementation

[0058] The embodiments described herein include a radio frequency (RF) switch that provides improved switching speed while maintaining high power capability. Generally, the embodiments described herein provide this improved switching speed by selectively biasing the outputs of one or more switching transistors in the RF switch. In one embodiment, this selective biasing of the outputs is provided by coupling the gate of one transistor stack to the output of another transistor stack. This type of gate-to-output coupling provides a bias that significantly reduces gate hysteresis without significantly reducing the power handling capability of the transistor stack.

[0059] In one embodiment, the RF switch includes an antenna node, a first input / output (I / O) node, a second I / O node, a first field-effect transistor (FET) stack, a second FET stack, and a first bias coupling circuit. In this embodiment, the first FET stack includes a first gate terminal and a first plurality of output terminals (e.g., a first plurality of source / drain terminals). The second FET stack similarly includes a second gate terminal and a second plurality of output terminals. The first bias coupling circuit electrically couples the first gate terminal to the second plurality of output terminals (e.g., a second plurality of source / drain terminals). Thus, the first bias coupling circuit provides a bias voltage to the source / drain terminals of the transistors in the second FET stack, and the bias significantly reduces gate hysteresis effects in the second FET stack.

[0060] Now go to Figure 1 The diagram illustrates a schematic of an RF switch 100 according to an embodiment. The RF switch 100 includes an antenna node 102, a first input / output (I / O) node 104, a second I / O node 106, a first field-effect transistor (FET) stack 108, a second FET stack 110, and a first bias coupling circuit 112. Generally, the first bias coupling circuit 112 is configured to selectively bias one or more outputs of one or more switching transistors in the second FET stack 110. Specifically, the first bias coupling circuit 112 couples one or more gate terminals in the first FET stack 108 to one or more output terminals of the second FET stack 110. This coupling from the gate terminals in the first FET stack 108 to the output terminals of the second FET stack 110 provides a bias voltage to the transistors of the second FET stack 110, which can significantly reduce gate hysteresis without significantly reducing the power handling capability of the transistor stack.

[0061] Specifically, when the FET stack is turned on and conducting, the coupling between one or more gate terminals in the first FET stack 108 and one or more output terminals in the second FET stack 110 provides a temporary forward bias voltage to one or more transistors in the second FET stack 110. This temporary forward bias of one or more transistors in the second FET stack 110 causes those transistors to turn on faster, and thus significantly reduces gate hysteresis problems. Furthermore, because the temporary forward bias is applied only when the transistors in the second FET stack 110 are turned on, the power shutdown capability of the transistors in the second FET stack 110 is not significantly reduced.

[0062] In one specific example, the first FET stack 108 includes a first gate terminal and a first plurality of output terminals. The second FET stack 110 may similarly include a second gate terminal and a second plurality of output terminals. A first bias coupling circuit 112 electrically couples the first gate terminal to one or more of the second plurality of output terminals. Thus, the first bias coupling circuit 112 can provide a bias voltage to the source / drain of one or more transistors in the second FET stack 110, and the bias can significantly reduce gate hysteresis effects in the second FET stack 110.

[0063] In other embodiments, the RF switch may include additional FET stacks and additional bias coupling circuitry. For example, in one embodiment, the RF switch 100 may additionally include a third FET stack, a fourth FET stack, and a second bias coupling circuit. In such embodiments, the second bias coupling circuitry may be configured to selectively bias one or more outputs of one or more switching transistors in the third FET stack 110. Specifically, the second bias coupling circuitry may couple one or more gate terminals in the first FET stack 108 to one or more output terminals of the third FET stack. This coupling from one or more gate terminals in the first FET stack 108 to one or more output terminals of the third FET stack also provides a bias voltage to one or more transistors in the third FET stack, which significantly reduces gate hysteresis without significantly reducing the power handling capability of the transistor stack.

[0064] In some embodiments, the first bias coupling circuit 112 may include a plurality of resistors, each of which is electrically coupled to one of a second plurality of output terminals. Similarly, the second bias coupling circuit may include a second plurality of resistors, each of which is electrically coupled to one of a third plurality of output terminals.

[0065] Go to Figure 2This diagram illustrates a simplified circuit diagram of an RF switch 200 according to an exemplary embodiment. The RF switch 200 includes a plurality of input / output (I / O) nodes, including a first I / O node 228 and a second I / O node 238. The RF switch 200 further includes an antenna node 248, a first reference node 252, and a second reference node 253. The RF switch 200 further includes a plurality of switches 220, 224, 230, and 234 electrically coupled between the respective nodes 228, 238, 248, 252, and 253. As will be described in more detail below, one or more of the switches 220, 224, 230, and 234 may be implemented as a stack of FETs.

[0066] According to the embodiments described herein, RF switch 200 includes at least a first bias coupling circuit 212 configured to selectively bias the outputs of one or more switching transistors in switch 230. Specifically, this first bias coupling circuit 212 couples one or more gate terminals in switch 220 to one or more output terminals in switch 230. Similarly, this coupling from the gate terminal in switch 220 to the output terminal of switch 230 provides a bias voltage to the transistors of switch 230, which significantly reduces gate hysteresis. Specifically, the coupling from the gate terminal in switch 220 to the output terminal of switch 230 provides a temporary positive bias voltage to the transistors of switch 230, which allows those transistors to turn on more quickly and thus significantly reduces the problem of gate hysteresis. Furthermore, because this temporary positive bias is applied only when the transistors of the second switch 230 are turned on, the power shutdown capability of switch 230 is maintained.

[0067] Furthermore, as will be described in more detail below, additional bias coupling circuitry can be provided to other switches in RF switch 200. For example, a second bias coupling switch can be used to provide a similar temporary forward bias voltage to one or more transistors in switch 224, causing those transistors to turn on faster and reducing gate hysteresis. And similarly, because the temporary bias is applied only when switch 224 is on, the power-off capability of switch 224 is maintained.

[0068] Go to Figure 3This diagram illustrates a more detailed circuit diagram of an RF switch 300 according to an exemplary embodiment. In the example shown here, the RF switch 300 also includes multiple input / output nodes, including a first I / O node 328 (e.g., a transmit node) and a second I / O node 338 (e.g., a receive node). The RF switch 300 further includes an antenna node 348, a first reference node 352, and a second reference node 353. The RF switch 300 further includes multiple switches 320, 324, 330, and 334 electrically coupled between the respective nodes 328, 338, 348, 352, and 353. In the embodiment shown here, each of the switches 320, 324, 330, and 334 is implemented as a stack of FETs.

[0069] Specifically, switch 330 is implemented as a first stack of series-coupled FETs 366 electrically coupled between antenna node 348 and I / O node 338. Similarly, switch 320 is implemented as a second stack of series-coupled FETs 362 electrically coupled between I / O node 328 and antenna node 348. Switch 324 is similarly implemented as a third stack of series-coupled FETs 364 electrically coupled between I / O node 328 and first reference node 352. Finally, switch 334 is similarly implemented as a fourth stack of series-coupled FETs 368 electrically coupled between I / O node 338 and second reference node 353. It should be noted that while the first reference node 352 and the second reference node 353 will typically be coupled to a ground reference (e.g., zero volts), alternatively, the nodes may be coupled to a positive or negative DC voltage reference.

[0070] As used herein, the term "series coupling" for electrical coupling between multiple FETs in a stack means that the output terminals (e.g., source / drain terminals) of multiple FETs are connected together to provide a continuous conductive channel / path between an input node (e.g., I / O node 328) and an output node (e.g., antenna node 348) when the multiple FETs are in a conductive state (e.g., "on" or "off"). For example, in a sequence of series couplings of FETs, the source terminal of one FET may be coupled to the drain terminal of an adjacent FET.

[0071] exist Figure 3In the diagram, each of the switches 320, 324, 330, and 334 shown includes three series-coupled FETs 362, 364, 366, and 368. However, this is only one example implementation. In other embodiments, alternatively, each of the switches 320, 324, 330, and 334 may include fewer than three FETs or more than three FETs (as indicated by ellipses in each FET stack). Furthermore, each of the switches 320, 324, 330, and 334 may include the same number of FETs or, conversely, may include different numbers of FETs.

[0072] In the example shown here, each of the FETs 362, 364, 366, and 368 includes a gate (or control) terminal, an input terminal (e.g., drain / source terminals), and an output terminal (e.g., source / drain terminals). As is typical for FETs, the conductivity of the channel between the source and drain terminals of each of the FETs 362, 364, 366, and 368 can be controlled by applying an appropriate voltage to the corresponding gate terminal.

[0073] For ease of operation, control signals (control) and inverted control signals are used. The control signals are used to control RF switches 300. Specifically, control signals are used to control switches 320 and 334, and inverted control signals are used to control switches 324 and 330. For this purpose, control signals are applied to the gates of FETs 362 and 368, and inverted control signals are applied to the gates of FETs 364 and 366. Typically, the control signals and inverted control signals provided to each gate of any particular switch 320, 324, 330, 334 are synchronized because the control signals and inverted control signals simultaneously cause all FETs in the stack to become significantly conductive (e.g., "on" or "off") or significantly non-conductive (e.g., "off" or "on"). However, it should be noted that in other embodiments, the control signals and inverted control signals may be asynchronous.

[0074] During typical operation, RF switch 300 is operated to alternate between coupling an RF transmit signal provided by a transmitter (not shown) coupled to I / O node 328 to antenna node 348 and coupling an RF receive signal provided by an antenna at antenna node 348 to a receiver (not shown) coupled to I / O node 338. Specifically, in the transmit state, switches 320 and 334 are closed, and switches 324 and 330 are open. Specifically, in the transmit state, control signals applied to the gate terminals of FETs 362 and 368 cause those FETs to be in a significantly conductive state, while inverted control signals applied to the gate terminals of FETs 364 and 366 cause those FETs to be in a significantly non-conductive state. Therefore, in the transmit state, the signal energy present at I / O node 328 is delivered to antenna node 348 through switch 320, and a conductive path is opened between I / O node 328 and reference node 352. Furthermore, in the transmit state, the signal energy present at I / O node 338 is transmitted to reference node 353 through switch 334, and the conductive path between I / O node 338 and antenna node 348 is opened.

[0075] Conversely, in the receive state, switches 330 and 324 are closed, and switches 320 and 334 are open. Specifically, in the receive state, the inverted control signal applied to the gates of FETs 364 and 366 causes those FETs to be in a significantly conductive state, while the control signal applied to the gates of FETs 362 and 368 causes those FETs to be in a significantly non-conductive state. Therefore, in the receive state, the signal energy present at antenna node 348 is delivered to I / O node 338 through switch 330, and a conductive path is opened between I / O node 338 and ground reference node 353. Furthermore, in the receive state, the signal energy present at I / O node 328 is delivered to ground reference node 352 through switch 324, and a conductive path is opened between I / O node 328 and antenna node 348.

[0076] The RF switch 300 can be implemented in various devices and structures. For example, in one embodiment, the RF switch 300 is monolithic, wherein the FETs 362, 364, 366, and 368 are formed in and on a single integrated circuit substrate (e.g., on a single semiconductor die). For example, according to an embodiment, the RF switch IC 300 can be formed on a gallium arsenide (GaAs)-based substrate. In other embodiments, other substrates can be used, including silicon (Si)-based substrates (e.g., bulk silicon, silicon-on-insulator (SoI), etc.) and gallium nitride (GaN)-based substrates (e.g., GaN on silicon, GaN on silicon carbide (SiC), etc.).

[0077] To implement switches 320, 324, 330, and 334, various types of FETs can be used. For example, one or more of FETs 362, 364, 366, and 368 can be implemented as multi-gate FETs, although some of these FETs can also be single-gate FETs. Furthermore, in one embodiment, one or more of FETs 362, 364, 366, and 368 can be implemented as pseudocrystalline high electron mobility transistors (pHEMTs). In other embodiments, one or more of FETs 362, 364, 366, and 368 can be implemented in a variety of different configurations of gate-controlled three-terminal devices or transistors, including, to name a few, different configurations of pHEMTs, metal-oxide-semiconductor FETs (MOSFETs), high electron mobility transistors (HEMTs), metal-semiconductor field-effect transistors (MESFETs), laterally diffused metal-oxide-semiconductor (LDMOS) FETs, enhancement-mode MOSFETs (EMOSFETs), and junction-gate FETs (JFETs).

[0078] As mentioned above, a persistent problem in RF switch implementations is the need to provide high switching speeds. Specifically, in some RF switches, the switching speed can be limited by "gate hysteresis" in the transistors of one or more FET stacks (e.g., FETs 362, 364, 366, and / or 368). For example, in some FETs formed of III-V type materials (e.g., GaAs and GaN FETs), undesirable surface trapping can lead to significant gate hysteresis. This gate hysteresis can result in slow steady-state stabilization, sometimes referred to as a "slow tail," which reduces the high-speed switching capability of the RF switch.

[0079] To overcome this, RF switch 300 includes at least a first bias coupling circuit 312 configured to selectively bias one or more outputs (e.g., source / drain terminals) of one or more FETs 366 in switch 330. Specifically, the first bias coupling circuit 312 couples the gate of one or more FETs 362 in switch 320 to one or more source / drain terminals of the FET 366 in switch 330. This coupling from the gate of switch 320 to the output of FET 366 provides a bias voltage to FET 366, which significantly reduces gate hysteresis and improves switching speed.

[0080] Specifically, when FET 366 is turned on and conducting, the coupling from the gate terminal in switch 320 to one or more of the output terminals of FET 366 provides a temporary strong forward bias voltage to FET 366. This strong forward bias of FET 366 reduces the "slow tail" phenomenon caused by gate hysteresis and causes FET 366 to turn on faster than without this additional bias. Furthermore, because the strong forward bias is applied only when FET 366 is turned on, the power turn-off capability of FET 366 is not significantly reduced when FET 366 is turned off. This maintains the power handling capability of FET 366 and thus facilitates high-power switching.

[0081] Specifically, in RF switch 300, the coupling from the gate of one or more FETs 362 in switch 320 to the output of FET 366 in switch 330 effectively provides a control signal to the output of FET 366 while simultaneously applying a control signal to the gate of FET 362. Furthermore, because an inverted control signal is applied to the gate of FET 366, when FET 366 is turned on and conducting, the gate voltage of FET 366 relative to the output (e.g., gate-source voltage V)... GS This greatly improves performance. Therefore, when those transistors are turned on, a strong forward bias is applied to the FET366.

[0082] although Figure 3 The embodiment shows a first bias coupling circuit 312 connected between one or more gate terminals in switch 320 and all output terminals of FET 366 in switch 330. However, in an alternative embodiment, the first bias coupling circuit 312 may be connected to fewer than all output terminals of FET 366 in switch 330. In one example, the first bias coupling circuit 312 may be connected between one or more gate terminals in switch 320 and as few as one output terminal of FET 366 in switch 330. In embodiments where the first bias coupling circuit 312 is connected to fewer than all output terminals of FET 366, it is desirable to connect the first bias coupling circuit 312 to one or more FETs 366 closest to antenna node 348 to facilitate rapid turn-on of those upstream FETs 366.

[0083] As a non-limiting example, the FET 366 can be implemented as an N-channel device, when V GS When the voltage is greater than approximately 0.0V, the FET 366 is in a ON state with low resistance between the source and drain terminals, and when V... GSWhen the voltage is -3.0V or less, the FET 366 is in the off state. In this type of embodiment, the control signal can be a signal that alternates between applying 3.0V and 0.0V, where an inverted control signal provides an inverted voltage. Of course, alternatively, voltages other than 3.0V and 0.0V (or their inversions) can be implemented as on and off state voltages.

[0084] Now go to Figure 4 Figure 400 illustrates an exemplary control signal (control) and an inverting control signal alternating between 3.0V and 0.0V. And the V obtained from FET 366 GS Let's refer to each other. Figure 3 and 4 These control signals can be applied to the gates of FETs 362 and 368, while inverted control signals are applied to the gates of FETs 364 and 366.

[0085] This results in the operation of RF switch 300 as described above. Generally, when the control signal is high (e.g., 3.0V) and the inverting control signal is low (e.g., 0.0V), FET 362 in switch 320 and FET 368 in switch 334 are turned on (i.e., off), while FET 364 in switch 324 and FET 366 in switch 330 are turned off (i.e., on). Conversely, when the control signal is low (e.g., 0.0V) and the inverting control signal is high (e.g., 3.0V), FET 362 in switch 320 and FET 368 in switch 334 are turned off, while FET 364 in switch 324 and FET 366 in switch 330 are turned on.

[0086] Furthermore, according to the embodiments described herein, an additional control signal is applied to the output (e.g., the drain or source terminal) of FET 366. This causes FET 366 to be strongly forward biased when turned on, thus reducing gate hysteresis. Figure 4 This occurs at time T1, when the control signal transitions from high to low (e.g., 0.0V) and the inverting control signal transitions from low to high (e.g., 3.0V). Figure 3 and 4 In the example, this results in the gate-source voltage (V) of FET 366 of switch 330. GS The voltage is approximately 3.0V. Similarly, in this example, at V... GS At 0.0V or higher, FET 366 turns on (and again, it should be noted that this is just one example, and other FETs that can be used will turn on at other voltages, where GaAs and GaN FETs are typically implemented to turn on between -0.5V and 0.5V). Therefore, by providing approximately 3.0V (significantly greater than the turn-on voltage) V...GS The first bias coupling circuit 312 provides a strong forward bias to the FET 366, which can significantly improve the switching speed of the FET 366.

[0087] Then at time T2, the control signal transitions from low to high (e.g., 3.0V) and the inverting control signal transitions from high to low (e.g., 3.0V). Figure 3 and 4 In this example, this results in the FET 366 of switch 330 having a VV of approximately -3.0V. GS Similarly, in this example, in V GS At voltages below 0.0V, FET 366 is off. Therefore, by providing a voltage of -3.0V... GS (Significantly less than the break voltage), FET 366 is completely disconnected to achieve good power handling.

[0088] In summary, Figure 3 and 4 In the example, when FET 366 is turned on, the first bias coupling circuit 312 applies a strong forward bias voltage (i.e., 3.0V V). GS This is supplied to FET 366, while allowing a strong reverse bias voltage (i.e., -3.0V V) when FET 366 is off. GS The first bias coupling circuit 312 is applied to FET 366. Therefore, the first bias coupling circuit 312 can reduce gate hysteresis and provide fast switching speed when FET 366 switches to the conducting state, while ensuring that FET 366 is fully reverse biased when FET 366 is turned off.

[0089] Now go to Figure 5A and 5B Figures 500 and 550 illustrate exemplary RF signals, as would be seen at the output node of an RF switch (e.g., RF switches 100, 200, 300). Specifically, these RF signals are amplitude-modulated carrier signals that are present at the output of the RF switch when the RF switch is turned on and then off. These amplitude-modulated carrier signals have a fundamental frequency (f0). These amplitude-modulated carrier signals are exemplary types of RF signals that can be generated by high-frequency RF devices in many typical applications.

[0090] Figure 500 illustrates an exemplary gate hysteresis effect at the output of an RF switch. Specifically, gate hysteresis is caused by a slow tail of switching during the initial turn-on of the RF switch. This increases the final settling time and the time to reach the final steady-state value. This slow tail and increased time to reach the final steady-state value can limit the effective switching speed of the RF switch.

[0091] Figure 550 illustrates an exemplary gate hysteresis effect when a positive bias voltage is applied according to an embodiment using bias coupling circuitry (e.g., bias coupling circuitry 112, 212, 312). In Figure 550, the resulting output of the RF switch exhibits a significantly reduced "slow tail," and therefore has a significantly reduced settling time and reaches the final steady-state value more quickly. Similarly, this reduction in the slow tail and the reduced time to the final steady-state value improves the high-speed switching capability of the RF switch.

[0092] Go to Figure 6 The diagram illustrates a circuit diagram of an RF switch 600 according to another exemplary embodiment. In the example shown here, the RF switch 600 also includes multiple input / output nodes, including a first I / O node 328 and a second I / O node 338. The RF switch 300 further includes an antenna node 348, a first reference node 352, and a second reference node 353. The RF switch 300 further includes multiple switches 320, 324, 330, and 334 electrically coupled between the respective nodes 328, 338, 348, 352, and 353. In the embodiment shown here, each of the switches 320, 324, 330, and 334 is also implemented as a stack of FETs.

[0093] Specifically, switch 330 is implemented as a first stack of series-coupled FETs 366, switch 320 is implemented as a second stack of series-coupled FETs 362, switch 324 is implemented as a third stack of series-coupled FETs 364, and switch 334 is implemented as a fourth stack of series-coupled FETs 368.

[0094] According to the embodiments described herein, RF switch 600 includes a first bias coupling circuit 312 and a second bias coupling circuit 314. Similarly, the first bias coupling circuit 312 is configured to selectively bias the output of one or more FETs 366 in switch 330. Specifically, the first bias coupling circuit 312 couples the gate of one or more FETs 362 in switch 320 to one or more source / drain terminals of the FET 366 in switch 330. As described above, this coupling from the gate of switch 320 to one or more outputs of FET 366 provides a temporary strong forward bias voltage to FET 366 when FET 366 is turned on and conducting. This strong forward bias of FET 366 reduces the "slow tail" phenomenon caused by gate hysteresis and causes FET 366 to turn on faster than without this additional bias. Furthermore, because the strong forward bias is applied only when FET 366 is turned on, the power turn-off capability of FET 366 is not significantly reduced. This maintains the power handling capability of the FET 366 and thus facilitates high-power switching.

[0095] Similarly, in the embodiment shown here, a second bias coupling circuit 314 is added to selectively bias the outputs of one or more FETs 364 in switch 324. Specifically, the second bias coupling circuit 314 couples the gate of one or more FETs 362 in switch 320 to one or more source / drain terminals of the FET 364 in switch 324. As described above, this coupling from the gate of switch 320 to one or more outputs of FET 364 provides a temporary strong forward bias voltage to FET 364 when FET 364 is turned on and conducting. This strong forward bias of FET 364 also reduces the "slow tail" phenomenon caused by gate hysteresis and causes FET 364 to turn on faster than without this additional bias. Furthermore, because the strong forward bias is applied only when FET 364 is turned on, the power turn-off capability of FET 364 is not significantly reduced. This maintains the power handling capability of FET 364 and thus facilitates high-power switching.

[0096] Specifically, in RF switch 600, the coupling between the gate terminals of one or more FETs 362 in switch 320 and the output terminals of one or more FETs 364 in switch 324 effectively provides a control signal to the output terminal of FET 366, while simultaneously applying a control signal to the gate terminal of FET 362. Furthermore, because an inverted control signal is applied to the gate terminal of FET 364, when FET 364 is turned on and conducting, the gate voltage of FET 364 relative to the output terminal (e.g., V) is... GS This significantly improves performance. Therefore, when those transistors are on, a strong forward bias is applied to FET 364. And similarly, this configuration allows for a strong reverse bias when FET 364 is off. Thus, the second bias coupling circuit 314 reduces gate hysteresis and provides fast switching speeds when FET 364 switches to a conducting state, while ensuring that FET 364 is fully reverse biased when it is off.

[0097] although Figure 6The embodiment shows a first bias coupling circuit 312 connected between one or more gate terminals in switch 320 and all output terminals of FET 366 in switch 330. However, in an alternative embodiment, the first bias coupling circuit 312 may be connected to fewer than all output terminals of FET 366 in switch 330. In one example, the first bias coupling circuit 312 may be connected between one or more gate terminals in switch 320 and as few as one output terminal of FET 366 in switch 330. In embodiments where the first bias coupling circuit 312 is connected to fewer than all output terminals of FET 366, it is desirable to connect the first bias coupling circuit 312 to one or more FETs 366 closest to antenna node 348 to facilitate rapid turn-on of those upstream FETs 366.

[0098] Similarly, although Figure 6 The embodiment shows a second bias coupling circuit 314 connected between one or more gate terminals in switch 320 and all output terminals of FET 364 in switch 324. However, in an alternative embodiment, the second bias coupling circuit 314 may be connected to fewer than all output terminals of FET 364 in switch 324. In one example, the second bias coupling circuit 314 may be connected between one or more gate terminals in switch 320 and as few as one output terminal of FET 364 in switch 324. In embodiments where the second bias coupling circuit 314 is connected to fewer than all output terminals of FET 364, it is desirable to connect the second bias coupling circuit 314 to one or more FETs 364 closest to the first input node 328 to facilitate rapid turn-on of those upstream one or more FETs 364.

[0099] Go to Figure 7 The diagram shows a detailed circuit diagram of a bias coupling circuit 700 according to an exemplary embodiment. The bias coupling circuit 700 is an example of a type of bias coupling circuit that can be used in the various RF switches described above (e.g., RF switches 100, 200, 300, 600). Thus, the bias coupling circuit 700 can be used to implement bias coupling circuits 112, 212, 312, and 314 to obtain several non-limiting examples. Similarly, the bias coupling circuit 700 is configured to couple the gate terminals of one or more FETs in one switch to the output terminals of FETs in another switch. As described above, when those FETs are turned on and conducting, this coupling from the gate terminals in the first switch to the output terminals of the FETs in the second switch provides a strong positive bias voltage to the FETs in the second switch.

[0100] In this example, the bias coupling circuit 700 includes multiple impedance elements that are coupled to the FET outputs of the RF switch. Specifically, the bias coupling circuit includes resistors 702, 704, and 706, each of which is coupled to an output of the corresponding FET in the RF switch. For example, each of resistors 702, 704, and 706 may be coupled to the corresponding source or drain terminal of the corresponding FET.

[0101] Generally, each of resistors 702, 704, and 706 is provided to limit AC (e.g., RF) current by providing high impedance to signal energy at RF frequencies. Therefore, resistors 702, 704, and 706 ensure that most of the AC current flows through the FET stack and does not return towards the gate of another switch. Thus, resistors 702, 704, and 706 will typically be implemented with relatively large resistive elements. As an example, the impedance of each of resistors 702, 704, and 706 may be greater than 10 kΩ. Of course, this is just one example, and other configurations are possible. Furthermore, it should be noted that while the bias coupling circuit 700 includes resistors coupling between one or more gate terminals of the FET in the first switch and each output terminal of the FET in the second switch, in other embodiments, additional or different impedance elements may be used to provide high impedance between one or more gate terminals of the FET in the first switch and the output terminals of the FET in the second switch at RF frequencies. For example, in other embodiments, the bias coupling circuit 700 may include an inductor or a quarter-wave emitter line.

[0102] Now go to Figure 8 A simplified block diagram of an example radio frequency (RF) transceiver system 800 is shown. The RF transceiver system includes an RF switch 810 (e.g., Figure 1-3 The transceiver system 800 comprises RF switches 100, 200, 300, and 600, a transmitter 820, a receiver 830, and an antenna 840. The transceiver system 800 is a half-duplex transceiver, wherein at any given time, only one of the transmitter 820 or the receiver 830 is coupled to the antenna 840 via the RF switch 810. More specifically, the state of the RF switch 810 is controlled by a control signal to alternate between coupling RF transmitted signals generated by the transmitter 820 to the antenna 840 or coupling RF received signals received by the antenna 840 to the receiver 830.

[0103] Transmitter 820 may include, for example, a transmit (TX) signal processor 822 and a power amplifier 824. The transmit signal processor 822 is configured to generate a transmit signal and provide the transmit signal to the power amplifier 824. The power amplifier 824 amplifies the transmit signal and provides the amplified transmit signal to the RF switch 810. Receiver 830 may include, for example, a receive amplifier 832 (e.g., a low-noise amplifier) ​​and a receive (RX) signal processor 834. The receive amplifier 832 is configured to amplify a relatively low-power received signal from the RF switch 810 and provide the amplified received signal to the receive signal processor 834. The receive signal processor 834 is configured to consume or process the received signal.

[0104] During each transmit time interval, the RF switch 810 is controlled to be in the first or "transmit" state, such as... Figure 8 As depicted, the transmit signal path is closed between transmitter node 828 and antenna node 848, and the receive signal path is open between antenna node 848 and receiver node 838. Conversely, during each receive time interval, RF switch 810 is controlled to be in a second or "receive" state, wherein the receive signal path is closed between antenna node 848 and receiver node 838, and the transmit signal path is open between transmitter node 828 and antenna node 848.

[0105] According to the embodiments described herein, the RF switch 810 includes at least one bias coupling circuit (e.g., Figure 1-3 The bias coupling circuits 112, 212, 312, 314, and 700 (or one or more bias coupling circuits in 6 and 7) are configured to selectively bias the outputs of one or more switching transistors. Specifically, each bias coupling circuit couples one or more gate terminals in the first FET stack to one or more output terminals in the second FET stack. Similarly, this coupling from the gate terminals in the first FET stack to the output terminals of the second FET stack provides a bias voltage to the transistors in the second FET stack, significantly reducing gate hysteresis without significantly reducing the power handling capability of the transistor stack.

[0106] The RF transceiver system 800 can be physically implemented using a variety of active and passive electrical devices, which can be housed on one or more printed circuit boards (PCBs) and / or other substrates. To facilitate the assembly of such systems, the various components of the RF transceiver system 800 can be implemented as self-contained modules or electrical devices that can be coupled to the PCB, which electrically connects the modules / devices to other parts of the RF transceiver system 800. As used herein, the term "module" means a collection of active and / or passive electrical devices (e.g., ICs and components) physically contained within a single housing (e.g., one or more devices included on a common substrate (referred to herein as a "module substrate") or within a single package). A "module" also includes multiple conductive terminals for electrically connecting the collection of devices to an external circuitry forming other parts of an electrical system. Essentially, the module substrate configuration, the method of coupling one or more devices to the module terminals, and the number of devices within the module define the module type. For example, in various embodiments, modules may take the form of surface mount devices, chip carrier devices, ball, pin, or grid array devices, flat package (e.g., square or double flat package) devices, chip-scale package devices, system-in-package (SiP) devices, or some other type of integrated circuit package. Although specific types of modules are described below, it should be understood that embodiments of the subject matter of this invention may also be included in other types of modules.

[0107] For example, go to Figure 9 This illustrates the embodiment according to the example. Figure 8 This is a top view of module 900, a part of an RF transceiver system 800. Module 900 includes a module substrate 902, which may be a relatively small PCB, a conductive flange, or another rigid structure. Module 900 also includes multiple ICs coupled to module substrate 902, including RF switch integrated circuits (ICs) 910 (e.g., ICs embodying RF switches 100, 200, 300, 600, 810), and receive amplifier ICs 932 (e.g.,...). Figure 8 The module 900 includes a receiver amplifier 832, a receiver matching circuit IC 934, and an RF switch controller IC 950. Furthermore, the module 900 includes a transmit signal input terminal 928 (e.g., corresponding to...). Figure 8 Transmitter node 828), receiver signal output terminal 938 (e.g., corresponding to...) Figure 8 Receiver node 838), antenna terminal 948 (e.g., corresponding to...) Figure 8The module 900 includes an antenna terminal 848, a transmit / receive (TX / RX) control signal terminal 952, one or more ground terminals 960, 961, and one or more power terminals 962. The individual ICs 910, 932, 934, 950 and terminals 928, 938, 948, 952, 960-962 are electrically connected together via multiple bonding wires (e.g., bonding wire 970). In other embodiments, the individual ICs 910, 932, 934, 950 and terminals 928, 938, 948, 952, 960-962 may be electrically connected together using other conductive structures (e.g., conductive traces on and within the module substrate 902 and / or through conductive vias in the module substrate 902). In various embodiments, the module 900 may be housed in an air-cavity package or an overmolded (e.g., encapsulated) package, although the module 900 may be considered complete without such a package.

[0108] When module 900 is incorporated into the transceiver system (e.g.) Figure 8 After the system (800) is connected, and during operation of the transceiver system, power and ground reference voltages can be provided to module 900 via power and ground terminals 960-962. RF switch controller IC 950 can convert the input power voltage (e.g., +5.0 volts) received via power terminal 962. Furthermore, RF switch controller IC 950 can receive switch control signals (e.g., TTL level signals) via TX / RX control signal terminal 952. Based on the received switch control signals, RF switch controller IC 950 provides switch control signals (e.g., the control and inverting control signals discussed above) to the control terminals (e.g., gates) of the individual transistors (e.g., transistors within RF switches 100, 200, 300, and 600) of RF switch IC 910. As described above, the switch control signals determine whether each of the individual transistors is in a conducting or non-conducting state at any given time. More specifically, the switch control signal determines whether the RF switch IC 910 is in a transmit state (i.e., the state in which the switch is configured to deliver an RF signal from the transmitter to the antenna) or a receive state (i.e., the state in which the switch is configured to deliver an RF signal from the antenna to the receiver) at any given time.

[0109] When the switch control signal configures the RF switch IC 910 to be in transmit mode, the RF switch IC 910 will transmit the signal from the power amplifier (e.g., ...) through the transmit signal input terminal 928. Figure 8The transmitted signal received by the power amplifier 824 is passed to the antenna terminal 948 via the RF switch IC 910. Conversely, when the switch control signal puts the RF switch IC 910 into the receive state, the signal received from the antenna terminal 948 is passed to the receive matching circuit IC 934 via the RF switch IC 910. The receive matching circuit IC 934 may include one or more integrated passive devices (e.g., capacitors, inductors, and / or resistors). The integrated passive devices, together with the inductance of the bonding wire 970 between the receive matching circuit IC 934, the RF switch IC 910, and the receive amplifier IC 932, form an impedance matching circuit between the RF switch IC 910 and the receive amplifier IC 932. In an alternative embodiment, the receive matching circuit IC 934 may be replaced by discrete components. In either case, the impedance matching circuit may also perform filtering on the received signal passed from the RF switch IC 910 to the receive amplifier IC 932 via the impedance matching circuit. The receive amplifier IC 932 receives the received signal from the receive matching circuit IC 934 and amplifies the received signal. The receiver amplifier IC 932 then provides the amplified received signal to the receive signal output terminal 938.

[0110] Figure 10 To fabricate according to various embodiments having one or more FETs (e.g. Figure 3 and 6 FETs 362, 364, 366, 368) and one or more bias coupling circuits (e.g., FETs 362, 364, 366, 368) Figure 1 , 2 The bias coupling circuits of 112, 212, 312, 314, and 700 are ICs (e.g., 112, 212, 312, 314, and 700). Figure 9 The flowchart illustrates a method for fabricating an RF switch IC (910). In typical IC fabrication processes, multiple ICs are fabricated in parallel on a semiconductor wafer, and a final fabrication step includes separating individual ICs from the wafer. For simplicity of description, the fabrication of a single IC is described below. Those skilled in the art will understand that, based on the description herein, multiple ICs can be fabricated simultaneously, as indicated above. Although not specifically indicated below, an IC separation process can be performed when a wafer fabrication process is employed, for example, after block 1004. Similarly, typical module fabrication processes (or IC packaging processes) may include simultaneously forming multiple modules on a leadframe or PCB, and subsequently separating each module from the leadframe or PCB. Although not specifically indicated below, a module separation process can be performed, for example, after block 1008.

[0111] For ease of understanding, a reference will be made to fabricate a circuit with one or more voltage leveling circuits (e.g. Figure 3 , Figure 6 RF switch 300 (circuit 312, 314) Figure 3The methods described below are used to carry out the invention. However, those skilled in the art will understand based on the description herein that, alternatively, the fabrication embodiments can be used to fabricate RF switch ICs or other types of devices with different configurations. Therefore, reference to the RF switch IC embodiments described above should not be construed as limiting the scope of the invention to those embodiments.

[0112] In box 1002, one or more FETs (e.g., FETs) can be formed in and above the semiconductor substrate. Figure 3 The method can be initiated using FETs 362, 364, 366, and 368. In some embodiments, multiple FETs may be formed and electrically interconnected as a FET stack. Generally, each FET includes a gate terminal and an output terminal (e.g., a source terminal and a drain terminal).

[0113] As discussed above, the semiconductor substrate can include any variety of different semiconductor substrate materials (e.g., GaAs, GaN, GaN on Si, GaN on SiC, Si, SoI, bulk silicon, etc.), and one or more FETs can have any variety of different structures (e.g., pHEMT, MOSFET, HEMT, MESFET, LDMOS FET, EMOSFET, JFET, etc.). According to embodiments, prior to forming the FET, conductive substrate vias (TSVs) can be formed partially or completely through the substrate to provide conductivity between the top and bottom surfaces of the substrate (e.g., between the conductive terminals of one or more FETs in the FET and a ground reference node at the bottom of the substrate).

[0114] In block 1004, the method can be achieved by forming one or more bias coupling circuits (e.g., over a semiconductor substrate) Figure 1 , 2 The bias coupling circuits 112, 212, 312, 314, and 700 (numbers 3, 6, and 7) continue. As previously discussed, in various embodiments, the bias coupling circuit includes one or more impedance elements (e.g., [missing information]). Figure 7 The resistors 702, 704, and 706, and the respective electrical connections between the gate and output terminals of the FET. In various embodiments, the impedance elements are integrated passive components (e.g., integrated capacitors, resistors, and / or inductors) and / or discrete components (e.g., discrete capacitors, resistors, and / or inductors).

[0115] In box 1006, the method can be achieved by electrically coupling the terminal of the FET to the bias coupling circuit and the respective I / O nodes (e.g., Figure 1 , 2The nodes 102, 104, 106, 228, 238, 248, 252, 253, 328, 338, 348, 352, and 353 continue. For example, the electrical connection between the FET and the bias coupling circuitry may include integrated electrical connections. Ultimately, during operation, electrical signals can be received from external circuitry through the nodes, and thus electrical signals processed by one or more FETs can be provided to external circuitry through the nodes. For example, as previously discussed, nodes may include a first I / O node, a second I / O node, a ground reference node, and an antenna node.

[0116] In box 1008, an IC (e.g., RF switch IC 910) is physically coupled to the module substrate (e.g., Figure 9 (Module substrate 902). In addition, one or more additional ICs and / or components may also be physically coupled to the module substrate.

[0117] In block 1010, one or more ICs and components are electrically coupled to each other and to terminals configured to deliver signals, power, and ground references between an external circuit system and one or more ICs / components of the module. The module substrate configuration, the method of coupling one or more ICs and components to the terminals of the module, and the number of ICs within the module define the module or package type. The module can then be completed (e.g., by encapsulating the module or containing the module in an air-cavity package). Once the module is completed, it can be physically and electrically coupled to an external circuit system (e.g., ...). Figure 8 (The rest of the system 800).

[0118] In one embodiment, an RF switch is provided, the RF switch comprising: a first input / output (I / O) node; a second I / O node; a first field-effect transistor (FET) coupled between an antenna node and the first I / O node, the first FET having a first gate terminal; a first FET stack coupled between the antenna node and the second I / O node, the first FET stack having a first plurality of output terminals; and a first bias coupling circuit electrically coupling the first gate terminal to one or more of the first plurality of output terminals.

[0119] In another embodiment, an RF switch is provided, comprising: an antenna node; a first input / output (I / O) node; a second I / O node; a first field-effect transistor (FET) stack coupled between the antenna node and the first I / O node, the first FET stack having a first gate terminal and a first plurality of output terminals; a second FET stack coupled between the antenna node and the second I / O node, the second FET stack having a second gate terminal and a second plurality of output terminals; and a first bias coupling circuit electrically coupling the first gate terminal to the second plurality of output terminals.

[0120] In another embodiment, an RF switch is provided, comprising: an antenna node; a transmitting node; a receiving node; a first reference node; a second reference node; a first field-effect transistor (FET) stack coupled between the antenna node and the transmitting node, the first FET stack comprising a plurality of FETs firstly series-coupled, each of the plurality of FETs having a first plurality of outputs, the first FET stack having a first gate terminal; and a second FET stack coupled between the antenna node and the receiving node, the second FET stack comprising a plurality of FETs secondly series-coupled, each of the plurality of FETs secondly series-coupled having a second plurality of outputs, the second FET stack having a second gate terminal. The third FET stack coupled between the transmitter node and the first reference node includes a third series-coupled plurality of FETs, each of the third series-coupled plurality of FETs having a third plurality of outputs, and the third FET stack having a third gate terminal; a fourth FET stack coupled between the receiver node and the second reference node includes a fourth series-coupled plurality of FETs, each of the fourth series-coupled plurality of FETs having a fourth plurality of outputs, and the fourth FET stack having a fourth gate terminal; a first bias coupling circuit electrically coupling a first gate terminal to a second plurality of outputs; and a second bias coupling circuit electrically coupling a first gate terminal to a third plurality of outputs.

[0121] In another embodiment, a method for controlling a radio frequency (RF) switch is provided, the RF switch comprising a first field-effect transistor (FET) stack between an antenna node and a first I / O node and a second FET stack between the antenna node and the second I / O node, the method comprising the steps of: providing a first control signal at a gate terminal of a FET in the first FET stack to at least one output terminal of at least one FET in the second FET stack; and simultaneously providing the first control signal to a second control signal at a gate terminal of a FET in the second FET stack, the second control signal being the inverse of the first control signal.

[0122] The foregoing detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the terms "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or illustrative should not necessarily be construed as preferred or advantageous over other embodiments. Furthermore, it is not intended to be bound by any expressed or implied theory presented in the foregoing technical field, background art, or detailed description.

[0123] For the sake of brevity, conventional semiconductor manufacturing techniques are not described in detail herein. Furthermore, certain terms may be used herein for reference only, and therefore these terms are not intended to be restrictive, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0124] The foregoing description refers to elements or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element, and not necessarily mechanically. Therefore, although the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0125] While at least one exemplary embodiment has been presented in the preceding detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing this patent application.

Claims

1. A radio frequency (RF) switch, characterized in that, include: Antenna node; First input / output (I / O) node; Second I / O node; A first field-effect transistor (FET) coupled between the antenna node and the first I / O node, the first FET having a first gate terminal; A first FET stack coupled between the antenna node and the second I / O node, the first FET stack having a first plurality of output terminals; and A first bias coupling circuit electrically couples the first gate terminal to one or more of the first plurality of output terminals. The first bias coupling circuit is configured to provide a control signal at the first gate terminal to one or more of the first plurality of output terminals.

2. The RF switch according to claim 1, characterized in that, The first bias coupling circuit includes a first plurality of impedance elements, each of the first plurality of impedance elements being coupled to one of the first plurality of output terminals.

3. The RF switch according to claim 1, characterized in that, The first bias coupling circuit includes a first plurality of resistors, each of the first plurality of resistors being electrically coupled to one of the first plurality of output terminals.

4. The RF switch according to claim 3, characterized in that, The resistance of each of the first plurality of resistors is greater than 10 kΩ.

5. The RF switch according to claim 1, characterized in that, In addition, including: A second FET stack coupled between the first I / O node and the first reference node, the second FET stack having a second plurality of output terminals; and A second bias coupling circuit electrically couples the first gate terminal to the second plurality of output terminals.

6. The RF switch according to claim 5, characterized in that, The second bias coupling circuit includes a second plurality of resistors, each of which is electrically coupled to one of the second plurality of output terminals.

7. The RF switch according to claim 1, characterized in that, The first FET and each of the first FET stacks are formed on a gallium arsenide (GaAs)-based substrate or a gallium nitride (GaN)-based substrate.

8. The RF switch according to claim 1, characterized in that, Each of the first plurality of output terminals includes a source terminal or a drain terminal.

9. A radio frequency (RF) switch, characterized in that, include: Antenna node; Launch node; Receive node; First reference node; Second reference node; A first field-effect transistor (FET) stack coupled between the antenna node and the transmitter node, the first FET stack comprising a first series-coupled plurality of FETs, each of the first series-coupled plurality of FETs having a first plurality of output terminals, the first FET stack having a first gate terminal; A second FET stack coupled between the antenna node and the receiving node, the second FET stack comprising a second series-coupled plurality of FETs, each of the second series-coupled plurality of FETs having a second plurality of output terminals, and the second FET stack having a second gate terminal; A third FET stack coupled between the emitter node and the first reference node, the third FET stack comprising a third series-coupled plurality of FETs, each of the third series-coupled plurality of FETs having a third plurality of output terminals, the third FET stack having a third gate terminal; A fourth FET stack coupled between the receiving node and the second reference node, the fourth FET stack comprising a fourth series-coupled plurality of FETs, each of the fourth series-coupled plurality of FETs having a fourth plurality of output terminals, the fourth FET stack having a fourth gate terminal; A first bias coupling circuit electrically couples the first gate terminal to the second plurality of output terminals; and A second bias coupling circuit electrically couples the first gate terminal to the third plurality of output terminals.

10. A method for controlling a radio frequency (RF) switch, characterized in that, The RF switch includes a first field-effect transistor (FET) stack between an antenna node and a first I / O node, and a second FET stack between the antenna node and the second I / O node. The method includes the following steps: A first control signal at the gate terminal of the FET in the first FET stack is provided to at least one output terminal of at least one FET in the second FET stack; and Simultaneously with providing the first control signal, a second control signal is provided to the gate of the FET in the second FET stack, the second control signal being the inverse of the first control signal.

Images