Method to fabricate strain-relaxed iii-nitride materials with an electrochemical etch

Abstract

A method to create strain-relaxed III-nitride templates for device fabrication includes: depositing a sacrificial layer below or under epitaxially-grown lattice-mismatched III-nitride layers, exposing the sacrificial layer, performing an electrochemical etch of the sacrificial layer so that the III-nitride layers become at least partially-detached from a growth substrate, thereby creating strain-relaxed III-nitride templates from the partially-detached III-nitride layers for subsequent device growth and fabrication.

Description

[0001] METHOD TO FABRICATE STRAIN-RELAXED III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH

[0002] CROSS REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned application:

[0004] U.S. Provisional Patent Application Serial No. 63 / 715,058, filed on November 1, 2024, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHOD TO FABRICATE STRAIN-RELAXED III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0863USP1 (UC-2025-351-1); which application is incorporated by reference herein.

[0005] This application is related to the following co-pending and commonly- assigned applications:

[0006] P.C.T. International Patent Application Serial No. PCT / US25 / 48683, filed on September 30, 2025, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHOD TO LIFT-OFF III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0861WOU1 (UC 2025-344-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Serial No. 63 / 700,896, filed on September 30, 2024, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHOD TO LIFTOFF III-NITRIDE MATERIALS WITH AN ELECTROCHEMICAL ETCH,” docket number G&C 30794.0861USP1 (UC 2025-344-1);

[0007] U.S. Provisional Patent Application Serial No. 63 / 722,720, filed on November 20, 2024, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “METHODS TO PRODUCE AND RECYCLE SUB STATES FOR III-NITRIDE MATERIALS WITH ELECTROCHEMICAL ETCHING,” docket number G&C 30794.0864USP1 (UC 2025-357-1); U.S. Provisional Patent Application Serial No. 63 / 794,481, filed on April 25, 2025, by Michael Iza, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “ELECTROCHEMICAL LIFT-OFF AND TRANSFER OF III- NITRIDE DEVICE LAYERS FOR HETEROGENEOUS INTEGRATION,” docket number G&C 30794.0873USP1 (UC 2025-381-1);

[0008] U.S. Provisional Patent Application Serial No. 63 / 798,679, filed on May 2, 2025, by Michael Iza, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “ELECTROCHEMICAL LIFT-OFF AND INTEGRATION OF III-NITRIDE THIN FILMS FOR PHOTONIC AND QUANTUM APPLICATIONS,” attorneys’ docket number G&C 30794.0878USP1 (UC-2025-388-1);

[0009] U.S. Provisional Patent Application Serial No. 63 / 814,824, filed on May 30, 2025, by Michael Iza, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “III-NITRIDE POWER DEVICES WITH BONDED THIN FILMS, POLARITY CONTROL AND THERMALLY OPTIMIZED CARRIER INTEGRATION,” docket number G&C 30794.0883USP1 (UC 2025-391-1);

[0010] U.S. Provisional Patent Application Serial No. 63 / 836,785, filed on July 1, 2025, by Yifan Yao, Hanyu Bi, Michael Iza, Shuji Nakamura and Steven P. DenBaars, entitled “SENSING DEVICE USING III-NITRIDE LIFT-OFF TECHNOLOGY FOR RAMAN SPECTROSCOPY AND FLUORESCENCE,” attorneys’ docket number G&C 30794.0875USP1 (UC-2025-382-1);

[0011] U.S. Provisional Patent Application Serial No. 63 / 846,495, filed on July 18, 2025, by Michael Iza, Xianqing Li, Kittamet Chanchaiworawit, Stephen Gee, Hanyu Bi, Yifan Yao, Steven P. DenBaars and Shuji Nakamura, entitled “III-NITRIDE- BASED VERTICAL CAVITY SURFACE EMITTING LASER (VCSEL) UTILIZING AN ELECTROCHEMICAL ETCH BASED LIFT-OFF,” docket number G&C 30794.0876USP1 (UC 2025-384-1); and

[0012] U.S. Provisional Patent Application Serial No. 63 / 907,194, filed on October 29, 2025, by Michael Iza, Torn Inatome, Yifan Yao, Hanyu Bi, Steven P. DenBaars and Shuji Nakamura, entitled “NITRIDE SEMICONDUCTOR DEVICES INCORPORATING DEFECT REDUCTION LAYERS AND

[0013] ELECTROCHEMICAL LIFT-OFF SACRIFICIAL LAYERS,” docket number G&C 30794.0896USP1 (UC 2026-793-1); all of which applications are incorporated by reference herein.

[0014] BACKGROUND OF THE INVENTION

[0015] 1. Fi el d of Inventi on

[0016] This invention relates to a method to grow and fabricate strain-relaxed templates for Ill-nitride devices by depositing and electrochemically etching a sacrificial layer.

[0017] 2. Description of the Related Art

[0018] (Note: This application references several different publications as indicated throughout the specification by one or more reference numbers within brackets, e.g., [x], A list of these different publications ordered according to these reference numbers can be found below in the section entitled “References”. Each of these publications is incorporated by reference herein.)

[0019] The terms “III-N” or “Group-Ill nitride” or “III-nitride” or “nitride” as used herein refer to any alloy composition of (Ga, Al, In, B)N having the formula GanALInyBzN where 0<n<l, 0<x<l, 0<y<l, 0<z< 1, and n+x+y+z=l.

[0020] III-nitride semiconductor materials are critical in the development of high performance optoelectronic and electronic devices, including light-emitting diodes (LEDs), lasers diodes (LDs), high-electron mobility transistors (HEMTs), radio frequency (RF) devices, and other devices. Nevertheless, because of their crystal structure and lattice mismatch with other types of conventional semiconductors, high- quality III-nitride based devices pose significant material growth challenges.

[0021] For example, AlGaN layers cannot be easily grown on GaN due to having a smaller lattice constant. There is an unavoidably large tensile stress due to the lattice mismatch during the material growth. Extended defects such as cracking are usually formed to relieve stress.

[0022] On the other hand, InGaN layers with high indium composition are also challenging to grow on GaN. While InGaN layers do not usually crack on GaN substrates, the high compressive stress can cause defects formation, surface morphology degradation and indium incorporation reduction.

[0023] In fact, there are certain limitations on the InGaN or AlGaN thickness growing on GaN before plastic deformation will occur through defect formation, which were extensively studied through experiments and theory [1], [2],

[0024] A key factor in describing the thickness and composition limits of lattice- mismatched thin films is the concept of critical thickness. Critical thickness hc(x) refers to the maximum thickness at which a strained layer can remain defect-free when depositing one material on a substrate with a different lattice constant. Beyond this thickness, misfit dislocations or other defects will start forming to relieve the strain caused by lattice mismatch between the thin film and the substrate.

[0025] A simplified version of the Matthews-Blakeslee model is often used to approximate the critical thickness: where:

[0026] • hc(x) is the critical thickness,

[0027] • b is the Burgers vector (approximately 3.189 A for GaN),

[0028] • e is the lattice mismatch, defined a substratewhere a is the asubstrate in-plane lattice parameter, and

[0029] • v is Poisson's ratio (typically v ~ 0.2 for these materials).

[0030] Examples include the following:

[0031] 1. AlGaN on GaN

[0032] For the AlGaN / GaN system, the lattice mismatch depends on the aluminum content x in AkGai-xN. The lattice mismatch (e) is: e ~ -0.0242-x

[0033] For 10% Al content (x=0.1): hc(x = 0.1) ~ 476.3 nm

[0034] This means that the critical thickness for a 10% aluminum content AlGaN film on GaN is about 476.3 nm before defects begin to form.

[0035] 2. InGaN on GaN

[0036] For the InGaN / GaN system, the lattice mismatch depends on the indium content y in InyGai-yN. The lattice constants of GaN and InN are more disparate, so the mismatch is larger. For indium content y, the mismatch is: e ~ 0.065-y

[0037] For 20% indium content (y=0.2): hc(y = 0.2) ~ 25 nm

[0038] The critical thickness for a 20% indium content InGaN film on GaN is approximately 25 nm before dislocations form.

[0039] Besides defects formation, the strain state of the film can also affect the incorporation of chemical species and therefore the composition of the film during material growth. For the growth of long wavelength InGaN-based LEDs or LDs on GaN layers, the active region needs to incorporate high indium composition for low energy photon emission, but the large compressive strain associated with growing high indium composition will reduce the amount of indium incorporation, which prevents the development of efficient red and green InGaN-based LEDs, and is commonly referred to as the “composition pulling effect” [3], Therefore, strain- relaxed InGaN layers using the present invention can allow us to achieve devices with higher efficiency and longer wavelength.

[0040] The same trend also goes for growing AlGaN-based devices on lattice- mismatched substrates. The strain associated with growing an AlGaN active region prevents more gallium from incorporation when growing on AIN layers (compressive) or prevents more aluminum from incorporation when growing on GaN layers (tensile). Thus, the important thing is that at least active layers should have a strain- relaxed layer to make the efficient emitting devices such as LEDs and LDs using the present invention of the strain-relaxed template.

[0041] Also, an active layer of other devices, such as solar cells, electric power devices, high frequency devices, etc., should have a strain-relaxed layer to make efficient, high power or reliable devices. Overall, the present invention to create strain-relaxed templates allows us to have more control over the growth of lattice- mismatched films and therefore allows us access wider range of compositions for III- nitride devices.

[0042] There are several existing methods of creating strain-relaxed templates or to alleviate growth stress when growing lattice-mismatched epitaxial layers on GaN substrates. For AlGaN growth on GaN, these include facet-controlled epitaxial lateral overgrowth [4] to exceed the critical thickness limit. To obtain thick, relaxed InGaN layers on GaN, some approaches use a nano-porous compliant GaN template [5] or SOITECH™ Smart Cut™ technology [6], These methods either involve complex processing techniques or can only achieve limited strain relaxation effects. A more recent approach uses decomposed InGaN layers [7] during the material growth to produce strain-relaxed templates, but such methods are prone to defect formation.

[0043] Nonetheless, there is a need in the art for improved methods of creating strain- relaxed Ill-nitride templates for device fabrication. The present invention satisfies this need.

[0044] SUMMARY OF THE INVENTION

[0045] The present invention discloses a method to create strain-relaxed Ill-nitride templates for device fabrication. The method comprises depositing sacrificial layers below or under epitaxially-grown lattice-mismatched Ill-nitride layers, exposing the sacrificial layers, performing an electrochemical etch of the exposed sacrificial layers so that the Ill-nitride layers become at least partially-detached from a growth substrate, thereby creating strain-relaxed Ill-nitride templates from the partially- detached Ill-nitride layers for subsequent device growth and fabrication. The present invention is superior to the prior art because it can achieve maximum biaxial or uniaxial lattice strain relaxation while maintaining crystal quality and is not constrained by device composition, device types or device sizes. The present invention also allows for further device fabrication with Ill-nitride layers beyond a critical thickness limit.

[0046] BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Referring now to the drawings in which like reference numbers represent corresponding parts throughout:

[0048] Fig. l is a process flowchart of fabricating a partially-detached Ill-nitride template for device fabrication using the present invention.

[0049] Figs. 2(a), 2(b) and 2(c) are schematics of fabricating a partially-detached III- nitride template for device fabrication using the present invention.

[0050] Figs. 3(a), 3(b), 3(c) and 3(d) are schematics of exemplary pattern designs to expose the sacrificial layer for electrochemical etching in a lateral electrochemical etching direction, wherein different pattern designs may affect different uniaxial or biaxial strain relaxation.

[0051] Fig. 4 is a schematic of an electrochemical etching apparatus.

[0052] Fig. 5 is a schematic of a light emitting diode (LED) structure fabricated on a partially-detached Ill-nitride template using the present invention.

[0053] Fig. 6 is a schematic of a laser diode structure (LD) fabricated on a partially- detached Ill-nitride template using the present invention.

[0054] Fig. 7 is a schematic of a vertical cavity surface emitting laser (VCSEL) structure fabricated on a partially-detached Ill-nitride template using the present invention.

[0055] Fig. 8 is a schematic of a power electronics structure fabricated on a partially- detached Ill-nitride template using the present invention.

[0056] Fig. 9 is a schematic of three strain-relaxed devices fabricated on the same substrate with 1stand 2ndsacrificial layers and Ill-nitride template layers. Figs. 10(a) and 10(b) are optical microscopy images of AlGaN layers after a trench etch as shown in Fig. 10(a), and after being partially-detached from the substrate as shown in Fig. 10(b); and Figs. 10(c) and 10(d) are reciprocal space mappings (RSMs) of a (105) reflection of AlGaN layers strained to thick GaN layers after the trench etch as shown in Fig. 10(c), and the AlGaN layers fully relaxed after being detached and lifted off from the substrate as shown in Fig. 10(d).

[0057] Fig. 11 is an atomic force microscopy (AFM) image of the lift-off surface using the present invention.

[0058] DETAILED DESCRIPTION OF THE INVENTION

[0059] In the following description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized, and structural changes may be made without departing from the scope of the present invention.

[0060] Overview

[0061] A process flow diagram is shown in Fig. 1, in which the creating a strain- relaxed Ill-nitride template for Ill-nitride device fabrication comprises the steps of: depositing a sacrificial layer on a substrate (101), epitaxially growing lattice- mismatched Ill-nitride layers above the sacrificial layer (102), electrochemical etching of the sacrificial layer (103), partially detaching the Ill-nitride layers to relieve growth strain (104), thereby creating strain-relaxed Ill-nitride templates from the partially-detached Ill-nitride layers for device growth and fabrication (105). The following disclosure demonstrates the flexibility of using partially-detached, strain relaxed Ill-nitride templates for device fabrication. Material deposition of the sacrificial layer and Ill-nitride layers

[0062] Schematics of fabricating a partially-detached Ill-nitride template for device fabrication using the present invention are shown in Figs. 2(a), 2(b) and 2(c), wherein the epitaxial structure comprises a growth substrate 201, buffer layer 202, sacrificial layer 203, Ill-nitride layers 204 and strain-relaxed device structure 205.

[0063] The sacrificial layer 203 can be deposited on the substrate 201 by metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or other Ill-nitride thin film deposition techniques. It is critical that the sacrificial layer 203 has an n-type carrier concentration high enough to be selectively etched during the electrochemical etching. More precisely, the sacrificial layer 203 can comprise a single layer or multiple layers, wherein the electron concentration should be between l * 1019cm’3and l >< 1021cnr3, and preferably above I M O20cm’3. The high carrier concentration can be from bulk n-type doping, such as Si, Ge, other n-type dopants, or from polarization charges from a Ill-nitride heterostructure interface, or any combination of the above. The electron concentration can also be achieved by, but not limited to, various ion implantation techniques, such as common plasma immersion, focused ion beam, molecular beam assisted, and high-energy ion implantation. The sacrificial layer 203 should be thick enough for its complete relaxation after detachment, but thin enough to keep the surface from degrading from the high doping.

[0064] Ill-nitride layers 204 are deposited on or above the sacrificial layer 203. The Ill-nitride layers 204 comprise GaN, InN, AIN or any alloy of the above. The III- nitride layers 204 can be lattice matched to the substrate 201 or the buffer layer 202, or they can contain at least one layer that is lattice-mismatched to the substrate 201 or the buffer layer 202. The Ill-nitride layers 204 can be unintentionally doped (UID) and doped. However, to keep the Ill-nitride layers 204 from being damaged during the electrochemical etching, the highest electron concentration must be one order of magnitude lower than the average carrier concentration in the sacrificial layer 203. The thickness of the Ill-nitride layers 204 is kept under 1 micron, and preferably below 0.5 microns, or the critical thickness limit as described above to maintain the crystal quality of the film for lattice mismatched layers, whichever is thinner. The III- nitride layers 204 are kept thin enough so that the lattice-mismatched Ill-nitride layers 204 are strained to the substrate 201 or the buffer layer 202 prior to the electrochemical etch.

[0065] Exposing and electrochemical etching the sacrificial layer

[0066] Figs. 3(a), 3(b), 3(c) and 3(d) show a few designs to expose and electrochemically etch the sacrificial layer to relieve the in-plane stress. The arrows show the lateral etching direction from circles 301 in Fig. 3(a), trenches 302 in Fig. 3(b), patterns 303 but not connected regions 304 in Fig. 3(c), and patterns 305 but not connected regions 306 in Fig. 3(d). For a partially-detached template, the etching process is controlled so that the Ill-nitride template layers remain attached after the etching through connected regions 304 in Fig. 3(c) and connected regions 306 in Fig. 3(d).

[0067] Different designs may affect the uniaxial or biaxial relaxation. For example, it is expected, for the design of Fig. 3(b), the strain relaxation mainly occurs uniaxially in the direction perpendicular to the trenches 302, while for the designs of Figs. 3(c) and 3(d), the strain relaxation can happen biaxially. The partially-detached layers allow for the growth of device layers with minimal strain. It is to be understood that the designs shown here are not a complete list and other embodiments can be utilized without departing from the scope of the present invention.

[0068] Following the material deposition, the sacrificial layer can be exposed by photolithography and etched away using electrochemical etching to detach the template layers to relieve the in-plane lattice stress. The electrochemical etching of the sacrificial layer is conducted by connecting a specimen 401 with the sacrificial layer to a positive terminal of an electrical DC power supply source 402 and connecting a negative electrode 403 comprised of platinum (Pt) immersed in the electrolyte 404 to form a circuit, as shown in Fig. 4. The electrolyte 404 contains at least some nitric acid, oxalic acid or other acid solutions. The typical DC applied voltage can range from 3 V to 30V for a carrier concentration of IO20cm’3in the sacrificial layer.

[0069] Device fabrication on the partially-detached template layers

[0070] After partial detachment of the Ill-nitride template layers, the device structures are grown on the Ill-nitride template layers. The device structures can include LEDs, LDs, VCSELs, resonant cavity light-emitting diodes (RCLEDs), and other device structures. The relaxed Ill-nitride template layers significantly improve the performance of these devices by minimizing the growth stress from lattice mismatch and allowing for the growth of thicker layers that exceed the critical thickness limits. After the growth of the device layers, the device layers and the partially-detached III- nitride template layers can be transferred to a carrier wafer by wafer bonding or by applying an adhesive layer, either before or after the device fabrication steps. The transfer process is described in more detail in the related patent applications cross- referenced above.

[0071] Embodiment 1 - LED fabrication on partially-detached Ill-nitride templates Further embodiments include the use of the present invention for Ill-nitride LED applications. Fig. 5 shows a schematic of a Ill-nitride LED comprised of a growth substrate 501, buffer layer 502, sacrificial layer 503, partially-detached III- nitride layers 504, and strain-relaxed LED structure 505, wherein the strain-relaxed LED structure 505 comprises a light-emitting active region, n-type current spreading layers, p-type layers, etc., grown on the Ill-nitride layers 504 that have been partially- detached by electro-chemical etching. Depending on the device design, the partially- detached Ill-nitride layers 504 may comprise InGaN or AlGaN layers that are biaxially relaxed by more than 20% regardless of the type of substrate 501 underneath. The partially-detached Ill-nitride layers 504 provide improved radiative recombination efficiency due to reduced strain and better epitaxial quality, as well as better light extraction efficiency

[0072] Embodiment 2 - Laser diode fabrication on partially-detached Ill-nitride layers

[0073] A Ill-nitride laser diode (LD) structure is fabricated on the partially-detached Ill-nitride layers as shown in Fig. 6. Fig. 6 shows a schematic of a Ill-nitride LD comprised of a growth substrate 601, buffer layer 602, sacrificial layer 603, partially- detached Ill-nitride layers 604, and strain-relaxed LD structure 605. The reduced strain allows for better optical confinement and improved laser performance.

[0074] Embodiment 3 - VCSEL fabrication on partially-detached Ill-nitride layers A Ill-nitride Vertical Cavity Surface Emitting Laser (VCSEL) structure is fabricated on the partially-detached Ill-nitride layers as shown in Fig. 7. Fig. 7 shows a schematic of a VCSEL comprised of a growth substrate 701, buffer layer 702, sacrificial layer 703, partially-detached Ill-nitride layers 704, and strain-relaxed VCSEL structure 705. The partially-detached Ill-nitride layers 704 allow for better cavity design and improved device efficiency, overcoming limitations associated with conventional strained layers.

[0075] Embodiment 4 - Power electronic fabrication on partially-detached Ill-nitride layers

[0076] A Ill-nitride power electronic device, such as an AlGaN / GaN high electron mobility transistor (HEMT), is fabricated on the partially-detached Ill-nitride layers as shown in Fig. 8. Fig. 8 shows a schematic of an AlGaN / GaN HEMT comprised of a growth substrate 801, buffer layer 802, sacrificial layer 803, partially-detached III- nitride layers 804, and strain-relaxed HEMT structure 805. The partially-detached III- nitride layers 804 allows for more degree of freedom of device design, overcoming the critical thickness limitation of growing AlGaN layers on GaN. Embodiment 5 - Different color emission devices on partially-detached III- nitride template layers with different strain relaxation

[0077] Different color emission devices can be grown on the partially-detached III- nitride layers with a plurality of different in-plane lattice constants or strain relaxations as shown in Fig. 9. Fig. 9 shows a schematic of a three devices fabricated on a growth substrate 901 and buffer layer 902, wherein the epitaxial structure includes 1stand 2ndsacrificial layers 905, 903, as well as 1stand 2ndIll-nitride template layers 906, 904, upon which the three devices 907 are fabricated.

[0078] In the case of growing red, green, blue emission devices 907 on the Ill-nitride template layers 906, 904, the red emission device (Device 1 907) has the largest inplane lattice constant or strain relaxation; the green emission device (Device 2 907) has the medium in-plane lattice constant or strain relaxation; and the blue emission device (Device 3 907) has the smallest in-plane lattice constant or strain relaxation. The different in-plane uniaxial and biaxial lattice constants or strain relaxations can be controlled by changing the thickness of the Ill-nitride template layers 906, 904. The thickness of the Ill-nitride template layers 906, 904 can be controlled by depositing multiple sacrificial layers 905, 903 and etching different depths of trenches to access different thickness.

[0079] As illustrated in Fig. 9, longer wavelength emission devices 907 (Device 1 907) can be grown on thinner Ill-nitride template layers 906, 904 to achieve higher strain relaxation, while shorter wavelength devices 907 (Device 2 907 and Device 3 907) benefit from thicker Ill-nitride template layers 906, 904 for lower strain relaxation. Alternatively, the in-plane lattice constant and strain relaxation can be controlled by adjusting the trench designs. By varying either the trench design or the thickness of the Ill-nitride template layers 906, 904, strain relaxation can be tailored for each device 907 individually, allowing for precise, independent control. This innovation enables the growth of Ill-nitride-based devices 907 with different in-plane lattice constants or strain relaxation on a single wafer. Since strain relaxation influences indium incorporation during growth, devices 907 with varying emission wavelengths can be produced simultaneously on a single wafer.

[0080] Process steps

[0081] Example 1

[0082] In Example 1, an instance is described in which a fully relaxed AlGaN layer template with 8% average Al composition was fabricated. During the material growth, a 50-nm n-type GaN layer (“sacrificial layer”) with Si doping concentration above IO20cm’3was grown below a 600-nm thick AlGaN layer with 8% average Al composition. The AlGaN layers were all strained to the thick GaN layers underneath on the sapphire substrate. After the growth, a photolithography was performed followed by a dry etch using BCI3 / CI2 by reactive ion etching (RIE) to etch trenches to expose the sacrificial layer. The dry etch depth is greater than the depth of the sacrificial layer and the Ill-nitride device layers (> 650 nm), so that the entire sacrificial layer can be accessed through sidewalls in subsequent electrochemical etching. An optional passivation layer (such as SiCh or AI2O3) can be deposited prior to the photolithography step in case the IIII-nitride device layers need to be protected from the electrochemical etching.

[0083] Next, the sample was submerged in the nitric acid solution for electrochemical etching. The positive terminal of a DC power supply was connected to an indium (In) contact soldered on the wafer and the negative electrode was connected to a platinum (Pt) wire immersed in the nitric acid solution, thereby forming a circuit. By applying a voltage of 10V or above, the sacrificial layer was etched away. The lateral etching rate is at least 10 micrometers per minute. The AlGaN layers were detached from the growth substrate after electrochemical etching and were still connected to each other by small joint area. This is to keep the partially-detached AlGaN layers from being lifted off from the substrate spontaneously. The fully relaxed template on the partially-detached AlGaN layer was created and can be used for device fabrication. Experimental results

[0084] Optical microscopy images and reciprocal space mappings (RSMs) of an AlGaN / GaN (105) peak reflection using the process described above are shown in Figs. 10(a), 10(b), 10(c) and 10(d). Fig. 10(a) shows the microscopy image of AlGaN- based LEDs grown on a reference GaN buffer layer and sapphire substrate without partial detachment and the device layers are still strained to the GaN buffer layer as shown in a reciprocal space mapping in Fig. 10(c). Fig. 10(b) shows partially- detached Al GaN layers after electrochemical etch and Fig. 10(d) shows a reciprocal space mapping of the same AlGaN-based LEDs on the partially-detached templates after being transferred from the growth substrate onto a carrier wafer. The transferred AlGaN-based LEDs are fully relaxed.

[0085] Fig. 11 is an AFM image of the lift-off surface using the present invention. A smooth surface allows the device for subsequent fabrication or wafer bonding.

[0086] Advantages and benefits

[0087] The addition of a partially-detached Ill-nitride template layers introduces several key advantages and benefits:

[0088] 1. Biaxial Relaxation: By relieving strain, the biaxially relaxed Ill-nitride template layers allow for the growth of thicker layers that exceed critical thickness, improving device performance. The present invention also allows for relaxation of both compressive and tensile stress.

[0089] 2. Enhanced Device Fabrication and Device Performance: The relaxed Ill-nitride template layers improve light extraction efficiency in optoelectronic devices and allows for more precise control in LD and VCSEL fabrication. The reduction of strain in devices can also decrease the unwanted piezoelectric field (such as Quantum Confined Stark Effect) in the polar Ill-nitride devices and improve the radiative recombination efficiency 3. Compatibility with Various Device Types: The relaxed Ill-nitride template layers can be used in a wide range of devices, including LEDs, LDs, power electronics, RF devices, or any device sizes.

[0090] 4. Controllable relaxation: The relaxation direction (uniaxial or biaxial) and strain relaxation ratio can be potentially controlled by changing the thickness of the Ill-nitride template layers or by adjusting the trench length, trench separation, shape, and sizes.

[0091] Alternatives and modifications

[0092] This invention includes a number of alternatives and modifications:

[0093] 1. A method for fabricating a device, comprising:

[0094] (a) epitaxially growing a Ill-nitride template including a sacrificial layer on or above a substrate, wherein the sacrificial layer has an electron carrier concentration of more than 1 x 1019cm’3;

[0095] (b) exposing a portion of the sacrificial layer to an electrolyte of an electrochemical etching apparatus;

[0096] (c) electro-chemical etching to at least partially etch away the sacrificial layer so that at least some part of the Ill-nitride template is at least partially-detached from the sacrificial layer;

[0097] (d) epitaxially growing a Ill-nitride device structure on or above the partially- detached Ill-nitride template wherein at least one layer of the Ill-nitride device structure has an in-plane lattice constant or strain that is at least 20% uniaxially or biaxially relaxed.

[0098] 2. The method of 1 above, wherein the partially-detached Ill-nitride template comprises GaN, InGaN, AlGaN, or AlInGaN.

[0099] 3. The method of 1-2 above, wherein a total thickness of the partially- detached Ill-nitride template is less than 1 micron, and preferably less than 0.5 microns, and the total thickness should not exceed a critical thickness when the III- nitride template is lattice mismatched to the substrate or a buffer layer on or above the substrate.

[0100] 4. The method of 1 above, wherein at least one layer of the Ill-nitride device structure has a different in-plane lattice constant from the substrate or a buffer layer on or above the substrate.

[0101] 5. The method of 4 above, wherein at least one layer of the Ill-nitride device structure comprises AlyGaxN in which 0.05<y<0.95 and y+x=l.

[0102] 6. The method of 4 above, wherein at least one layer of the Ill-nitride device structure comprises InyGaxN in which 0.05<y<0.95 and y+x=l.

[0103] 7. The method of 4 above, wherein at least one layer of the Ill-nitride device structure comprises AlxInyGazN in which 0.05<y<0.95 and y+x+z=l.

[0104] 8. The method of 5-7 above, wherein at least one layer of the Ill-nitride device structure exceeds a critical thickness on the buffer layer.

[0105] 9. The method of 1 above, wherein the sacrificial layer is an alloy composition of (Ga, Al, In, B)N of a Ill-nitride semiconductor material system comprising GanAlxInyBzN, where 0<n<l, 0<x<l, 0<y<l, 0<z< 1, and n+x+y+z=l.

[0106] 10. The method of 9 above, wherein the sacrificial layer comprises a single layer or multiple layers having at least two periods of alternating layers of AlxInyGai-x-yN and AUnbGai-a-bN, where 0<x<l, 0<y<l, and 0<a<l, 0<b<l, 0<b<l and y Ab.

[0107] 11. The method of 9-10 above, wherein the sacrificial layer comprises a single layer or multiple layers having at least one layer with an n-type carrier concentration ranging from IxlO19cm'3to lxl021cm'3, and preferably above IxlO20

[0108] -3 cm .

[0109] 12. The method of 9-10 above, wherein a thickness of the sacrificial layer is less than 100 nm, and preferably less than 50 nm.

[0110] 13. The method of 11 above, wherein the sacrificial layer is doped by Si, Ge, or other n-type dopants, with a dopant concentration ranging from IxlO19cm'3to lxl021cm'3, and preferably more than IxlO20cm'3. 14. The method of 11 above, wherein the sacrificial layer has an electron carrier concentration of more than IxlO19cm'3formed by polarization charges at a heterostructure interface thereof, such as a two-dimensional electron gas (2DEG).

[0111] 15. The method of 11 above, wherein the sacrificial layer has an electron carrier concentration of more than IxlO19cm'3formed by an ion implantation technique, such as a common plasma immersion, focused ion beam, molecular beam assisted, or high-energy ion implantation.

[0112] 16. The method of 1 above, wherein a trench is formed to expose the sacrificial layer to the electrolyte from a top surface after epitaxial growth, and the electro-chemical etching of the sacrificial layer is performed through the trench.

[0113] 17. The method of 16 above, wherein the trench does not fully enclose the partially-detached Ill-nitride layers, so that the partially-detached Ill-nitride layers at least connect to an area outside the trench after etching.

[0114] 18. The method of 1 above, wherein the electro-chemical etching of the sacrificial layer is conducted by: connecting a sample including the Ill-nitride template to a positive terminal of an electrical DC power supply source; connecting a negative electrode immersed in the electrolyte to form a circuit; and applying a DC voltage ranging from 3 volts to 30 volts of the electrical DC power supply source.

[0115] 19. The method of 18 above, wherein the electrolyte contains at least nitric acid, oxalic acid, or another acid solution.

[0116] 20. The method of 1 above, wherein the Ill-nitride device structure comprises a Light-Emitting Diode (LED) structure.

[0117] 21. The method of 1 above, wherein the Ill-nitride device structure comprises a Laser Diode (LD) structure.

[0118] 22. The method of 1 above, wherein the Ill-nitride device structure comprises a Resonant Cavity Light-Emitting Diode (RCLED) structure. 23. The method of 1 above, wherein the Ill-nitride device structure comprises a Vertical Cavity Surface-Emitting Laser (VCSEL) structure.

[0119] 24. The method of 1 above, wherein the Ill-nitride device structure comprises a power device, radio frequency (RF) device, or other electronic device.

[0120] 25. The method of 1 above, wherein the Ill-nitride device structure has a different uniaxial or biaxial relaxation of in-plane lattice constant or strain.

[0121] 26. The method of 25 above, wherein the Ill-nitride device structure has a plurality of different uniaxial or biaxial relaxations of in-plane lattice constant or strain.

[0122] 27. The method of 26 above, wherein a red color emission wavelength device has a largest uniaxial or biaxial relaxation of in-plane lattice constant or strain, a green color emission device has a medium uniaxial or biaxial relaxation of in-plane lattice constant or strain, and a blue color emission device has a smallest uniaxial or biaxial relaxation of in-plane lattice constant or strain.

[0123] 28. The method of 25-27 above, wherein the uniaxial or biaxial relaxation of in-plane lattice constant or strain of the Ill-nitride device structures is controlled by changing a thickness of the partially-detached Ill-nitride template.

[0124] 29. The method of 28 above, wherein the thickness ranges from 0.05 microns to 400 microns.

[0125] 30. The method of 29 above, wherein the thickness is changed by depositing a plurality of the sacrificial layers and then etching trenches to access different ones of the plurality of the sacrificial layers.

[0126] 31. The method of 25-27 above, wherein the uniaxial and biaxial relaxation of in-plane lattice constant or strain of the Ill-nitride device structure is controlled by changing shapes, sizes, and pitches of the trench patterns.

[0127] References

[0128] The following publications are incorporated by reference herein: 1. Reed, M. J., El-Masry, N. A., Parker, C. A., Roberts, J. C., & Bedair, S. M. (2000). Critical layer thickness determination of GaN / InGaN / GaN double heterostructures. Applied Physics Letters, 77(25), 4121-4123.

[0129] 2. Holec, D., Zhang, Y, Rao, D. V, Kappers, M. J., McAleese, C., & Humphreys, C. J. (2008). Equilibrium critical thickness for misfit dislocations in III- nitrides. Journal of Applied Physics, 104(12).

[0130] 3. Kawaguchi Y, Shimizu M, Hiramatsu K, Sawaki N. The Composition Pulling Effect in InGaN Growth on the GaN and AlGaN Epitaxial Layers Grown by MOVPE. MRS Proceedings. 1996; 449:89. doi: 10.1557 / PROC-449-89

[0131] 4. H. Yoshida, Y. Yamashita, M. Kuwabara and H. Kan, "A 342-nm ultraviolet AlGaN multiple-quantum-well laser diode," Nature Photonics, vol. 2, pp. 551-554, 2008.

[0132] 5. Pasayat, S. S., Gupta, C., Acker-James, D., Cohen, D. A., DenBaars, S. P, Nakamura, S., ... & Mishra, U. K. (2019). Fabrication of relaxed InGaN pseudosubstrates composed of micron-sized pattern arrays with high fill factors using porous GaN. Semiconductor Science and Technology, 34(11), 115020.

[0133] 6. Dussaigne, A., Barbier, F., Haas, H., Pillet, J. C., Samuel, B., Veux, G., & Le Maitre, P. (2023, March). Native InGaN red-green-blue micro-LEDs for full color micro-displays. In Light-Emitting Devices, Materials, and Applications XXVII (Vol. 12441, pp. 40-48). SPIE.

[0134] 7. Chan, P, DenBaars, S. P., & Nakamura, S. (2021). Growth of highly relaxed InGaN pseudo-substrates over full 2-in. wafers. Applied Physics Letters, 119(13).

[0135] Conclusion

[0136] This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.

Claims

WHAT IS CLAIMED IS:

1. A method for fabricating a device, comprising:(a) epitaxially growing a Ill-nitride template including a sacrificial layer on or above a substrate, wherein the sacrificial layer has an electron carrier concentration of more than 1 x 1019cm’3;(b) exposing at least a portion of the sacrificial layer to an electrolyte of an electro-chemical etching apparatus;(c) electro-chemical etching to at least partially etch away the sacrificial layer so that at least some part of the Ill-nitride template is at least partially-detached from the sacrificial layer;(d) epitaxially growing a Ill-nitride device structure on or above the partially- detached Ill-nitride template wherein at least one layer of the Ill-nitride device structure has an in-plane lattice constant or strain that is at least 20% uniaxially or biaxially relaxed.

2. The method of claim 1, wherein the partially-detached Ill-nitride template comprises GaN, InGaN, AlGaN, or AlInGaN.

3. The method of claim 1, wherein a total thickness of the partially- detached Ill-nitride template is less than 1 micron, and the total thickness does not exceed a critical thickness when the Ill-nitride template is lattice mismatched to the substrate or a buffer layer on or above the substrate.

4. The method of claim 1, wherein at least one layer of the Ill-nitride device structure has a different in-plane lattice constant from the substrate or a buffer layer on or above the substrate.

5. The method of claim 4, wherein at least one layer of the Ill-nitride device structure exceeds a critical thickness on the buffer layer.

6. The method of claim 1, wherein at least one layer of the Ill-nitride device structure comprises AlxInyGazN in which 0.05<y<0.95 and x+y+z=l.

7. The method of claim 1, wherein the sacrificial layer is an alloy composition of (Ga, Al, In, B)N of a Ill-nitride semiconductor material system comprising GanAlxInyBzN, where 0<n<l, 0<x<l, 0<y<l, 0<z< 1, and n+x+y+z=l.

8. The method of claim 7, wherein the sacrificial layer comprises a single layer or multiple layers having at least two periods of alternating layers of AlxInyGai-x-yN and AlalmGai-a-bN, where 0<x<l, 0<y<l, and 0<a<l, 0<b<l, and y Ab.

9. The method of claims 7, wherein the sacrificial layer comprises a single layer or multiple layers having at least one layer with an n-type carrier concentration ranging from IxlO19cm'3to lxl021cm'3.

10. The method of claim 9, wherein the sacrificial layer is doped by Si, Ge, or other n-type dopants or11. The method of claim 9, wherein the sacrificial layer has an electron carrier concentration of more than IxlO19cm'3formed by polarization charges at a heterostructure interface thereof, such as a two-dimensional electron gas (2DEG) or by an ion implantation technique, such as a common plasma immersion, focused ion beam, molecular beam assisted, or high-energy ion implantation.

12. The method of claim 1, wherein a thickness of the sacrificial layer is less than 100 nm.

13. The method of claim 1, wherein a trench is formed to expose the sacrificial layer to the electrolyte from a top surface after epitaxial growth, and the electro-chemical etching of the sacrificial layer is performed through the trench.

14. The method of claim 13, wherein the trench does not fully enclose the partially-detached Ill-nitride layers, so that the partially-detached Ill-nitride layers at least connect to an area outside the trench after etching.

15. The method of claims 13, wherein the Ill-nitride device structure has a uniaxial or biaxial relaxation of in-plane lattice constant or strain that is controlled by changing shapes, sizes, and pitches of the trench patterns.

16. The method of claim 1, wherein the Ill-nitride device structure has a uniaxial or biaxial relaxation of in-plane lattice constant or strain that is different from the substrate.

17. The method of claim 16, wherein the Ill-nitride device structure has a plurality of different uniaxial or biaxial relaxations of in-plane lattice constant or strain.

18. The method of claim 16, wherein a red color emission wavelength device has a largest uniaxial or biaxial relaxation of in-plane lattice constant or strain, a green color emission device has a medium uniaxial or biaxial relaxation of in-plane lattice constant or strain, and a blue color emission device has a smallest uniaxial or biaxial relaxation of in-plane lattice constant or strain.

19. The method of claims 16, wherein the uniaxial or biaxial relaxation of in-plane lattice constant or strain of the Ill-nitride device structures is controlled bychanging a thickness of the partially-detached Ill-nitride template, and the thickness ranges from 0.05 microns to 400 microns.

20. The method of claim 19, wherein the thickness is changed by depositing a plurality of the sacrificial layers and then etching trenches to access different ones of the plurality of the sacrificial layers.

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