Power device driving method and circuit

Abstract

The present invention relates to a power device driving method and circuit, which control the output of a multi-channel driving circuit by adjusting an inputted driving signal. The driving signal comprises a main driving signal and at least one enable signal, the main driving signal is formed into a main output signal by the multi-channel driving circuit, the multi-channel driving circuit is activated or disabled on the basis of the received enable signal so as to determine whether to output auxiliary output signals, and a driving voltage signal for driving a power device is formed on the basis of the main output signal or the auxiliary output signals. In the present application, the driving rate can be quickly adjusted, so that the response speed is fast, and the stability is high; additionally, the turn-on rate or the turn-off rate can be separately adjusted by means of different inputs of enable signals, so that the adjustment adaptability is strong.

Description

Power device driving methods and circuits Technical Field

[0001] This invention relates to the field of safety circuit technology, specifically to a power device driving method and circuit. Background Technology

[0002] In driving and controlling power devices, the drive circuit is a key component connecting the control circuit and the power device. It amplifies the control signal to drive the power device to achieve the corresponding function. However, in some operating scenarios, the voltage stress of the power device may reach its maximum withstand capacity. Traditional fixed drive circuit solutions are simple to implement and do not require additional adjustment mechanisms, making it difficult to balance reducing voltage stress with reducing losses in the power transistor and drive circuit. Furthermore, to ensure the reliability of the equipment, a large safety margin may be required for the power device and drive circuit, which undoubtedly increases the overall cost of the power converter. Therefore, in operating conditions where the voltage stress of the power device may reach its maximum withstand capacity, the drive circuit should be able to reduce its own drive rate to suppress the voltage rise of the power device too quickly, thus keeping the voltage stress of the power device below the limit; in operating conditions where the voltage stress of the power device is significantly lower than its maximum withstand capacity, the drive circuit should be able to increase its own drive rate to reduce the voltage-current overlap time within the power device and the voltage-current overlap time in the drive circuit, thereby reducing losses in the power device and drive circuit.

[0003] Currently, there are several main solutions to this problem:

[0004] One approach is to adjust the driving impedance network.

[0005] Advantages: It allows direct adjustment of the driving impedance network.

[0006] Limitations: To directly adjust the drive impedance network, a significant amount of additional circuitry is required, including but not limited to amplifier and isolation circuits. This results in wasted board space and a substantial increase in cost.

[0007] Second, the driving voltage adjustment scheme.

[0008] Advantage: The drive circuits for all power transistors can be adjusted uniformly.

[0009] Limitations: The driving voltage is usually filtered by a large-capacity capacitor, resulting in a slow voltage change rate and difficulty in quickly responding to the adjustment requirements of the driving rate.

[0010] Third, multiple driving voltage schemes are added.

[0011] Advantages: It can provide more flexible drive speed adjustment capabilities.

[0012] Limitations: Introducing multiple drive voltage branches may result in some branches being idle, which not only increases the cost of the power converter but also reduces its power density.

[0013] Fourth, adjust the number of drive circuits.

[0014] Advantages: Stable and reliable.

[0015] Limitations: Drive circuits typically need to output a definite level. When multiple drive circuits are connected in parallel, if they output different drive levels, it may cause instability in the gate voltage of the power transistor, thereby affecting the operating state of the system.

[0016] In summary, directly adjusting the drive impedance network requires more additional circuitry, leading to increased costs and wasted space; uniformly adjusting the drive voltage makes it difficult to respond quickly to changes in drive rate because the large-capacity capacitor filtering results in a slow voltage change rate; adjusting the number of drive circuits is limited by the fixed output level of the drive circuits, leading to system instability.

[0017] Therefore, the technical problem addressed by this application is how to achieve adjustable drive speed while ensuring stable system operation and controlling costs. Summary of the Invention

[0018] A primary objective of this invention is to overcome at least one of the aforementioned deficiencies by providing a power device driving method and circuit that possesses high flexibility and adaptability, fast response speed, high stability, and safer operation.

[0019] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0020] This invention provides a power device driving method, wherein the output of a multi-channel driving circuit is controlled by adjusting an input driving signal. The driving signal includes a main driving signal and at least one enable signal. The main driving signal is converted into a main output signal by the multi-channel driving circuit. The multi-channel driving circuit determines whether to output an auxiliary output signal based on the activation or deactivation of the received enable signal. A driving voltage signal for driving the power device is formed based on the main output signal or the auxiliary output signal.

[0021] According to one embodiment of the present invention, the auxiliary output signal follows the driving signal, and the waveform of the auxiliary output signal is substantially the same as the waveform of the main output signal.

[0022] According to one embodiment of the present invention, the main drive signal is divided into multiple inputs. One input is processed and amplified to form the main output signal. The other inputs are processed and amplified together with each enable signal. When the enable signal is activated, the auxiliary output signal is output. The auxiliary output signal and the main output signal are superimposed to form the drive voltage signal.

[0023] According to one embodiment of the present invention, the main drive signal is divided into multiple inputs. One input is processed and amplified to form a main output signal. The main output signal is sent to a first drive impedance network in the multi-channel drive circuit to control the operation of the first drive impedance network. The remaining inputs are processed and amplified together with each enable signal. When the enable signal is activated, the auxiliary output signal is output. Each auxiliary output signal is sent to a second drive impedance network in the multi-channel drive circuit. Each auxiliary output signal controls a second drive impedance network to work together with the first drive impedance network to control and adjust the drive voltage signal driving the power device.

[0024] According to one embodiment of the present invention, the multi-channel drive circuit includes at least one second drive impedance network, wherein the current flow direction of at least one of the at least one drive impedance network is unidirectional, and the conduction direction is either from the output terminal of the drive impedance network to the input terminal or from the input terminal of the drive impedance network to the output terminal.

[0025] According to one embodiment of the present invention, when the enable signal is disabled, the input terminal of each enable signal is in a high impedance state with the output terminal of the drive voltage of the multiplexer circuit.

[0026] According to one embodiment of the present invention, it includes at least one first auxiliary output signal for power device turn-on rate control and at least one second auxiliary output signal for power device turn-off rate control, and the output of the first auxiliary output signal or the second auxiliary output signal is determined according to the selection input of each enable signal.

[0027] According to one embodiment of the present invention, at least two of the enable signals are combined, and the combined enable signals are used for enable control.

[0028] In particular, the present invention also provides a power device driving circuit, which includes a multi-channel driving circuit, wherein the input terminal of the multi-channel driving circuit is used to receive driving signals, and the multi-channel driving circuit has at least two output terminals.

[0029] The multi-channel drive circuit includes a main drive circuit and at least one auxiliary drive circuit. The drive signal includes a main drive signal and at least one enable signal. The main drive signal is divided into at least two paths and is respectively input to the main drive circuit and each auxiliary drive circuit. The main drive signal is converted into a main output signal by the main drive circuit. Each enable signal is input to each auxiliary drive circuit. Each auxiliary drive circuit is activated or disabled according to the received enable signal to enable or disable the auxiliary drive circuit. When the enable signal is activated, the auxiliary drive circuit is enabled and forms an auxiliary output signal.

[0030] A drive voltage signal for driving power devices is formed based on the main output signal or the auxiliary output signal.

[0031] According to one embodiment of the present invention, the main driving circuit includes a main driving logic circuit and a main driving amplifier circuit, and the main driving signal is processed and amplified by the main driving logic circuit and the main driving amplifier circuit to form a main output signal;

[0032] Optionally, the main driving circuit further includes an isolation circuit, which is located between the main driving logic circuit and the main driving amplifier circuit, or inside the main driving logic circuit, or in front of the main driving logic circuit.

[0033] According to one embodiment of the present invention, the auxiliary driving circuit includes an auxiliary driving logic circuit and an auxiliary driving amplifier circuit. The main driving signal and the enable signal are connected to the input terminal of the auxiliary driving logic circuit. The output terminal of the auxiliary driving logic circuit is connected to the auxiliary driving amplifier circuit. The output terminal of the auxiliary driving amplifier circuit outputs the auxiliary output signal when the enable signal is activated.

[0034] Optionally, the auxiliary driving circuit further includes an isolation circuit, which is located between the auxiliary driving logic circuit and the auxiliary driving amplifier circuit, or inside the auxiliary driving logic circuit, or in front of the auxiliary driving logic circuit.

[0035] According to one embodiment of the present invention, the auxiliary driving logic circuit includes a logic gate device or a tri-state buffer device, the enable signal and the main driving signal are connected to the input terminal of the logic gate device or the tri-state buffer device, and the auxiliary output signal is output from the output terminal of the logic gate device or the tri-state buffer device when the enable signal is activated.

[0036] The auxiliary output signal follows the driving signal, and the waveform of the auxiliary output signal is basically the same as the waveform of the main output signal.

[0037] According to one embodiment of the present invention, the main driving circuit includes a first driving impedance network, each of the auxiliary driving circuits includes a second driving impedance network, the main output signal is sent to the first driving impedance network to control the operation of the first driving impedance network, each of the auxiliary output signals is sent to each of the second driving impedance networks, and each of the auxiliary output signals controls a second driving impedance network to work together with the first driving impedance network to control and adjust the driving voltage signal driving the power device.

[0038] According to one embodiment of the present invention, the main drive circuit includes a first upper drive switch, a first lower drive switch, and a first drive impedance network.

[0039] In this circuit, the first end of the circuit after the first upper drive switch and the first lower drive switch are connected in series is connected to the power supply VCC terminal, and the second end is grounded.

[0040] The first end of the first driving impedance network is connected to the midpoint between the first upper driving switch and the first lower driving switch, and the second end is connected to the control electrode of the power device.

[0041] The main output signal is divided into two paths, which are respectively connected to the first upper drive switch and the first lower drive switch to control the on / off state of both.

[0042] Optionally, a voltage regulator unit is connected in parallel across the circuit formed by the first upper drive switch and the first lower drive switch connected in series.

[0043] According to one embodiment of the present invention, the auxiliary drive circuit includes a second upper drive switch and a second drive impedance network. The first end of the second upper drive switch is connected to the power supply VCC terminal, and the second end is connected to the first end of the second drive impedance network. The second end of the second drive impedance network is connected to the second end of the first drive impedance network and then connected to the control electrode of the power device. The auxiliary output signal is connected to the second upper drive switch and controls its on / off state.

[0044] According to one embodiment of the present invention, a unidirectional conduction device is provided in the second driving impedance network, and the unidirectional conduction direction of the current is from the first end of the second driving impedance to the second end.

[0045] According to one embodiment of the present invention, the auxiliary drive circuit includes a second lower drive switch, the first terminal of the second lower drive switch is grounded, the second terminal of the second lower drive switch is connected to the second terminal of the second upper drive switch, and the auxiliary output signal is divided into two paths and respectively connected to the second upper drive switch and the second lower drive switch to control the on / off state of both.

[0046] The first terminal of the second upper drive switch is connected to a high-level signal, and the second terminal is connected to the first terminal of the second drive impedance. The second terminal of the second drive impedance is connected to the second terminal of the first drive impedance and then connected to the control electrode of the power device. The auxiliary output signal is connected to the second upper drive switch and controls its on / off state.

[0047] According to one embodiment of the present invention, a unidirectional conduction device is provided in the second driving impedance network, and the unidirectional conduction direction of the current is from the second end of the second driving impedance to the first end.

[0048] Compared with the prior art, the advantages and beneficial effects of the power device driving method and circuit of this invention patent application are as follows:

[0049] This application enables the formation of auxiliary output signals that follow the main drive signal by introducing enable signals. The activation or disabling of each enable signal controls the output of each auxiliary output signal. The output auxiliary signals are then combined with the main output signal to control the drive impedance of the power device, ultimately adjusting the drive rate of the power device. This application offers rapid drive rate adjustment, fast response, high stability, and allows for individual adjustment of the turn-on or turn-off rate through different enable signal inputs, providing strong adaptability.

[0050] Furthermore, the power device driving method and circuit of this application can be implemented by independent components, integrated circuits, or a combination of both, which can meet different design requirements and application scenarios, and can be adapted to different implementation methods according to different application scenarios, thereby further reducing configuration costs.

[0051] In addition, the power device driving method and circuit of this application can introduce a high impedance state or an equivalent high impedance state at the output terminal of the auxiliary output signal when the enable signal is disabled, thereby eliminating the control effect of the auxiliary driving circuit on the power device. Attached Figure Description

[0052] The following sections will describe some specific embodiments of the invention in a detailed manner by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0053] Figure 1 is a schematic diagram of the overall framework of a power device driving circuit according to an embodiment of the present invention;

[0054] Figure 2 is a schematic diagram of the logical relationship between the input and output ports of the multi-channel drive circuit in a power device drive circuit according to an embodiment of the present invention;

[0055] Figure 3 is a schematic diagram of the framework structure of a non-isolated multiplex drive circuit in a power device drive circuit according to an embodiment of this application;

[0056] Figure 4a is a schematic diagram of a frame structure of an isolated multiplex drive circuit in a power device drive circuit according to an embodiment of the present application;

[0057] Figure 4b is a schematic diagram of a second frame structure of an isolated multiplex drive circuit in a power device drive circuit according to an embodiment of this application;

[0058] Figure 4c is a schematic diagram of a third frame structure of an isolated multiplex drive circuit in a power device drive circuit according to an embodiment of this application.

[0059] Figure 5a is a schematic diagram of a power supply structure for a multi-channel drive circuit in a power device drive circuit according to an embodiment of this application;

[0060] Figure 5b is a schematic diagram of a second power supply structure for a multi-channel drive circuit in a power device drive circuit according to an embodiment of this application;

[0061] Figure 5c is a schematic diagram of a third power supply structure of a multi-channel drive circuit in a power device drive circuit according to an embodiment of this application.

[0062] Figure 6 is a schematic diagram of the power device driving circuit according to Embodiment 3 of this application;

[0063] Figure 7 is a schematic diagram of the power device driving circuit according to Embodiment 4 of this application;

[0064] Figure 8 is a schematic diagram of the power device driving circuit according to Embodiment 5 of this application;

[0065] Figure 9a is a schematic diagram of a power device drive circuit according to Embodiment 6 of this application, wherein only the control of the turn-on drive rate is implemented;

[0066] Figure 9b is a schematic diagram of a second circuit structure of a power device drive circuit according to Embodiment 6 of this application, wherein only the control of the turn-on drive rate is implemented;

[0067] Figure 9c is a schematic diagram of a third circuit structure of a power device driving circuit according to Embodiment 6 of this application, wherein only the control of the turn-on driving rate is realized.

[0068] Figure 10a is a schematic diagram of a power device drive circuit according to Embodiment 7 of this application, wherein only the control of the turn-off drive rate is implemented.

[0069] Figure 10b is a schematic diagram of a second circuit structure of a power device drive circuit according to Embodiment 7 of this application, wherein only the control of the turn-off drive rate is implemented.

[0070] Figure 10c is a schematic diagram of a third circuit structure of a power device drive circuit according to Embodiment 7 of this application, wherein only the control of the turn-off drive rate is realized.

[0071] Figure 11 is a schematic diagram of the framework structure of the power device driving circuit according to Embodiment 7 of this application. Detailed Implementation

[0072] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0073] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0074] Example 1:

[0075] This embodiment describes a power device driving method, wherein the output of a multi-channel driving circuit is controlled by adjusting an input driving signal. The driving signal includes a main driving signal and N enable signals, where N ≥ 1. As shown in Figure 1, the main driving signal is processed by the multi-channel driving circuit to form a main output signal. The multi-channel driving circuit determines whether to output an auxiliary output signal based on the activation or deactivation of the received enable signals. A driving voltage signal for driving the power device is formed based on the main output signal or the auxiliary output signal.

[0076] First, after the drive signal is input to the multi-channel drive circuit, it generates a main output signal. The main output signal follows the main drive signal, and its output level is fixed. The auxiliary output signal follows the drive signal, and its waveform is essentially the same as the main output signal, ensuring synchronous control between the auxiliary and main output signals. It is understood that each additional auxiliary output signal generates and outputs changes the drive impedance associated with the drive voltage signal. For example, each additional auxiliary output signal adds an equivalent parallel auxiliary drive impedance network to the main drive impedance network, reducing the drive impedance in the multi-channel drive circuit and thus increasing the drive speed for power devices.

[0077] Based on this design, this application allows for flexible adjustment of the circuit architecture of the multi-channel drive circuit as needed. By activating or disabling each enable signal, the output control of the auxiliary output signal can be achieved, thereby adjusting the drive rate of the power device to meet different application scenarios and performance requirements.

[0078] In one implementation, as shown in the logic relationship between the input and output ports of the multi-channel drive circuit in Figure 2, the main drive signal is divided into multiple inputs. One input is processed and amplified to form the main output signal. The other inputs are processed and amplified together with the enable signals. When the enable signal is activated, the auxiliary output signal is output. The auxiliary output signal and the main output signal are superimposed to form the drive voltage signal.

[0079] In another implementation, the main drive signal is divided into multiple inputs. One input is processed and amplified to form a main output signal, which is sent to the first drive impedance network in the multi-channel drive circuit to control its operation. The remaining inputs are processed and amplified together with enable signals. When an enable signal is activated, an auxiliary output signal is output. Each auxiliary output signal is sent to a second drive impedance network in the multi-channel drive circuit. Each auxiliary output signal controls a second drive impedance network to work in conjunction with the first drive impedance network, for example, by connecting the second and first drive impedance networks in parallel to change the overall drive impedance, thereby controlling and adjusting the drive voltage signal driving the power device. In other words, after generation, the auxiliary output signal and the main output signal control their respective connected drive impedance networks, causing a change in the overall drive impedance, thus controlling the drive rate of the power device.

[0080] Furthermore, in application environments with multiple enable signals, enable signals 1 to N can be arbitrarily arranged and combined. For example, enable signal 1 can be combined with enable signal 2, enable signal 3 with enable signal 4, and so on. Alternatively, all enable signals from 1 to N can be combined. This allows the input drive signal to simultaneously control the activation or deactivation of two or more auxiliary drive circuits, making the drive rate adjustment range of power devices more diverse.

[0081] When a certain enable signal is disabled, the corresponding auxiliary drive circuit is also disabled. In this case, the auxiliary drive circuit needs to be in a high-impedance state or an equivalent high-impedance state with respect to the control electrode of the power device to prevent abnormal gate voltage and improve the reliability of the power device. There are two ways to achieve a high-impedance state or an equivalent high-impedance state between the auxiliary drive circuit and the control electrode of the power device: one is to have the auxiliary drive circuit in a high-impedance state, and the other is to utilize the unidirectional conduction capability of some components in the auxiliary drive circuit (such as logic devices in the auxiliary drive logic circuit or diodes in the second drive impedance network) to achieve an equivalent high-impedance state.

[0082] Specifically, in one embodiment, when the enable signal is disabled, the input terminals of each enable signal and the output terminals of the drive voltage of the multiplexer circuit are in a high-impedance state. For example, after the enable signal is disabled, the drive switch in the auxiliary drive circuit can be normally open, thereby making the auxiliary drive circuit exhibit high-impedance characteristics. In other words, the drive impedance network in the auxiliary drive circuit can be designed as a circuit with high impedance characteristics, and the high impedance characteristics of the drive impedance network when the enable signal is disabled will ensure that the auxiliary drive circuit does not affect the operation of the power device.

[0083] In another embodiment, the multi-drive circuit includes at least one second drive impedance network, wherein some or all of the current flowing in the at least one drive impedance network is unidirectional. The specific direction of the unidirectional current flow depends on whether turn-off drive rate control or turn-on drive rate control is being implemented. If turn-off drive rate control for power devices is being implemented, the current flow direction is from the output terminal of the drive impedance network to the input terminal; if turn-on drive rate control for power devices is being implemented, the current flow direction is from the input terminal of the drive impedance network to the output terminal. One implementation method is to design the logic device of the auxiliary drive circuit as a device such as a tri-state buffer; another implementation method is to design unidirectional devices such as diodes in the drive impedance network of the auxiliary drive circuit, thereby ensuring that its impact on the power transistor is minimized when the auxiliary drive circuit is not needed.

[0084] Example 2:

[0085] This embodiment describes a power device driving circuit, which includes a multi-channel driving circuit. The input terminal of the multi-channel driving circuit is used to receive driving signals, and the multi-channel driving circuit has at least two output terminals. The multi-channel driving circuit includes a main driving circuit and at least one auxiliary driving circuit. The driving signals include a main driving signal and at least one enable signal. The main driving signal is divided into at least two paths and input to the main driving circuit and each auxiliary driving circuit respectively. As shown in Figure 1, the main driving signal is processed by the main driving circuit to form a main output signal. Each enable signal is input to each auxiliary driving circuit. Each auxiliary driving circuit is activated or disabled according to the received enable signal, thus enabling or disabling the auxiliary driving circuit. Activation of the enable signal enables the auxiliary driving circuit to form an auxiliary output signal. A driving voltage signal for driving the power device is formed based on the main output signal or the auxiliary output signal.

[0086] The driving circuits in the multi-channel driving circuit generally include logic circuits for logic processing and amplifier circuits for signal amplification. In addition, isolation circuits are also provided in the driving circuits that isolate the input and output signals of the multi-channel driving circuit.

[0087] Specifically, as shown in Figure 3, the main driving circuit includes a main driving logic circuit and a main driving amplifier circuit. The main driving signal is processed and amplified by the main driving logic circuit and the main driving amplifier circuit to form the main output signal. The auxiliary driving circuit includes an auxiliary driving logic circuit and an auxiliary driving amplifier circuit. The main driving signal and the enable signal are connected to the input terminal of the auxiliary driving logic circuit. The output terminal of the auxiliary driving logic circuit is connected to the auxiliary driving amplifier circuit. The output terminal of the auxiliary driving amplifier circuit outputs the auxiliary output signal when the enable signal is activated. The auxiliary driving logic circuit includes logic gate devices. The enable signal and the main driving signal are connected to the input terminal of the logic gate device or a tri-state buffer device. The auxiliary output signal is output only when the enable signal is activated.

[0088] Additionally, as shown in Figures 4a to 4c, an isolation circuit can be provided in the main driving circuit. This isolation circuit can be located between the main driving logic circuit and the main driving amplifier circuit, or inside the main driving logic circuit, or before the main driving logic circuit. Similarly, an isolation circuit can be provided in the auxiliary driving circuit. This isolation circuit can be located between the auxiliary driving logic circuit and the auxiliary driving amplifier circuit, or inside the auxiliary driving logic circuit, or before the auxiliary driving logic circuit.

[0089] The multi-channel driver circuit of this embodiment can be configured with various power supply structures as needed. For example, when the input and output sides of the multi-channel driver circuit are not isolated, the power supply methods shown in Figures 5a and 5b can be used. One or two power supply VCC terminals can be set to provide high-level signals to the driver logic circuit and the driver amplifier circuit, and only one ground terminal can be set. When the input and output sides of the multi-channel driver circuit are isolated, the power supply method shown in Figure 5c can be used. Two power supply VCC terminals are used to provide high-level signals to the driver logic circuit and the driver amplifier circuit, and a ground terminal is set for each of the driver logic circuit and the driver amplifier circuit.

[0090] In summary, after the drive signal is input to the main drive circuit, it generates a main output signal. The main output signal follows the main drive signal, and its output level is fixed. When the enable signal input to the auxiliary drive circuit is activated, the auxiliary drive circuit is enabled. The auxiliary output signal generated by the auxiliary drive circuit follows the drive signal, and its waveform is essentially the same as that of the main output signal, ensuring that the auxiliary output signal is synchronously output with the main output signal and has a basically consistent waveform. It can be understood that each additional auxiliary output signal generated and output enables the drive impedance network of the auxiliary drive circuit, causing a change in the overall drive impedance and increasing the drive rate for power devices.

[0091] Example 3:

[0092] To facilitate the explanation of the power device driving method and circuit of this application, this embodiment uses a multi-channel driving circuit combining one main driving circuit and one auxiliary driving circuit to drive a power transistor as an example to illustrate the circuit structure and working process. The number of main driving circuits or auxiliary driving circuits can be selected according to needs, but the general working principle is as described in the embodiment of this application.

[0093] The auxiliary driver logic circuit in the auxiliary driver circuit has different implementation methods.

[0094] In this embodiment, as shown in FIG6, the auxiliary driving logic circuit includes a logic gate device. The enable signal and the main driving signal are connected to the input terminal of the logic gate device. When the enable signal is activated, the output terminal of the logic gate device will output the auxiliary output signal to the second upper driving switch or the second lower driving switch. The auxiliary output signal follows the driving signal, and the waveform of the auxiliary output signal is basically the same as the waveform of the main output signal.

[0095] The main drive circuit includes a first upper drive switch, a first lower drive switch, and a first drive impedance network. The first end of the circuit formed by the series connection of the first upper drive switch and the first lower drive switch is connected to the power supply VCC terminal, and the second end is grounded. The first end of the first drive impedance network is connected to the midpoint between the first upper drive switch and the first lower drive switch, and the second end is connected to the control electrode of the power transistor. The main output signal is divided into two paths, which are respectively connected to the first upper drive switch and the first lower drive switch to control their on / off states. Furthermore, to ensure the stability of the drive voltage signal input to the power transistor, voltage regulator units (positive and negative voltage regulator units in the figure) are connected in parallel across the circuit formed by the series connection of the first upper drive switch and the first lower drive switch.

[0096] The auxiliary drive circuit includes a second upper drive switch and a second drive impedance network. The first end of the second upper drive switch is connected to the power supply VCC terminal, and the second end is connected to the first end of the second drive impedance network. The second end of the second drive impedance network is connected to the second end of the first drive impedance network and then connected to the control electrode of the power transistor. The auxiliary output signal is connected to the second upper drive switch and controls its on / off state.

[0097] The main output signal is sent to the first driving impedance network to control its operation. Each auxiliary output signal is sent to a second driving impedance network, and each auxiliary output signal controls a second driving impedance network to work together with the first driving impedance network. In this embodiment, the corresponding auxiliary driving circuit is activated when the enable signal is activated, so that the second driving impedance network in the auxiliary driving circuit is connected in parallel with the first driving impedance network of the main driving circuit, causing the overall driving impedance to change, thereby controlling and adjusting the driving voltage signal that drives the power transistor.

[0098] After the auxiliary drive circuit receives the enable signal and is activated, it generates an auxiliary output signal. This auxiliary output signal and the main output signal change almost synchronously with the changes in the drive signal (because there may be a slight delay between the two different drive circuits, but this is negligible; of course, the synchronization and consistency can be improved through the design of a delay circuit). Therefore, in this situation, the auxiliary drive circuit is activated, meaning the main drive signal can simultaneously drive both the main drive circuit and the auxiliary drive circuit. Changes in the input of the main drive signal allow the first and second upper drive switches to operate almost simultaneously, as do the first and second lower drive switches.

[0099] The first upper drive switch, the first lower drive switch, the second upper drive switch, and the second lower drive switch mentioned above can be any device with switching capabilities, including but not limited to transistors, MOSFETs, IGBTs, relays, etc. Under normal circumstances, all four drive switches are in the normally off state, and switch to the normally on state after receiving the main output signal or the auxiliary output signal.

[0100] It is understandable that when the enable signal is activated, an auxiliary output signal is output, enabling the auxiliary drive circuit. This allows control to simultaneously close the first and second upper drive switches, or simultaneously close the first and second lower drive switches. This causes the second drive impedance network in the auxiliary drive circuit to connect in parallel with the first drive impedance network of the main drive circuit, reducing the overall drive impedance and increasing the drive voltage signal, thereby improving the drive rate of the power transistor. Conversely, when the enable signal is disabled, the auxiliary drive circuit is disabled, and only the main drive signal acts on the main drive circuit. This means only the first drive impedance network participates in driving the power transistor, resulting in a reduction in the drive rate of the power transistor.

[0101] When the control causes the second upper drive switch and the first upper drive switch to close simultaneously, the turn-on rate of the power transistor can be increased accordingly. When the control causes the second lower drive switch and the first lower drive switch to close simultaneously, the turn-off rate of the power transistor can be increased accordingly. When the control causes the second upper drive switch to turn off, the turn-on rate of the power transistor can be kept at a lower level. When the control causes the second lower drive switch to turn off, the turn-off rate of the power transistor can be kept at a lower level. In view of this, by designing the auxiliary drive circuit to conduct current unidirectionally, or by removing some drive switches in the auxiliary drive circuit, the drive rate adjustment for the turn-on or turn-off of the power transistor can be achieved independently, meeting the needs of users in different application scenarios. This will be elaborated in the following embodiments 6 and 7.

[0102] Example 4:

[0103] This embodiment describes a power transistor drive rate adjustment circuit, whose main structure is basically the same as that of Embodiment 3, the difference being the selection of logic devices in the auxiliary drive logic circuit.

[0104] In this embodiment, as shown in FIG7, the auxiliary driving logic circuit includes a tri-state buffer device. The enable signal and the main driving signal are connected to the input terminal of the tri-state buffer device. When the enable signal is activated, the output terminal of the logic gate device will output the auxiliary output signal to the second upper driving switch or the second lower driving switch. The auxiliary output signal follows the driving signal, and the waveform of the auxiliary output signal is basically the same as the waveform of the main output signal.

[0105] The tri-state output of the tri-state buffer is controlled by the enable output terminal. When the enable signal is activated, the device outputs in the normal logic state (logic 0, logic 1). When the enable input is disabled, the output is in a high-impedance state, which is equivalent to being disconnected from the connected circuit. This allows the auxiliary drive circuit to exhibit a high-impedance state, which can prevent abnormal gate voltage of the power transistor and improve the reliability of the power transistor.

[0106] Example 5:

[0107] This embodiment describes a power transistor drive rate adjustment circuit, whose main structure is basically the same as that of Embodiment 4, the difference being the selection of logic devices in the auxiliary drive logic circuit.

[0108] In this embodiment, as shown in FIG8, the auxiliary driving logic circuit includes a tri-state buffer switch device. The second upper driving switch and the second lower driving switch in Embodiment 4 are eliminated, which is equivalent to integrating the tri-state buffer device of the auxiliary driving circuit in Embodiment 4 with the second upper driving switch and the second lower driving switch into a tri-state buffer switch device.

[0109] Similarly, this tri-state buffer can output a high-impedance state when the enable input is disabled, which is equivalent to being disconnected from the connected circuit. This allows the auxiliary drive circuit to exhibit a high-impedance state, which can prevent abnormal gate voltage of the power transistor and improve the operating reliability of the power transistor.

[0110] Example 6:

[0111] This embodiment describes a power device driving circuit, which is an improvement on embodiment 3. The improvement is that a unidirectional conducting device is provided in the second driving impedance network, and the unidirectional current conduction direction is from the first end of the second driving impedance to the second end.

[0112] In this embodiment, the power transistor only needs to control the turn-on rate. The auxiliary drive circuit not only presents a high impedance state when the auxiliary drive signal is disabled, but also a high impedance state on the connection path of the second lower drive switch and the second drive impedance network. The second lower drive switch is grounded. Therefore, during the turn-on process, the first end of the second drive impedance is in the conduction state, and during the turn-off process, the second end of the second drive impedance is in the cut-off high impedance state, pointing from the first end.

[0113] Figures 9a to 9c illustrate three implementation methods for controlling only the turn-on drive rate of the power transistor.

[0114] As shown in Figure 9a, by configuring the unidirectional conduction direction of the second driving impedance network as the turn-on direction, that is, the conduction state is from the first end to the second end of the second driving impedance. In this way, the second driving impedance network only participates in the driving process during turn-on, while maintaining a high impedance state during turn-off. When the auxiliary driving circuit is activated by the enable signal and participates in the turn-on driving of the power device, the auxiliary output signal of the auxiliary driving circuit follows the input main driving signal. This means that the second upper driving switch can operate simultaneously with the first upper driving switch, and the second lower driving switch can operate simultaneously with the first lower driving switch.

[0115] During the turn-on process of the power transistor, if it is necessary to increase the turn-on drive rate, the enable signal activates the auxiliary drive circuit. The second upper drive switch follows the first upper drive switch and switches to normally on, while the second lower drive switch follows the first lower drive switch and switches to normally off. The second drive impedance network is connected in parallel with the first drive impedance network, which reduces the overall drive impedance and improves the turn-on drive rate. If it is necessary to reduce the turn-on rate, the enable signal is disabled, and the auxiliary drive circuit is also disabled. The second upper drive switch remains normally off, and the second lower drive switch remains normally on. The auxiliary drive circuit outputs a low level. Since the second drive impedance network is unidirectional and has unidirectional conductivity (the current conduction direction is from the first end of the second drive impedance to the second end), the low level output by the auxiliary drive circuit will not affect the control electrode of the power transistor. Thus, the auxiliary drive circuit presents a high impedance state, thereby reducing the turn-on drive rate and ensuring that its impact on the power transistor is minimized when the auxiliary drive circuit is not needed.

[0116] As shown in Figure 9b, a further optimization based on Figure 9a is achieved by removing the second lower drive switch. The second drive impedance network can still participate in the drive during the turn-on process, while maintaining a high impedance state during the turn-off process. During the turn-on process of the power transistor, if it is necessary to reduce the turn-on rate, the enable signal is disabled, and the auxiliary drive circuit is also disabled. The second upper drive switch remains normally open, thus preventing the voltage at the first end of the second drive impedance network from increasing. Furthermore, since the second lower drive switch is removed, the voltage at the first end of the second drive impedance network will not decrease. Combined with the fact that the second drive impedance network is unidirectional and has unidirectional conductivity (the current conduction direction is from the first end of the second drive impedance to the second end), it is possible to reduce the turn-on drive rate while keeping the second drive impedance network in a high impedance state and not participating in the drive. This ensures that when the auxiliary drive circuit is not needed, its impact on the power transistor is minimized.

[0117] As shown in Figure 9c, the design is further simplified based on Figure 9b by removing the conduction direction restriction in the second driving impedance network. This modification does not affect the auxiliary driving circuit's ability to participate in driving during turn-on, and the auxiliary driving circuit can still maintain a high impedance state during turn-off because the second upper driving switch is normally open.

[0118] The above unidirectional current can be passed through devices with unidirectional conductivity, such as diodes, or controllable power switches, relays, etc.

[0119] Example 7:

[0120] This embodiment describes a power device driving circuit, which is an improvement on embodiment 3. The improvement is that a unidirectional conducting device is provided in the second driving impedance network, and the unidirectional current conduction direction is from the second end of the second driving impedance to the first end.

[0121] In this embodiment, the power transistor only needs to control the turn-off rate. The auxiliary drive circuit not only presents a high impedance state when the auxiliary drive signal is disabled, but also a high impedance state in the connection path of the second drive switch and the second drive impedance network. Therefore, during the turn-off process, the second end of the second drive impedance pointing to the first end is in the conduction state, and during the turn-on process, the first end of the second drive impedance pointing to the second end is in the cut-off high impedance state.

[0122] Figures 10a to 10c illustrate three implementation methods for controlling only the power transistor turn-off drive rate.

[0123] As shown in Figure 10a, by configuring the unidirectional conduction direction of the second driving impedance network as the turn-off direction, that is, the second end of the second driving impedance is in the conducting state towards the first end. This ensures that the second driving impedance network only participates in the driving process during turn-off, while maintaining a high impedance state during turn-on. When the auxiliary driving circuit is activated by the enable signal and participates in the turn-off driving of the power device, the auxiliary output signal of the auxiliary driving circuit follows the input main driving signal. This means that the second upper driving switch can operate simultaneously with the first upper driving switch, and the second lower driving switch can operate simultaneously with the first lower driving switch.

[0124] During the turn-on process of the power transistor, if it is necessary to increase the turn-off drive rate, the enable signal activates the auxiliary drive circuit. The second upper drive switch follows the first upper drive switch and switches to normally off, while the second lower drive switch follows the first lower drive switch and switches to normally on. The second drive impedance network is connected in parallel with the first drive impedance network, which reduces the overall drive impedance and improves the turn-off drive rate. If it is necessary to reduce the turn-off rate, the enable signal is disabled, and the auxiliary drive circuit is also disabled. The second upper drive switch remains normally on, and the second lower drive switch remains normally off. The auxiliary drive circuit outputs a high level. Since the second drive impedance network is unidirectional and has unidirectional conductivity (the current conduction direction is from the second end of the second drive impedance to the first end), the high level output of the auxiliary drive circuit will not affect the control electrode of the power transistor. Thus, the auxiliary drive circuit presents a high impedance state, which reduces the turn-off drive rate and ensures that its impact on the power transistor is minimized when the auxiliary drive circuit is not needed.

[0125] As shown in Figure 10b, a further optimization based on Figure 10a is achieved by removing the second upper drive switch. The second drive impedance network can still participate in the drive during the turn-off process, while maintaining a high-impedance state during turn-off. During the turn-on process of the power transistor, if it is necessary to reduce the turn-off rate, the enable signal is disabled, and the auxiliary drive circuit is also disabled. The second lower drive switch remains normally open, thus preventing the voltage at the first terminal of the second drive impedance network from being lowered. Furthermore, since the second upper drive switch is removed, the voltage at the first terminal of the second drive impedance network will not be raised. Combined with the fact that the second drive impedance network is unidirectional and has unidirectional conductivity (the current conduction direction is from the second terminal of the second drive impedance to the first terminal), it is possible to reduce the turn-off drive rate while keeping the second drive impedance network in a high-impedance state and not participating in the drive. This ensures that when the auxiliary drive circuit is not needed, its impact on the power transistor is minimized.

[0126] As shown in Figure 10c, the design is further simplified based on Figure 10b by removing the conduction direction restriction in the second driving impedance network. This modification does not affect the auxiliary driving circuit's ability to participate in driving when turned off, and the auxiliary driving circuit can still maintain a high impedance state during the turn-on process because the second lower driving switch is normally open.

[0127] The above unidirectional current can be passed through devices with unidirectional conductivity, such as diodes, or controllable power switches, relays, etc.

[0128] Example 8:

[0129] As shown in Figure 11, according to the implementation methods in the above embodiments, by adjusting the design of the multi-channel drive circuit, the power device drive circuit can have a separate first auxiliary output signal (auxiliary output turn-on signal) for controlling the power device turn-on rate. The output of the first auxiliary output signal is determined by the activation or disabling of the first enable signal. Additionally, the power device drive circuit also has a separate second auxiliary output signal (auxiliary output turn-off signal) for controlling the power device turn-off rate. The output of the first auxiliary output signal is determined by the activation or disabling of the second enable signal. This allows for diversified power device driving, better meeting user needs.

[0130] In addition, if necessary, the multi-channel drive circuit can be adjusted to have two or even three auxiliary drive circuits that generate the turn-on signals of each auxiliary output, or two or even three auxiliary drive circuits that generate the turn-off signals of each auxiliary output. These will not be described in detail here.

[0131] In addition, two or more enable signals can be combined to perform enable control together, meeting different user needs. For example, by combining the first and second enable signals, if an enable signal is activated, the turn-on and turn-off rates of the power devices can be controlled.

[0132] The power device driving method and circuit described in the above embodiments have high flexibility and adaptability, and can be implemented in the following ways:

[0133] Component-based implementation: This approach can be built entirely from discrete electronic components, such as resistors, capacitors, and transistors. This method offers maximum flexibility, allowing designers to select and adjust component parameters according to specific needs. Both the drive logic circuitry and the drive amplifier circuitry can be implemented using independent components and interconnected.

[0134] Integrated Circuit Implementation: To simplify design and improve reliability, this solution can also utilize integrated circuits (ICs). ICs provide compact, pre-designed solutions, reducing the number of external components, lowering design complexity, and improving circuit performance and stability. The driver logic circuits and driver amplifier circuits can be implemented separately by integrated circuits and connected together, or implemented within the same integrated circuit without external connections.

[0135] Implementation using a combination of independent components and integrated circuits: Furthermore, this solution supports the combined use of independent components and integrated circuits to leverage the advantages of both. For example, the drive logic circuit can be implemented using integrated circuits, while the drive amplifier circuit can be implemented using independent components, and then connected together; or the drive logic circuit can be implemented using independent components, while the drive amplifier circuit can be implemented using integrated circuits, and then interconnected.

[0136] In summary, this application enables the formation of auxiliary output signals that follow the main drive signal by introducing enable signals. Furthermore, it controls the output of each auxiliary output signal based on the activation or disabling of each enable signal. The output auxiliary output signals are then combined with the main output signal to control the drive impedance of the power device, ultimately adjusting the drive rate of the power device. This application offers rapid drive rate adjustment, fast response, high stability, and allows for individual adjustment of the turn-on or turn-off rate through different enable signal inputs, demonstrating strong adaptability.

[0137] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A power device driving method, characterized in that, The output of the multi-channel drive circuit is controlled by adjusting the input drive signal. The drive signal includes a main drive signal and at least one enable signal. The main drive signal is converted into a main output signal by the multi-channel drive circuit. The multi-channel drive circuit determines whether to output an auxiliary output signal based on the activation or deactivation of the received enable signal. A drive voltage signal for driving the power device is formed based on the main output signal or the auxiliary output signal.

2. The power device driving method according to claim 1, characterized in that, The auxiliary output signal follows the driving signal, and the waveform of the auxiliary output signal is basically the same as the waveform of the main output signal.

3. The power device driving method according to claim 1 or 2, characterized in that, The main drive signal is divided into multiple inputs. One input is processed and amplified to form the main output signal. The other inputs are processed and amplified together with the respective enable signals. When the enable signal is activated, the auxiliary output signal is output. The auxiliary output signal and the main output signal are superimposed to form the drive voltage signal.

4. The power device driving method according to claim 1 or 2, characterized in that, The main drive signal is divided into multiple inputs. One input is processed and amplified to form the main output signal. The main output signal is sent to the first drive impedance network in the multi-channel drive circuit to control the operation of the first drive impedance network. The other inputs are processed and amplified together with the respective enable signals. When the enable signal is activated, the auxiliary output signal is output. Each auxiliary output signal is sent to the respective second drive impedance network in the multi-channel drive circuit. Each auxiliary output signal controls a second drive impedance network to work together with the first drive impedance network to control and adjust the drive voltage signal driving the power device.

5. The power device driving method according to claim 4, characterized in that, The multi-channel drive circuit includes at least one second drive impedance network. The current flow direction of at least one of the at least one drive impedance network is unidirectional, and the conduction direction is either from the output terminal of the drive impedance network to the input terminal or from the input terminal of the drive impedance network to the output terminal.

6. The power device driving method according to claim 1, characterized in that, When the enable signal is disabled, the input terminal of each enable signal is in a high impedance state with the output terminal of the drive voltage of the multiplexer circuit.

7. A power device driving circuit, characterized in that, It includes a multi-channel drive circuit, the input of which is used to receive drive signals, and the multi-channel drive circuit has at least two output terminals; The multi-channel drive circuit includes a main drive circuit and at least one auxiliary drive circuit. The drive signal includes a main drive signal and at least one enable signal. The main drive signal is divided into at least two paths and is respectively input to the main drive circuit and each auxiliary drive circuit. The main drive signal is converted into a main output signal by the main drive circuit. Each enable signal is input to each auxiliary drive circuit. Each auxiliary drive circuit is activated or disabled according to the received enable signal to enable or disable the auxiliary drive circuit. When the enable signal is activated, the auxiliary drive circuit is enabled and forms an auxiliary output signal. A drive voltage signal for driving power devices is formed based on the main output signal or the auxiliary output signal.

8. The power device drive circuit according to claim 7, characterized in that, The main driving circuit includes a main driving logic circuit and a main driving amplifier circuit. The main driving signal is processed and amplified by the main driving logic circuit and the main driving amplifier circuit to form the main output signal.

9. The power device drive circuit according to claim 7, characterized in that, The auxiliary driving circuit includes an auxiliary driving logic circuit and an auxiliary driving amplifier circuit. The main driving signal and the enable signal are connected to the input terminal of the auxiliary driving logic circuit. The output terminal of the auxiliary driving logic circuit is connected to the auxiliary driving amplifier circuit. When the enable signal is activated, the output terminal of the auxiliary driving amplifier circuit outputs the auxiliary output signal.

10. The power device drive circuit according to claim 9, characterized in that, The auxiliary driving logic circuit includes logic gate devices or tri-state buffer devices. The enable signal and the main driving signal are connected to the input terminal of the logic gate device or tri-state buffer device. When the enable signal is activated, the output terminal of the logic gate device or tri-state buffer device outputs the auxiliary output signal. The auxiliary output signal follows the driving signal, and the waveform of the auxiliary output signal is basically the same as the waveform of the main output signal.

11. The power device drive circuit according to claim 7, characterized in that, The main drive circuit includes a first drive impedance network, and each of the auxiliary drive circuits includes a second drive impedance network. The main output signal is sent to the first drive impedance network to control the operation of the first drive impedance network. Each of the auxiliary output signals is sent to each of the second drive impedance networks. Each of the auxiliary output signals controls a second drive impedance network to work together with the first drive impedance network to control and adjust the drive voltage signal that drives the power device.

12. The power device drive circuit according to claim 11, characterized in that, The main drive circuit includes a first upper drive switch, a first lower drive switch, and a first drive impedance network. In this circuit, the first end of the circuit after the first upper drive switch and the first lower drive switch are connected in series is connected to the power supply VCC terminal, and the second end is grounded. The first end of the first driving impedance network is connected to the midpoint between the first upper driving switch and the first lower driving switch, and the second end is connected to the control electrode of the power device. The main output signal is divided into two paths, which are respectively connected to the first upper drive switch and the first lower drive switch to control the on / off state of both.

13. The power device drive circuit according to claim 12, characterized in that, The auxiliary drive circuit includes a second upper drive switch and a second drive impedance network. The first end of the second upper drive switch is connected to the power supply VCC terminal, and the second end is connected to the first end of the second drive impedance network. The second end of the second drive impedance network is connected to the second end of the first drive impedance network and then connected to the control electrode of the power device. The auxiliary output signal is connected to the second upper drive switch and controls its on / off state.

14. The power device drive circuit according to claim 13, characterized in that, The second driving impedance network is provided with a unidirectional conduction device, and the current conduction direction is from the first end of the second driving impedance to the second end.

15. The power device drive circuit according to any one of claims 11 to 14, characterized in that, The auxiliary drive circuit includes a second lower drive switch, the first terminal of the second lower drive switch is grounded, the second terminal of the second lower drive switch is connected to the second terminal of the second upper drive switch, and the auxiliary output signal is divided into two paths and respectively connected to the second upper drive switch and the second lower drive switch to control the on and off of the two.

16. The power device drive circuit according to claim 15, characterized in that, The second driving impedance network is provided with a unidirectional conduction device, and the current conduction direction is from the second end of the second driving impedance to the first end.

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