On-chip electrostatic discharge protection for semiconductor devices

Abstract

A semiconductor structure, preferably a semiconductor die, is described wherein the structure comprises; a semiconductor substrate comprising a device area; one or more dielectric insulating layers over the semiconductor substrate; a plurality of electrode terminals for controlling one or more semiconductor devices, preferably semiconductor quantum devices, in the device area, the electrode terminals being formed in or over the one or more dielectric insulating layers in an fanout area of the semiconductor area outside the device area, the electrode terminals extending from the fanout area towards the device area; each electrode terminal being connected to the semiconductor substrate through a galvanic connection formed in the one or more dielectric insulating layers in the fanout area; and, the semiconductor substrate being configured as an NTC thermistor and the galvanic connections electrically connecting the electrode terminals at room temperature to each other via the semiconductor substrate.

Description

[0001] On-chip electrostatic discharge protection for semiconductor devices

[0002] Technical field

[0003] The disclosure relates to electrostatic discharge protection for semiconductor device, and, in particular, though not exclusively, to on-chip electrostatic discharge protection for semiconductor devices, including semiconductor quantum devices.

[0004] Background

[0005] Semiconductor quantum devices, such as quantum dots, provide a versatile and scalable hardware platform for building semiconductor quantum processing units (QPUs) that are compatible with semiconductor manufacturing. A QPU includes a plurality of semiconductor qubit devices, each having an arbitrary number of terminals for controlling and readout of qubits, either individual and / or collectively. Here, a terminal is an electrical connection to any part of the qubit structure such as electrostatic gates or ohmic contacts.

[0006] The article by Hendrickx et al, A single hole spin qubit, Nature Communications, 3478 (2020), describes an example of Silicon Germanium spin qubit devices. The devices are typically operated at cryogenic temperatures lower than 10 Kelvin to suppress the influence of thermal noise. The semiconductor qubit devices have dimensions in the nano-scale range thus making them very sensitive to any type of electric discharge. Hence, effective electrostatic discharge (ESD) protection for semiconductor qubit devices is essential.

[0007] US11735578 describes on-chip semiconductor quantum device electrostatic discharge protection circuit for protecting circuits that operate at cryogenic temperatures. Each ESD protection circuit comprises a relatively large number of bulky semiconductor elements, including diodes. In order to provide the desired thermal behavior the circuit needs to be carefully designed and fabricated in terms of number of diodes, geometry of the diodes and dopant concentration, thereby making practical implementations of the circuit challenging.

[0008] Hence, from the above, it follows that there is a need in the art for improved electrostatic discharge protection for semiconductor device. In particular, there is a need in the art for simple, effective and scalable on-chip electrostatic discharge protection for semiconductor devices, in particular semiconductor quantum devices, which operate at cryogenic temperatures.

[0009] It is an objective of the embodiments in this disclosure to reduce or eliminate at least one of the drawbacks known in the prior art.

[0010] In an aspect, the embodiments may relate to a semiconductor structure, preferably a semiconductor die, comprising; a semiconductor substrate comprising a device area; one or more dielectric insulating layers over the semiconductor substrate; a plurality of electrode terminals for controlling one or more semiconductor devices, preferably semiconductor quantum devices, in the device area, the electrode terminals being formed in or over the one or more dielectric insulating layers in an fanout area of the semiconductor area outside the device area, the electrode terminals extending from the fanout area towards the device area; each electrode terminal having an ohmic connection to the semiconductor substrate through a galvanic connection formed in the one or more dielectric insulating layers in the fanout area; and, the semiconductor substrate being configured as an NTC thermistor; and, the galvanic connections electrically connecting the electrode terminals at room temperature to each other via the semiconductor substrate.

[0011] Hence, at room temperature, excitations in the semiconductor substrate will cause the semiconductor substrate to have a high conductivity thereby galvanically short circuiting the electrode terminals of one or more semiconductor devices via the substrate. The semiconductor substrate provides a low-ohmic shunt between the different electrode terminals, thus keeping the relative potential between the electrode terminals close to zero, protecting the sensitive semiconductor devices, such as semiconductor quantum devices, from breakdown as a result of electrostatic discharges. At low temperatures, the semiconductor substrate freezes out, resulting in a very high resistance between the terminals and thus an effective open circuit between the electrode terminals that are connected via the galvanic connection and the Ohmic contacts to the substrate. The semiconductor substrate may be configured as a NTC thermistor by calibrating the carrier concentration because of thermal excitations by engineering the band gap size and / or doping levels in the substrate.

[0012] When all electrode terminals of the device are electrically connected together, the potential of all the electrodes of the device move together so that the potential difference between the terminals will be small and damage, such as breakdown of dielectrics, due to electrostatic discharges is prevented. This way, the semiconductor chip can be handled at room temperature without or at least with a substantial reduction of damage due to electrostatic discharges. This implementation of ESD protection is particularly advantageous when transporting the semiconductor chip, such that no ground reference is present.

[0013] In an embodiment, the galvanic connection in the fanout area may include a first conductive via through the one or more dielectric layers and an Ohmic contact in the semiconductor substrate connecting the conductive via to the semiconductor substrate.

[0014] In an embodiment, the Ohmic contact in the semiconductor substrate is a metal diffused area in the semiconductor substrate. In an embodiment, the Ohmic contacted may be formed by the diffusion of a metal in a SiGe substrate and subsequent formation of (germano)-silicides area, for example a platinum (germano)- silicides area, in the substrate.

[0015] In an embodiment, the Ohmic contact in the semiconductor substrate is a highly doped area in the semiconductor substrate.

[0016] In an embodiment, each electrode terminal may include a bonding pad and a fanout electrode extending from the bonding pad to the device area, the fanout electrode electrically connecting the bonding pad to a gate electrode in the device area, a gate dielectric layer separating the gate electrode from the semiconducting surface.

[0017] In an embodiment, a second conductive via through the one or more dielectric insulating layers electrically connects an end of the fanout electrode at the device area to the gate electrode.

[0018] In an embodiment, the thickness of the one or more dielectric insulating layers in the fanout area separating the fanout electrode from the surface of the semiconductor substrate may be larger than the thickness of the dielectric gate layer separating the gate electrode from the surface of the semiconductor substrate. For example, typically the gate dielectric may be selected between 2-8 nm, preferably between 3-6 nm. The thickness in of the dialectic layers in the fanout area, for example a back-end-of-line (BEOL) metallization layer, of the semiconductor substrate may be selected between 50 and 500 nm, preferably between 60 and 400 nm, more preferably between 80 and 200 nm.

[0019] In an embodiment, the one or more dielectric insulating layers may be part of a metallization layer comprising an alternating stack of dielectric layers and patterned metal layers, preferably the metallization layer in at least the fanout area being a back-end-of-line (BEOL) metallization layer, preferably the fanout electrode being formed in one of the upper layers of the BEOL metallization layer.

[0020] In an embodiment, the semiconductor structure may further comprise: one or more depletion gates for introducing one or more depletion zones in the semiconductor substrate to minimize conductive paths in the semiconductor substrate between the plurality of electrode terminals and / or the device area.

[0021] In an embodiment, the semiconductor structure may further comprise: one or more insulating areas, preferably silicon oxide areas, formed in the semiconductor substrate to minimize conductive paths in the semiconductor substrate between the plurality of electrode terminals and / or the device area.

[0022] In an embodiment, the thickness of the one or more dielectric insulating layers outside device area may be selected between 10 and 1000 nanometers, preferably between 50 and 500 nanometers, more preferably between 80 and 200 nanometers.

[0023] In an embodiment, the semiconductor substrate may comprise a semiconductor heterostructure, preferably a buried semiconductor heterostructure, for example a SiGe / Ge, SiGe / Si, Si, Ge, GaAs, InAs, InSb heterostructure.

[0024] In an embodiment, at cryogenic temperatures a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) may be formed in the semiconductor heterostructure.

[0025] In an embodiment, the 2DEG / 2DHG may be formed in the semiconductor heterostructure, preferably a group lll-IV semiconductor heterostructure such as a GaAs heterostructure, at zero gate voltage

[0026] In an embodiment, the 2DHG may be formed in the semiconductor heterostructure, preferably a group IV semiconductor heterostructure such as a SiGe / Ge or SiGe / Si heterostructure, at a predetermined gate voltage.

[0027] The invention will be further illustrated with reference to the attached drawings, which schematically will show embodiments according to the invention. It will be understood that the invention is not in any way restricted to these specific embodiments.

[0028] Brief description of the drawings

[0029] Fig. 1 depicts a schematic of a known semiconductor structure comprising a qubit circuit connected to an on-chip electrostatic discharge protection circuit; Fig. 2 depicts semiconductor structure comprising a qubit circuit connected to an on-chip electrostatic discharge protection circuit according to an embodiment;

[0030] Fig. 3 depicts semiconductor structure comprising a qubit circuit connected to an on-chip electrostatic discharge protection circuit according to another embodiment;

[0031] Fig. 4 depicts semiconductor structure comprising a qubit circuit connected to an on-chip electrostatic discharge protection circuit according to another embodiment;

[0032] Fig. 5 depicts semiconductor structure comprising a qubit circuit connected to an on-chip electrostatic discharge protection circuit according to another embodiment;

[0033] Fig. 6A and 6B depict a top view of a semiconductor die comprising a semiconductor structure connected to an on-chip electrostatic discharge protection circuit according to an embodiment;

[0034] Fig. 7A and 7B depict cross-sectional views of a semiconductor die at room temperature and cryogenic temperature respectively comprising on-chip ESD protection elements according to an embodiment;

[0035] Fig. 8 shows the resistance of an ESD-protector element as described with reference to the embodiments in this disclosure as a function of temperature.

[0036] Description of the embodiments

[0037] The embodiments in this application aim to provide effective and scalable on-chip electrostatic discharge (ESD) protection for quantum devices formed in a semiconductor heterostructure. These devices are typically operated at cryogenic temperatures below 10 K, including temperatures below 4K down to 5 mK. The embodiments make use of the native, and / or thermal, and / or optical population of charge carriers of the semiconductor substrate in which the quantum devices are realized. In particular, the embodiments make use of the fact that a semiconductor substrate in which semiconductor quantum devices are realized functions as a negative temperature coefficient (NTC) thermistor allowing ESD protection of the quantum devices at room temperature and normal device operation at cryogenic temperatures. The embodiments use on-chip thermal switches that can be integrated within the semiconductor or quantum circuits, enabling to connect or disconnect certain elements by controlling the temperature. The embodiments include methods for forming and integrating NTC thermistor elements on the quantum chip, providing intrinsic ESD protection during all relevant fabrication, packaging, and handling stages and requiring minimal space and / or additional manufacturing steps. The embodiments further include semiconductor structures comprising qubit devices and on-chip NTC thermistor elements for effective and scalable on-chip ESD protection of the qubit devices.

[0038] Fig. 1 depicts a cross-sectional view of a semiconductor structure comprising a qubit circuit 104 formed in a silicon substrate and an on-chip a ESD protection circuit 106 known from the prior art. Terminals 102 for controlling the qubit circuits are connected to the ESD protection circuit that includes a number carefully designed diodes IO81.3 which is connected to ground 110. At high temperatures the ESD circuit forms a clamping diode to ground thereby effectively limiting the maximum voltage across the device terminals because of electrostatic discharges to which the terminal may be exposed to. In contrast, at low temperatures the clamping voltage of the ESD circuit increases, so that the terminal can be used for controlling the quantum circuit. In order to provide the desired thermal behavior, the ESD circuit needs to be carefully designed and fabricated in terms of number of diodes, geometry of the diodes and dopant concentration, thereby making practical implementations of the circuit challenging and bulky. Moreover, this design relies on change of the threshold voltage of diodes when the circuit is cooled down. However, even at room temperature these circuits have a finite voltage for which there is no conduction. Hence, there is still a chance that unwanted charge can build up.

[0039] Fig. 2 depicts a high-level cross-sectional view of a semiconductor structure comprising a semiconductor device connected to an on-chip electrostatic discharge protection circuit according to an embodiment. Here, the semiconductor structure is formed in a semiconductor substrate. In an embodiment, the semiconductor substrate may be a group IV, a group lll-V or a group ll-VI semiconductor substrate. In an embodiment, the semiconductor substrate may comprise a semiconductor heterostructure, e.g. a SiGe / Ge, SiGe / Si, Si, Ge, GaAs, InAs, InSb heterostructure.

[0040] In an embodiment, the semiconductor heterostructure may be a buried quantum well semiconductor heterostructure. Such buried quantum well semiconductor heterostructure may include a strained quantum well layer provided over a base layer; an insulating inorganic dielectric layer, for example an oxide layer such as an SiO2 layer, an AI2O3 layer or a layer of any other suitable dielectric material, provided over the quantum well layer; and, a semiconductor barrier layer provided between the quantum well layer and the dielectric layer. In an embodiment, the heterostructure may comprise Ge / SiGe or a Si / SiGe heterostructure.

[0041] The semiconductor device formed in the semiconductor substrate can have an arbitrary number of terminals, a terminal is an electrical connection to any part of the semiconductor device including but not limited to electrostatic gates, barrier gates, plunger gates, screening gates, ohmic contacts, source contacts, drain contacts, etc. In some embodiments, the semiconductor device may be semiconductor quantum devices, such as semiconductor quantum dots, which may form a platform for building a semiconductor quantum processing unit (QPU). Examples of semiconductor heterostructures and semiconductor quantum devices formed in such heterostructures are described in the articles by Sammak et al., Shallow and Undoped Germanium Quantum Wells: A Playground for Spin and Hybrid Quantum Technology, Advanced Functional Materials, 29(14), 2019 and Hendrickx et al, A single hole spin qubit, Nature Communications, 3478 (2020).

[0042] Large arrays of semiconductor devices, e.g. quantum devices such as quantum dots, and integrated read-out circuitry, e.g. single-electron or single-hole tunneling (SE / HT) transistors, may be formed in the semiconductor substrate. To that end, a metallization layer including a stack of dielectric layers and patterned metal layers may be formed over the semiconductor substrate. The patterned metal layers at different levels in the stack may be connected to each other using one or more conductive via’s, i.e. conductive holes through one or more dielectric layers, e.g. silicon dioxide and / or silicon nitride layers, connecting patterned metal layers at both side of the one or more dielectric layers. This way, electrodes, e.g. gate electrodes (e.g. plunger gates and barrier gates) and other electrodes, e.g. source and drain electrodes, may be formed to control the quantum devices and read-out circuits. The electrodes formed by the metallization layer may be further connected to input-output pads, e.g. wire bonding pads or bump bonding pads, for chip-to-package connections. The process of forming such a metallization layer is well-known and referred to as a back-end-of-line (BEOL) processing. Examples of large arrays of semiconductor quantum devices comprising electrodes formed through multi-layer metallization structures are described in WO 2023 / 277686 and WO 2023 / 277687, which are hereby incorporated by reference into this application.

[0043] As shown in the figure, the semiconductor structure includes a semiconductor substrate 202 including a device area 204 in which one or more semiconductor devices may be formed. The structure may further include a plurality of (in this example two) electrode terminals 204-I,2formed over the substrate for controlling the quantum device. One or more insulating layers (not shown) may be used to isolate the electrode terminals from the substrate.

[0044] Each electrode terminal may include a device electrode 208-I,2for controlling the semiconductor device. An electrode terminal may further include a galvanic connection 206-I,2to the substrate. In an embodiment, the electrode terminal may be connected through one or more conductive vias in the insulating layers to one or more Ohmic contacts 210-I,2formed in the semiconductor substrate. In an embodiment, the Ohmic contacts may be formed through diffusion of metals into the semiconductor substrate. In case of a SiGe substrate a metal may be diffused into the substrate to form a (germano)-silicide. In another embodiment, the Ohmic contacts may be formed through the definition of highly doped areas in the semiconductor substrate.

[0045] At room temperature, excitations in the heterostructure will cause the semiconductor substrate to have a high conductivity thereby effectively galvanically short circuiting the different terminals of the quantum device via the substrate. This way, the semiconductor substrate provides a low-ohmic shunt between the different electrode terminals, thus keeping the relative potential between the electrode terminals close to zero, protecting the sensitive qubit circuit from breakdown as a result of electrostatic discharges. At low temperatures, the semiconductor substrate freezes out, resulting in a very high resistance between the terminals and thus an effective open circuit between the auxiliary terminals that are connected via the Ohmic contacts to the substrate.

[0046] When all electrode terminals of the device are electrically connected together, the potential of all the electrodes of the device move together so that the potential difference between the terminals will be small and damage, such as breakdown of dielectrics, due to electrostatic discharges is prevented. This way, the semiconductor chip can be handled at room temperature without or at least with a substantial reduction of damage due to electrostatic discharges. This implementation of ESD protection is particularly advantageous when transporting the semiconductor chip, such that no ground reference is present.

[0047] The semiconductor heterostructure substrate effectively acts as an NTC thermistor 212 in the sense that it conducts at room temperature and is highly resistive at cryogenic temperatures. In the latter case, conduction between the different terminals is no longer possible and the potential on the different terminals can be controlled independently, as required for controlling the qubit device.

[0048] Fig. 3 depicts a cross-sectional view of a semiconductor structure comprising a qubit device connected to an on-chip electrostatic discharge protection circuit according to an embodiment. The figure depicts a semiconductor structure including a qubit device and a ESD protective circuit that is similar to the one depicted in Fig. 2. In this embodiment however, each electrode terminal is connected via an auxiliary electrode and a first Ohmic contact 310i to the substrate. The substrate is electrically connected via one or more second Ohmic contacts 3102to ground 314. Hence, in this implementation all electrode terminals are connected via the heterostructure substrate to ground at room temperature so that no charge can build up and they are protected from ESD breakdown and isolated from each other at cryogenic temperatures so that they can be used to control the qubit device. The advantage of keeping a ground contact is to prevent the chip from charging up as a whole, which, when later connected to a groundreference, may lead to a fast discharge.

[0049] As shown in Fig. 2 and Fig. 3 the ESD protective circuit requires a conductive via connecting the electrode terminal via an ohmic contact to the semiconductor heterostructure substrate. In principle, at low temperatures, the high resistive substate ensures electrical isolation of the device terminals and minimization of the influence of the connection to the substrate.

[0050] A further embodiment of a semiconductor structure comprising at least one qubit device connected to an on-chip electrostatic discharge protection circuit is illustrated in Fig. 4A (room temperature) and 4B (cryogenic temperature). The figures illustrate a cross-sectional view of a semiconductor structure comprising a semiconductor substrate 400 and a metallization layer 401 over the substrate. The semiconductor structure may be part of a chip or a chiplet, i.e. a die.

[0051] The semiconductor structure may include one or more device areas 414 in which the quantum devices are located and / or in which the quantum devices can be formed, and one or more fanout areas 416I,2. The fanout areas are areas of the semiconductor structure outside the device areas in which contact pads for the electrode terminals are formed. Hence, the fanout areas are peripheral areas of the semiconductor structure in which metal interconnects can be formed that connect the electrodes to contact pads 406-I,2formed over the metallization layer. The contact pads may be conductive pads for connecting the die though a suitable bonding technique, e.g. wire bonding or bump bonding, to other elements, e.g. a PCB or a packaging structure.

[0052] As shown in this figure, an electrode terminal may include a bonding pad 406-I,2, a fanout electrode 408-I,2extending from the bonding pad over part of the fanout area towards the device area. One or more first conductive vias 410-I,2 through the metallization layer may connect a first part of a fanout electrode that is located over or close to the device area to a gate electrode 412-I,2formed on top of a dielectric gate layer 411i,2above the device area. The gate electrode may be formed close to the surface of the semiconductor substrate, wherein the dielectric gate layer 411i,2separates the gate electrode from the semiconductor substrate. The thickness of the dielectric gate layer may be selected such that the electrode can sufficiently control and / or form a (part of a) quantum device below it. Further, a second part of the fanout electrode that is positioned above the fanout area may be connected to an Ohmic contact 402-i,2, e.g. through the formation of in-diffused (germano)-silicides or highly-doped regions, in the fanout area of the substrate through one or more second conductive vias 404-I,2so that - at room temperature - the electrode terminals are all shunted at the same potential level. In an embodiment, the second part of the fanout electrode may be located under or close to the bonding pad 406-I,2.

[0053] In an embodiment, the metallization layer may include one or more dielectric layers 401 and fanout electrodes 408-I,2formed over the semiconductor substrate wherein the first and second conductive vias 404I,2, 410I,2connect the fanout electrodes to the semiconductor substrate and gate electrodes 410I,2respectively.

[0054] In another embodiment, the metallization layer may include a stack of alternating dielectric layers and patterned metal layers, wherein conductive vias are used to connect the patterned metal layers to form electrodes including the fanout electrodes in the fanout area and gate electrodes in the device area. The metallization layer may be formed using a BEOL process or any other process that is suitable for forming metal-dielectric metallization structures on a semiconductor substrate. Hence, in this embodiment, the fanout electrodes, the first and second vias and the gate electrode may be part of a multilayer dielectric / metal metallization layer formed by any suitable process, e.g. a BEOL process.

[0055] In the embodiment as shown in Fig. 4A and 4B, the bonding pads 406-I,2and the vias connecting the fanout electrode to the Ohmic contact may be formed in the fanout areas 416I,2away from the device area to minimize influence of the connection of the electrode terminal to the substrate. The fanout electrode may be formed over and / or formed in an upper-part of the metallization stack (e.g. one of the metal layers in the upper part of the stack of alternating dielectric I metallic layers forming the metallization layer), so that the distance between the fanout electrode and the surface of the semiconductor heterostructure substrate is relatively large. At least one via through the dielectric layers over and / or close by the device area may be used to connect the fanout electrode to the gate electrode close to the surface of the semiconductor substrate.

[0056] Hence, forming the fanout electrode over a relatively thick dielectric layer or in one of the upper layers of a BEOL-type metallization layer provides a distance between the fanout electrode and the semiconducting substrate, thereby reducing the effective lever arm of the gate in this area, as compared to the lever arm of the gate in the device area.

[0057] Alternatively and / or in addition, different oxides with different dielectric constants for both types of dielectrics may be used to further enhance lever arm discrimination between the two areas. For example a high-k gate dielectric (for example AI2O3) and a low-k BEOL dielectric (for example SiO2) for the dielectric layers in the fanout area.

[0058] This will reduce the effective electric field underneath the BEOL structures experienced in the substrate at a certain gate voltage. Here, the distance between the fanout electrode and semiconductor substrate is significantly larger than the distance between the gate electrode and the semiconductor substrate. The gate oxide is selected to be thin enough to ensure that the gates do have sufficient influence on the conductance of the substrate in the device area. At cryogenic temperatures (when the electrode terminals are electrically isolated from each other), this structure ensures an effective working range of gate voltage where accumulation 418I,2is achieved in the device area, but no accumulation is achieved in fanout areas (as shown in Fig. 4B).

[0059] Fig. 5A and 5B depict a semiconductor structure comprising at least one qubit device connected to an on-chip electrostatic discharge protection circuit according to an embodiment, wherein Fig. 5A illustrates the structure at room temperature and 5B at cryogenic temperature. In this embodiment, the semiconductor structure includes a semiconductor substrate that includes a device area 514 in which one or more semiconductor devices, including semiconductor quantum devices, are formed or can be formed. One or more dielectric layers may be formed over the semiconductor substrate. The structure further includes electrode terminals that may include contact pads 506-i,2, fanout electrodes 508-I,2connecting the contact pads to gate electrodes 512I,2in the device area. Further, one or more conducting via’s 504-I,2may connect each electrode terminal via an Ohmic contact 502-I,2to the semiconductor substrate so that the electrode terminals are electrically connected to each other at room temperature.

[0060] The semiconductor structure may further include one or more depletion gates 514I,2to locally introduce depletion zones 520-I,2in the semiconductor substrate to stop or at least substantially reduce unwanted current paths between different electrode terminals and / or the device area. This embodiment is especially advantageous if no thick dielectric layer is available that can be used to create a large separation between the fanout electrode elements and the device area, or when the semiconductor substrate, for example a semiconductor heterostructure, operates in a so-called ‘always on’ regime, wherein at cryogenic temperatures a two-dimensional electron gas (2DEG) or two- dimensional hole gas (2HG) is formed in the heterostructure substrate at zero gate voltage. Such semiconductor heterostructure substrates may include lll-V heterostructures, such as GaAs and InP heterostructures.

[0061] The depletion gates 514I,2that are located between the ESD protection elements, and the device area can be biased oppositely of the gate electrodes for controlling a quantum device. This way, a local depletion area 520-I,2may be formed that stops or at least substantially reduces unwanted current paths between the Ohmic contact of the ESD protector element and the device area.

[0062] In further embodiments, local insulating areas 516I,2may be included in the semiconductor substrate. For example, in an embodiment, trenches in the semiconductor substrate that can be filled with a dielectric insulating material, e.g. silicon oxide and / or silicon nitride, may be formed close to the ohmic contacts and / or device area to stop or substantially reduce unwanted current paths between the Ohmic contact of the ESD protector element and the device area.

[0063] The embodiments shown in Fig. 4 and 5 are non-limiting examples of on-chip ESD protection elements for quantum devices that operate at cryogenic temperatures and many further embodiments are foreseen without departing from the gist of the invention. For example, in further embodiments, features from the embodiments of Fig. 5 may be used in the semiconductor structure of Fig. 4. In particular, fanout electrodes as described with reference to Fig. 4, which are formed over a relatively thick dielectric layer or formed in the upper layers of a multilayer dielectric I metallic metallization layer, may be combined with depletion electrodes and / or local insulating areas as explained with reference to Fig. 5.

[0064] Fig. 6A and 6B schematically depicts a top view of a semiconductor die comprising a semiconductor structure connected to an on-chip electrostatic discharge protection circuit according to an embodiment. The semiconductor die may be semiconductor substrate, and a metallization layer as described with reference to the embodiments in this disclosure over the semiconductor substrate. The semiconductor die includes a fanout area 602 including electrode terminals formed over the dielectric insulating layer, each electrode terminal including a bonding pad 6O61.4 connected to a fanout electrode 6IO1.4 which extends towards and over a device area 604. Further, each of electrode terminals may include an on-chip ESD protection element 6O81.4 in the form of one or more galvanic connections between the electrode terminal and the substrate. The galvanic connections may be implemented as conductive vias through the insulating layer connecting the electrode terminal with an Ohmic contact in the substrate.

[0065] As shown in Fig. 6B, the semiconductor substrate acts as an NTC thermistor 612I.4which conducts at room temperature connecting the electrode terminals and which is highly resistive at cryogenic temperatures so that each of the electrodes are electrically isolated from each other.

[0066] Fig. 7A and 7B depict cross-sectional views of a semiconductor die at room temperature and cryogenic temperature respectively comprising on-chip ESD protection elements according to an embodiment. As shown in Fig. 7A, the semiconductor die includes terminals 708I_4provided over a dielectric insulating layer 702. Conductive via’s 706I.4galvanically connect the terminals to the substrate, which is conductive at room temperature thus forming a conductive path 704 between the terminals. The devices here are shown as packaged, meaning that the substrate is attached to a frame or PCB and to ground, the terminals are wire bonded to a PCB. At cryogenic temperatures the substrate becomes highly resistive effectively isolating the terminals that have a galvanic connection to the substrate.

[0067] Fig. 8 shows the resistance of an ESD-protector element as described with reference to the embodiments in this disclosure as a function of temperature. The graph shows a low resistance connection at room temperature and a very high resistance (higher than can be determined experimentally) at low temperatures.

[0068] The description and drawings merely illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. More generally, the concept of the invention can be applied to components based on semiconductor materials of column V, columns lll-V, and to any compatible substrate.

[0069] Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

Claims

CLAIMS1 . A semiconductor structure, preferably a semiconductor die, comprising: a semiconductor substrate comprising a device area; one or more dielectric insulating layers over the semiconductor substrate; a plurality of electrode terminals for controlling one or more semiconductor devices, preferably semiconductor quantum devices, in the device area, the electrode terminals being formed in or over the one or more dielectric insulating layers in an fanout area of the semiconductor area outside the device area, the electrode terminals extending from the fanout area towards the device area; each electrode terminal being connected to the semiconductor substrate through a galvanic connection formed in the one or more dielectric insulating layers in the fanout area; and, the semiconductor substrate being configured as an NTC thermistor and the galvanic connections electrically connecting the electrode terminals at room temperature to each other via the semiconductor substrate.

2. The semiconductor structure according to claim 1 , wherein the galvanic connection in the fanout area includes at least a first conductive via through the one or more dielectric layers and an ohmic contact in the semiconductor substrate connecting the conductive via to the semiconductor substrate.

3. The semiconductor structure according to claim 2 wherein the galvanic connection includes a metal diffused area in the semiconductor substrate.

4. The semiconductor structure according to any of claims 1-3 wherein each electrode terminal includes a bonding pad and a fanout electrode extending from the bonding pad to the device area, the fanout electrode electrically connecting the bonding pad to a gate electrode in the device area, a gate dielectric layer separating the gate electrode from the semiconducting surface.

5. The semiconductor structure according to claim 4 wherein at least a second conductive via through the one or more dielectric insulating layers electrically connects an end of the fanout electrode at the device area to the gate electrode.

6. The semiconductor structure according to claims 4 or 5 wherein the thickness of the one or more dielectric insulating layers in the fanout area separating the fanout electrode from the surface of the semiconductor substrate is larger than the thickness of the dielectric gate layer separating the gate electrode from the surface of the semiconductor substrate.

7. The semiconductor structure according to any of claims 1-6 wherein the one or more dielectric insulating layers are part of a metallization layer comprising an alternating stack of dielectric layers and patterned metal layers.

8. The semiconductor structure according to any of claims 1-7 wherein the metallization layer in at least the fanout area is a back-end-of-line (BEOL) metallization layer, preferably the fanout electrode being formed in one of the upper layers of the BEOL metallization layer.

9. The semiconductor structure according to any of claims 1-8 further comprising: one or more depletion gates for introducing one or more depletion zones in the semiconductor substrate to minimize conductive paths in the semiconductor substrate between the plurality of electrode terminals.

10. The semiconductor structure according to any of claims 1-9 further comprising: one or more insulating areas, preferably silicon oxide areas, formed in the semiconductor substrate to minimize conductive paths in the semiconductor substrate between the plurality of electrode terminals.11 . The semiconductor structure according to any of claims 1-10 wherein the thickness of the one or more dielectric insulating layers outside the device area is selected between 10 and 1000 nanometers, preferably between 50 and 500 nanometers, more preferably between 50 and 200 nanometers.

12. The semiconductor structure according to any of claims 1-11 wherein the dielectric constant of the one or more dielectric insulating layers outside the device area is selected to be smaller than the dielectric constant of the insulating layer within the device area, preferably the dielectric constant of the one or moredielectric insulating layers being a factor 3, preferably 10, more preferably 50, smaller than the than the dielectric constant of the insulating layer within the device area.

13. The semiconductor structure according to any of claims 1-12 wherein the semiconductor substrate comprises a semiconductor heterostructure, preferably a buried semiconductor heterostructure, for example a SiGe / Ge, SiGe / Si, Si, Ge, GaAs, InAs, InSb heterostructure.

14. The semiconductor structure according to claim 13 wherein at cryogenic temperatures a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG) is formed in the semiconductor heterostructure.

15. The semiconductor structure according to claim 14 wherein the 2DEG / 2DHG is formed in the semiconductor heterostructure, preferably a group lll-IV semiconductor heterostructure such as a GaAs heterostructure, at zero gate voltage or wherein the 2DEG / 2DHG is formed in the semiconductor heterostructure, preferably a group IV semiconductor heterostructure such as a SiGe / Ge or SiGe / Si heterostructure, at a predetermined gate voltage.

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