Semiconductor laser element manufacturing method

Abstract

This semiconductor laser element manufacturing method is for forming a semiconductor mesa (M) on a substrate (2) by etching an object (10) that includes a substrate (2), which has a main surface (2s), and a semiconductor lamination part (30), which includes an active layer for a semiconductor laser and which is laminated on the main surface (2s) along a first direction (Z-axis direction) intersecting the main surface (2s), the semiconductor laser element manufacturing method comprising: a first step (S104) for forming a first resist (R2) on a surface (30s) of the semiconductor lamination part (30); a second step (S105) for forming a second resist (R3) from the first resist (R2) by heat-treating the first resist (R2) after the first step (S104); and a third step (S106) for forming the semiconductor mesa (M) by using the second resist (R3) to etch the object (10).

Description

Method for manufacturing semiconductor laser device

[0001] The present disclosure relates to a method for manufacturing a semiconductor laser device.

[0002] Patent Document 1 describes a method for manufacturing a laser diode. In this manufacturing method, first, a wafer including an n-type GaAs substrate, an n-type first semiconductor stacked portion stacked on the n-type GaAs substrate, and a second stacked portion stacked on the first semiconductor stacked portion and including a CdZnAs quantum well layer is prepared. Subsequently, a photoresist mask stripe is patterned on a part of the second stacked portion. Then, the second stacked portion is etched by ion beam etching using this photoresist mask stripe to form a mesa.

[0003] Japanese Patent Publication No. 8-506694

[0004] When the second stacked portion has a mesa planned region where a mesa (the above-mentioned mesa) is to be formed and a peripheral region extending outward from the mesa planned region as in the manufacturing method described in Patent Document 1 above, and a resist mask is formed only on the mesa planned region, the angle of the outer surface (the side surface on the peripheral region side) of the resist mask from the surface of the second stacked portion may be larger than the desired angle. And in etching using such a resist mask, it becomes difficult to form a tapered mesa having a desired angle. Therefore, in the above technical field, it is desirable to form a suitable resist mask such that the angle of the outer surface becomes the desired angle.

[0005] Therefore, an object of the present disclosure is to provide a method for manufacturing a semiconductor laser device capable of forming a suitable resist.

[0006] The semiconductor laser device manufacturing method according to the present disclosure is a method for manufacturing a semiconductor laser device by etching an object having a substrate having a main surface and a semiconductor laminated portion having an active layer for a semiconductor laser and being laminated on the main surface along a first direction intersecting the main surface, comprising: a first step of forming a first resist on the surface of the semiconductor laminated portion; a second step of forming a second resist from the first resist by performing a heat treatment on the first resist after the first step; and a third step of forming the semiconductor mesa by etching the object using the second resist, wherein the semiconductor laminated portion, when viewed from a second direction intersecting the first direction, has a mesa planned region where the semiconductor mesa is to be formed and the mesa planned region The semiconductor laser device manufacturing method comprises a first resist, which includes a peripheral region extending outside the mesa planned region, and includes a first portion provided continuously on the mesa planned region and the peripheral region when viewed from the second direction, and a second portion provided on the first portion in the mesa planned region so as to expose the first portion in the peripheral region; a second resist, which is formed by performing the heat treatment such that the angle of the outer surface of the second portion from the surface decreases when viewed from the second direction; and a third resist, which is formed by etching, which has a taper in which the width in a third direction intersecting the first and second directions decreases as it moves away from the substrate along the first direction.

[0007] In this manufacturing method, first, in the first step, a first resist is formed including a first portion continuously formed in the mesa planned region of the semiconductor stack and the peripheral region outside the mesa planned region, and a second portion provided on the first portion in the mesa planned region so as to expose the first portion in the peripheral region. Subsequently, in the second step, the first resist is heat-treated to form a second resist. Here, the outer surface of the second portion does not directly reach the surface of the semiconductor stack, but reaches the first portion which is the resist. In this case, compared to the case where the outer surface of the resist on the mesa planned region directly reaches the surface of the semiconductor stack, the angle of the outer surface of the second portion can be made smaller by the heat treatment. That is, in the second step, the heat treatment is performed so as to reduce the angle of the outer surface of the second portion from the surface of the semiconductor stack when viewed from a second direction, thereby suitably forming the second resist. As a result, in the subsequent third step, by etching the target object using the second resist thus formed, it is possible to suitably form a semiconductor mesa having a taper of a desired angle.

[0008] The semiconductor laser device manufacturing method according to this disclosure may also be [2] "the semiconductor laser device manufacturing method according to [1] above, wherein the etching is dry etching." In this case, for example, by setting the taper angles of each part of the semiconductor mesa to a desired angle, it is possible to suppress the taper angles of each part of the semiconductor mesa being different from each other, and to suitably form the semiconductor mesa.

[0009] The semiconductor laser device manufacturing method according to this disclosure may also be [3] "the semiconductor laser device manufacturing method according to [1] or [2] above, wherein the semiconductor stack portion and the semiconductor mesa include a plurality of active layers stacked in the first direction." In this way, by including a plurality of active layers (the semiconductor laser is of a multi-stage stack type), even when deeper etching is required, the taper angles of each part of the semiconductor mesa can be formed to a desired angle, for example, and the semiconductor mesa can be suitably formed.

[0010] The semiconductor laser element manufacturing method according to this disclosure may also be [4] "the semiconductor laser element manufacturing method according to any one of [1] to [3] above, wherein the outer surface has a curvature such that it is convex toward the outside of the second portion." In this case, it is possible to suppress the taper angle at the top of the semiconductor mesa from becoming larger than the taper angle at the middle or base of the semiconductor mesa.

[0011] The semiconductor laser element manufacturing method according to this disclosure may also be [5] "the semiconductor laser element manufacturing method according to any one of [1] to [4] above, wherein the angle of the outer surface from the surface is 30° or less." In this case, by setting the taper angle of the semiconductor mesa to a desired angle, the oscillation stability is improved by suppressing unintended modes.

[0012] The semiconductor laser element manufacturing method according to this disclosure may also be [6] "the semiconductor laser element manufacturing method according to any one of [1] to [5] above, wherein, when viewed from the second direction, the angle of the taper from the main surface is 60° or more and 70° or less." In this case, by setting the taper angle of the semiconductor mesa to a desired angle, the stability of oscillation is improved by suppressing unintended modes.

[0013] The semiconductor laser element manufacturing method according to this disclosure may also be [7] "the semiconductor laser element manufacturing method according to any one of [1] to [6] above, wherein in the second step, the heating treatment is performed such that, when viewed from the second direction, the angle of the outer surface from the surface gradually decreases as it moves inward from the outer edge of the planned mesa region." In this case, the taper angle at the top of the semiconductor mesa can be made smaller than the taper angles at the base and middle of the semiconductor mesa, making it less likely for the upper corner of the semiconductor mesa to chip. Also, for the same reason, when forming a film on the semiconductor mesa, it becomes less likely for the film to break or peel off.

[0014] The semiconductor laser element manufacturing method according to the present disclosure may also be [8] "the semiconductor laser element manufacturing method according to any one of [1] to [7] above, wherein in the second step, the second resist is formed such that the surface of the second resist at the connection portion between the first portion and the second portion is curved inward toward the inside of the second resist." In this case, etching using such a second resist makes it possible to make the connection portion between the substrate and the base of the semiconductor mesa have a curvature that is convex toward the inside of the connection portion when viewed from the second direction, thereby suppressing stress concentration at the base of the semiconductor mesa.

[0015] The semiconductor laser element manufacturing method according to this disclosure may also be the semiconductor laser element manufacturing method according to any one of [1] to [8] above, wherein, when viewed from the second direction, the taper has a straight portion. In this case, the beam quality is better compared to the case where the taper has curvature throughout the semiconductor mesa.

[0016] The semiconductor laser element manufacturing method according to this disclosure may also be

[10] "the semiconductor laser element manufacturing method according to any one of [1] to [9] above, wherein, when viewed from the second direction, the taper is linear, and in the third step, etching is performed so that the linear taper reaches the substrate." In this case, the beam quality is improved. In addition, in this case, the point of change in the angle of the taper of the semiconductor mesa can be moved away from the emitter, so stress concentration is suppressed and reliability is improved.

[0017] This disclosure provides a method for manufacturing a semiconductor laser device capable of forming a suitable resist.

[0018] Figure 1 is a cross-sectional view showing an example of a semiconductor laser element that can be manufactured by the semiconductor laser element manufacturing method according to this embodiment. Figure 2 is a diagram showing one step of the semiconductor laser element manufacturing method according to this embodiment. Figure 3 is a diagram showing one step of the semiconductor laser element manufacturing method according to this embodiment. Figure 4 is a diagram showing one step of the semiconductor laser element manufacturing method according to this embodiment. Figure 5 is a diagram showing one step of the semiconductor laser element manufacturing method according to this embodiment. Figure 6 is an SEM image showing a semiconductor mesa formed by etching. Figure 7 is another SEM image showing a semiconductor mesa formed by etching.

[0019] A semiconductor laser element manufacturing method according to one embodiment will be described below with reference to the drawings. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numeral, and redundant explanations may be omitted. In addition, each figure may show a Cartesian coordinate system defined by the X, Y, and Z axes.

[0020] Figure 1 is a cross-sectional view showing an example of a semiconductor laser element that can be manufactured by the semiconductor laser element manufacturing method according to this embodiment. As shown in Figure 1, the semiconductor laser element 1 comprises a semiconductor substrate 2 (substrate) and a semiconductor laminated portion 3 stacked on the semiconductor substrate 2. Here, the Z-axis direction (first direction) is defined as the thickness direction of the semiconductor substrate 2, the direction parallel to the optical waveguide direction (resonator length direction) of the semiconductor laminated portion 3 is defined as the X-axis direction (second direction), and the direction intersecting the thickness direction and the optical waveguide direction (X-axis direction) is defined as the Y-axis direction (third direction). The semiconductor laminated portion 3 is stacked on the semiconductor substrate 2 along the Z-axis direction, and the multiple layers included in the semiconductor laminated portion 3 are stacked along the Z-axis direction.

[0021] The semiconductor laser element 1 is configured as an end-face emission type laser diode that resonates laser light between the end faces of semiconductor stacked portions 3 facing each other in the X-axis direction and emits laser light from one end face along the X-axis direction. The length of the semiconductor laser element 1 in the X-axis direction (resonator length) is, for example, 0.5 mm to 2.0 mm, and in this embodiment, it is 1.0 mm as an example. The width of the semiconductor laser element 1 in the Y-axis direction is, for example, 300 μm to 1000 μm, and in this embodiment, it is 500 μm as an example.

[0022] The semiconductor substrate 2 is, for example, a GaAs substrate formed of GaAs. The semiconductor substrate 2 has a surface (main surface) 2s on which the semiconductor laminate 3 is formed, and a back surface 2r opposite to the surface 2s. The Z-axis direction is the direction that intersects (is perpendicular to) the surface 2s. For example, the surface 2s of the semiconductor substrate 2 is the (100) plane. That is, the Z-axis direction perpendicular to the surface 2s may be the direction parallel to the

[100] direction of the semiconductor substrate 2.

[0023] The semiconductor stacked portion 3 is stacked on the surface 2s along the Z-axis direction. The semiconductor stacked portion 3 has a top surface 3t on the side opposite to the side facing the surface 2s, and an outer surface 3a that intersects in the Y-axis direction. The outer surface 3a is provided continuously with the side surface 2c of the semiconductor substrate 2. That is, at the connection portion (boundary portion) between the outer surface 3a and the side surface 2c, the outer surface 3a is smoothly connected to the side surface 2c. The outer surface 3a of the semiconductor stacked portion 3 and the portion of the side surface 2c of the semiconductor substrate 2 that is continuous with the outer surface 3a are configured as inclined surfaces that are tilted with respect to the Z-axis direction by etching, which will be described later.

[0024] More specifically, the outer surface 3a is inclined with respect to the Z-axis direction such that it is directed outward in the Y-axis direction relative to the center of the semiconductor laser element 1 as it moves from the semiconductor stacking portion 3 side toward the semiconductor substrate 2 side along the Z-axis direction. As a result, the semiconductor stacking portion 3 is formed in a mesa shape. That is, the semiconductor stacking portion 3 constitutes a semiconductor mesa M having a taper T in which the width in the Y-axis direction decreases as it moves away from the semiconductor substrate 2 along the Z-axis direction when viewed from the X-axis direction. The semiconductor mesa M is formed extending from the semiconductor stacking portion 3 to the semiconductor substrate 2. In other words, a portion of the semiconductor substrate 2 on the semiconductor stacking portion 3 side also constitutes the semiconductor mesa M.

[0025] Viewed from the X-axis direction, the angle θt of the taper T from the surface 2s of the semiconductor substrate 2 (i.e., the outer surface 3a of the semiconductor stacked portion 3) is, for example, 60° or more and 70° or less. In other words, the outer surface 3a of the semiconductor stacked portion 3 and the portion of the side surface 2c of the semiconductor substrate 2 that is continuous with the outer surface 3a are inclined surfaces that are tilted with respect to the Z-axis direction such that the angle from the surface 2s is angle θt. Furthermore, when viewed from the X-axis direction, the semiconductor mesa M is symmetrical with respect to a center line along the Z-axis direction that passes through the center of the semiconductor mesa M in the Y-axis direction, and is formed in a trapezoidal shape overall.

[0026] The edges of the top surface 3t of the semiconductor stack 3 in the Y-axis direction, the entire outer surface 3a of the semiconductor stack 3, and the portion of the side surface 2c of the semiconductor substrate 2 that is continuous with the outer surface 3a are covered with an insulating film 4. The insulating film 4 can be formed from, for example, a silicon nitride film or a silicon oxide film. The portion of the insulating film 4 that covers the top surface 3t is provided with an opening 4a to expose a part of the top surface 3t (in this embodiment, the central part of the top surface 3t in the Y-axis direction). The opening 4a has a constant width in the Y-axis direction and extends in the X-axis direction.

[0027] The semiconductor laser element 1 includes electrodes 5 and 6. Electrode 5 contacts the top surface 3t through an opening 4a in the insulating film 4 and is formed to cover at least a portion of the portion of the insulating film 4 that covers the top surface 3t. The contact surface between electrode 5 and the top surface 3t extends in the X-axis direction, and laser resonance occurs along the X-axis direction. Electrode 6 is provided on the back surface 2r of the semiconductor substrate 2. Electrode 5 may be formed from, for example, Ti / Pt / Au. Electrode 6 may be formed from, for example, AuGe / Ni / Au.

[0028] As an example, the semiconductor stacked portion 3 has the following layers stacked in this order on the surface 2s of the semiconductor substrate 2: a lower first cladding layer 301, a lower active layer 302 (active layer), a lower second cladding layer 303, a lower tunnel barrier layer 304, an intermediate first cladding layer 305, an intermediate active layer 306 (active layer), an intermediate second cladding layer 307, an intermediate tunnel barrier layer 308, an upper first cladding layer 309, an upper active layer 310 (active layer), an upper second cladding layer 311, and a contact layer 312. The semiconductor stacked portion 3 can be formed, for example, by growing each layer on the surface 2s of the semiconductor substrate 2 using the MOCVD (metal-organic vapor deposition) method.

[0029] In this embodiment, as an example, the semiconductor stack 3 includes a plurality (three in this case) of active layers. That is, the semiconductor laser element 1 is a multi-stage stack type. The semiconductor laser element 1 can be considered as a series connection of a first laser diode including an upper first cladding layer 309, an upper active layer 310, and an upper second cladding layer 311, a second laser diode including an intermediate first cladding layer 305, an intermediate active layer 306, and an intermediate second cladding layer 307, and a third laser diode including a lower first cladding layer 301, a lower active layer 302, and a lower second cladding layer 303. By flowing a current in the forward direction from electrode 5 (the electrode on the P-type semiconductor side) to electrode 6 (the electrode on the N-type semiconductor side), each of the first to third laser diodes emits light and emits laser light L in the X-axis direction.

[0030] Table 1 shows an example of the thickness of each layer constituting the semiconductor stacked portion 3, the preferred range of thickness, and the combination of conductivity types.

[0031] Table 2 shows an example of the combination of materials and impurity concentrations for each layer constituting the semiconductor stacked portion 3.

[0032] The above example is an example where the semiconductor laser element 1 has a three-stage stack structure. However, the semiconductor laser element 1 may have, for example, a five-stage stack structure. In this case, the semiconductor laser element 1 may further include a two-stage stack structure below the lower first cladding layer 301, consisting of semiconductor layers equivalent to the lower first cladding layer 301, lower active layer 302, lower second cladding layer 303, and lower tunnel barrier layer 304. The following describes the case where the semiconductor laser element 1 has such a five-stage stack structure. The semiconductor laser element 1 may also have a four-stage stack structure, a six-stage stack structure, or a seven-stage stack structure.

[0033] Next, an example of a method for manufacturing the semiconductor laser element 1 will be described. Figures 2 to 5 are diagrams showing one step of the method for manufacturing the semiconductor laser element according to this embodiment. Figure 4(b) is an SEM image, and the others are schematic cross-sectional views. In this method, first, as shown in Figure 2(a), a workpiece 10 to be processed, which will be the basis for the semiconductor laser element 1, is prepared (step S101).

[0034] The object 10 comprises a semiconductor substrate 2 having a surface 2s, and a semiconductor laminate 30 stacked on the surface 2s of the semiconductor substrate 2 along the Z-axis direction. The semiconductor laminate 30 is an epitaxial growth layer having a layer structure similar to that of the semiconductor laminate 3 described above. The semiconductor laminate 30 includes a surface 30s that includes a region that will later become the top surface 3t of the semiconductor laminate 3, and a back surface 30r opposite to the surface 30s.

[0035] The semiconductor stacked portion 30 includes a mesa-planned region 31 where a semiconductor mesa M is to be formed, and a peripheral region 32 extending from the mesa-planned region 31 to the outside of the mesa-planned region 31, as viewed from the X-axis direction intersecting the Z-axis direction. Although not shown in the figure, the peripheral region 32 is provided on both sides of the mesa-planned region 31 as viewed from the X-axis direction. The semiconductor stacked portion 30 can include multiple sets of mesa-planned regions 31 and peripheral regions 32. In this case, the object 10 may be a wafer containing regions that will become multiple semiconductor laser elements 1.

[0036] Next, as shown in Figure 2(b), a resist R1 is formed (film-formed) on the surface 30s of the semiconductor stacked portion 30 (step S102, first step). The resist R1 is used as an etching mask in a later step, and in this case, it is a photoresist. In step S102, the resist R1 is formed continuously on at least the mesa planned region 31 and the surrounding region 32. Note that there may be areas outside the surrounding region 32 where the resist R1 is not provided.

[0037] Next, as shown in Figure 3(a), a photomask is placed on the mesa planned region 31, and the resist R1 is exposed using the photomask to form an exposure region P0 on the resist R1 (step S103: first step). The exposure region P0 is a region of the resist R1 where the exposure amount exceeds a threshold exposure amount and can be dissolved in the subsequent development step. Here, the exposure region P0 is made so as not to reach the surface 30s of the semiconductor stack 30 in the Z-axis direction by adjusting the distance of the photomask from the resist R1 and the exposure amount.

[0038] Next, as shown in Figure 3(b), resist R1 is developed to form resist R2 (first resist) from resist R1 (step S104: first step). In step S104, the exposure region P0 formed in step S103 is dissolved in the developer to form resist R2. As described above, the exposure region P0 is located in the peripheral region 32 and does not reach the surface 30s of the semiconductor laminate 30. Therefore, after development in step S104, a thinned resist portion remains on the peripheral region 32.

[0039] In other words, the resist R2 formed in step S104 includes a first portion P1 that is continuously provided on the mesa planned region 31 and the peripheral region 32 when viewed from the X-axis direction, and a second portion P2 provided on the first portion P1 in the mesa planned region 31 such that the first portion P1 is exposed in the peripheral region 32. Thus, the resist R2 is relatively thin on the peripheral region 32 and relatively thick on the mesa planned region 31. At least on the peripheral region 32, the thickness of the first portion P1 in the Z-axis direction is substantially constant. The second portion P2 has an outer surface P2s that intersects the Y-axis direction when viewed from the X-axis direction, and this outer surface P2s has an angle θr from the interface between the first portion P1 and the second portion P2 (the surface of the first portion P1). Here, the interface between the first portion P1 and the second portion P2 is substantially parallel to the surface 30s of the semiconductor stack 30. Therefore, the angle θr is the angle from the surface 30s of the outer surface P2s.

[0040] Next, as shown in Figure 4(a), a heat treatment (post-bake) is performed on the resist R2 to form resist R3 (second resist) from resist R2 (step S105: second step). More specifically, in step S105, resist R3 is formed by performing a heat treatment such that the angle θr from the surface 30s of the outer surface P2s of the second portion P2 becomes smaller when viewed from the X-axis direction (i.e., the inclination angle of the outer surface P2s with respect to the Z-axis direction becomes larger when viewed from the X-axis direction). As a result, at least after this heat treatment, the outer surface P2s becomes an inclined surface with respect to the Z-axis direction.

[0041] As an example, before the heat treatment in step S105, the outer surface P2s is a vertical plane along the Z-axis direction (i.e., the angle θr is 90°), and the angle θr becomes smaller due to the heat treatment in step S105, so that the outer surface P2s becomes an inclined surface. However, even before the heat treatment in step S105, the angle θr may be less than 90° and the outer surface P2s may be an inclined surface. That is, in steps S102 to S104, the resist R2 may be formed such that the outer surface P2s becomes an inclined surface. Even in this case, the angle θr becomes smaller due to the heat treatment in step S105, and the outer surface P2s becomes an inclined surface that is more inclined with respect to the Z-axis direction.

[0042] FIG. 4(b) is a SEM image showing an enlarged example of the object after step S105. As shown in FIG. 4(b), as an example, the angle θr of the outer surface P2s can be made 30° or less by the heat treatment in step S105. In the illustrated example, the angle θr is about 10° at the boundary portion (the boundary portion between the mesa planned region 31 and the peripheral region 32) with the first portion P1 on the outer surface P2s. Here, the outer surface P2s (inclined surface) has a curvature so as to be convex toward the outside of the resist R3.

[0043] Therefore, the angle θr gradually decreases as it moves away from (towards the inside) the boundary portion with the first portion P1 of the outer surface P2s. In other words, in step S105, when viewed from the X-axis direction, the heat treatment is performed such that the angle θr gradually decreases as it moves from the outer edge of the mesa planned region 31 towards the inside. Further in other words, in the heat treatment of step S105, the second portion P2 of the resist R3 is made such that its thickness in the Z-axis direction gradually increases as it moves towards the inside. In the example of FIG. 4(b), the angle θr is 10° or less over the entire second portion P2.

[0044] In the subsequent step, as shown in Figures 5(a) and 5(b), the resist R3 formed in step S105 is used as a mask to etch the object 10, thereby forming a semiconductor mesa M (step S106, third step). More specifically, in step S106, the etching forms a semiconductor mesa M (i.e., semiconductor stacked portion 3) having a taper T such that, when viewed from the X-axis direction, the width in the Y-axis direction decreases as it moves away from the semiconductor substrate 2 along the Z-axis direction. The etching in step S106 is an anisotropic dry etching, such as a reactive ion etching such as high-density plasma RIE (Reactive Ion Etching).

[0045] After etching begins in step S106, the mesa area 31 and the surrounding area 32 are covered with resist R3. Therefore, in the mesa area 31 and the surrounding area 32, only the resist R3 is removed first. Subsequently, as etching continues, the relatively thin first portion P1 of the resist R3 on the surrounding area 32 is removed, exposing the surrounding area 32 from the resist R3, and the surrounding area 32 begins to be removed.

[0046] As described above, the thickness of the first portion P1 is approximately constant on the peripheral region 32. Therefore, etching starts and progresses roughly simultaneously across the entire peripheral region 32, forming a substantially flat semiconductor surface in the peripheral region 32. On the other hand, as etching progresses further, the outer edge of the second portion P2 of the resist R3 is gradually removed, causing the outer edge of the mesa area 31 to gradually become exposed from the resist R3, and the mesa area 31 begins to be shaved away. As described above, the second portion P2 of the resist R3 is designed so that its thickness in the Z-axis direction gradually increases as it moves inward. Therefore, in the mesa area 31, as etching progresses, the resist R3 gradually disappears from its outer edge, causing the mesa area 31 to gradually become exposed and shaved away, forming an outer surface 3a and a taper T, which are inclined surfaces with respect to the Z-axis direction.

[0047] Figure 6 is a SEM image (viewed from the X-axis direction) showing a semiconductor mesa formed by etching. As shown in Figure 6, the semiconductor mesa M formed in step S106 has a taper T, and the angle θt of the taper T is 60° or more and 70° or less. The semiconductor mesa M includes a base MA, an intermediate portion MB, and an upper portion MC in order from the semiconductor substrate 2 side. The upper portion MC includes the top surface 3t of the semiconductor stack portion 3.

[0048] When viewed from the X-axis direction, the angle θt of the taper T of the semiconductor mesa M is constant at the base MA. The angle θt of the taper T at the base MA and the intermediate portion MB is, for example, about 65° to 67°. In other words, the taper T has a straight portion where the angle θt is constant. On the other hand, the angle θt of the taper T at the upper portion MC is, for example, about 60° to 63°, which is smaller than the angle θt of the taper T at the base MA and the intermediate portion MB.

[0049] In other words, in step S106, the semiconductor stack portion 30 is etched using the resist R3 so that the angle θt of the taper T becomes smaller at the upper portion MC. For this purpose, in step S105, as described above, the second portion P2 of the resist R3 is heat-treated so that the angle θr gradually decreases as it goes from the outer edge of the mesa planned region 31 toward the inside. In step S106, by transferring the shape of such a second portion P2 of the resist R3 (gradual decrease of the angle θr) to the semiconductor stack portion 30, the relationship of the angle θt of the taper T as described above is formed.

[0050] Also, when viewed from the X-axis direction, the connection portion CP of the semiconductor substrate 2 with the base MA of the semiconductor mesa M has a curvature such that it is convex toward the inside of the connection portion CP. In other words, the surface 2h of the semiconductor substrate 2 (and further, the entire surface 2p formed by etching the semiconductor substrate 2) at the connection portion CP with the semiconductor mesa M is formed in an arc shape that is convex toward the inside of the semiconductor substrate 2.

[0051] This is thought to be partly due to the fact that in the resist R3 used as a mask in step S106, if the surface of the resist R3 at the connection portion between the first portion P1 and the second portion P2 is formed in an arc shape that is convex inward, the shape of the resist R3 is transferred to the semiconductor substrate 2 by etching in step S106. In other words, in step S105, the resist R3 can be formed such that the surface of the resist R3 at the connection portion between the first portion P1 and the second portion P2 is formed in an arc shape that is convex inward.

[0052] As described above, in the semiconductor laser element manufacturing method according to this embodiment, first, in steps S102 to S104, a resist R2 is formed including a first portion P1 continuously formed in the mesa planned region 31 of the semiconductor stacked portion 30 and the peripheral region 32 outside the mesa planned region 31, and a second portion P2 provided on the first portion P1 in the mesa planned region 31 so as to expose the first portion P1 in the peripheral region 32. Subsequently, in step S105, the resist R2 is heat-treated to form a resist R3. Here, the outer surface P2s of the second portion P2 does not directly reach the surface 30s of the semiconductor stacked portion 30, but reaches the first portion P1 which is the resist. In this case, compared to the case where the outer surface P2s of the resist R3 directly reaches the surface 30s of the semiconductor stacked portion 30, the angle θr of the outer surface P2s can be made smaller by the heat treatment. In other words, in step S105, the heat treatment is performed so that the angle θr of the outer surface P2s of the second portion P2 from the surface 30s of the semiconductor laminated portion 30 is reduced when viewed from the X-axis direction, thereby enabling the suitable formation of the resist R3. As a result, in the subsequent step S106, the object 10 is etched using the resist R3 thus formed, thereby enabling the suitable formation of a semiconductor mesa M having a taper T of a desired angle θt.

[0053] Here, as in the manufacturing method described in Patent Document 1 above, if a resist mask is formed on a part of the semiconductor stack (the mesa-planned region where a mesa is to be formed), and the remaining part of the semiconductor stack (the peripheral region of the mesa-planned region) is exposed from the resist mask, it is difficult to process the semiconductor stack with high precision by etching the semiconductor stack using the resist mask.

[0054] In other words, for example, until etching occurs in the mesa area of ​​the semiconductor stack that is exposed by the removal of the resist mask, only the peripheral area of ​​the semiconductor stack that was previously exposed from the resist mask is etched first. As a result, there is a risk that vertical etching will occur on the outer surface of the semiconductor mesa at the base of the semiconductor mesa.

[0055] Another example is to perform a post-bake (heat treatment) of the resist mask in addition to the manufacturing method described in Patent Document 1 above, in order to reduce the angle between the outer surface of the resist mask and the surface of the semiconductor laminate. However, in this case, if the outer surface of the resist mask directly reaches the surface of the semiconductor laminate, the angle between the outer surface and the surface of the semiconductor laminate tends to remain relatively large (the angle does not decrease easily). Therefore, in this case, even immediately after etching begins in the mesa area of ​​the semiconductor laminate that is exposed as etching progresses and the resist mask is removed, etching is performed using the part of the resist mask with a relatively large angle, which may cause pillars to form on the outer surface of the semiconductor mesa in the middle part of the semiconductor mesa.

[0056] Another example is when post-baking is performed on a resist mask. After etching progresses and the resist mask is removed beyond a certain point, etching is performed using a portion of the resist mask with a relatively small angle from the surface of the semiconductor stack. As a result, the outer surface of the semiconductor mesa at the top of the semiconductor mesa becomes an inclined surface with a certain angle. Consequently, the state of the outer surface at the top of the semiconductor mesa may differ from the state of the outer surface at the base and middle of the semiconductor mesa.

[0057] Therefore, in this embodiment, the aim is to improve processing accuracy. Specifically, in the manufacturing method according to this embodiment, in addition to the mesa planned region 31 of the object 10, the surrounding region 32 is also covered with resist R3 (first portion P1). For example, this prevents the situation where only the pre-exposed surrounding region is etched before etching occurs in the mesa planned region. Thus, the occurrence of perpendicular etching on the outer surface of the semiconductor mesa M at the base of the semiconductor mesa is suppressed.

[0058] Furthermore, in the manufacturing method according to this embodiment, the angle θr of the outer surface P2s of the second portion P2 on the mesa planned region 31 of the resist R3 is made smaller by the heat treatment compared to the case where the outer surface P2s directly reaches the surface 30s of the semiconductor laminate 30. For this reason, as an example, even immediately after etching has progressed as described above and etching of the mesa planned region 31 has started, the occurrence of pillars on the outer surface of the semiconductor mesa on the semiconductor mesa side surface, which would otherwise be caused by etching using a portion of the resist with a relatively large angle, is suppressed.

[0059] Furthermore, according to the manufacturing method of this embodiment, as described above, vertical etching and pillar formation are suppressed in the base MA and intermediate MB of the semiconductor mesa M, and a suitable outer surface of the semiconductor mesa M is formed. As a result, the state of the outer surface of the upper MC of the semiconductor mesa M, which is formed as etching progresses further, is suppressed to differ from the state of the outer surface of the base MA and intermediate MB of the semiconductor mesa M.

[0060] Furthermore, in the semiconductor laser element manufacturing method according to this embodiment, etching is dry etching. Therefore, for example, by setting the angle θt of the taper T of each part of the semiconductor mesa M to a desired angle, it is possible to suppress the differences in the angles θt of the taper T of each part of the semiconductor mesa M, thereby enabling the formation of a suitable semiconductor mesa M and further improving processing accuracy.

[0061] Furthermore, in the semiconductor laser element manufacturing method according to this embodiment, the semiconductor stacked portion 30 and the semiconductor mesa M include a plurality of active layers stacked in the Z-axis direction. By including a plurality of active layers in this way (the semiconductor laser is a multi-stage stacked type), even when deeper etching is required, for example, the angle θt of the taper T of each part of the semiconductor mesa M can be formed to a desired angle, thereby enabling the suitable formation of the semiconductor mesa M and reliably improving processing accuracy.

[0062] Furthermore, in the semiconductor laser element manufacturing method according to this embodiment, the outer surface P2s of the second portion P2 of the resist R3 has a curvature such that it is convex toward the outside of the second portion P2. Therefore, it is possible to suppress the angle θt of the taper T at the upper MC of the semiconductor mesa M from becoming larger than the angle θt of the taper T at the intermediate MB and base MA of the semiconductor mesa M.

[0063] Furthermore, in the semiconductor laser element manufacturing method according to this embodiment, the angle from the surface 30s of the outer surface P2s of the second portion P2 is 30° or less. Therefore, by setting the angle θt of the taper T of the semiconductor mesa M to a desired angle, the oscillation stability is improved by suppressing unintended modes.

[0064] Furthermore, in the semiconductor laser element manufacturing method (and semiconductor laser element 1) according to this embodiment, the angle θt of the taper T from the surface 2s of the semiconductor substrate 2, when viewed from the X-axis direction, is 60° or more and 70° or less. Therefore, the stability of oscillation is improved by suppressing unintended modes.

[0065] Furthermore, in the semiconductor laser element manufacturing method according to this embodiment, in step S106, the heat treatment is performed such that the angle θr of the outer surface P2s gradually decreases as viewed from the X-axis direction, moving inward from the outer edge of the planned mesa region 31. This makes the angle θt of the taper T of the upper MC of the semiconductor mesa M smaller than the angle θt of the taper T of the base MA and intermediate MB of the semiconductor mesa M, thus making it less likely for the upper corner of the semiconductor mesa M to chip. Also, for the same reason, when forming a film (e.g., insulating film 4) on the semiconductor mesa M, it becomes less likely for the film to break or peel off.

[0066] Furthermore, in the semiconductor laser element manufacturing method (and semiconductor laser element 1) according to this embodiment, the resist R3 can be formed such that the surface of the resist R3 at the connection portion between the first portion P1 and the second portion P2 is curved in a convex shape toward the inside of the resist R3. In this case, etching using such a resist R3 can make the connection portion Cp between the semiconductor mesa M and the base MA on the semiconductor substrate 2 have a curvature that is convex toward the inside of the connection portion Cp when viewed from the X-axis direction, thereby suppressing stress concentration at the base MA of the semiconductor mesa M.

[0067] Furthermore, in the semiconductor laser element manufacturing method (and semiconductor laser element 1) according to this embodiment, the taper T has a straight portion (base MA) when viewed from the X-axis direction. Therefore, the beam quality is better compared to the case where the taper T has curvature throughout the entire semiconductor mesa M.

[0068] The above embodiments illustrate one aspect of the semiconductor laser device manufacturing method according to this disclosure. Therefore, the semiconductor laser device manufacturing method according to this disclosure is not limited to the above embodiments and can be modified as desired.

[0069] Figure 7 is another SEM image (viewed from the X-axis direction) showing a semiconductor mesa formed by etching. As shown in Figure 7, when viewed from the X-axis direction, the taper T of the semiconductor mesa M is linear overall, and in step S106, etching may be performed so that the linear taper T reaches the semiconductor substrate 2. In this case, the beam quality is improved. Also, in this case, the point of change in the angle θt of the taper T of the semiconductor mesa M can be moved away from the emitter, so stress concentration is suppressed and reliability is improved.

[0070] In the example shown in Figure 7, a state is shown in which multiple semiconductor mesas M are formed on a single semiconductor substrate 2. In this case, between the connection points CP of adjacent semiconductor mesas M in the Y-axis direction, points K that are convex toward the outside of the semiconductor substrate 2 may be formed by connecting the arc-shaped surfaces 2h that are convex toward the inside of the semiconductor substrate 2.

[0071] Furthermore, in the above embodiment, high-density plasma RIE was given as an example of etching in step S106, but the etching in step S106 may be wet etching, chemical etching, plasma etching (PE), capacitive RIE (CCP-RIE), ion milling, sputter etching, etc.

[0072] Furthermore, although the above embodiment described an example in which the semiconductor stacked portion 30 to be etched in step S106 includes multiple active layers, the semiconductor stacked portion 30 may also include a single active layer.

[0073] Furthermore, the angle θr and curvature of the outer surface P2s of the second portion P2 of the resist R3, and the angle θt and curvature of the taper T are not limited to the above example and can be set arbitrarily.

[0074] 1...Semiconductor laser element, 10...Object, 2...Semiconductor substrate, 2s...Surface (main surface), 30...Semiconductor stacked portion, 30s...Surface, 302...Lower active layer (active layer), 306...Intermediate active layer (active layer), 310...Upper active layer (active layer), R2...Resist (first resist), R3...Resist (second resist), P1...First part, P2...Second part, P2s...Outer surface, M...Semiconductor mesa, MA...Base, T...Taper, θr, θt...Angle.

Claims

1. A semiconductor laser element manufacturing method for forming a semiconductor mesa on a substrate by etching an object having a substrate having a main surface and a semiconductor laminated portion having an active layer for a semiconductor laser and laminated on the main surface along a first direction intersecting the main surface, comprising: a first step of forming a first resist on the surface of the semiconductor laminated portion; a second step of forming a second resist from the first resist by performing a heat treatment on the first resist after the first step; and a third step of forming the semiconductor mesa by etching the object using the second resist, wherein the semiconductor laminated portion includes, when viewed from a second direction intersecting the first direction, a mesa planned region on which the semiconductor mesa is to be formed and a peripheral region extending from the mesa planned region to the outside of the mesa planned region, and in the first step, the first resist is formed including, when viewed from the second direction, a first portion continuously provided on the mesa planned region and the peripheral region and a second portion provided on the first portion in the mesa planned region so as to expose the first portion in the peripheral region, A method for manufacturing a semiconductor laser element, comprising: a second step in which the second resist is formed by performing the heat treatment such that the angle of the outer surface of the second portion from the surface becomes smaller when viewed from the second direction; and a third step in which the semiconductor mesa is formed by etching, wherein the width in a third direction intersecting the first and second directions decreases as it moves away from the substrate along the first direction.

2. The semiconductor laser device manufacturing method according to claim 1, wherein the etching is dry etching.

3. The semiconductor laser element manufacturing method according to claim 1 or 2, wherein the semiconductor stacked portion and the semiconductor mesa include a plurality of active layers stacked in the first direction.

4. The method for manufacturing a semiconductor laser element according to any one of claims 1 to 3, wherein the outer surface has a curvature such that it is convex toward the outside of the second portion.

5. The method for manufacturing a semiconductor laser element according to any one of claims 1 to 4, wherein the angle of the outer surface from the surface is 30° or less.

6. The semiconductor laser element manufacturing method according to any one of claims 1 to 5, wherein, when viewed from the second direction, the angle of the taper from the main surface is 60° or more and 70° or less.

7. The semiconductor laser element manufacturing method according to any one of claims 1 to 6, wherein in the second step, the heating treatment is performed such that, when viewed from the second direction, the angle of the outer surface from the surface gradually decreases as you move inward from the outer edge of the planned mesa region.

8. The semiconductor laser element manufacturing method according to any one of claims 1 to 7, wherein in the second step, the second resist is formed such that the surface of the second resist at the connection portion between the first portion and the second portion is in an arc shape that is convex toward the inside of the second resist.

9. The semiconductor laser element manufacturing method according to any one of claims 1 to 8, wherein, when viewed from the second direction, the taper has a straight portion.

10. The semiconductor laser element manufacturing method according to any one of claims 1 to 9, wherein, when viewed from the second direction, the taper is linear, and in the third step, etching is performed so that the linear taper reaches the substrate.

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