Systems and methods for integrated processor module layout

Abstract

Devices and methods for heterogeneous integrated devices (HID) with stacked and interconnected components, along with passive elements, mounted on a substrate and having reduced skew and optimized size.

Description

SYSTEMS AND METHODS FOR INTEGRATED PROCESSOR MODULE LAYOUTTECHNICAL FIELD

[0001] The present disclosure provides a processor module of reduced size containing multiple active components for use in heterogeneous integrated circuit devices (HIDs) or similar devices.BACKGROUND

[0002] Heterogeneous integrated circuit devices (HIDs) are typically used in the semiconductor industry to incorporate multiple passive and active components in a single semiconductor package to form one circuit or system, and often to assemble multiple integrated devices, other active devices, and passive components in one package. Some examples of HIDs include System-in-Package (SiP) devices and Multi-Chip Modules (MCMs), among others.

[0003] General purpose integrated circuits (ICs) are typically designed without emphasis on optimizing the physical layout of the pins or balls of the package that will ultimately be connected to a larger system design. There may be exceptions, for instance, when considering combinations of devices such as a processor and its memory, the power management for a system design, and the relationship between digital, analog, and power pins with respect to potential noise issues in analog ICs. However, with the advent HID-based approaches, there may be new design complexities, including how to optimize a pin arrangement or ball map, for instance, of an HID, or how to optimize the layout of the larger system PCB to which it may be attached.SUMMARY

[0004] One or more embodiments described herein provide a processor module that is a HID containing a microprocessor, memory, and redistribution layer (RDL) that is optimized for active component die, minimum substrate area, reduced passives, thermal management of the components (microprocessor and memory), exterior output pin locations optimized for a later mounting platform, like a system PCB, and / or minimized skew for groups of memory signals (between a microprocessor and memory).

[0005] According to embodiments, a packaged semiconductor device is provided. The device comprises a substrate, a first device, and a second device. The second device is stacked on the first device ,and the first and second device are mounted on the substrate. Incertain aspects, a plurality of signal paths between the first device and the second device have substantially the same electrical length, such that they arrive at the same time as each other when sent between the first and second device.

[0006] According to embodiments, a HID system is provided. The system comprises, for example, a system printed circuit board (PCB) with a plurality of components mounted thereon and operationally interconnected. An HID module that is a System-in-Package (SiP), includes a SiP substrate that is populated with components on its top surface and comprises an array of exterior connectors arranged on a bottom surface of the SiP substrate that is electrically and mechanically attached to a system printed circuit board (PCB). The SiP may be any form of HID, for instance. In certain aspects, the SiP substrate contains a microprocessor die mounted on and electrically connected to the SiP substrate, a memory die physically located on the processor and electrically connected to a redistribution layer (RDL) located on top of the memory die. The RDL is electrically connected to the SiP substrate, and a plurality of supportive passive surface mount components are mounted on the SiP substrate and are operatively interconnected with the microprocessor and memory. The system PCB (or portions of the PCB) comprises at least a top layer, a ground layer (or island in a layer), and a power layer (or island in a layer), wherein the top layer (or layers) of the PCB comprises a plurality of escape traces on the top surface (or surfaces) of the system PCB for connection to the SIP array of exterior connectors. The number of and location of the escape traces is dependent upon the pin spacing selected for the SiP substrate. The use of escape traces for the PCB may allow the PCB to contain fewer layers of traces, for example, only 4 layers. That is the exterior pins for a SiP may be aligned / arranged so that the PCB on which the SiP is to be interconnected with and mounted on has a reduced number of layers (from the number of layers without this alignment). Using escape traces on the top surface of the PCB generally reduces the number of PCB layers by two or more, by allowing signals to escape to the PCB top layer out from underneath the SiP substrate. However, escape traces may also be used on other layers.

[0007] According to some embodiments, an HID (such as a SiP) is provided. The SiP may be, for example, the SiP used in the system described above, and comprise: a SiP substrate, having an array of exterior connectors arranged on a bottom surface of the SiP substrate; a microprocessor die positioned / mounted on and electrically connected to the SiP substrate; a memory die physically located on the processor and electrically connected to a redistribution layer (RDL) located on top of the memory die where the RDL is electrically connected to the SiP substrate via wire bonds; a plurality of supportive surface mounted passive componentsare mounted on the SiP substrate and are interconnected with the microprocessor and the memory. In certain aspects, a first group of the array of exterior connectors is configured for providing the external signals from at least one of said plurality of SiP components to a plurality of electronic components mounted on a PCB, a second group of the array of exterior connectors is configured for providing power and ground connections for the SiP from the power layer(s) and the ground plane layer(s) of the PCB, respectively. The first group of the plurality of the array of exterior connectors is arranged along one or more outer edges of the SiP substrate and the second group of the array of exterior connectors is arranged in a center of the substrate.

[0008] According to embodiments, methods for designing HID devices and resulting devices containing a selected microprocessor, selected memory, redistribution layer (RDL), and supportive passives in a reduced component size and reduced substrate size, with reduced passives, specially arranged outputs, and minimized skew for groups of memory signals in a thermally managed package are provided.

[0009] According to embodiments, methods for designing HID devices and resulting devices containing die for selected active arranged in an optimal manner where such active devices may include, but are not limited to, microprocessors, microcontrollers, memories, power management devices and other active components, optionally a redistribution layer (RDL), and supportive passives in a reduced size substrate, with reduced numbers of recommended passives, specially arranged outputs, and minimized skew for groups of memory signals in a thermally managed package are provided.BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various embodiments.

[0011] FIG. 1 depicts an example of a Heterogenous Integrated Device (HID).

[0012] FIGs. 2A-2G depict devices according to embodiments. The figures show various stacked combinations of components, including combinations of a processor and its associated memory for a processor module (PM) of embodiments.

[0013] FIGs. 3A-3B depict devices according to embodiments having thermal management features.

[0014] FIG. 4 depicts a processor module (PM) embodiment having a split capacitor layout in a system.

[0015] FIGs. 5A-5E depict aspects of example designs with different numbers and sizes of passive devices according to embodiments.

[0016] FIGs. 6A-6D illustrate skew compensation in accordance with embodiments.

[0017] FIGs. 7A-7C depict external connector layouts in accordance with embodiments.

[0018] FIGs. 8A-8E are flow charts illustrating methods according to embodiments.

[0019] FIG. 9 is a flow chart illustrating a method for designing a PM according to embodiments.DETAILED DESCRIPTION

[0020] Conventional systems typically include individually packaged Integrated Circuit devices (I / Cs), which are electrically and mechanically attached to a printed circuit board (PCB) to create a system. Often, each packaged I / C device may be large compared to the size of the actual die inside the package, and further, all of the needed passive and active devices are typically attached to the PCB. Therefore, the size of a PCB-based system design is significantly larger in all three dimensions compared to what is now needed for a state-of-the- art system design. In addition to offering compact size, heterogeneous integrated circuit device (HID) concepts may provide higher performance due to the traces on (and in) the substrate (e.g., those used to electrically interconnect the various components) being significantly shorter than in a PCB-based system design, as well as a reduction of parasitics on the I / O’s from the elimination of IC packages.

[0021] There remains a need for new devices and methods to realize the next generation of reduced-size and high-performance system integration.

[0022] Aspects of the disclosure provide a HID that is optimized for a reduced component size, reduced substrate size, reductions in passives, thermal management, exterior output pin arrangement / placement, and minimizing skew for groups of signals associated with memory and other groups of signals, as an example of combining next generation of components with improved combinations of optimized methods. The HID may include one or more of the following devices: microprocessors, microcontrollers, memories, and other active and passive components. While processors and memories are used as examples, embodiments are applicable to other devices, such as other active devices.

[0023] In one example, a HID contains a selected microprocessor, selected memory, redistribution layer (RDL), and supportive passives in a reduced size substrate, with reduced passives, and component size specially arranged outputs, and minimized signal skew for groups of signals associated with memory and other groups of signals in a thermally managed package.The active devices that are selected as die, and the passives, are surface mounted devices. The type of microprocessor (or other type of processor), and its supporting independent memory (or memories), are selected based upon identified performance criteria and desired peripherals, and optionally vendor / supplier support. Such support may include, for example, software availability, support, and tools. After selection of the processor, the size of the substrate may be estimated / selected based on the physical size of a die for the selected processor, the maximum pin count for the processor, and / or the selected exterior pin spacing of the substrate (e.g., based on the number of exterior pins needed to provide inputs and outputs for the selected processor). For some embodiments, the RDL may be optional, depending on physical arrangements of the components.

[0024] In embodiments, the size of the substrate may need to be adjusted depending upon the size of the die for the selected processor and the size needed to provide the maximum number of pins for the selected processor, as well as device external pin spacing. Moreover, the number and type of connections between processor and memory, required passives, and external connections may be determined from a schematic of the device to select the internal connections and the number of needed external connections. The number, size, value, and location of passives that are recommended by the data sheet of the vendor supplying the processor and the data sheet of the vendor supplying the memory die are determined - and minimized - based on reduced spacings between components in the device in one or more embodiments. A portion of those reduced passives may be selected to be off-chip (e.g., not placed on the substrate of the PM device) to minimize the substrate size and reduce the number of external connectors (pins).

[0025] In embodiments, the substrate is designed with connections for the processor that are located on the surface of the substrate (the processor may be mounted as a flip-chip), surface connections for connection with the memory, passives, and for selected pin spacing for external connections.

[0026] In embodiments, the memory die is physically located on the top surface of the processor and the connections to and from the memory are provided on the top surface of the substrate, via an RDL located on top of the memory. The memory may have a redistribution layer (RDL) located on and interconnected with the external connectors of the memory, where the RDL is connected to the memory’ s connections on the surface of the substrate using bond wires, although other connections may be employed. In general, the interconnections between the memory and processor are optimally contained inside the package. Adjustments may be made in traces for signal paths to minimize skew for communication signals (e.g., address anddata) between the processor and memory. For other arrangements of active components / devices an RDL may not be needed.

[0027] In embodiments, a thermal insulator / barrier may be located between the processor and memory to provide for separate thermal management of the two active components. The external connections can be arranged on the bottom surface of the substrate in a manner to support any PCB on which the device is to be mounted. Although not always required, the HID device may be encapsulated.

[0028] One HID-implementation advantage of the present disclosure is that the number of capacitors may be fewer in number, and their capacitive values may be smaller than those recommended by a product data sheet for a particular active component. By reducing the number of capacitors, not only does the bill of material (BoM) cost go down, but the surface area of a HID’s substrate may either be reduced or have more components added to it.

[0029] In some aspects and embodiments, there are many instances in electronic circuitry where a group of signals from a device needs to leave the device at the same time and anive at a receiving component at the same time. This may be needed for the communications between a microprocessor and memory of the present disclosure. One example would be for all the signals representing a memory address to show up at the same time to be used in a memory component. Accordingly, in embodiments, the communications between a processor and its associated separate memory need have a minimum amount of skew. For instance, to minimize skew, all the lengths of physical connections (traces and vias) between two components are the same length. However, in actual integrated circuits design and fabrication, this may be difficult to achieve as some trace connections may be made through traces and vias in a substrate and different connectors on different components mounted thereon; it may also involve wire bond connectors between the two components. One solution is to add serpentine segments to any associated shorter trace so that the physical lengths of the traces are the same. Some trace adjustments may also be needed to compensate for other variations, such as for example, different contact materials on portions of the interconnection paths to optimize interconnections between components for improved / faster system operations.

[0030] As another example, a microprocessor and a memory do not normally have the same operating temperature ranges when they are in the same package, thus, it may be advantageous to thermally manage them separately. Certain embodiment thermally isolate the two active devices from each other, using for example, a thermal insulator / barrier.

[0031] FIG. 1 illustrates an example of a Heterogenous Integrated device (HID) 100. Here, the HID includes a packaged processor 103 and a packaged memory 101 attached to substrate104, which is connected to a HID substrate 110 using bond wires 102. In this example, the HID substrate has other components, such as active components l l la / b and passive devices 112. Such other components may be included to perform the HID’s various functions. The substrate 110 has traces 113 and vias 114 to interconnect the various components, and can use external connectors 115 to connect to the rest of the system’s PCB (not depicted). Other examples of device and arrangements and available components are depicted in U.S. Patent 11,610,844 (“High Performance Module for SiP”), which issued March 21, 2023, the contents of which are incorporated herein by reference.

[0032] FIGs. 2A-2G, 3A-3B, and 4, illustrate one or more embodiments of processor modules, HID, and / or SiP devices and their component arrangements.

[0033] FIGs. 2A-2B depict side views of processor module (PM) devices 200, 250 according to embodiments. The devices 200, 250 comprise, forinstance, a memory device 201, processor 202, and Redistribution Layer (RDL) 206, along with one or more passive devices. In these embodiments, the selection of a processor and memory as the active components is one example of employing the teachings of the present disclosure. However, other active components may be used. Additionally, the processor may be a microcontroller that includes its own memory, and the second (or third or more) active device may be any sort of device, such as for example, but not limited to a wireless device, an optical device, etc.

[0034] Referring now to FIG. 2A, a HID substrate is illustrated according to embodiments, with a microprocessor die 202 flip-chip mounted thereon and connected to the substrate 203 with connectors 415. In this example, the microprocessor 202 has a memory device die 201 mounted its top surface. Additionally, the memory device 201 has a Redistribution Layer (RDL) 206 on its top surface. The external contactors of the memory 201 are interconnected with and operably connected with RDL external connectors on the RDL surface (e.g„ facing the top of the memory 201). Moreover, the memory’s external connectors are routed to bond pads 207, then through (the layer(s) and vias of) RDL 206 where bond wires 205 are connected from the RDL bond pads 207 to the PM substrate 203 bond pads 208. In embodiments, the PM is encapsulated 210. However, other embodiments of the PM may not be encapsulated.

[0035] In certain aspects, the processor module (PM) comprises the microprocessor die 202 and its associated high-performance memory die 201 (or memories), and active and passive devices 212a / b / c / d. In some embodiments, most (or all) of any necessary large bulk capacitors for power management are not part of the PM 200, but instead, are part of the system PCB (not shown) on which the PM is electrically mounted and mechanically attached. Although a few of these large passives can be selected to be on the PM substrate, to minimize the surface areaof the substrate 203 of the PM. and accordingly the size of the substrate and the number of its trace layers 113, most large passives are located on the system PCB (not shown) in embodiments.

[0036] Passive devices 212a / b / c / d on the PM include, for instance, bypass capacitors, selected small-valued bulk capacitors, and resistors. These passives are selected to minimize the surface area of the PM substrate. Finally, PM substrate 203 has multiple conductive layers 113 and vias 114; although 7 layers are depicted in FIG. 2 A, other numbers of layers may be so employed as a PM substrate (e.g., with as few as three possible under certain circumstances / conditions). RDL layer 206 has one or more conductive layers 216 and vias 217 in this example. And the two active devices (201 and 202) have multiple internal conductive layers 218 and vias 219, as does the RDL.

[0037] Referring now to FIG. 2B, an embodiment 250 of a PM is provided, with memory device die 201 having a Redistribution Layer (RDL) 206 on its bottom surface. The memory’s external connectors are routed to bond pads 207 through the RDL 206 where bond wires 205 are connected from the RDL bond pads 207 to the PM substrate 203 bond pads 208. In this embodiment the PM is encapsulated 210; however, in other embodiments the PM may not be encapsulated.

[0038] FIGs. 2C-2D depict additional embodiments 270, 280 of a PM. In these examples, the memory 201 and the processor 202 are both electrically connected to the top and bottom surfaces of an interposer 276 (e.g., using bumps 208). The interposer 276 is then electrically connected to the substrate 203 using wire-bonds 205 and / or bumps 208. As in FIGs. 2A-2B, stacking options include having the processor 202 on the top of the die stack and the memory on the bottom of the stack. Other options may be but are not limited to, the use of bond-wires 205, bumps 208, or both to connect to the substrate 203, stacking order of the memory 201 and processor 202, and electrically connecting the processor 202 and memory 201 using RDL rather than an interposer. The physical arrangement of multiple active devices may be based upon the different die sizes for the selected active devices and the types of desired interconnections between the devices. The region -AA- of FIG. 2C is shown in FIG. 2D, in certain embodiments.

[0039] FIG. 2E depicts an arrangement 290, with memory device 201 on the bottom of the die stack mechanically and electrically connected 415a to the substrate 203 with an interposer / RDL 206 located on its top surface (e.g., but not electrically attached). In this example, the processor 202 is mechanically and electrically connected to the interposer / RDL 206 via external connectors 415b and then routed to interposer / RDL bond pads 207 thenthrough the interposer / RDL 206. Bond wires 205 are connected from the RDL bond pads 207 to bond pads 208 of the PM substrate 203. In this embodiment the PM is encapsulated 210; however, in other embodiments the PM may not be encapsulated. According to some embodiments, passive devices 212a / b / c / d on a PM comprise bypass capacitors, small-valued bulk capacitors, and / or resistors. These passives are selected to minimize the surface area of the PM substrate 203. Finally, in embodiments, the substrate 203 has multiple conductive layers 113 and vias 114; the RDL layer 206 has one or more conductive layers 216 and vias 217. The two devices 201 and 202 can have multiple internal conductive layers 218 and vias 219 of their own.

[0040] FIG. 2F depicts an embodiment 295-1 with a memory device 201 on the bottom of the die stack and mechanically and electrically mounted to the substrate 203 via external connectors 415. In this example, processor 202 is located on top of memory 201 and bond wires 205 are connected from the processor bond pads 207 to bond pads 208 of the PM substrate 203. In this specific embodiment the PM is encapsulated 210, but in other embodiments the PM may not be encapsulated. Additionally, the physical arrangement of the active devices may be based upon the respective die sizes of the device, and certain arrangements and devices and die sizes, an RDL may not be required in embodiments. Passive devices 212a / b / c / d on the PM comprise bypass capacitors, small-valued bulk capacitors, and / or resistors. These passives are selected to minimize the surface area of the PM substrate 203. The substrate has external connectors 215 on its bottom surface. Finally, the substrate 203 has multiple conductive layers 113 and vias 114. The two devices 201 and 202 have multiple internal conductive layers 218 and vias 219.

[0041] FIG. 2G depicts an embodiment 295-2 that is largely the same PM as depicted in FIG. 3F, but with the processor device 202 on the bottom of the die stack and mechanically and electrically attached to the substrate 203 via external connectors 415. The memory device 201 is located on top of the processor 202. Bond wires 205 are connected from the memory bond pads 207 to bond pads 208 of the PM substrate 203. The substrate has external connectors 215 on its bottom surface. Finally, the substrate 203 has multiple conductive layers 113 and vias 114. The two active devices 201 and 202 also have multiple internal conductive layers 218 and vias 219. As in FIG. 3F, the PM is encapsulated 210, but in other embodiments the PM may not be encapsulated. The physical arrangement of the active devices may be based upon the respective die sizes of the devices. For this embodiment an RDL may not be required.

[0042] In certain aspects and embodiments, the interaction between passives / capacitors and exterior pin alignment involves the optimization of the passives on the substrate versus the number of external pins, and alignment of those external pins on the bottom of the substrate.

[0043] FIGs. 3A-3B depict embodiments 300, 350 of a processor module (PM). This example includes a thermal barrier 304 separating the memory device 201 and the processor 202. By thermally isolating the two devices, the memory can then be thermally managed 321 through the top surface of the PM (e.g., using passive and active devices such as, but not limited to, heat sinks, fans, and active thermal management devices). Further the microprocessor (uP) may be managed 322 through the bottom surface of the PM (e.g., by taking advantage of the thermal conductivity of the external conductor pins 215 and, 415, and the traces 113 and vias 114 of the PM, and the Heterogeneous Integrated Circuit Device (HID) to which the PM is attached). Other active and passive thermal management techniques may be employed based on the use and environmental requirements of the end equipment of which the PM is a component.

[0044] For instance, FIG. 3 A depicts a processor module (PM) with a memory device 201 with a Redistribution Layer (RDL) 206 on its top surface. The memory’s external connectors are routed to bond pads through the RDL 206 where bond wires 205 are connected from the RDL bond pads 207 to the PM substrate 203 bond pads 208. The thermal barrier 304 thermally isolates memory 201 from microprocessor 202. Once the two devices (201 and 202) are thermally isolated from each other the two can be thermally managed separately. That is, microprocessor 202 can be managed 322 via the PM’s substrate 203 while the memory device is managed 321 through the top surface of the PM using heat sinks or other active and passive methods. In this specific embodiment the PM is encapsulated 210. But in other embodiments the PM 300 may not be encapsulated 210 (e.g., given other thermal management options). The Passive devices 212a / b / c / d on the PM 300 comprise one or more of bypass capacitors, smallvalued bulk capacitors, and resistors. These passives are selected to minimize the surface area of the PM. Finally, substrate 203 has multiple conductive layers 113 and vias 114, and the RDL layer has one or more conductive layers 315 and vias 316. In embodiments, the two devices 201 and 202 have multiple internal conductive layers 317 and vias 318. Although not shown, the thermal isolation device 304 may have active and passive elements included.

[0045] FIG. 3B 350 depicts embodiments 350 of a processor module (PM) with a memory device 201 with a Redistribution Layer (RDL) 206 on its bottom surface on top of the thermal isolation 304. The memory’s external connectors are routed to bond pads through the RDL 206 where bond wires 205 are connected from the RDL bond pads 207 to the PM substrate 203bond pads 208. The thermal barrier 304 thermally isolates memory 201 from microprocessor 202. Once the two devices (201 and 202) are thermally isolated from each other the two can be thermally managed separately. That is, the microprocessor 202 can be managed 322 via the PM’s substrate 203 while the memory device is managed 321 through the top surface of the PM 350 using heat sink 325, and / or other active and passive methods. In this specific embodiment the PM is encapsulated 210; in other embodiments the PM may not be encapsulated 210 based on other thermal management considerations. The passive devices 212a / b / c / d on the PM comprise one or more of bypass capacitors, small-valued bulk capacitors, and resistors. These passives are selected to minimize the surface area of the PM 350. Finally, substrate 203 has multiple conductive layers 113 and vias 114. RDL layer has one or more conductive layers and vias. The two devices 201 and 202 have multiple internal conductive layers 113 and vias 1 14. Although not shown, the thermal isolation device 304 may have active and passive elements included.

[0046] FIG. 4 depicts a HID 420 according to embodiments, with a Processor Module (PM) 200 attached. In this example, the passives for the HID include the bypass capacitors (e.g. a set of capacitors necessary for the HID to function correctly). Integrated on the PM are the processor 202, memory 201, and RDL 206 mounted on the PM’s substrate 203. In addition, several bypass capacitors 212a / b / c / d are mounted on the PM’s substrate 203. According to some embodiments, the PM is mounted on a system PCB 303 along with the Power Management Integrated Circuit (PMIC) 401, along with one or more bulk capacitors 421a / b / c and / or bypass capacitors 42 Id for the HID. In certain aspects, the capacitors are split such that the bulk capacitors 421a / b / c are generally attached to the HID’s PCB 303, and the bypass capacitors 212a / b / c / d for the PM are generally attached to its substrate 203. By doing so, the PM’s size may be minimized. That is, attaching the bypass capacitors 212a / b / c, which are much smaller than the bulk capacitors 421a / b / c / d, to the PM substrate 203 minimizes the overall size of the PM as compared to having the majority of the larger bulk capacitors 421a / b / c / d on the PM substrate, and instead attaching them on the HID’s PCB 303. In embodiments, once the PM (encapsulated in this depiction) is attached to the HID substrate via external connectors 215, the capacitors 421a / b / c / d, and the other components are attached to the HID PCB 303, and the HID is encapsulated 210. It may then be attached (in this example) to the rest of the system via the HID’s external connectors 425 to the larger system PCB. In this example, the HID 420 may extend beyond the left and right edge of the HID 420, as only a portion of the FIG. 4 example depicts certain aspects.

[0047] There may be several aspects that are considered when specifying the voltages to be used for a selected microprocessor and other devices in a system

[0048] The voltages are typically based on vendor data sheets for the selected microprocessor and other devices. Thus, a first consideration may be the specific value of voltage to be supplied based on vendor data sheets. For example, an input voltage may have a nominal specification of 1.8 volts but will then have a minimum and maximum requirement of 1.7 volts and 1.9 volts, respectively. However, there may be other concerns about the quality of the voltage over its specified range. Two typical measures of the quality of the voltage supply are the allowable voltage sag and the high frequency noise that may be present on the voltage supply lines and signal traces. For example, decoupling capacitors are required to suppress the switching noise generated by high frequency sources and to stabilize the supply voltage. Vendor data sheets of active devices generally provide the underlying assumptions that relate to how far the components are apart from each other and have cautionary wording that recommends the passives needed to assure device performance. In a typical HID system design, the electrical distance between any power source supplied to components receiving the power is millimeters rather than centimeters in a PCB design. Also, with the power requirement for many high-performance devices, such as microprocessors, there are typically many pins dedicated to the voltage supplies and grounds. The result is a recommendation from each of the vendors who manufacture an active component to include the size or value, location and number of decoupling or bypass capacitors to be included in a design using their component; these recommendations are to ensure that the reliability and operation of their components do not suffer due to a voltage sag or excessive noise on a voltage supply. However, such recommendations may be overstated for HID implementations. And often the data sheet adds that a decoupling capacitor is most effective when it is close to the device, because this minimizes the effect of the inductance of the circuit board wiring and interconnects. Inductance and parasitic aspects may also be impacted. Manufacturer data sheets may also require other passives such as resistors and inductors of which an HID device may be able to perform well with further reductions / optimizations (smaller size, lower voltage, lower operating power).

[0049] For instance, reduction in length of a power trace (or power rail), or signal trace in a heterogeneous integrated device (HID) allows the capacitive values and numbers of devices recommended by the various component manufacturers to be reduced to smaller capacitive values and / or in number, which saves in both cost and size for an HID substrate implementation according to some embodiments. This reduction in vendor recommended passive values and numbers (and physical size) is applicable to HID devices.

[0050] Generally, the technique used to manage the sag and noise on the voltage rails is to use bulk and bypass capacitors on the voltage supply lines. Larger value capacitors (i.e., bulk capacitors) typically in the 1 to 200uF range, are used to minimize any voltage sag due to current demand in a system. Smaller capacitors (i.e, bypass capacitors) typically in the range of .OOluF to 0. luF, are used to eliminate or reduce high frequency noise on the voltage supply lines (and signal traces) resulting from sources like clocks or communications signals.

[0051] However, there are also considerations for interconnections between components, such as, for example, a microprocessor and memory for addresses and data / signals. Tn the case of an HID, the distances between the various components are typically measured in millimeters rather than centimeters. Preferably all active components may be attached to the HID's substrate in die form rather than as a packaged device. In some cases, this may also reduce the electrical distance between the power source and a component by eliminating the necessary trace length inside and outside of the active component’s package.

[0052] A HID implementation advantage, therefore, is that the number of bypass or decoupling capacitors may be fewer in number and their capacitive values may be smaller than those recommended by a product data sheet for a particular active component. By reducing the number of bypass capacitors, not only does the bill of material (BoM) cost go down, but the surface area of a HID’s substrate may either be reduced or have more components added to it.

[0053] The various physical sizes (capacitance value, physical size and location) of the surface mounted devices and surface mounted capacitors may be chosen based on the requirements for the HID. For example, a so-called “0603” sized capacitor device that is a surface mounted capacitor, has the physical size of 60 mils (1.6mm) by 30 mils (0.8mm) by 30 mils (0.8mm) in the X, Y and Z dimensions. Such things as capacitive value, voltage, tolerance and cost will often dictate the physical size of the device. As one non-limiting example, a capacitive device size for a lOuF capacitor (e.g., to have a reasonable operating voltage of 10 volts and lowest cost) is a 0603 package. But moving to a 2.2uF capacitor, the best size is a 0402 for a 10-volt operating range and lower cost. For capacitor values greater than lOuF, one may need an 0805 package, which could create another problem of it being too large in the “Z” dimension to fit into HID packages. Taking advantage of the reduced numbers and values and corresponding physical sizes of bypass capacitors to become smaller may allow the size and design of a HID substrate to be reduced.

[0054] As a result of reducing the number of bypass capacitors, the cost may be reduced. At the same time there is a resulting reduction in substrate area for capacitors. This provides atotal cost savings. It also provides a total area savings for the substrate size. When one or more capacitors have been removed, new components may be added to the HID substrate in those or other locations. According to embodiments, the HID design for components and passive layouts is updated based on a reduced size substrate to take advantage of the reduced capacitor sizes, reduced capacitive value and reduced number of capacitor locations used in an HID design.

[0055] Reducing the impact of a large capacitor’s effect on a HID design may be done in several ways. For instance, benefits may be achieved by inserting a lower capacitive value to replace the large one; doing this may allow a smaller physically sized component to be used (e.g., use a 0402 rather than a 0603 or 0805).

[0056] The value of the bypass capacitors is typically based on the expected high frequency of noise on the voltage lines. However, these capacitive values may optionally be left as the vendor recommended values and not reduced. But the number of these capacitors may be reduced.

[0057] Accordingly, in embodiments, a reduction in number, value and size of vendor recommended passives is available for use in HID devices / systems that contain multiple active and passive components.

[0058] Another factor in designing a decoupling system for high frequencies may not be the amount of capacitance, but rather, the amount of inductance in the traces and vias that attach the capacitors to the power and ground planes. In addition, the signal paths (traces) between a microprocessor and memory must also deal with signal skews. The amount of inductance in series with the decoupling capacitors from the leads is a function of the trace length. Typical inductance of a FR-4 microstrip trace exposed to air on one side may be about 8nH / inch. Keeping the traces short in the HID compared to a PCB makes the inductance lower and the capacitance more effective. However, the trace lengths between a microprocessor and a memory may need adjustments to avoid signal skew, as discussed later herein. The amount of inductance from the vias in series with the decoupling capacitors is a function of the length of the traces and vias. According to some embodiments, a substrate dielectric thickness of 35um may be used, and when compared to a typical PCB dielectric thickness of 1 lOum, the result is three times less inductance for vias. Again, this helps to keep the inductance lower and make the capacitance more effective. The use of more parallel vias in a HID design helps to minimize the inductance.

[0059] In certain aspects, optimal high frequency performance may be achieved by having several distributed capacitors at short distances from where needed, so that there is minimaleffect from the series inductance. Since a HID typically will have dielectrics which are three times, or more, thinner / less than a PCBs, creating adjacent power and ground planes, as much as possible, creates the distributed capacitance. Again, this reduces the need for high-frequency decoupling capacitors in number, location and even capacitive values.

[0060] FIGs 5A-5B depict top views of a SiP design that was initially designed based on the vendor recommendations for the values and numbers of bypass capacitors for the components used in the example SiP. In FIG. 5 A, for the populated substrate 501, there are large capacitance value capacitors 502 and 503, and small capacitance value capacitors 504 and 505. In FIG. 5B, a top view of the same SiP design of FIG. 2A is shown, with a memory 521, power management device 522, and processor 523, except many of the capacitors have been removed, both large value capacitors 512 and 513 and smaller value capacitors 514 and 515. In the example of FIGs 5A-5B, the number of bypass capacitors was reduced from 118 to 70, while the SiP with the reduced values, sizes, and reduced number of capacitors can perform as well as the SiP that was designed using the size and number of manufacturer recommended bypass capacitors. The reduction in values and numbers of bypass capacitors used in FIG. 5B may be possible, for instance, as a result of the shorter interconnection distance between the various components used in the SiP.

[0061] FIGs 5C-5D depict a further example of reducing the value, size, and number of bypass capacitors. FIG. 5C mirros FIG. 5B and is provided for comparison. The layout in FIG. 5B / 5C has seen a reduction in the size and number of large value capacitors, and reduction in numbers of smaller value capacitors, as described earlier, but with the same actual performance of the SiP of FIG. 5A. The original layout of the SiP example (FIG. 5B / 5C) with the microprocessor 523, memory 521, power management device (PMIC) 522 and Low Drop Out power supply (LDO) 525 has a further cost and size reduction by modifying the layout of the substrate 501 to be a re-layout, an in FIG. 5D, with substrate 541 taking advantage of the reduced numbers and values (sizes) of bypass capacitors. In embodiments, it is not only smaller with the same devices 521, 522, 523, 525, as in FIGs. 5B / 5C, but it has an added component 546. The overall size reduction was from a substrate size of 27mm on a side for FIG. 5B / 5C to 21mm on a side for FIG. 2D, as an example, making a total reduction in area from 729mmA2 to 441mmA2. Again, the actual performance of SiP of FIG. 5D can be the same as that of the SiP of FIGs. 5A-5C.

[0062] FIG. 5E depicts a chart summarizing an original SiP design based on vendor recommendations for bypass capacitors, like the design of FIG. 5A. FIG. 5E further depicts two variations of a reduced set of bypass capacitors, Example A and Example B, which maycorrespond to the examples of FIGs. 5B / 5C and 5D, respectively. The first of the two variations was to remove the unneeded capacitors shown as Example A, and then reduce the size of the larger capacitors in addition to the reduction in the numbers of the capacitors shown at Example B. A typical set of capacitor values shown in the first column can be used, where the sizes used are based on the vendors’ recommendations. In this example, the number of capacitors shown in the number row is reduced from 118 to 70. As indicated in the the two examples, in Example B, not only were the number of capacitors reduced, but the values of the larger capacitors were reduced from lOuF to 2.2uF. This value reduction allows for the larger capacitors to not only be fewer in number but smaller in both physical size and cost. As a result of the bypass capacitor reductions in these examples, the cost shown in the Cost row is reduced from $0.73 to $0.43 in Example A and to $0.26 for Example B. At the same time, the areas shown in the Area row are reduced from 97.8mmA2 to 59.1mmA2 in Example A and to 44.6mmA2 in Example B. This provides a total cost savings shown in the Delta $ / Area row of $0.30 690 and $0.47 in Examples A and B, respectively. It also provides a total area savings of 38.7mmA2 1291 and 53.2mmA2 from Examples A and B, respectively.

[0063] In embodiments, a processor module (PM) contains a microprocessor and associated memory, and one or more goals may be to minimize skew for their interconnections.

[0064] “Skew” may refer to various signal timing features, including: (a) the difference between the arrival times of two signals at their intended destinations, and / or (b) the difference between the distances which two signals must travel to arrive at their intended destinations. Thus, the term skew is often used in the context of electrical circuits containing multi-terminal high speed components in which a group of signals are intended to leave the terminals of one of the components at the same time and arrive at the terminals of the other component at the same time. Often, the difference in the electrical length of the shortest and the longest signal line within the group of signals determines the maximum “skew” among the group of signals. Skew reduction may be accomplished by adjusting the physical layout of the substrate. Additionally, skew may refer generally to signal latency. That is, the signal delay of the slowest signal’s arrival time at the destination component from the fastest signal’s arrival.

[0065] With respect to distance or length, there are typically two different measurements of length in a circuit layout: (i) the physical length of the individual signal lines, and (ii) the electrical length of the individual signal lines. The total physical length for a specific signal line between components may simply be the distance between the two components before they are electrically connected. Or in some instances, the physical length is defined as the total (minimal) length of the signal trace to connect a specific signal output of a component to theinput of the signal's destination component. The total electrical length may be different. For example, the electrical length of a specific signal line between two components may be calculated as the addition of one or more of: (i) the total physical length of all of the signal trace segments, (ii) the sum of all the lengths of the vias, (iii) the sum of all the bond wire physical segment lengths, (iv) the sum of all the connector segment lengths, (v) the sum of all the pad segment lengths, and (vi) the sum of all the solder segment lengths. In certain aspects, the electrical length can take into account the signal speed (e.g., the speed at which an electrical signal passes through a specific segment of the signal path). For example, the speed at which an electrical signal passes through signal traces is different from the speed of light, or the signal speed through bond wires, through vias, through connectors, through pads, or solder joints. The electrical length of a segment of the signal line (or trace) may be determined to be the speed of light times the time taken to traverse the segment where the speed is determined by a ratio term for that segment. For example, the electrical length of a trace can be determined by the speed of the signal times the time for the signal to traverse the trace.

[0066] FIG.s 6A-6C depict representations 600, 630, 660 that illustrate one or more aspects of signal skew in a Heterogeneous Integrated circuit device (HID), and a way in which the signal skew may be minimized in the PM according to embodiments. For instance, these figures illustrate a reduced set of the signal lines between two components, such as for example, the address and data lines between memory 201 and the microprocessor 202 of embodiments.

[0067] FIG. 6A depicts one or more aspects that can cause signal skew, can be used to describe concepts of minimizing it by adding serpentine trace segments to the shorter traces, according to some embodiments. On the left side of FIG. 6A are five pairs of traces for signals where one of the traces is a straight line and the other traces have been modified to minimize signal skew across the group of the five traces by adding serpentine trace segments. One of the signal lines 601a is one physical unit in length, one of the signal lines 602a is two physical units in length, one of the signal lines 603 a is three physical units in length, one of the signal lines 604a is four physical units in length, and one of the signal lines 605 is five physical units in length. Each of the four physical trace lines 601a, 602a, 603 a, and 604a are different physical distances (that is point to point) as their companion signal traces 601b, 602b, 603b, and 604b. But these latter four companion signal traces (601b, 602b, 603b, and 604b) have been modified such that the physical length of each of these four lines is the same electrical length as trace 605. Thus, signals on all five lines would “arrive” at the same time.

[0068] According to embodiments, to minimize the skew among the five signals 621 as they traverse their respective traces, serpentine trace segments are added into the four shorter traces601a, 602a, 603a and 604a. With the addition of specific serpentine physical segments (611, 612, 613, 614, and 615) each new physical length presents itself with an electrical distance 601b, 602b, 603b, 604b, and 605 (signal delay) associated with its physical distance making all five signal traces the same physical length. The latter four companion signal traces (601b, 602b, 603b, and 604b) have been modified such that the signal length of each of these four signal lines is the same signal length as 605. In this example each of the signal lengths is five units long. That is, the same length as the longest trace line 605.

[0069] The middle portion of FIG. 6A (Table 622) compares the physical lengths 622a to the signal lengths 622b for each of the five traces on the left side of FIG. 6A after the serpentine trace segments have been injected into the physical traces 601a, 602a, 603a, 604a and 605 listed in 622a to create 622b. While serpentine shape is used as an example, other lengthening shapes may be used according to embodiments.

[0070] On the left side of FIG. 6A is an example where there is a set of five signal traces 601a, 602a, 603a, 604a, and 605 connecting two devices, each with a different physical length. For simplicity their lengths are one unit in length (601), 2 units (602), 3 units (603), 4 units (604) and 5 units (605). For example, replacing trace 601a with a five-unit serpentine length 615, 601b replaces 601a giving it five units of length. In the same way replacing one unit segment of 604a with a two-unit seipentine segment 612, the new five -unit trace 604b is created.

[0071] On the right side of FIG. 6A is a set of examples of modified signal traces with injected serpentine signal traces, giving:1 unit of signal to physical length (StPL) length 611,2 units signal to physical (StPL) length StPL 612,- 3 units signal to physical (StPL) length StPL 613,- 4 units signal to physical (StPL) length StPL 614, and5 units signal to physical (StPL) length StPL 615.

[0072] FIG. 6B depicts 630 the skew resulting from groups of signals with different physical signal lengths 635a, 634a, 633a, 632a and 631a, each of which need to arrive at a destination 645 at the same time, and presents an example of the signal skew among the five signal traces. In this example, five signals connect two components, for example between microprocessor 202 and its associated memory 201 according to embodiments. Since the physical length of the five signal traces vary from a trace of one segment 601a to a trace of five segments 605, the first of the five signals to arrive at its destination is signal 631a / b (where 63 la and 63 lb are the signal leaving one component and the second is the arriving signal at the secondcomponent) and the last signal to arrive, four time-segments later, is signal 635b. As may be seen in the figures, the differences in length of the five signal traces between the signals’ sources and their destinations affect their times of arrival, 635b, 634b, 633b, 632b, 631b, as shown for example in graph 642.

[0073] FIG. 6C depicts the same example of the signal skew after the serpentine segments have been added into the original traces 671, 672, 673, and 674. In this illustration, the longest physical line 675 is 5 units in length. To minimize the Skew among the five signal lines 635a, 634a, 633a, 632a, and 631a, at their destination, each of the four associated signal lines with 675 must be lengthened to the same 5 units length as the longest 675. For example, by replacing one of the segment units in signal line 674 with the serpentine unit 612, its new signal length becomes 5 units (3 of one StPL and 1 of two StPLs) while maintaining its four-unit physical length. The same method is used in this embodiment for the other three signals 673, 672, and 671 by using two 2 StPLs and one 1 StPL for 673; two 2StPLs and one 3 StPLs for 672; and one 5 StPL for 671. By doing so all five associated signals arrive at their destination at the same time, 5 units of time after having left the output pin of the source device. That is, all five signal traces are the same five units in length. Further, all five signals 631a, 632a, 633a, 634a and 635a leave the first component at the same time 644 and all arrive at the second component at the same time, five time-units later 646.

[0074] FIG. 6D depicts an example PCB layout with serpentine signal traces to reduce skew. Two examples include skew elimination 691 and differential pair skew elimination 692.

[0075] With respect to skew, often the propagation speed of a signal through a physical structure is a function of the impedance of the structure. And the impedance itself is a function of the structure’s physical materials, the shape of the structure, and the frequency components of the signal. Therefore, according to embodiments, when assessing the electrical length, an accurate calculation may require an integration over constantly changing impedance along the length of the signal route rather than using a single average velocity per segment. Additionally, when a serpentine shape is used to extend the physical length of a signal line, the “tightness” spacing of the serpentine should be large enough for the signal frequencies of interest; otherwise, the signal will “jump over” the serpentine without increasing the electrical trace length as desired. One or more current commercially available layout tools may be used to simulate or otherwise measure physical lengths and / or electrical lengths of traces and other connectors when considering skew.

[0076] The number of external connectors on a packaged device is increasing as the industry moves from components to system components. Although it might seem that with industrymoving to system components the actual number of external connections required is reduced, that is not the case. The reason for needing more external or exterior connectors has to do with managing the power rails and ground planes, for instance. This can result in an increasing demand for more connectors rather than the need for more I / O signal connectors. Further, as the size of each system component shrinks, the surface available for internal components and external or exterior connectors also shrinks. One or more embodiments can address such design considerations.

[0077] A typical processor / memory device, though not all, uses two types of inputs / outputs: power inputs and external signals. The physical locations of inputs / outputs of each device in its packaged or unpackaged form may be optimized specifically for that device and may be used in a typical PCB for a system. For example, an HID device may have two active components: a memory device 201, and a microprocessor 202. To connect these components within the HID, there are several internal connections.

[0078] The Processor Module (PM) of embodiments may comprise a microprocessor die, its associated high-performance memory die (or memories), an RDL. and one or more supporting active and passive devices. In certain aspects, most of the necessary large bulk capacitors for power management are not part of the PM, but rather, are part of the system PCB on which the PM is electrically mounted and mechanically attached. The passives used are selected to minimize the surface area of the substrate of the PM, and accordingly, the size of the substrate and the number of its layers.

[0079] FIG. 7A is a block diagram 700 of a power management device 701 and a processor / memory device 702. Power management device 701 uses three types of inputs / outputs: power inputs 703, power outputs 704 and external signals 705 that go to and from the system. In this example, processor / memory device 702 uses two types of inputs / outputs: power inputs 706 and external signals 707. The physical locations of inputs / outputs of each device 701, 702 when in a package may be optimized specifically for that device.

[0080] FIG. 7B depicts an example grouping 750 of system PCB layout traces that are used to allow the signals from a SiP to escape from under the SiP package 771, for instance when mounted on the top layer of the system PCB. In this example, the connection balls 773, 774, 775, and 776 in the middle of the SiP are the external power and ground connections for the SiP. The outer three rows 760, 762 and columns 761 , 763 of connection balls of which connect the SiP’s internal signals to the system PCB through escape traces. Escape traces allow the signals to escape from the SiP to the system PCB on the top layer of the PCB. These escapetraces allow the signals to escape out from under the SiP package to other components on the system PCB. Signals can include, for example, the oscillator, USB, MMI, MMC, UART / SPI / I2C, Analog to Digital Converter, LCD Control, LCD Data, JTAG, GPMC address and data. Signals that are connected from the SiP to the system PCB using these outer rows and columns may do so without the need to incorporate vias in the system PCB signal path. Using this pin arrangement of signals for escape traces and then power and ground using the center portion of the ball map. This helps to directly attach to the power and ground planes of the system PCB and reduces the number of trace layers required for the system PCB.

[0081] Additionally, and in accordance with some embodiments, FIG. 7B includes the external connector or ball locations 752 of a SiP substrate from a top view (e.g., looking through the package of the SiP 771), where the overall pinout for all components in the SiP has been optimized for use in a system on a system PCB using a minimum number of PCB layers. According to embodiments, these SiP substrate ball locations are the same locations as the balls on the top surface of the system PCB. The three rows and columns are a result of how many traces on the PCB surface can be routed between the outer most rows and columns of the SIP connection balls. In this particular example, the ball to ball spacing is 1mm, which allows for two 0.127 mm PCB traces to be routed between the outermost rows and columns of SIP connection balls. Other pin spacings will provide for different routings between rows. The black lines 751 attached to the black dots 752 represent how signal traces on the top surface layer of the PCB on which the SiP is mounted are connected to the connection pads of the SiP. These traces are used to get signals from the SiP balls out from under the SiP package to other components on the system PCB. These lines are escape traces and are only illustrated here in a length sufficient to get the trace out from under the SiP package, where the package 771 is depicted by a shaded area in the box. But the traces would be longer than depicted to connect to other components on the top surface of the system’s PCB.

[0082] According to some embodiments, the outer three rows / columns of the BGA are routable on a single top layer of the system PCB to reduce the number of PCB layers. The connection balls in the four center boxes 773, 774, 775, and 776 are not routable on the same layer of the system PCB where the components are mounted. In this embodiment, power input / output external connectors in the four boxes 773, 774, 775, and 776 in the center are placed such that it is easy to group these connectors together and connect to the underlying power planes of the system PCB using vias.

[0083] In this example of a system’s PCB, the system components may be mounted on the top layer of the system PCB. To reduce the number of PCB layers, signals from the device arebrought out using escape traces on the surface of the PCB for the external signal balls such as 760, 762, 761, and 763 which are placed in the outer three rows / columns of the HID / SiP package. And continuing to refer to the example of FIG. 7B, PCB traces 751 can be routed between SiP package pins and their corresponding traces, thus bringing all four of the traces out on the top surface of the system PCB. In this example, power inputs / outputs 773, 774, 775 and 776 are placed such that it is easy to group these pins together and connect to the underlying power planes of the PCB using vias. Associated internal signals, connected externally may be placed next to each other to allow for easy connection; internal signals that are needed for a common purpose, like for example, but not limited to, a communication port, may be grouped together. For a communication port, these types of signals may be, for example, address lines, control lines, data lines, and clock signals.

[0084] In some embodiments, if an internal signal of one component must be connected to the signal of another component externally, it may be placed on connection balls that would not normally be routed on the PCB surface for mounting components, thus saving those connectors for external signals. Although in some embodiments it is possible for two internal signals to be connected together externally, they may be brought out on the PCB surface on which components are mounted. In this case, one pin should be placed on a ball that would not be routable on a single layer and the other ball should be placed on a pad that would be routable on a single layer. Signals such as test points may be connected using vias to another PCB layer such that they can easily connect to a test pad, if necessary. In some embodiments, the test points are not placed in the balls that are not routable in a single layer unless there are unused signal ball connections available that are routable in the PCB layer for mounting components. Similarly, and according to some embodiments, unconnected pins should be placed on pads that may not be routable in a single layer. This can reduce the overall number of PCB layers required to route the HID signals. The terms “exterior” and “external” may be used interchangeably when referring to output connectors or pads for interconnection with other components or devices.

[0085] In certain aspects, the three rows and columns are a result of how many traces on the PCB surface can be routed between the connection balls located in the outermost rows and columns of HID connection balls. In this example, the ball to ball spacing is 1mm, which allows for two traces to be routed between connection balls.

[0086] According to some embodiments, grouping of the PCB layout traces is used to allow the signals from the HID to escape from under the HID package on one layer of the PCB. In example embodiments, the connection balls in the middle of the HID have been blacked out asthey are the power and ground external connections for the HID. In this example there are several groups of signals identified which are typical, but not limited to, a microprocessor system. These escape traces allow the signals to escape out from under the HID package to other components on the PCB board or substrate.

[0087] FIG. 7C depicts one of the four square segments 775 in the center of the ball map in FIG. 7B. In each of the segments, multiple smaller boxes 752, each having four connectors 781 and one via 782. With this arrangement the four connectors 781 may be electrically connected to one via 782 to connect to a power or ground plane. A non-standard pad design may be employed, which is a copper plate instead of BGA balls.

[0088] According to some embodiments, an HID such as a SiP is provided. The SiP may be, for example, the SiP used in a system, and comprise: a SiP substrate, having an array of external connectors arranged on a bottom surface of the SiP substrate; a microprocessor die mounted on and electrically connected to the SiP substrate; a memory die attached to the processor and electrically connected to a redistribution layer (RDL) located on top of the memory and the RDL is electrically connected to the SiP substrate; and a plurality of supportive passive components mounted on the SiP substrate and at least partially interconnected with the microprocessor and the memory. In certain aspects, a first plurality of groups of the array of exterior connectors is configured for providing the external signals from at least one of said plurality of SiP components to a plurality of electronic components mounted on a PCB, a second plurality of the array of exterior connectors is configured for providing power and ground connections for the SiP from the power layer and the ground plane layer of the PCB, respectively, and the first plurality of groups of the array of exterior connectors is arranged along one or more outer edges of the SiP substrate and the second plurality of connectors is arranged in a center of the substrate.

[0089] Using methods according to one or more embodiments, a PM chip can be constructed with an AM6254 processor available from Texas Instruments in flip-chip die form. The die has over 1000 bumps and has approximately 20 power inputs and approximately 10 I / O power inputs. The main processor is a quad-core A53 (with R5 and M4 co-processors) with clock speeds up to 1400 MHz. Some peripherals are display (parallel RGB and LVDS), GPU, Ethernet, and a CSI camera interface. For this example, the memory selected is DDR4 die available from memory manufacturers, including, but not limited to Micron, Winbond, ISSI, Nanya, Hynix, Samsung, etc. Memory size may be 8Gb or 16Gb. The memory has approximately 100 bond pads and approximately 5 power and ground inputs. LPDDR4 memory may also be employed, but its 32bit bus does not match the 16bit bus width of theselected processor. The processor is mounted on a 4-layer substrate that is 9mm by 14mm and has 500 BGA balls with a pin spacing of 0.5mm. Each layer of the four layers may have power and ground islands in addition to signal traces. The substrate has upwards of 1500 surface connectors (over 1000 processor, -100 memory, -100 passives). A Redistribution Layer (RDL) is employed that has 1 routing layer with at least other layers for passivation and bond pads. The number of routing layers may change depending upon the selected memory and other factors. The RDL is the same size as the memory die and has approximately 100 connectors. The RDL is connected to the memory and uses bond wires to make connections from the RDL to the substrate. The memory and processor signal and address interconnections are balanced in signal lengths to minimize signal skew between these two components.

[0090] In embodiments, the PM chip has reduced the number of small capacitance value capacitors to approximately 30, and large capacitance value capacitors on chip to approximately 5, and pullup / pulldown resistors to approximately 10 that are all surface mounted passive devices.

[0091] EIG. 8A is a flow chart for a method 800 for the design of a Processor Module (PM) according to embodiment. Lirst, a microprocessor (uP) or family of microprocessors is selected 801 based on a specified performance selection criterion. Next, the maximum external pin count is determined 802 for the selected uP. Next, the types and sizes of the selected memories are chosen 803 to be integrated on the PM (see PIGs. 2-4). Next, the electrical circuit (schematic) is designed 804 with the selected uP, memory and passives. Next, the substrate’s optimal size is determined 805 based on the trade-off of the uP’s pin count, pin spacing, and the core size (e.g.„ the sum of the components’ areas). Next the interconnections between the uP, the selected memory and the necessary passives are laid out 806. Next, how many of the PM’s uP I / O, power and ground signals need to have external pins is determined 807. Next, the recommended number of bulk capacitors, bypass capacitors, and other passive devices needed is determined 808. Next, the quantity and values of the capacitors are reduced 809 based on design constraints and vendor recommendations. Next, the capacitors and the resistor pull ups and pull downs based on the vendor recommendations and the PM’s pin count constraints are minimized 810. Next, selected power rail bulk capacitors are moved from the PM and placed on the system PCB substrate 811, and the final substrate size is determined 812. Linally, the signal connection lengths between the microprocessor 202 and the memory 201 are adjusted 813 to minimize signal skew.

[0092] Additional aspects of a processor module design method can include a method for managing the thermal aspects of the PM. As the uP 202 and memory 201 do not have the sameoperating temperature ranges, it is advantageous to thermally manage them separately, as much as possible. The first step is to, as much as possible, thermally isolate the two devices from each other (see FIG.s 3A-3B, for example). By thermally isolating the two devices, the memory can then be managed through the top surface of the PM using passive and active devices such as, for example, but not limited to, heat sinks, fans, and active thermal management devices. Further the uP 202 can be managed through the bottom surface of the PM by, such as, for example, but not limited to, taking advantage of the thermal conductivity of the external conductor pins 215 and, 425, and the traces and vias of both the PM and the Heterogeneous Integrated Circuit Device (HID) or system in package (SiP) 420 to which the PM is attached. In embodiments, these adjustments may be made between steps 811 and 812. However, they may occur elsewhere. Finally, other active and passive thermal management techniques may be employed based on the use and environmental requirements of the end equipment of which the PM is a component.

[0093] FIG. 8B depicts a method 820 for designing a Processor Module (PM). In some embodiments, the first step is to determine 822 system requirements: package size, power pins, signal pins, processor, memory size, etc. The next step is to design 824 the schematic, PM package (x, y and z dimensions), and pin assignments. Next is to lay out PM substrate in step 826. The next step is to build and populate PM substrates 828 to create prototypes, and then evaluate 830 the PM prototypes. If the prototypes do not function correctly, a (FAIL) return is used back to step 824. If the prototypes function correctly (PASS), the PM is released 832 to production.

[0094] FIG. 8C depicts a process 840 to determine the optimal placement of connectors in a SiP substrate for minimizing the number of layers in a system PCB using that SiP. According to some embodiments, all pins or signals of all the components in the SiP are classified into different categories in first step 841. These may include, for example, power and ground inputs, power outputs, internal power connections (e.g., those used only internally), internal signals used only internally, internal signals connected externally, external signals, and test points (required for monitoring internal signals and / or internal power connections). The data sheets for the components used in the SiP may be consulted to determine what signals and passives are needed for each component in the SiP and their respective classification or category. Additionally, the data sheet for the SiP components may be consulted to determine which, if any, components in the SiP are only used for internal interconnections with the other components in the SiP and have no requirement for external connections. In step 842, power inputs, grounds and power outputs are consolidated in one category by voltage and powerdomains to determine the number of package pins needed for each power input, ground or power output.

[0095] In certain aspects, the initial number of external connectors needed for power and ground may be reduced by consolidating some of the same voltages and grounds to a single external connector by voltage value and by ground, depending upon maximum current demands for that external connection and the maximum internal currents for the interconnections between that external connector and the internal or external devices / components being supplied by that external connector.

[0096] In some embodiments, the category for internal signals that are used only internally and internal power connections that do not require monitoring test points, as well as any other signals that do not need to be connected to external pins (or balls) may be eliminated from consideration, as they have no need for any external connection. According to some embodiments, the process may move to step 843 for consolidating the set of signals that require external connectors, or package pins (or balls) for use in the system and accordingly connections to the system PCB.

[0097] Next, and according to some embodiments, how many pins are available for use in the SiP package must be determined 844, and accordingly the corresponding connecting locations on the system PCB. That is, determining the number of package pins that can be routed on a given PCB layer for a given PCB technology node 844 can be based on the package used for the SiP. For example, using 1 mm pitch BGA pins and a 5 mil PCB trace spacing with 6 mil tolerance between traces, this results in the outer three rows / columns of the BGA being able to be routed on a single layer of the PCB substrate. According to some embodiments, any pins inside the outer three rows / columns of the BGA cannot be routed on a single PCB layer, if needed externally. In certain aspects, once the numbers, spacing and size of pins for a package have been determined for a given PCB in step 844, then placement of the minimal set of signals determined through step 843 can begin.

[0098] According to some embodiments, initially, the external signals can be placed 845 on package connection balls such that they can be routed in the fewest number of PCB layers. Second, the power inputs, grounds and power outputs should be centrally placed 846 such that it is easy to connect to PCB power and ground planes. Then, associated internal signals connected externally should be placed 847 next to each other. Next, test points should be placed 848 such that it is easy to connect to a test pad. Finally, any remaining pins are left unconnected 849.

[0099] Using the methods of the present disclosure can allow for a reduced number of layers in a system PCB using a SiP device, thereby reducing the system PCB costs, as well as eliminating the need to place components on the bottom or underside of the system PCB because of these optimum interconnections.

[0100] Referring now to FIG. 8D, a process is provided for optimizing a system comprising a printed circuit board (PCB) and a System-in-Package (SiP) mounted on the PCB according to some embodiments. In step 861, signals generated by or used by components of the SiP are identified. In step 862, signals of the identified SiP components that are internal signals of the SiP are grouped, and signals of the identified SiP components that are external signals for the SiP are grouped together. In step 863, power input, power output, and ground lines for the SiP components are identified and grouped together. In step 864, an array of package connectors of the SiP, such as pins or balls, are arranged such that all of the external signals are connected to one or more escape traces on a top layer of a PCB and such that at least one of the power input, power output, and ground lines is connected to a power or ground via of the PCB through at least one of the package connectors.

[0101] FIG. 8E depicts a method 880 to design and create smaller integrated devices (like a SiP) that use die for the active devices and surface mounted passive devices. The initial step is selecting the die for the active devices and then selecting the optimum physical layout of those devices. A method for reducing or otherwise optimizing a system integrated circuit size (SiP) is provided according to embodiments, with main steps as follows:Selecting a processor with a feature set (CPU performance, co-processors, and peripherals) that meets the needs of a system for a specific application (881), Selecting a circuit diagram for the system having active and passive components (882),- Selecting die for the active components with feature sets that meet the need of the selected system (883),Selecting passive components based on manufacturer data sheets for active components and system substrate size constraints (884),- Selecting a physical arrangement of active components on a substrate (885), Selecting a substrate for assembly of active and passive components (886), Selecting the substrate size based on passive components and the die sizes of the active components and their physical arrangement and mounting arrangement on the substrate (887),Selecting the pin spacing for the substrate and evaluating the I / O and power pin requirements for the active components based on manufacturer data sheets for the die selected size (888),Adjusting the substrate size based on the size of the die for the active components mounted thereon and pin spacing and I / O and power pin requirements (889),- Creating a substrate with spaced multiple layers of conductive traces that are insulated from each other and vias for interconnecting selected traces and that reflects / implements the circuit diagram (890),- Reducing / adjusting number, size and value of passive components from manufacturer data sheets (891),- Reducing skew between active components by matching signal trace lengths between those components for groups of signal lines (892),Arranging exterior input / output signal pins in groups of similar signals along the outer periphery of the substrate so that signals can escape from beneath the substrate to the system PCB on which it to be mounted using a minimum number of PCB layers (893),Arranging exterior input / output power / ground pins in groups in the center portion of the substrate (894),Selecting thermal components to provide thermal isolation for selected active components (895), and- Thermally isolate and / or manage the active components independently, and potentially capture and utilize any heat when captured (896).

[0102] FIG. 9 is an overview of one process flow 900 for embodiments of the Processor Module and its further integration in a System in Package (SiP). The PM 200 integrates the processor 202 with a memory 201 and a portion of the passive devices 212a / b / c / d needed to properly condition the processor 202 and memory 201. It further includes the necessary components for thermally managing 304 / 321 / 322 / 325 the PM 200. Once these components 921 are attached to the substrate 203 and external connectors 215 are attached, the PM 200 is ready for further integration with the external support components 922: power management 401, large passives 421a / b / c / d such as bulk capacitors, resistors and inductors. These support components 931 are integrated with the PM 200 on a System PCB 303 with external connectors attached 425. Not shown in this flow graph is that the process may continue with either the PM 200, the SiP 420 or both being encapsulated.

[0103] Summary of Embodiments.

[0104] According to embodiments, a SiP is used in a system PCB and comprises: a substrate, having an array of external connectors arranged on a first surface of the substrate; a processor mounted on and electrically connected to the substrate on a surface opposite from the first surface; a memory attached to and thermally isolated from the processor and electrically connected to an RDL located on top of the memory and the RDL is electrically and operatively connected to the substrate; and a plurality of passive electronic components mounted on the substrate and operatively interconnected with the processor and the memory, wherein a first plurality of exterior connectors is configured for providing external signals from the components on said substrate to a plurality of electronic components mounted on said PCB and arranged along one or more outer edges of the substrate, and a second plurality of exterior connectors is configured for providing power and ground connections from the power layer and the ground plane layer of said PCB to the components on the substrate and arranged in a center of the array. Other physical arrangements may be employed, which may result in the RDL becoming optional.

[0105] According to embodiments, a system is provided. The system comprises, for example, a System-in-Package (SiP), wherein the SiP comprises an array of connectors on a bottom surface of the SiP, and a printed circuit board (PCB). In certain aspects, the PCB comprises a top layer, a ground layer, and a power layer, wherein the top layer comprises a plurality of escape traces on a top surface of the PCB. The PCB may include, for example, only 4 layers. The system may also comprise a plurality of electronic components mounted on the top surface of the PCB, wherein at least one of the plurality of electronic components is electrically connected to at least one of the plurality of escape traces. In certain aspects, the SiP is mounted on the top surface of the PCB and is arranged such that all external signals of the SiP are connected to the plurality of escape traces using the array of connectors. The connectors may be, for instance, one or more of an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on the PCB. In some embodiments, the PCB has a bottom surface and no components are mounted on that bottom surface. Additionally, at least one of the connectors in the array of connectors may be a test point of the SiP and contact at least one of the ground layer and the power layer using a via of the PCB. In some embodiments, the electronic component electrically connected to the at least one escape trace is a digital processor, memory, graphics device, analog device, power management circuit, communications device, or sensor.

[0106] According to embodiments, a SiP is provided. The SiP may be, for example, the SiP used in the system described above, and comprise: a SiP substrate, wherein the array ofconnectors on a bottom surface of the SiP substrate; a processor mounted on and electrically connected to the SiP substrate; a memory mounted on and electrically connected to the SiP substrate; and a plurality of SiP electronic components mounted on the SiP substrate and at least partially interconnected with one or more of the processor and the memory. In certain aspects, a first plurality of the connectors is configured for providing the external signals from at least one of said plurality of SiP electronic components to the plurality of electronic components mounted on the top surface of said PCB, a second plurality of the connectors is configured for providing power and ground connections for the SiP to the power layer and the ground layer of said PCB, respectively, and the first plurality of connectors is arranged along one or more outer edges of the array and the second plurality of connectors is arranged in a center of the array.

[0107] According to embodiments, a System-in-Package (SiP) is provided. The SiP comprises, for example, a SiP substrate; a processor mounted on and electrically connected to the SiP substrate; a memory mounted on and electrically connected to the SiP substrate; a plurality of electronic components mounted on the SiP substrate and at least partially interconnected with one or more of the processor and the memory; and an array of connectors arranged on a bottom surface of the SIP package. In certain aspects, a first plurality of the connectors is configured for providing signals from at least one of said plurality of electronic components to an external device, and a second plurality of the connectors is configured for providing power and ground connections for the SiP. In some embodiment, the first plurality of connectors is arranged along one or more outer edges of the array and the second plurality of connectors is arranged in a center of the array. In some embodiments, the outer edge of the array is the outermost three rows of connectors.

[0108] In some embodiments, the array of connectors is one or more of an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on a PCB. Additionally, the electronic components may comprise one or more of a digital processor, memory, graphics device, analog device, power management circuit, communications device, and sensor.

[0109] According to some embodiments, a method for optimizing a system comprising a printed circuit board (PCB) and a System-in-Package (SiP) mounted on the PCB is provided. The method may include identifying signals generated by or used by components of the SiP, grouping signals of the identified SiP components that are internal signals of the SiP, and grouping signals of the identified SiP components that are external signals for the SiP. The method may also include identifying and grouping power input, power output, and ground linesfor the SiP components. In some embodiments, the method also includes arranging the components and their connection to an array of package connectors of the SiP such that all of the external signals are connected to one or more escape traces on a top layer of said PCB and such that at least one of the power input, power output, and ground lines is connected to a via of the PCB through at least one of the package connectors, wherein the via is electrically connected to a power or ground layer of the PCB. The arranging may comprise, for example, determining the number and location of the package connectors, routing the external signals to one or more package connectors along one or more outer edges of the array, and routing one or more of the power input, power output, and ground lines to one or more package connectors in a center of the array.

[0110] One advantage of a SiP device is the potential opportunity to optimize the pin arrangement (or other set of connections, such as a ball grid array) with respect to the system of which it may become a part. According to some embodiments, this is possible in either general puipose SiPs, which may be used in a variety of different system implementations, or in a specific system implementation where the pin arrangement of the SiP may be designed specifically for an optimal layout for a larger system.

[0111] According to some embodiments, a system is provided. The system comprises, for example, a System-in-Package (SiP), wherein the SiP comprises an array of connectors on a bottom surface of the SiP, and a printed circuit board (PCB). In certain aspects, the PCB comprises a top layer, a ground layer, and a power layer, wherein the top layer comprises a plurality of escape traces on a top surface of the PCB. The PCB may include, for example, only 4 layers. The system may also comprise a plurality of electronic components mounted on the top surface of the PCB, wherein at least one of the plurality of electronic components is electrically connected to at least one of the plurality of escape traces. In certain aspects, the SiP is mounted on the top surface of the PCB and is arranged such that all external signals of the SiP are connected to the plurality of escape traces using the array of connectors. The connectors may be, for instance, one or more of an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on the PCB. In some embodiments, the PCB has a bottom surface and no components are mounted on that bottom surface. Additionally, at least one of the connectors in the array of connectors may be a test point of the SiP and contact at least one of the ground layer and the power layer using a via of the PCB. In some embodiments, the electronic component electrically connected to at least one escape trace is a digital processor, memory, graphics device, analog device, power management circuit, communications device, or sensor.

[0112] One or more embodiments relate to heterogeneous integrated circuit devices (HIDs). HIDs can include devices with multiple active and passive components integrated together in a single package. Such HID devices are attractive because they may allow for miniaturization of a complete system in a single package. In some cases, use of HID can reduce an entire microelectronic system on a printed circuit board (which may be tens of square cm in size) to a single package of a square cm or less. HID technology is used in Systems on Module (SOM) devices, System in Package (“SiP”) devices, Multi-Chip Module (MCM) devices, that can provide components or systems that are otherwise impossible or impractical to integrate in a single silicon circuit such as an ASIC or SoC.

[0113] In certain aspects, heterogeneous integrated circuit devices (HID) enable integration of devices, with diverse fabrication technologies, such as digital, analog, optical, and memory processes. Other devices may also be integrated, including active and / or passive devices and components (e.g., discrete circuits, sensors, power management devices, and various nonsilicon devices). Some examples of non-silicon devices are mechanical, biologic, organic, fluid, etc. components, as well as germanium and gallium nitride (GaN). In some embodiments, even HID devices, such as SiPs for instance, may be integrated as a component in another HID device. Additionally, HID devices may include mechanical devices. One example is mechanical energy source using vibration or heat to create electrical energy (e.g., a self -winding watch concept). A HID device may provide a combination of components that are difficult to properly interface with each other (like a processor and memory) in a single package.

[0114] One or more embodiments include processors or CPUs, which can include the logic circuitry that responds to and processes the basic instructions that drive / control / operate a computer system. In some embodiments, a processor may be responsible for the execution of computer commands. The different types of processors that may be used in PM devices of the present disclosure include, for example, Central Processing Units (CPUs), Graphics Processing Units (GPUs), Multi-Core Processors (MCPs), Microprocessors (uP), Microcontrollers / Microcomputers (uC), and Quantum Processors. Other types also include Digital Signal Processors (DSPs), Analog Signal Processors (ASP), and Application-Specific Integrated Circuit (ASIC). A processor may be either fixed function or programmable. Programmable computers are typically programmed using software as in a digital processor (e.g., uC or uP); or may be hardware configurable as in a Field Programmable Gate Array (FPGA), or a Configurable Logic Device (CLD).

[0115] One or more embodiments use passive devices, which can include, for instance, electronic devices that do not need an external power source for them to function properly. The three most common types of passive devices are resistors, capacitors and inductors. There are other devices / components or elements that fit into the definition of a passive, for example, but not limited to, diodes, and many optical passives.

[0116] Many semiconductor (S / C) devices, including HIDs, may use a ball grid array for external attachment to a printed circuit board (PCB) (or substrate). Other types of attachment, such as for example, but not limited to, QFN or POP may be employed. The HID may be interconnected to other components located on a PCB to form a system. Systems may employ multiple S / C devices, packaged and / or unpackaged, and operatively interconnected via layers of signal traces and vias.

[0117] Some embodiments add serpentine segments to associated physical traces so that the electrical lengths of the associated traces are as close as possible to the same. However, in actual integrated circuits design and fabrication this may be difficult to achieve as some trace connections may be made through traces and vias in a substrate and different connectors on different components mounted thereon; it may also involve wire bond connectors between the two components. Some trace length adjustments may also be needed to compensate for other variations, such as for example, but not limited to different contact materials on portions of the interconnection paths to optimize interconnections between components for improved / faster system operations.

[0118] The external / exterior connectors in a HID substrate may be optimized for minimizing the number of layers in a system PCB using that HID. In embodiments, first, all pins or signals of all the components in the HID are classified into different categories. These may include, for example, power and ground inputs, power outputs, internal power connections (e.g. those used only internally), internal signals used only internally, internal signals connected externally, external signals, and test points (required for monitoring and managing internal signals and / or internal power connections). The data sheets for the components used in the HID may be consulted to determine what signals are needed for each component in the HID and their respective classification or category. Additionally, the data sheet and schematic for the HID may be consulted to determine which, if any, components in the HID are only used for internal interconnections with the other components in the HID and have no requirement for external connections.

[0119] According to some embodiments, a system is provided. The system comprises, a system printed circuit board (PCB) with a plurality of components operably interconnected, anHID that is a System-in-Package (SiP), with a SiP substrate that comprises an array of exterior connectors arranged on a bottom surface of the SiP substrate that is attached to the system printed circuit board (PCB). The system PCB comprises a top layer, a ground layer, and a power layer, wherein the top layer comprises a plurality of escape traces on a top surface of the PCB to connect to the SIP array of exterior connectors. The use of escape traces on the PCB for the array of exterior connectors on the SiP substrate may allow the PCB to contain fewer layers of traces, for example, only 4 layers. That is the exterior pins for an HID may be aligned so that the PCB on which the HID is to be mounted on and interconnected with has a reduced number of layers from the number of layers required without this alignment.

[0120] The system PCB may also comprise a plurality of electronic devices mounted on the top surface of the PCB, wherein at least one of the plurality of electronic devices is electrically connected to at least one of the plurality of escape traces. The system PCB typically has as many components as possible on the top surface to minimize the cost of the PCB. In certain aspects, the SiP is mounted on the top surface of the system PCB and is arranged such that external signals of the SiP are connected to the plurality of escape traces on the PCB using the SiP’s substrate array of exterior connectors. The exterior connectors may be, for instance, one or more of, an array of pins, an array of balls, and an array of contact surfaces, adapted for surface mount on the PCB. In some embodiments, the system PCB has a bottom surface, and no components are mounted on that bottom surface.

[0121] Additionally, at least one of the connectors in the array of exterior connectors may be a test point of a SiP and contact at least one of the ground layers and the power layers using a via of the PCB. In some embodiments, the electronic component electrically connected to at least one escape trace is a digital processor, memory, graphics device, analog device, power management circuit, communications device, sensor, or other active device.

[0122] According to some embodiments, an HID or SiP is provided. The SiP may be, for example, the SiP used in the system described above, and comprise: a SiP substrate, having an arranged array of external connectors on a bottom surface of the SiP substrate; a processor die mounted on and electrically connected to the SiP substrate using connections on the top surface of the substrate and external connectors on a surface of the microprocessor; a memory die located on the processor; redistribution layer (RDL) mounted on and electrically connected to the memory and electrically connected to the SiP substrate; and a plurality of passive electronic components mounted on the SiP substrate and at least partially interconnected with one or more of the processor and the memory. In certain aspects, a first plurality of the exterior connectors is arranged to provide external signals from at least one of said plurality of SiP components tothe plurality of electronic components mounted on the top surface of said PCB, a second plurality of the exterior connectors is configured for providing power and ground connections for the SiP to the power layer and the ground layer of said PCB, respectively, and the first plurality of connectors is arranged along one or more outer edge of the device and the second plurality of connectors is arranged in a center of the device. Other physical arrangement for the components may be employed as noted herein, such as for example, but not limited to mounting memory on the substrate and locating the microprocessor on top of the memory.

[0123] In HID devices, many power, ground and conductive signal planes of traces and vias may be used to properly power and interconnect its internal active and passive components. These conductive planes of traces may be attached to multiple external connectors.

[0124] Ball grid arrays (BGAs) are used as examples herein, as they are widely used in the industry to attach packaged devices to printed circuit boards (PCB) and other connection surfaces. But other external connection structures such as, but not limited to, QFN, POP, through hole, leaded, leadless, magnetic, and optical connectors have similar issues and may also use, and benefit from, embodiments described herein.

[0125] Vendor data sheets for various general-purpose components are typically written for a PCB type design case, rather than a heterogeneous integrated device (HID) design case, and thus are overly conservative for an HID design. For instance, reduction in the size of a device reduces the length of a power trace, or power rail, and other signal traces in a heterogeneous integrated circuit device (HID) which allows the capacitive values and numbers of devices recommended by the various component manufacturers to be reduced to smaller capacitive values and / or in number and physical size, which saves in both cost and size for an HID substrate implementation. In addition to capacitors, manufacturer data sheets may also require other passives such as resistors and inductors for which an HID device may be able to perform well with further optimizations for such passives (like smaller physical and electronic value size, lower voltage, lower operating power).

[0126] Additional embodiments are provided below.

[0127] Al. A packaged semiconductor device (HID), comprising: a substrate having conductive traces in layers separated by insulators and vias interconnecting portions of the traces and having a first and second set conductors on a top surface and a plurality of external connectors on the opposite surface of the substrate, a microprocessor die having external connectors on one surface of the die and mounted on the substrate such that the external connectors are operatively attached to a first set of conductors on the top surface of the substrate, a memory die with a first surface mounted on the top of the microprocessor and asecond surface opposite the first surface with a plurality of external connectors thereon, an interposer substrate (RDL) with a first surface mounted on top of the memory second surface and having a first plurality of conductors on the first surface operatively interconnected to the plurality of external connectors of the memory on the second surface of the memory, [a second plurality of conductors on the first surface of the interposer substrate (RDL) spaced apart from the first plurality of conductors] and having a plurality of external connectors on a second surface opposite the first surface, a plurality of one or more of bond wires, connectors or bumps operatively interconnecting appropriate external connectors of the interposer substrate with the second set of conductors on the substrate, wherein the bond wires in combination with the second and first plurality of conductors operatively interconnect the memory and the microprocessor, and the external connectors of the substrate provide control, input and output signals to the microprocessor and power and ground signals to the memory, and an encapsulant containing the microprocessor, memory, bond wires and selected passive components mounted on the substrate.

[0128] A2. The packaged semiconductor device (HID) of Al, further comprising: a plurality of high frequency [bypass | capacitors located on the RDL, each in one of the connections between the memory input and output and the output and input of the microprocessor, respectively.

[0129] A3. The packaged semiconductor device (HID) of Al, further comprising: a first portion of the bulk capacitors needed for voltage maintenance located on the substrate.

[0130] A4. The packaged semiconductor device (HID) of Al, wherein the RDL comprises a substrate.

[0131] A5. The packaged semiconductor device (HID) of Al, wherein said connection balls interconnect appropriate external connectors.

[0132] BL A method for designing a processor and memory semiconductor device, comprising: selecting a microprocessor based on specified selection criteria, selecting a memory type and memory device capacity, determining the connections between the selected microprocessor and memory, determining the number of microprocessor and memory input / output signals that may be contained within the device and do not need external connections, determining the number of external connections for the selected microprocessor and pin spacing and memory, and other desired external connections, determining the die size for the selected microprocessor and memory, determining the number, size, value and location of capacitors that are recommended by the vendors of the data sheets for the selected microprocessor and memory to minimize voltage sag and noise, placing / providing on thedevice a selected portion of capacitors from those recommended by data sheets for power supply and ground for the microprocessor and memory, deducing the number, size and capacitance values of those capacitors on the device from those recommended by data sheets for power supply and ground for the microprocessor and memory based on component spacings in the device, determining a substrate size and number of layers based on the die size for the selected microprocessor and memory, microprocessor pin count, number of passives and desired pin spacing / pitch, adjusting the interconnections between the microprocessor and memory to minimize any signal skew, adjusting the external package pin locations for the device to arrange locations by types of input / output, control and test signals along the outer edges of the device with spacing determined by the desired external pin count related to selected application use and selected pin spacing therebetween for the device, and the external package pins for power and ground in the center of the device, and determining a substrate size and number of layers based on a tradeoff between (i) the die sizes for the selected microprocessor and memory, the number of passives and (ii) the desired pin pitch based upon the selected microprocessor pin count.

[0133] Cl. A method for designing a reduced size processor semiconductor device, comprising: selecting a microprocessor with a feature set (CPU performance, co-processors, and peripherals) that meets the needs of a system for a specific application, determining the maximum pin count for the selected microprocessor, selecting a memory type and size, determining the die size for the selected microprocessor and memory, determining a substrate size and number of layers based on the die size for the selected microprocessor and memory (e.g., based on microprocessor pin count required for external connections and size and quantity of any other active and passive devices), determining the connections between the selected microprocessor and memory, determining the number of microprocessor and memory input / output signals that may be contained within the device and do not need external connections, determining the number, size, value and location of bypass and batch capacitors that are recommended by the vendors of the data sheets for the selected microprocessor and memory, deducing the number, size and values of those determined capacitors based on unique design requirements for component spacings in the device, determining a first number of bulk capacitors for the power supplies and grounds for the microprocessor in the device, adjusting the interconnections between the microprocessor and memory to remove any signal skew, adjusting the input / output pin locations for the device to arrange input / output, control and test signals in outer rows along the edge of the device with spacing determined by the external pincount of the substrate and for a system PCB and spacing therebetween for the device and the power and ground pins in the center of the pin array of the device.

[0134] DI. A method for optimizing a system integrated circuit, comprising: selecting a processor with a feature set (CPU performance, co-processors, and peripherals) that meets the needs of a system for a specific application, selecting a circuit diagram for the system having active and passive components, selecting die for the active components, selecting passive components based on manufacturer data sheets for active components and system input / output substrate size constraints, selecting a physical arrangement of active components on a substrate, selecting a substrate for assembly of active and passive components, selecting the substrate size based on the physical die sizes of the active and passive components and their physical arrangement and mounting arrangement on the substrate, selecting the pin spacing for the substrate and evaluating the I / O and power pin requirements for the active components based on manufacturer data sheets for the die selected size, adjusting the substrate size based on the size of the die for the active components mounted thereon and pin spacing and I / O and power pin requirements, creating a substrate with spaced multiple layers of conductive traces that are insulated from each other and vias for interconnecting selected traces and that reflects / implements the circuit diagram, reducing / adjusting number, size and value of passive components from manufacturer data sheets, reducing signal skew among groups of signal lines between active components by matching signal trace lengths between those components, arranging exterior input / output signal pins in groups of similar signals along the outer periphery of the substrate so signals can escape from under the substrate, arranging exterior input / output power / ground pins in groups in the center portion of the substrate, selecting thermal components to provide thermal isolation for selected active components, and thermally isolate and / or manage the active components independently and potentially capture and utilize any heat when captured.

[0135] El. A packaged semiconductor device, comprising: substrate having conductive traces in layers separated by insulators and vias interconnecting portions of the traces and having a first set conductors on a top surface arranged in a first pattern and second set conductors on a top surface spaced apart from said first set of conductors and a plurality of external connectors on the opposite surface of the substrate from the top surface arranged in a second pattern, a microprocessor die having external connectors on one surface of the die arranged in a mirror image of said first set of conductors on the top surface of said substrate and mounted on the substrate such that the external connectors are operatively attached to said first set of conductors on the top surface of the substrate, a memory die with a first surfacemounted on the top of the microprocessor and a second surface opposite the first surface with a plurality of external connectors thereon, a redistribution layer (RDL) with a first surface mounted on top of the second surface of said memory and having a first plurality of conductors on the first surface operatively interconnected to the plurality of external connectors of the memory on the second surface of the memory, a second plurality of conductors on the first surface of the RDL spaced apart from the first plurality of conductors and having a plurality of external connectors on a second surface opposite the first surface, a plurality of one or more of bond wires, connectors or bumps operatively interconnecting appropriate external connectors of the RDL with the second set of conductors on the top surface substrate, wherein the bond wires in combination with the second and first plurality of conductors and the layers and vias operatively interconnect the memory and the microprocessor, and the external connectors of the substrate provide control, input and output signals to the microprocessor and power and ground signals to the memory, and an encapsulant containing the microprocessor die, memory die, bond wires and passive components mounted on the substrate.

[0136] FL A packaged semiconductor device, comprising: a substrate having conductive traces in layers separated by insulators and vias interconnecting portions of the traces and having a first set conductors on a top surface arranged in a first pattern and second set conductors on a top surface spaced apart from said first set of conductors, a plurality of external connectors on the opposite surface of the substrate from the top surface arranged in a second pattern, and passive components mounted on the top surface of the substrate, a microprocessor die having external connectors on one surface of the die arranged in a mirror image of said first set of conductors on the top surface of said substrate and mounted on the substrate such that the external connectors are operatively attached to said first set of conductors on the top surface of the substrate,

[0137] a memory die with a first surface mounted on the top of the microprocessor and a second surface opposite the first surface with a plurality of external connectors thereon, a plurality of one or more of bond wires, connectors or bumps operatively interconnecting appropriate external connectors of the memory die with the second set of conductors on the top surface substrate, wherein the bond wires in combination with the second and first plurality of conductors and the layers and vias operatively interconnect the memory and the microprocessor, and the external connectors of the substrate provide control, input and output signals to the microprocessor and power and ground signals to the memory, and an encapsulant containing the microprocessor die, memory die, bond wires and passive components mounted on the substrate.

[0138] Gl. A packaged semiconductor device, comprising: a substrate having conductive traces in layers separated by insulators and vias interconnecting portions of the traces and having a first set conductors on a top surface arranged in a first pattern and second set conductors on a top surface spaced apart from said first set of conductors, a plurality of external connectors on the opposite surface of the substrate from the top surface arranged in a second pattern, and passive components mounted on the top surface of the substrate, a processor die having external connectors on one surface of the die arranged in a mirror image of said first set of conductors on the top surface of said substrate and mounted on the substrate such that the external connectors are operatively attached to said first set of conductors on the top surface of the substrate, a device die with a first surface mounted on the top of the microprocessor and a second surface opposite the first surface with a plurality of external connectors thereon, a plurality of one or more of bond wires, connectors or bumps operatively interconnecting appropriate external connectors of the device die with the second set of conductors on the top surface substrate, wherein the bond wires in combination with the second and first plurality of conductors and the layers and vias of the substrate operatively interconnect the memory and the device, and the external connectors of the substrate provide control, input and output signals, and power and ground signals to the processor and device, an encapsulant containing the microprocessor die, device die, bond wires and passive components mounted on the substrate.

[0139] G2. The packaged semiconductor device of claim 11, further comprising: a second device die operatively interconnected with the processor die and device die.

[0140] While various embodiments of the present disclosure are described herein, it should be understood that they have been presented by way of example only, and not by way of any limitation. Thus, the breadth and scope of the present disclosure should not be limited by any of the herein above -described exemplary embodiments. Moreover, any combination of herein above-described elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context. Accordingly, other embodiments, variations, and improvements not described herein are not excluded from the scope of the present disclosure. Such variations include but are not limited to new substrate material, different kinds of devices attached to the substrate not discussed, or new packaging concepts.

Claims

What is claimed:

1. A packaged semiconductor device (295), comprising: a substrate (203); a first device (202); and a second device (201), wherein the second device is stacked on the first device and the first and second device are mounted on the substrate, wherein a plurality of signal paths between the first device and the second device have substantially the same electrical length, such that they arrive at the same time as each other when sent between the first and second device.

2. The device of claim 1, wherein the first device is a processor and the second device is a memory.

3. The device of claim 1 or 2, further comprising one or more bond wires, wherein the bond wires connect an upper surface of the second device to an upper surface of the substrate.

4. The device of any of claim 1-3, wherein the signals comprise data and address signals.

5. The device of any of claims 1-4, wherein all signal paths between the first and second device has substantially the same electrical path.

6. The device of any of claim 1-5, wherein at least one of the signal path comprises a serpentine section configured to elongate the electrical length of the path.

7. The device of any of claims 1-6, further comprising a plurality of passive components mounted on the substrate.

8. The device of claim 7, wherein the first device, the second device, and the plurality of passive components are encapsulated together.

9. The device of any of claims 1-8, wherein the substrate comprises: conductive traces in layers separated by insulators, and vias interconnecting portions of the traces, a first set of conductors on a top surface of the substrate that are arranged in a first pattern, a second set of conductors on the top surface that are spaced apart from the first set of conductors, and a plurality of external connectors on the opposite surface of the substrate from the top surface that arranged in a second pattern, wherein the passive components are mounted on the top surface of the substrate.

10. The device of claim 9, wherein the first device comprises: a plurality of external connectors on a first surface of the device that are aligned with the first set of conductors on the top surface of the substrate, wherein the first device is mounted on the substrate such that the external connectors are operatively attached to the first set of conductors on the top surface of the substrate.

11. The device of claim 10, wherein the second device comprises a first surface and a second surface opposite the first surface, and wherein the second surface has a plurality of external connectors attached to the bond wires.

12. The device of claim 11, wherein the bond wires in combination with the second and first plurality of conductors and the layers and vias of the substrate operatively interconnect the memory and the processor, and wherein the external connectors of the substrate provide control, input and output signals, and power and ground signals to the processor and memory.

13. The device of any of claims 1-12, further comprising:an interposer redistribution layer.

14. A heterogeneous integrated device (270, 290), comprising: a substrate (203) having traces in layers separated by insulators and vias interconnecting portions of traces and having a first set of conductors on a top surface arranged in a pattern and a second set of conductors on said top surface and having a plurality of external connectors on the opposite surface of the substrate; a bumped microprocessor die (202) having external bumps arranged in a mirror of said pattern on one surface on the die and mounted on the substrate such that said external bumps are operatively attached to said first set of conductors arranged in said pattern on the surface of said substrate; a memory die (201) with a first surface mounted on the top surface of the microprocessor and a second surface opposite the first surface with a plurality of external connectors thereon; a single layer interposer substrate (RDL) (206, 276) with a first surface mounted on top of the memory second surface and having a first plurality on the first surface operatively interconnected to the plurality of external connectors of the memory on the second surface of the memory and having a plurality of external connectors on the second surface opposite the first surface for a first set of realigned signals to and from memory and at least partially balanced lengths for signal traces; one or more bond wires (205) operatively interconnecting at least one external connector of the interposer substrate with the second set of conductors on the substrate, wherein the bond wires in combination with the second and first plurality of conductors and bumps operatively interconnect the memory and microprocessor providing at least partially balanced length signal traces, wherein the external connectors of the substrate provide control, input and output signals to the microprocessor and power and ground signals to the memory, and wherein the power and ground external connectors of the substrate are arranged in a pattern in the center of the substrate.

15. The device of claim 14, wherein:the substrate comprises four layers, the external connectors have a spacing of 0.5mm, and / or the microprocessor, memory, and interposer substrate RDL are encapsulated together.

16. A method (800) comprising: selecting (801, 803) a plurality of components, wherein components comprise one or more processors, memories, and / or passives; determining (804) an electrical design for the components; determining (805) a substrate initial size; determining (809) a reduced number and / or value of capacitors: determining (812) a final substrate size; and adjusting (813) one or more signal connection lengths between the components, wherein the adjusting is based at least in part on minimizing signal skew.

17. The method of claim 16, further comprising: determining (802) one or more of pin count, pin spacing, and / or core size, wherein the substrate initial size is based on the determined pin count, pin spacing, and / or core size.

18. The method of claim 16 or 17, wherein determining a reduced number and / or value of capacitors comprises first determining (808) a vendor recommended number and / or value of capacitors.

19. The method of any of claims 16-18, further comprising one or more of: determining (806) connections between the components; determining (807) required I / O, power, and / or ground signals;minimizing (810) capacitor and resistor pull up / down vendor recommendations relative to pin count; and / or removing (811) power rail bulk capacitors and placing them on a system substrate.

20. The method of any of claims 16-19, wherein the method is a method to design a device according to any of claims 1-13 or 14-15.

21. A method (880), comprising: designing an integrated device for optimized size, skew, and / or thermal properties, wherein the designing comprises one or more of: selecting (881) a processor with a feature set that meets the needs of a system for a specific application; selecting (882) a circuit diagram for the system having active and passive components; selecting (883) die for the active components; selecting (884) passive components based on manufacturer data sheets for active components and system input / output substrate size constraints; selecting (885) a physical arrangement of active components on a substrate; selecting (886) a substrate for assembly of active and passive components; selecting (887) the substrate size based on the physical die sizes of the active and passive components and their physical arrangement and mounting arrangement on the substrate; selecting (888) selecting the pin spacing for the substrate and evaluating the I / O and power pin requirements for the active components based on manufacturer data sheets for the die selected size; adjusting (889) the substrate size based on the size of the die for the active components mounted thereon and pin spacing and I / O and power pin requirements; creating (890) a substrate with spaced multiple layers of conductive traces that are insulated from each other and vias for interconnecting selected traces and that reflects / implements the circuit diagram; adjusting (891) a number, size and value of passive components relative to one or more manufacturer data sheets; reducing signal skew (892) among groups of signal lines between active components by matching signal trace lengths between those components;arranging (893) exterior input / output signal pins in groups of similar signals along the outer periphery of the substrate so signals can escape from under the substrate; arranging (894) exterior input / output power / ground pins in groups in the center portion of the substrate; selecting thermal components (895) to provide thermal isolation for selected active components; and thermally isolate and / or manage the active components (896) independently to capture and utilize heat.

22. The method of claim 21, wherein the method is a method to design a device according to any of claims 1-13 or 14-15.

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